High speed input buffer

High speed input buffer

FIELD OF THE INVENTION The present invention relates generally to integrated circuits, and more particularly to data input buffers capable of receiving high-speed data transmissions.

Typically, integrated circuits include many input/output pins that are used to communicate with additional circuitry. For example, an integrated memory device, such as a dynamic random access memory (DRAM), includes control inputs for receiving memory operation control signals, and data pins for bidirectional data communication with an external system or processor.

The data transfer speed of modern integrated circuits is mainly limited by the operating speeds of internal circuits. That is, a communication network capable of transmitting signals between circuits at a faster speed than the capacity of many integrated circuits has been developed. To address the need for faster circuits, a group of integrated circuits can be coupled to a common bus. In this configuration, each integrated circuit operates in a coordinated manner with the other integrated circuits to share data transmitted at high speed. For example, a group of memory devices such as DRAM, static RAM, or read-only memories (ROMs) may be connected to a common data bus. The data rate of the bus is substantially higher than the possible operating speed of the individual memories. Thus, each memory is operated to receive new data while one memory is processing the received data. By providing an adequate number of memory devices and a useful control system, very high speed data transfers can be achieved.

As the transmission rate of data communication signals continues to increase, new circuits and methods for accurately receiving data in each integrated circuit are required. One proposed solution is the bus interface described in US Pat. No. 5,513,327. This bus interface uses two edge triggered receivers to latch data. The first receiver operates in response to the rising edge of the clock signal, and the second receiver operates in response to the falling edge of the clock. Furthermore, the data bus is not terminated at an intermediate supply level and the output is sent over the bus using an open drain configuration.

For the above reasons and other reasons described below that will become apparent to those skilled in the art upon reading and understanding this specification, the art provides, independently, or There is a need for a high-speed input buffer that can operate in combination with other input buffers.

SUMMARY OF THE INVENTION The above and other problems with integrated circuit data transmission are addressed by the present invention and will be understood by reading and examining the following specification. An input buffer circuit is described that equalizes, samples, senses, and latches the data signals for each clock signal.

In particular, the present invention describes an input buffer circuit adapted to be coupled to a high-speed data bus. The input buffer circuit includes a differential sense amplifier circuit selectively coupled to a data input node and a data bus termination voltage. An equalization circuit is connected to the differential sense amplifier circuit and the data bus terminal circuit to equalize the differential sense amplifier circuit to the data bus terminal voltage in response to the equalization signal. and coupling circuitry for selectively coupling the data input node and data bus terminal voltages to the differential sense amplifier circuit in response to the sample signal. The input circuit further includes sense amplifier activation circuitry for activating the differential sense amplifier circuit in response to the sense signal. The latch circuit is coupled to the differential sense amplifier circuit. The latch circuit is adapted to latch the data state of the differential sense amplifier circuit in response to the latch signal.

1 shows a memory bus;

Fig. 2 shows an alternative memory bus;

3 is a block diagram of a dual receiver input buffer circuit;

4 is a schematic diagram of a high-speed input buffer of a single receiver;

Fig. 5 is a timing diagram for the operation of the input buffer of Fig. 4;

6 is a timing diagram of a selection voltage of the input buffer of FIG. 4;

7 is a schematic diagram of an alternative high-speed input buffer;

8A, B, and C are timing diagrams of the operation of the input buffer of FIG. 7;

9 is a schematic diagram of an output driver circuit;

Fig. 10 is a block diagram of a memory device equipped with a high-speed input buffer;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following detailed description of preferred embodiments, reference is made to the accompanying drawings, which form a part hereof, and in which the invention may be practiced, showing by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments have been described in such detail as to enable those skilled in the art to practice the invention, and it should be understood that logical, mechanical and electrical changes may be made therein without departing from the spirit and scope of the invention. . Accordingly, the present invention is not limited to the following detailed description.

1 illustrates a memory bus 100 including a control circuit 102 that provides control and data signals to a number of integrated circuits 104(0)-104(x) via a plurality of communication lines 106. shown simply. Communication lines are connected to the terminal voltage (V_term) is terminated with a suitable terminal circuit 108 (usually illustrated as a resistor) coupled to .

2 is a centralized control providing control and data signals to a number of integrated circuits 104(0)-104(x) and 114(0)-114(x) via a plurality of communication lines 116 . A simplified illustration of a memory bus 112 including circuitry 102 is shown. Communication lines are connected to the terminal voltage (V_term) are terminated at both ends with suitable terminal circuits 118(1) and 118(2) (usually exemplified as resistors) coupled to . V_termA preferred value of is 1/2 (Vdd-Vss), but may be any intermediate supply level.

3 is a block diagram of an input buffer 119 connected to a data input 120 . The buffer includes two receiver circuits 122 , 126 and two latch circuits 124 , 128 connected in parallel. Each latch circuit outputs data to either node 130 (data-odd*) or node 132 (data-even*). The receivers operate from different phases of a common data clock signal provided on the busline. Therefore, the receivers are controlled using internal vernier delays rather than being triggered at the edge. Vernier delays are adjusted at system startup to maximize valid data reception. That is, the data sampling is done when there is valid data and the delay is adjusted so that it is not limited to the edge transition of the clock signal. The illustrated dual receiver input buffer can be used for high-speed data communication in the range of 800 megabits per second. For slow data rates of, say, 400 megabits per second, a single receiver and latch circuit can be used for the input buffer.

Referring to FIG. 4 , a high-speed input buffer 150 using a receiver 152 and a latch circuit 154 to output an internal data signal Data to an output 156 will be described. Receiver 152 circuitry operates in response to internal signals based on different phases of a common clock signal provided to a bus coupled to another integrated circuit. The internal signals are an equalization signal (EQ*), a detection signal (sensing), and a sample signal (sample). The receiver is connected to the bus terminal voltage (V_term) and connected to the bus data line through a data input connection 120 .

Receiver 152 includes a p-type sense amplifier circuit 158 having a pair of cross-coupled p-type transistors, and an n-type sense amplifier circuit 158 having a pair of cross-coupled n-type transistors. The equalization circuit 162 converts the common node of the sense amplifiers (nodes A and B) to V_termIt is provided to equalize. Combining circuits 164 and 166 are responsive to the sample signal at node 12 and V_termis provided to selectively bind to nodes A and B, respectively. To understand the operation of the input buffer, refer to the timing diagram of FIG. 5 .

As shown in FIG. 5 , the equalization signal EQ* transitions low at time t1 to activate the transistors 168 , 170 , and 172 of the equalization circuit 162 . Transistors 170 and 172 connect nodes B and A to a terminal voltage V, respectively._termbind to Therefore, the sense amplifiers are equalized to the bus terminal voltage. At time t2, the equalization circuit is deactivated, the sample signal transitions high and activates the coupling circuit 164 to couple the input 120 to node A. Similarly, the coupling circuit 166 connects the node B to the terminal voltage V_termactivated to bind to At time t2 the sense signal is pulled low, so node 180 of p-sense amplifier circuit 158 is coupled low, and node 174 of n-sense amplifier is connected to V through transistor 176._termis coupled to At time t3, the sense signal transitions high, activating transistor 178 and coupling node 174 to ground. The sample signal transitions low such that nodes A and B are isolated so that the p-sense amplifier and the n-sense amplifier amplify nodes A and B to the appropriate voltage level. The latch* signal transitions high at time t3 to activate the latch circuit 154 . Thus, coupling circuit 182 is activated to couple the inverse of node B to inverter circuit 184 . When the latch* signal returns to the low state, circuit 182 is deactivated and circuit 186 is activated to latch inverter 184 . Although the latch is connected to node B, the latch circuit 154 may be coupled to node A and is not intended to be limiting of the present invention. Those skilled in the art will recognize that the signal shown in FIG. 5 is generated internally in response to a clock signal received from the outside. Thus, the input data buffer operates from different phases of the clock signal.

6 shows the voltages across nodes A and B and output node 156 when a high input data signal is received. At time t1 nodes A and B are V_termis equalized to At time t2, node A is coupled to input 120 and the voltage increases. At time t3, the sense amplifier circuit is activated and nodes A and B are amplified. At the same time, node B is coupled to the latch circuit and the output data signal of 156 is coupled to node B.

FIG. 7 is a schematic diagram of a high-speed input buffer having two parallel receivers 122 and 126 and two latch circuits 124 and 128 as shown in FIG. 3 . Receivers 122 and 126 generally include the circuitry of receiver 152 and operate in a similar manner as described above with reference to FIG. The timing diagrams of FIGS. 8A, 8B, and 8C show the operation of the high-speed input buffer of FIG. 7 . The provided data signal on the DQ line is sampled by the two receivers 122 and 126 at the rising edge of their respective sample signals. Therefore, the DQ line is sampled by two receiver circuits. The outputs (data-even* and data-odd*) together represent the data provided to the DQ line. The external bus clock signal and the internal clock signal operating at twice the frequency of the external clock are shown. The equalization signals EQ1* and EQ2* are substantially matched to the clock signals. As such, the external clock signal can be logically defined as equal to 1/2 (EQ1* AND EQ2*). The sample signals are timed using a vernier delay circuit to sample the DQ line when the data signals are in a signal peak state.

9 is a schematic diagram of a push/pull output driver 200 connected to a data output connection (DQ) of an integrated circuit. Pull-up and pull-down signals are provided to nodes 202 and 204 to activate pull-up transistor 206 or pull-down transistor 208, respectively. The driver circuit has optional slew rate control circuits (210). These control circuits can be tuned using the Vslew signal to selectively activate a series of transistors. That is, by activating any of the transistors, the parallel resistor is bypassed and the response time of the circuit is changed. Accordingly, the activation timing of the transistors 206 and 208 can be adjusted.

A pullup drive adjust circuit 214 is provided within the output driver circuit 200 to adjust the voltage coupled to the pullup transistor 206 . Similarly, a pull-down drive steering circuit 216 is provided within the output driver circuit 200 to regulate the voltage coupled to the pull-down transistor 206 . In operation, the gates of transistors 218 are selectively activated to bypass resistors 220 . Adjusting the output driver circuit is done after the integrated circuit is installed on the bus. That is, the output driver voltages can be adjusted to suit specific bus system requirements. Those of ordinary skill in the art will appreciate that slew rate control circuits may be eliminated without departing from the present invention.

10 is a block diagram of a dynamic random access memory device 240 (DRAM) having a high-speed input butter 248 as described above. The memory includes an address circuit 242 that accesses the memory array 241 in response to address signals provided to the output lines 243 . A control circuit 252 is provided to control reading and writing of the memory in response to the control signals 254 . A phase generator circuit 244 is provided to generate the internal signals DQ*, sample, sense, and latch* for the input buffer circuit. A vernier adjustment circuit 254 is coupled to the phase generator to adjust the timing of the internal signals. The input buffer circuit 248 includes a high-speed input data circuit as described above for each data line DQ. An output driver circuit 250 is provided for driving an output signal suitable for the DQ lines. Although the example shown in Fig. 10 is DRAM, the high-speed input buffer circuit of the present invention may be included in any integrated circuit device such as SRAM and ROM memory devices.

<Conclusion>

An integrated circuit input buffer circuit that samples and latches a data signal using a receiver circuit and a latch has been described. The buffer operates in response to internal signals generated in different phases of an externally provided clock signal. The input buffer may include two receiver circuits and two latch circuits for use on a data bus operating at a high data rate. The receiver circuit includes a sensing circuit for sensing an input data signal, an equalization circuit for equalizing the sensing circuit, and a sensing activation circuit for activating the sensing circuit.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will recognize the specific embodiments shown herein in any configuration intended to achieve the same purpose. You will find that you can replace it. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is expressly intended that the invention be limited only by the claims and their equivalents.