High speed input buffer

<u style="single">Technical field of invention</u>The present invention relates generally to integrated circuits, and more specifically to data input buffers capable of receiving high speed data transmissions.<u style="single">Background of the invention</u>Integrated circuits typically include many input / output pins used to communicate with additional circuits. For example, an integrated memory device such as a dynamic random access memory (DRAM) includes both a control input for receiving a memory operation control signal and a data pin for directional data communication with an external system or processor. The data transmission speed of current integrated circuits is mainly limited by the operating speed of internal circuits. That is, communication networks have been developed that can transmit signals between circuits at a speed faster than the capacity of many integrated circuits. A group of integrated circuits can be combined on a common bus to meet the demand for faster circuits. In this configuration, each integrated circuit operates in a coordinated manner with other integrated circuits and shares data transmitted at high speed. For example, a group of memory devices such as DRAM, static RAM, or read-only memory (ROM) can be connected to a common data bus. The data rate of the bus can be substantially faster than the possible operating speed of the individual memories. Therefore, each memory is operated so that one memory processes the input data and another memory receives new data. Very fast data transmission can be achieved by providing the right number of memory devices and an efficient control system. As the transmission rate of data communication signals continues to increase, new circuits and methods are needed to accurately receive data in each integrated circuit. One proposed solution is U.S. Pat. No. 5,513, This is the bus interface described in No. 327. This bus interface uses two edge trigger receivers to latch the data. The first receiver operates in response to the rising edge of the clock signal, while the second receiver operates in response to the falling edge of the clock. In addition, the data bus is not terminated at the intermediate supply level, and the output is transmitted over the bus using an open drain configuration. Independently or to receive data in response to bus clock transitions for the reasons described above, and for other reasons apparent to those skilled in the art in reading and understanding the specification, described below. There is a demand in the art for high speed input buffers that can operate in combination with other input buffers.<u style="single">Abstract of the invention</u>The above and other problems with integrated circuit data transmission are addressed by the present invention and are understood by reading and reviewing the following specification. An input buffer circuit that balances, samples, senses, and latches the data signals on each clock signal is described. In particular, the present invention describes an input buffer circuit adapted to be coupled to a high speed data bus. The input buffer circuit comprises a differential sensing amplifier circuit that is selectively coupled to a data input node and a data bus termination voltage. The balanced circuit is connected to the differential sensing amplifier circuit and the databus termination voltage for balancing the differential sensing amplifier circuit to the databus termination voltage in response to the balanced signal. The coupling circuit is provided to selectively couple the data input node and data bus termination voltage to the differential sensing amplifier circuit in response to the sample signal. The input buffer further includes a sensing amplifier actuating circuit for actuating the differential sensing amplifier circuit in response to the sensing signal. The latch circuit is coupled to the differential sensing amplifier circuit. The latching circuit is adapted to latch the data state of the differential sensing amplifier circuit in response to the latching signal.<u style="single">[Simple explanation of drawings]</u>FIG. 1 is a diagram of a memory bus. FIG. 2 is a diagram of another memory bus. FIG. 3 is a block diagram of a dual receive input buffer circuit. FIG. 4 is a schematic diagram of a single reception high-speed input buffer. FIG. 5 is a timing diagram of the operation of the input buffer of FIG. FIG. 6 is a timing diagram of the selected voltage of the input buffer of FIG. FIG. 7 is a schematic diagram of another high-speed input buffer. 8A, B, and C are timing diagrams of the operation of the input buffer of FIG. 7. FIG. 9 is a schematic diagram of the output driver circuit. FIG. 10 is a block diagram of a memory device having a built-in high-speed input buffer.<u style="single">Detailed description of the invention</u>In the following detailed description of preferred embodiments, reference is made to the accompanying drawings that form part of this specification and are shown in a manner illustrating specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to allow one of ordinary skill in the art to carry out the invention, and other embodiments may be utilized, as well as logical, mechanical, and electrical modifications. It is understood that it can be done without departing from the spirit and scope of the invention. Therefore, the following detailed description is not taken in a limited sense, and the scope of the invention is defined only by the appended claims. FIG. 1 is a simplified example of a memory bus 100 that includes a control circuit 102 to provide control and data signals to many integrated circuits 104 (0) to 104 (x) over multiple communication lines 106. is there. The communication line is terminated with a suitable termination circuit 108 (typically exemplified as a register) coupled to a termination voltage (Vterm). Figure 2 is centered to provide control and data signals to many integrated circuits 104 (0) to 104 (x) and 114 (0) to 114 (x) over multiple communication lines 116. It is a simplified example of the memory bus 112 including the control circuit 102. The communication line is terminated at both ends using the appropriate termination circuits 118 (1) and 118 (2) (typically exemplified as registers) coupled to the termination voltage (Vterm). A preferred value for Vterm is 1/2 (Vdd-Vss), but it can be any intermediate supply level. FIG. 3 is a block diagram of the input buffer 119 connected to the data input 120. The buffer includes two receiving circuits 122 and 126 and two latching circuits 124 and 128 connected in parallel. Each latch circuit has node 130 (data odd number)^*) Or node 132 (data even^*) To generate a data output above. The receiver operates out of phase with a common data clock signal provided on the bus line. Therefore, the receiver is not edge-triggered and is controlled using an internal vernier delay. Vernier delays are adjusted during system operation to maximize effective data reception. That is, the delay is made in the presence of data for which data sampling is valid and is adjusted so that it is not limited to the edge transitions of the clock signal. The illustrated dual receive input buffer can be used for high speed data communication in the range of 800+ megabits per second. For slower data communication speeds, such as 400 megabits per second, a single receiver and latch circuit can be used in the input buffer. With reference to FIG. 4, a high speed input buffer 150 is described that uses the receiver 152 and the latch circuit 154 to generate an internal data signal (Data) on the output 156. The receiver 152 circuit operates in response to an internal signal based on a common clock signal of different phases provided on a bus coupled to another integrated circuit. The internal signal is an equilibrate signal. signal) (EQ^*), Sensing signal (Sense), and sample signal (Sample). The receiver is connected to the bus termination voltage (Vterm) and is connected to the bus data line via the data input connection 120. The receiver 152 consists of a p-type sensing amplifier circuit 158 having a pair of cross-coupled p-type transistors and an n-type sensing amplifier 160 having a pair of cross-coupled n-type transistors. A balancing circuit 162 is provided to balance the common nodes of the sensing amplifier (nodes A and B) to the Vterm. Coupling circuits 164 and 166 are provided to selectively couple nodes 120 and Vterm to nodes A and B, respectively, in response to the sample signal. To better understand the behavior of the input buffer, refer to the timing diagram in Figure 5. Balanced signal (EQ) as shown in Figure 5^*) Transitions low at time t1 to activate the transistors 168, 170 and 172 of the equilibrium circuit 162. Transistors 170 and 172 couple nodes B and A to the termination voltage Vterm, respectively. The sensing amplifier is therefore balanced to the bus termination voltage. At time t2, the equilibrium circuit is stopped, the sample signal transitions high, activates coupling circuit 164, and couples input 120 to node A. Similarly, the coupling circuit 166 is activated to couple node B to the terminating voltage Vterm. At time t2, at the low sensing signal, node 180 of the p-type sensing amplifier circuit 158 is coupled to low and node 174 of the n-type sensing amplifier is coupled to Vterm via the transistor 176. At time t3, the sense signal transitions high, activating transistor 178 and coupling node 174 to ground. The sample signal transitions low, separating nodes A and B so that the p-type and n-type sensing amplifiers amplify nodes A and B to the appropriate voltage level. latch^*The signal transitions high at time t3, activating latch circuit 154. Therefore, the coupling circuit 182 is activated to couple the reverse of node B to the inverter circuit 184. latch^*When the signal returns to the low state, the circuit 182 is stopped and the circuit 186 is activated to latch the inverter 184. Although the latch is connected to node B, the latch circuit 154 can be coupled to node A and is not intended to limit the invention. It will be understood by those skilled in the art that the signal shown in FIG. 5 is internally generated in response to a clock signal received from the outside. In this way, the input data buffer operates depending on the clock signals of different phases. FIG. 6 shows the voltage on nodes A and B and the output node 156 when the high input data signal is received. At time t1, nodes A and B are equilibrated to Vterm. At time t2, node A is coupled to input 120 to increase the voltage. At time t3, the sensing amplifier circuit is activated to amplify nodes A and B. At the same time, node B is coupled to the latch circuit and the output data signal on 156 is coupled to node B. FIG. 7 shows a schematic diagram of a fast input buffer with the two parallel receivers 122 and 126 shown in FIG. 3 and the two latch circuits 124 and 128. As described above with reference to FIG. 4, receivers 122 and 126 typically include the circuit of receiver 152 and operate in a similar manner. The timing diagrams of FIGS. 8A, 8B and 8C show the operation of the high-speed input buffer of FIG. 7. The data signal provided on the DQ line is sampled by both receivers 122 and 126 on the rising edge of each sample signal. Therefore, the DQ line is sampled by both receiver circuits. Output (data-even^*And data-odd^*) Both indicate the data provided on the DQ line. The external bus clock signal and the internal clock signal operating at twice the frequency of the external clock will be described. Balanced signal (EQ1^*And EQ2^*) Is substantially aligned with the clock signal. Theoretically, the external clock signal is 1/2 (EQ1)^*AND EQ2^*) Can be defined. The sample signal is tuned using a vernier delay circuit to sample the DQ line when the data signal is at the signal peak. FIG. 9 is a schematic diagram of the push / pull output driver 200 connected to the data output connection (DQ) of the integrated circuit. The pull-up and pull-down signals are provided to nodes 202 and 204, respectively, to activate either the pull-up transistor 206 or the pull-down transistor 208. The driver circuit includes an optional slew rate control circuit 210. The control circuit is tuned using the Vslew signal and can selectively operate a series of transistors. That is, by activating either transistor, the parallel resistor is bypassed and the response time of the circuit changes. In this way, the timing of operation of transistors 206 and 208 can be adjusted. A pull-up drive adjustment circuit 214 is provided in the output driver circuit 200 to adjust the voltage coupled to the pull-up transistor 206. Similarly, a pull-down drive adjustment circuit 216 is provided in the output driver circuit 200 to adjust the voltage coupled to the pull-down transistor 206. In operation, the gate of transistor 218 is selectively actuated, bypassing resistor 220. After the integrated circuit is installed on the bus, the output driver circuit is tuned. That is, the output driver voltage is adjusted to meet the requirements of a particular bus system. It will be appreciated by those skilled in the art that the slew rate control circuit can be removed without departing from the present invention. FIG. 10 is a block diagram of a dynamic random access memory device 240 (DRAM) incorporating the high-speed input buffer 248. The memory includes an address circuit 242 for accessing the memory array 241 in response to an address signal provided on the input line 243. A control circuit 252 is provided to control memory read and write operations in response to control signal 254. Phase generator circuit 244 is provided and the input^*, Sample signal, sense signal, and latch^*Generate a signal. The vernier adjustment circuit 245 is coupled to a phase generator for adjusting the timing of the internal signal. It is understood that the input buffer circuit 248 includes the high speed input buffer circuit described above for each data line DQ. An output driver circuit 250 is provided to drive the appropriate output signal on the DQ line. Although a specific example of FIG. 10 is DRAM, the high-speed input buffer circuit of the present invention can be included in any integrated circuit device such as SRAM and ROM memory device.<u style="single">Conclusion</u>An integrated circuit input buffer circuit that uses a receiver circuit and a latch to a sample and latches a data signal is described. The buffer operates in response to internal signals generated by externally provided clock signals of different phases. The input buffer may include two receiver circuits and two latch circuits used on a data bus operating at higher transmission rates. The receiver circuit includes a sensing circuit for sensing the input data signal, a balancing circuit for balancing the sensing circuit, and a sensing activation circuit for operating the sensing circuit. Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that any configuration presumed to achieve the same object can be replaced with the particular embodiments shown herein. obtain. This application covers any conformance or modification of the invention. Therefore, it is clear that the present invention is limited only by the claims of the present invention and its equivalents.