Semiconductor memory

Semiconductor memory device {SEMICONDUCTOR MEMORY}

1 is a diagram showing a semiconductor memory device according to an embodiment of the present invention;

Fig. 2 is a diagram showing the configuration of the memory cell array and data storage circuit in Fig. 1;

Fig. 3 is a diagram showing the structure of a memory cell and a selection transistor in Fig. 2;

Fig. 4 is a diagram showing the configuration of a memory cell unit;

Fig. 5 is a diagram showing a specific configuration example of a data storage circuit according to an embodiment of the present invention;

Fig. 6 is a diagram showing a specific configuration of a clock synchronous inverter;

Fig. 7 is a diagram showing a read operation of the semiconductor memory device according to the embodiment of the present invention;

Fig. 8 is a diagram showing a read operation of the semiconductor memory device according to the embodiment of the present invention;

Fig. 9 is a diagram showing a read operation of the semiconductor memory device according to the embodiment of the present invention;

Fig. 10 is a diagram showing a first write operation of the semiconductor memory device according to the embodiment of the present invention;

Fig. 11 is a diagram showing a second write operation of the semiconductor memory device according to the embodiment of the present invention;

Fig. 12 is a diagram showing a third write operation of the semiconductor memory device according to the embodiment of the present invention;

Fig. 13 is a diagram showing a fourth write operation of the semiconductor memory device according to the embodiment of the present invention;

Fig. 14 is a diagram showing a write verification operation of the semiconductor memory device according to the embodiment of the present invention;

Fig. 15 is a diagram showing a write verification operation of the semiconductor memory device according to the embodiment of the present invention;

Fig. 16 is a diagram showing a write verification operation of the semiconductor memory device according to the embodiment of the present invention;

<Explanation of symbols for main parts of the drawing>

One : memory cell array

2 : bit line control circuit

3 : column decoder

4 : data input/output buffer

5 : Data input/output terminal

6 : word line control circuit

7 : Control signal and control potential generation circuit

8 : Control signal input/output terminal

10 : data storage circuit

11 : p-type semiconductor substrate

12 : n-type diffusion layer

13, 17: gate insulating film

14 : floating gate

15 : insulating film

16 : control gate

18 : selection gate

M: memory cell

S: select transistor

WL : word line

BL: bit line

SG: selection gate

SRC: source line

Qn : n-channel MOS transistor

Qp : p-channel MOS transistor

VCC : power supply potential

CI : Clock Synchronous Inverter

<background-art><p>BACKGROUND OF THE INVENTION Field of the Invention [0001] The present invention relates to semiconductor memory devices, and is particularly used for multi-value flash memories, multi-value EEPROMs, and multi-value EPROMs. </p><p>A MOSFET structure having a floating gate (charge accumulation layer) and a control gate on a semiconductor substrate is well known as a type of memory cell of a flash memory.</p><p>Usually, one bit of data, that is, data "0" or "1", is stored in one memory cell of the flash memory. In addition, whether the data of the memory cell is "0" or "1" can be identified by the amount of charges accumulated in the floating gate.</p><p>On the other hand, in recent years, in order to secure a large data capacity, development of a multi-value storage method in which data of multiple bits is stored in one memory cell is being developed. For example, in the 4-value storage method, data "0", "1", "2" or "3" is stored in one memory cell.</p><p>In the multi-value memory type flash memory, which data is stored in the memory cell is judged by the amount of charge accumulated in the floating gate.</p><p>Hereinafter, a flash memory of a 4-value storage method will be described as an example according to a data storage state, that is, a relationship between data and an amount of charge among floating gates.</p><p>First, data "0" corresponds to an erased state.</p><p>The erased state is a state in which positive charges are accumulated in the floating gate. That is, in the erased state, the floating gate is positively charged with respect to the neutral state in which the amount of charge in the floating gate is zero (0).</p><p>The erased state is obtained, for example, by applying a high potential (about 20 V) to the semiconductor substrate, setting the control gate to a ground potential (0 V), and transferring positive charges from the semiconductor substrate to the floating gate.</p><p>Next, data "1", "2" and "3" correspond to the write state.</p><p>The write state is a state in which negative charges are accumulated in the floating gate. However, the amount of negative charge in the floating gate in the data "2" state is greater than the negative charge in the floating gate in the data "1" state, and the negative charge in the floating gate in the data "3" state is equal to the amount of negative charge in the data "2" floating gate. It is set so as to be larger than the amount of negative charge in the floating gate in the state of ".</p><p>In the write state, the floating gate is negatively charged with respect to the neutral state in which the amount of charge in the floating gate is zero.</p><p>The write state is obtained, for example, by setting the semiconductor substrate, the source, and the drain to the ground potential (0V), respectively, applying a high potential (about 16V) to the control gate, and moving negative charges from the semiconductor substrate to the floating gate .</p><p>During the write operation, in the memory cell to hold data "0", the source, drain, and channel are set to 5V. In this case, even if a high potential (about 16V) is applied to the control gate and the substrate is set to the ground potential (0V), data "0" is maintained because positive charges are held in the floating gate.</p><p>As described above, four types of write states ("0", "1", "2", and "3") can be realized with one memory cell.</p><p>It is known that a flash memory has a NAND type memory cell unit.</p><p>This memory cell unit includes a memory cell column composed of a plurality (eg, four) of memory cells, a first select transistor connected between one end of the memory cell column and a bit line, and between the other end of the memory cell column and a source line. and a second selection transistor connected to</p><p>In addition, the source line is common to all memory cell units.</p><p>In a flash memory having a NAND type memory cell unit, when data "0" is written, the bit line is set to a power source potential (VCC; for example, 3V), and the gate of the first selection transistor is selected to be at a power source potential (VCC). The control gate of the memory cell is set to a first high potential (eg, 16V) and the control gate of the unselected memory cell is set to a second high potential (eg, 10V), and accumulated in the floating gate of the selected memory cell. holds an electric charge.</p><p>At this time, since the channel of each memory cell of the NAND-type memory cell unit is connected to the bit line via the first selection transistor, the channel potential of each memory cell is determined by considering the so-called threshold drop of the first selection transistor, Initially, it is set to a predetermined potential equal to or less than the power supply potential (VCC; for example, 3V).</p><p>After that, when the first selection transistor becomes non-conductive, the channel potential of each memory cell of the NAND type memory cell unit rises due to the electrostatic capacitance generated between the control gate and the channel. For example, if the coupling ratio of the capacitance is 50%, the potential of the channel becomes about 5V.</p><p>However, when negative charges are accumulated in the floating gate of the memory cell, the threshold value of the memory cell becomes high. Accordingly, the channel potential of each memory cell during the data "0" write operation becomes lower as the threshold value of the memory cell becomes higher, and the reliability in retaining the data "0" decreases.</p><p>However, when the threshold of the memory cell is -1 V, when the potential of the control gate is about 0 V, the potential of the channel becomes about 1 V, and when the potential of the control gate is about 10 V, the potential of the channel becomes about 6 V (coupled rain 50%).</p><p>Further, when the threshold of the memory cell is 1 V, when the potential of the control gate is about 1 V, the channel potential is about 0 V, and when the potential of the control gate is about 10 V, the channel potential is about 4.5 V (coupled) rain 50%).</p><p>In a flash memory cell having a NAND type memory cell unit, the data of the memory cell applies a predetermined read potential to the control gate so that the memory cell is turned on or off according to the data of the memory cell, at which time the memory It can be read by detecting the cell current flowing in the channel of the cell.</p><p>Here, when three types of read potentials are prepared, it is possible to discriminate four types of write states (states in which the types and amounts of electric charges in the floating gate differ, that is, states with different threshold values).</p><p>Furthermore, the NAND type memory cell unit has a configuration in which a plurality of memory cells are connected in series, and therefore is characterized in that the cell current during the read operation is small (eg, about 1 mu A).</p><p>As for the read time, for example, if the bit line capacity connected to the selected memory cell is set to about 5 pF, it takes about 5 mu sec for the potential of the bit line to fluctuate by 1 V due to the cell current.</p><p>In order to read data from a memory cell at high speed with a small cell current, for example, an N-channel MOS transistor is connected between the bit line and the read circuit, and a potential of about 2 V is applied to the gate of the MOS transistor to precharge the bit line. do.</p><p>In this case, when the threshold of the N-channel MOS transistor is set to about 1 V, the bit line is precharged to about 1 V when the so-called threshold drop of the MOS transistor is taken into consideration.</p><p>When the bit line is precharged, the N-channel MOS transistor then becomes high in resistance, and then becomes non-conductive. However, the precharge of the bit line is not interrupted until the N-channel MOS transistor is completely non-conductive, considering the effective precharge time.</p><p>During a read operation, when a cell current flows through the selected memory cell and the potential of the bit line decreases, the channel resistance of the N-channel MOS transistor connected to the bit line decreases. When this state is detected, the potential of the bit line is high. It becomes possible to detect changes (data in memory cells).</p><p>The change in the channel resistance of the N-channel MOS transistor can be detected by comparing the resistance value of the channel resistance of the MOS transistor with the resistance value of the so-called reference resistance. For this reason, a current path is provided in the reference resistor, the N-channel MOS transistor, and the memory cell.</p><p>However, in such a read operation, when data of a plurality of selected memory cells is read simultaneously, a large current flows through the source line common to all cell units depending on the threshold of each selected memory cell, or no conversely flows at all. do.</p><p>For example, when a cell current flows through most of the selected memory cells, that is, when the data of most of the selected memory cells is "0", a large current flows through the source line and the potential of the source line fluctuates. Variation in the potential of the source line creates a state in which data in the selected memory cell cannot be accurately read.</p><p>As described above, when data "0" is written, for example, if the threshold value of a memory cell in the memory cell unit is high, the channel potential of the memory cell does not rise sufficiently. , there is a risk that data "1" will be written.</p><p>In addition, while it takes a very long time to detect the state of a memory cell with a small cell current at the time of reading, there is a drawback in that the state of the memory cell cannot be accurately detected if the state of the memory cell is to be detected at high speed.</p></background-art><tech><p>SUMMARY OF THE INVENTION The present invention has been made to solve the above drawbacks, and an object thereof is to sufficiently secure the channel potential of a memory cell at the time of writing, and to detect the state of the memory cell at high speed and accurately at the time of reading.</p><p>In order to solve the above problems, a semiconductor memory device of the present invention includes a memory cell, a bit line connected to the memory cell, a read circuit including a precharge circuit, and a first transistor connected between the bit line and the read circuit and the bit line is precharged by the precharge circuit when a first potential is applied to the gate of the first transistor, and the read circuit provides a second lower potential than the first potential to the gate of the first transistor. A change in the potential of the bit line is sensed when a potential is applied.</p><p>The precharge circuit includes a second transistor connected between the first transistor and a power supply terminal, and the second transistor is set to a non-conductive state while the second potential is applied to the gate of the first transistor. do.</p><p>In a preferred embodiment of the present invention, the first and second transistors are n-channel MOS transistors, and the capacitance of the bit line is greater than the capacitance of the connection portion between the first transistor and the read circuit.</p><p>According to the semiconductor memory device of the present invention, a MOS transistor is connected between a bit line and a read circuit, a first potential is applied to the gate of the MOS transistor when the bit line is precharged, and a first potential is applied to the gate of the MOS transistor during readout. A lower second potential is being applied.</p><p>Therefore, after precharging the bit line, the MOS transistor can be made non-conductive in a short time, so that the potential change of the bit line can be detected without using a reference resistor or the like, and the write state of the memory cell can be detected with high speed and precision. can do.</p><p>A semiconductor memory device of the present invention includes a NAND type memory cell unit in which a plurality of memory cells are connected in series between first and second selection transistors, and means for performing writing to a selected memory cell among the plurality of memory cells. wherein the writing means applies a first potential to the gate electrode of the selected memory cell at the time of writing, and a second potential lower than the first potential to the gate electrode of a memory cell adjacent to one side of the selected memory cell is applied, and a third potential lower than the first potential and higher than the second potential is applied to the gate electrodes of the remaining memory cells.</p><p>One side of the selected memory cell is on the side of the second selection transistor with respect to the selected memory cell, the first selection transistor is connected to the bit line, and the second selection transistor is connected to the source line.</p><p>For the plurality of memory cells, sequential writing is performed from the memory cell adjacent to the second transistor toward the memory cell adjacent to the first selection transistor.</p><p>the writing means applies a fourth potential to a gate electrode of a memory cell existing on the first selection transistor side with respect to the selected memory cell among the remaining memory cells before the writing, and the selected memory cell among the remaining memory cells A fifth potential is applied to the gate electrode of the memory cell present on the side of the second selection transistor to charge the channels of the plurality of memory cells.</p><p>The fifth potential is higher than the fourth potential.</p><p>The writing means applies the fourth potential to the gate electrode of the selected memory cell before the writing, and applies the second potential to the gate electrode of a memory cell adjacent to one side of the selected memory cell.</p><p>The writing means applies the fifth potential to the gate electrode of the selected memory cell before the writing, and applies the second potential to the gate electrode of a memory cell adjacent to one side of the selected memory cell.</p><p>The fourth and fifth potentials are lower than the third potential. The fourth potential is a power supply potential.</p><p>In the writing, the writing means applies the third potential to the gate electrode of the memory cell present on the side of the second selection transistor with respect to the selected memory cell among the remaining memory cells, and thereafter, among the remaining memory cells. The third potential is applied to the gate electrode of the memory cell on the side of the first selection transistor with respect to the selected memory cell.</p><p>The writing means applies the third potential to the gate electrode of the memory cell existing on the side of the second selection transistor with respect to the selected memory cell among the remaining memory cells during the writing, and then, after applying the third potential to the gate electrode of the selected memory cell. The first potential is applied to</p><p>When the first potential is applied to the gate electrode of the selected memory cell, the third potential is applied to the gate electrode of the memory cell present on the side of the first selected transistor with respect to the selected memory cell among the remaining memory cells. practically the same as when</p><p>According to the semiconductor memory device having the above configuration, it is possible to generate a sufficient and stable channel potential at the time of writing "0" data without depending on the threshold value of the written memory cell.</p></tech>

<p>DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device of the present invention will be described in detail with reference to the drawings.</p><p>Fig. 1 shows the configuration of a NAND-type flash memory of a multi-value storage system according to an embodiment of the present invention.</p><p>The memory cell array 1 includes a plurality of NAND type memory cell units, a plurality of bit lines, a plurality of word lines, and a source line. A NAND type memory cell unit is constituted by a memory cell column comprising a plurality of memory cells connected in series, and a selection transistor respectively connected to both ends of the memory cell column. The source line is common to all memory cell units.</p><p>The bit line control circuit 2 reads data of the memory cell through the bit line of the memory cell array 1, detects the state of the memory cell through the bit line, or applies a write control voltage to the memory cell through the bit line. is applied to write to the memory cell.</p><p>The bit line control circuit 2 includes a plurality of data storage circuits. A data storage circuit is provided for a column of the memory cell array 1 . The data of the memory cell read by the data storage circuit selected by the column decoder 3 is read out from the data input/output terminal 5 via the data input/output buffer 4 .</p><p>Further, write data input from the outside to the data input/output terminal 5 is latched as initial control data to the data storage circuit selected by the column decoder 3 via the data input/output buffer 4 . The control data of the data storage circuit controls the write control voltage applied to the selected memory cells of the memory cell array 1 via the bit lines.</p><p>The word line control circuit 6 selects one of a plurality of word lines of the memory cell array 1 and applies a predetermined potential necessary for a read operation, a write operation, or an erase operation to the one word line.</p><p>The operations of the memory cell array 1, the bit line control circuit 2, the column decoder 3, the data input/output buffer 4 and the word line control circuit 6 are, respectively, the control signal and the control potential generating circuit 7 controlled by</p><p>Further, the control signal and control potential generating circuit 7 operates based on a control signal applied to the control signal input terminal 8 from the outside.</p><p>FIG. 2 shows an example of the configuration of the memory cell array 1 and the bit line control circuit 2 of FIG. 1 .</p><p>A NAND type memory cell unit includes a memory cell column composed of four memory cells M serially connected to each other, a selection transistor S connected between one end of the memory cell column and a bit line BL, and the other of the memory cell column. and a selection transistor S connected between the other end and the source line SRC.</p><p>The control gate of the memory cell M is connected to the word line WLm; m is any one of 1 to 4), the selection transistor S on the bit line side is connected to the selection gate SG1, and the selection transistor S on the source line side Transistor S is connected to selection gate SG2.</p><p>A plurality of memory cells M sharing one word line WLm constitute a unit called a page, and in this example, one block consists of four pages. In addition, although only two blocks are shown in this example, the memory cell array 1 is actually comprised by an arbitrary number of blocks (for example, 1024 blocks). Note that the number of bit lines BL0, BL1, ... BL4223 is 4224 in this example, but may be any number (eg, 2112).</p><p>The bit line control circuit 2 includes a plurality of data storage circuits 10 . In this example, one data storage circuit 10 is provided for two bit lines BLi and BLi+1 (i is 0 or even), but an arbitrary number, for example, 1, 4, 6 One for each or 9 bit lines may be installed.</p><p>The column selection signals CSL0, CSL1, ... CSL4223 are output signals of the column decoder. The column selection signals CSLi and CSLi+1 are input to the data storage circuit 10 connected to the bit lines BLi and BLi+1.</p><p>At the time of reading, the data of the memory cell latched in the data storage circuit 10 selected by the column selection signals CSLi and CSLi+1 is transferred to the data input/output buffer as read data.</p><p>Further, prior to writing, on the basis of the column selection signals CSLi and CSLi+1, control data for controlling the write control voltage applied to the memory cell at the time of writing to any one of the bit lines BLi and BLi+1 is initially transmitted.</p><p>When detecting the write state, the write state of the memory cell connected to any one of the bit lines BLi and BLi+1 is detected.</p><p>FIG. 3 shows the structure of the memory cell M and the selection transistor S of FIG. 2 .</p><p>An n-type diffusion layer 12 serving as a source or drain is formed on the surface of the p-type semiconductor substrate 11 .</p><p>The memory cell M includes an n-type diffusion layer 12 in a semiconductor substrate 11 , a gate insulating film 13 on the semiconductor substrate 11 , a floating gate 14 on the gate insulating film 13 , and a floating gate 14 on the floating gate 14 . It includes an insulating film 15 and a control gate (word line) 16 on the insulating film 15 . The selection transistor S includes an n-type diffusion layer 12 in the semiconductor substrate 11 , a gate insulating film 17 on the semiconductor substrate 11 , and a selection gate 18 on the gate insulating film 17 .</p><p>When a potential greater than or equal to the threshold of the memory cell M is applied to the control gate 16 of the memory cell M, a channel is formed on the surface of the semiconductor substrate 11 just below the floating gate 14 .</p><p>For example, the capacitance between the control gate 16 and the floating gate 14 is 1 fF, the capacitance between the floating gate 14 and the channel is 1 fF, the capacitance between the channel and the semiconductor substrate 11 is 0.25 fF, and the n-type capacitance is Assuming that the capacitance between the diffusion layer 12 and the semiconductor substrate 11 is 0.25 fF, the capacitive coupling ratio between the control gate 16 and the channel and the capacitive coupling ratio between the control gate 16 and the n-type diffusion layer 12 are 50% each.</p><p>In this case, when the channel and the n-type diffusion layer 12 are in a floating state, the potential of the channel and the n-type diffusion layer 12 rises by 0.5V when the control gate 16 rises by 1V.</p><p>FIG. 4 shows the structure of the NAND type memory cell unit of FIG. 2 .</p><p>A memory cell column is composed of four memory cells M, one end of the memory cell column is connected to a source line SRC via a select transistor S, and the other end of the memory cell column is a select transistor S. connected to the bit line BL via</p><p>In the erase operation, the potential Vsub of the semiconductor substrate is set to about 20 V, the potentials of the selection gates SG1 and SG2, the source line SRC, and the bit line BL are set to about 20 V, and the block erase (block) The potential of the word lines WL1 to WL4 of the selection block for which data of all memory cells in the memory cell is simultaneously erased) is set to 0V.</p><p>At this time, since negative charges (electrons) move from the floating gate to the channel, and the floating gate is positively charged with respect to a neutral state (a state in which no charge exists), the threshold of all memory cells M in the selected block is Negative (state of data "0").</p><p>In an unselected block for which block erasing is not performed, the potential of the word lines WL1 to WL4 is set to about 20V. As a result, the data of each memory cell maintains the state prior to the execution of the erase operation.</p><p>In the write operation, collectively, the potential of one selected word line of the selected block is set to about 16 V, the potentials of three unselected word lines of the selected block are set to a potential lower than the write potential, and the selection gate SG1 is The power supply potential VCC is set, the selection gate SG2 is set to 0V, and the potentials of all word lines and all selection gates of the unselected block are set to 0V.</p><p>For example, if the case of the 4-value storage method is described, the potential of the bit line BL is set to 0 V when data "1", "2", and "3" are written. At this time, in the selected memory cell, electrons are injected into the floating gate, and the threshold value becomes positive (+).</p><p>When data "0" is written, the bit line BL is set to the power supply potential VCC. At this time, since the potential of the selection gate SG1 is the power supply potential VCC, the selection gate S on the bit line side is in a non-conductive state, and the channel of the memory cell and the n-type diffusion layer are in a floating state.</p><p>The potential of the channel is raised by capacitive coupling of the channel and the control gate. Assuming that the potential less than the write potential applied to each control gate is about 10 V, if the coupling ratio of capacitive coupling is 50%, the potential of the channel becomes about 5 V. However, as the threshold value of the memory cell becomes higher, the channel potential of the memory cell at the time of writing data "0" becomes lower.</p><p>This is because, for example, if the threshold of the memory cell is about 1 V, the channel is not formed until the potential of the control gate reaches about 1 V.</p><p>In other words, when the threshold of the memory cell is about 1 V, since the potential of the channel is about 0 V when the potential of the control gate is about 1 V, the potential of the channel becomes about 4.5 V when the potential of the control gate is about 10 V ( binding ratio 50%).</p><p>In contrast, when the threshold of the memory cell is about -1V, the potential of the channel can be charged to about 1V even when the potential of the control gate is about 0V. In other words, when the control gate becomes about 10V, the channel potential becomes about 6V.</p><p>In the present invention, at the time of writing data "0", the potential of the unselected word line (e.g., WL3) adjacent to the source line side with respect to the selected word line (e.g. WL2) in the selected block is In particular, it is set to about 0V, and a potential of about 10V is applied to the remaining unselected word lines (eg, WL1 and WL4) in the selected block.</p><p>In addition, the writing order of data "0" in the memory cell unit is first, the memory cell connected to the word line WL4 closest to the source line, and sequentially moved to the memory cell connected to the word line on the bit line side, The last is the memory cell connected to the word line WL1 closest to the bit line.</p><p>In other words, in the memory cell unit, all data of the memory cells existing on the bit line side of the memory cells connected to the selected word line are erased, that is, data "0" is written. In other words, the threshold value of the memory cell existing on the bit line side of the memory cell connected to the selected word line is negative.</p><p>On the other hand, since the control gate of the memory cell adjacent to the source line side with respect to the memory cell connected to the selected word line is 0 V, the source and drain potentials of the adjacent memory cell are capacitively coupled between the control gate and the channel of the memory cell. rising by , the adjacent memory cell becomes non-conductive.</p><p>Accordingly, the channel potential of the selected memory cell rises as the selected memory cell and the erased memory cell existing on the bit line side of the selected memory cell are integrated together. For this reason, the channel potential of the selected memory cell is always secured at, for example, about 6V or more. In other words, no electrons are injected into the floating gate, and data "0" can be written.</p><p>For example, when the selected word line is WL4, the potential of the unselected word lines WL1 to WL3 is set to about 10V. When the selected word line is WL3, the potential of the unselected word lines WL1 and 2 is set to about 10V, and the potential of the unselected word line WL4 is set to 0V.</p><p>However, when the selected word line is WL3, the memory cell connected to the unselected word line WL4 is non-conductive because there is no memory cell on the source line side of the memory cell connected to the unselected word line WL4. There are things you can't do. However, there is no problem because the number of memory cells on the bit line side is greater than that of the memory cells connected to the unselected word line WL4.</p><p>Further, when the selected word line is WL3, the potential of the unselected word line WL4 may be set to about 10V. When the selected word line is WL1, the potential of the unselected word lines WL3 and 4 is about 10V, and the potential of the unselected word line WL2 is about 0V.</p><p>It should be noted here that the unselected word line existing on the bit line side with respect to the selected word line should not be set to 0V. For example, when the word line WL2 is selected, the word line WL1 should not be set to 0V. This is because, when the word line WL1 is set to 0V, the memory cell connected to the word line WL1 becomes non-conductive.</p><p>Note that the potential of the bit line at the time of writing data "1", "2", and "3" does not need to be 0V. For example, when writing data "1", the potential of the bit line may be 1.2 V, and when writing data "2" and "3", the potential of the bit line may be set to 0 V.</p><p>This means that the amount of electrons to be injected into the floating gate of the memory cell M to store data "1" is higher than the amount of electrons to be injected into the floating gate of the memory cell M to store data "2" and "3". Because less is better.</p><p>In addition, the potentials of the bit lines when writing data "1", "2", and "3" may be different. For example, the potential of the bit line when writing data "1" is about 2.4 V, the potential of the bit line when writing data "2" is about 1.2 V, and the potential of the bit line when writing data "3". may be set to 0V.</p><p>In the case of the 4-value memory method, for example, the threshold value of the memory cell corresponding to data "0" is 0V or less, the threshold value of the memory cell corresponding to data "1" is 0.4V to 0.8V, and the threshold value of the memory cell corresponding to data "2" is 0.4V to 0.8V. The threshold value of the memory cell is set to 1.6V to 2.0V, and the threshold value of the memory cell corresponding to data "3" is set to 2.8V to 3.2V.</p><p>At the time of reading, the potential of the selected word line WL2 of the selected block is set to Vread. The potentials of the unselected word lines WL1, WL3, and WL4 of the selected block are set to, for example, about 4V. The potentials of the selection gates SG1 and SG2 of the selection block are also set to, for example, about 4V. The potentials of all word lines and all selection gates SG of the unselected block are 0V. The source line SRC is connected to the ground point through a parasitic resistor.</p><p>Also, if the potential of the source line does not rise due to the parasitic resistance,</p><p>(1) When the potential (Vread) of the selected word line is 0 V and the selected memory cell stores data "1", "2" or "3", the bit line is pre-charged to 1 V and becomes a floating state. After that, it is still 1V. When the selected memory cell stores the data "0", the bit line is precharged to 1V, and then goes down to 0.5V after entering the floating state.</p><p>(2) When the potential (Vread) of the selected word line is 1.2 V, if the selected memory cell stores data "2" or "3", the bit line is pre-charged to 1 V and 1 V even after entering the floating state stays When the selected memory cell stores data "0" or "1", the bit line is precharged to 1V and goes down by 0.5V after entering the floating state.</p><p>(3) When the potential (Vread) of the selected word line is 2.4 V and the selected memory cell stores data "3", the bit line is precharged to 1 V and remains at 1 V even after entering the floating state. When the selected memory cell stores data "0", "1" or "2", the bit line is precharged to 1V and then goes down to 0.5V after entering the floating state.</p><p>As described above, the data stored in the memory cell M is read using the three types of read potentials.</p><p>FIG. 5 shows a more specific configuration example of the memory cell array 1 and the data storage circuit 10 shown in FIG. Here, as an example, a configuration example of a 4-value storage flash memory is shown.</p><p>The first sub data circuit is constituted by the clock synchronous inverters CI1 and CI2 and the n-channel MOS transistors Qn4, Qn5, and Qn6. In addition, the second sub data circuit is constituted by the clock synchronous inverters CI3 and CI4 and the n-channel MOS transistors Qn10, Qn11, and Qn12.</p><p>The first and second sub data circuits store the first and second sub data at the time of writing, respectively. The first and second sub data circuits store the first and second read sub data at the time of reading, respectively.</p><p>The state in which the node Nai in the first sub data circuit is "H" level is a state in which the first sub data circuit stores the first read sub data of "1" or the first sub data of "1".</p><p>Also, when the node Nai+1 in the second sub data circuit is at the "H" level, the second sub data circuit stores the second read sub data of "1" or the second sub data of "1". is the state</p><p>The state in which the node Nai in the first sub data circuit is at the "L" level is a state in which the first sub data circuit stores the first read sub data of "0" or the first sub data of "0".</p><p>The state in which the node Nai+1 in the second sub data circuit is at the "L" level is a state in which the second sub data circuit stores the second read sub data of "0" or the second sub data of "0". am.</p><p>The n-channel MOS transistors Qn1 and Qn7 have a signal PRST of "H" to set sub data "0" in the first and second sub data circuits.</p><p>The n-channel MOS transistors Qn2 and Qn8 are for electrically connecting the first and second sub data circuits and the data input/output lines IOL and IOU, respectively. Outputs CSLi and CSLi+1 from the column decoder 3 are respectively applied to each gate electrode.</p><p>For example, when CSLi becomes "H", the first sub data circuit of the data storage circuit 10 provided on the bit lines BL1 and BLi+1 and the data input/output line IO are electrically connected. The data input/output lines IOL and IOU are connected to the data input/output buffer 4, so that sub data can be set in the first or second sub data circuit. Alternatively, the read sub data of the first or second sub data circuit may be output to the data input/output buffer 4 .</p><p>The n-channel MOS transistors Qn3 and Qn9 detect whether the sub data of the first sub data circuit and the second sub data circuit are both "0". Since there are 2112 data storage circuits 10 in this example, if both the 2112 first sub data and 2112 second sub data are "0", the common signal line PT and the ground line are detected as non-conductive.</p><p>Capacitor C1, together with n-channel MOS transistors Qn13 and Qn14, is for amplifying changes in the bit line potential, as will be described in detail later, when the signal PREC changes to the power supply potential (VCC ; for example, 3V). BIAS turns to 2V to charge the bit line.</p><p>When the threshold of the n-channel MOS transistor is set to 1V, the bit line is charged to close to 1V. Since it takes time to charge the bit line until the n-channel MOS transistor Qn14 becomes non-conductive, the signals PREC and BIAS are set to 0V after a predetermined time has elapsed.</p><p>When detecting the bit line potential, the signal BIAS is set to, for example, 1.8V. This potential of 1.8 V is set so that the n-channel MOS transistor Qn14 becomes non-conductive if there is no change in the bit line potential. If there is a change in the bit line potential and it is set to 0.8 V, the n-channel MOS transistor Qn14 conducts.</p><p>When it conducts, the potential of the node (Nsense) goes down. For example, if the bit line capacitance is 5 pF and the capacitor C1 is smaller than that, for example 0.5 pF, the change in the bit line potential greatly affects the change in the node Nsense. Therefore, the bit line potential can be amplified with good sensitivity.</p><p>For example, when the bit line goes from 1V to 0.7V, the node Nsense goes from 2V to about 0.73V. Even if the bit line changes from 1V to 0.9V, Nsense remains at 2V. Accordingly, the change in Nsense is about 1.27V for a change of 0.2V in the bit line.</p><p>The n-channel MOS transistors Qn15 and Qn17 control the electrical connection between the first and second sub data circuits and the bit line BLi or BLi+1. When the signal BLC1 is "H" and BLC2 is "L", the first and second sub data circuits and the bit line BLi are electrically connected.</p><p>When the signal BLC1 is "L" and BLC2 is "H", the first and second sub data circuits and the bit line BLi+1 are electrically connected. The n-channel MOS transistors Qn16 and Qn18 control the electrical connection between the bit line BLi and the potential VBL1 and the bit line BLi+1 and the potential VBL2.</p><p>When the signal PRE1 is "H", the bit line BLi and the potential VBL1 are electrically connected. When the signal PRE2 is "H", the bit line BLi+1 and the potential VBL2 are electrically connected.</p><p>A signal indicating the data or writing state of the memory cell M is transmitted through the bit line BLi or BLi+1. The clock synchronous inverter CI1 in the first sub data circuit and the clock synchronous inverter CI3 in the second sub data circuit also act as a sense amplifier for detecting the logic level of the bit line BL signal.</p><p>In this example, the clock synchronous inverter senses the absolute value of the potential of the bit line BL as a logic level, but a differential (differential) sensing amplifier or the like may be used. In that case, the difference from the reference (reference) potential is logically detected as a level.</p><p>A specific configuration of the clock synchronous inverter CI is shown in FIG. 6 .</p><p>The input terminal of the inverter circuit composed of the n-channel MOS transistor Qn19 and the p-channel MOS transistor Qp2 is IN and the output terminal OUT. An n-channel MOS transistor Qn20 and a p-channel MOS transistor Qp1 are provided to activate or deactivate this inverter circuit by the signal CLOCK and its inverted signal CLOCKB. Signal CLOCK is activated with "H" and CLOCKB is "L", and signal CLOCK is deactivated with "L" and CLOCKB is "H".</p><p>Signals SEN1, LAT1, SEN2, LAT2, PRO1, PRO2, BLC1, BLC2, PRE1, PRE2, VRFY1, VRFY2, PRST, potentials VBL1, VBL2, VREG, BIAS, PREC, PT are control signals and control potential generating circuit (7) is an output signal of , which is common to all of the data storage circuits 10 as seen in FIG. The potential VCC is a power supply potential and is, for example, 3V.</p><p>The first and second sub data circuits store sub data of "0" or "1", and respectively store the sub data of "1" stored in response to the "H" level of the bit line signal to the sub data of "0". It is changed to data, and it is configured to maintain sub data of "0".</p><p>According to the specific configuration of the present embodiment , it can be implemented similarly using various various circuits having the above functions . In the sub data circuit of this embodiment, before the signal PRO1 or PRO2 becomes "H" and the potential level of the bit line BL is sensed by the clock synchronous inverter CI1 or CI3, the bit line according to the first or second sub data The potential level of (BL) is adjusted by the N-channel MOS transistors Qn5, Qn6 or Qn11, Qn12.</p><p>Only when the first or second sub data is "0", the potential level of the bit line BL becomes "H". When the signal PRO1 or PRO2 becomes "H" and the "H" level of the bit line at this time is transmitted to the input terminal of the clock synchronous inverter (CI1 or CI3), the node Nai or Nai1 becomes "L" level.</p><p>In addition, sub data "0" is stored by the clock synchronous inverter (CI2 or CI4). Therefore, the sub data of "0" stored from the beginning is not changed. When the sub data stored from the beginning is "1", when the level of the bit line BL is "H", the sub data is changed to "0" and stored, and the level of the bit line BL is "L". When , the sub data of "1" is maintained.</p><p>7, 8, and 9 show the operation of reading the 4-value data stored in the memory cell.</p><p>Here, the bit lines BL0, BL2, ... , BLi, , BL4222 is selected (representing BLi as a representative) and the word line WL2 is selected as an example of the 4-value storage method.</p><p>If the memory level is limited to three levels, three-value memory can be easily performed. Here, the potentials VBL1 and VBL2 are 0V, BLC2 is "L", PRE2 is "H", PRST is "L", the bit line BLi+1 is 0V, CSLi and CSLi+1 are 0V, and the potential VREG is Since it remains 0V, the display in FIG. 7, FIG. 8, and FIG. 9 is abbreviate|omitted.</p><p>First, the signal PRE1 becomes "L" and BLC1 becomes "H", and the bit line BLi is selected. The signal PREC turns to VCC and the signal BIAS turns to 2V, and the bit line BLi is charged to 1V (t2). The threshold of the n-channel MOS transistor Qn is 1V unless otherwise specified.</p><p>The signal BIAS turns to 0V, and the charging of the bit line BLi is finished (t3). Next, the signal PREC turns to 0V, and the charging of the node Nsense ends (t4). The selection gates SG1, SG2 and unselected word lines WL1, WL3, and WL4 of the selected block turn to 4V, and the selected word line WL2 turns to 2.4V (t4).</p><p>Table 1 shows the relationship between the data stored in the memory cell M and the threshold value.</p><p><tables id="1"><table id="1" cols="2"><row><entry he="130" wi="3500" rb="1" re="1" cb="1" ce="1" al="l">data in memory cells</entry><entry he="130" wi="3500" rb="1" re="1" cb="2" ce="2" al="l">memory cell threshold</entry><row><entry he="528" wi="3500" rb="2" re="2" cb="1" ce="1" al="c">0 1 2 3 </entry><entry he="528" wi="3500" rb="2" re="2" cb="2" ce="2" al="c">0V or less 0.4V to 0.8V 1.6V to 2.0V 2.8V to 3.2V </entry></row></row></table></tables></p><p>When the selected word line WL2 becomes 2.4V, the bit line BLi remains at 1V only when the memory cell stores data "3". In other cases, the bit line BLi is 0.7V or less. After a certain period (t4 to t5) has elapsed, the signal BIAS is set to 1.8V. Only when the memory cell stores "3" data, the node (Nsense) remains at 2V.</p><p>In other cases, Nsense is 0.8V or less. After the signal BIAS becomes 0V again and the bit line BLi and Nsense are separated, the signals SEN2 and LAT2 become "L", and the clock synchronous inverters CI3 and CI4 are deactivated (t6).</p><p>When the signal PRO2 turns to "H" (t7) and the signal SEN2 turns to "H" (t8), the clock synchronous inverter CI3 is activated, and the potential of the node Nsense is sensed. When the signal LAT2 becomes "H" (t9), the clock synchronous inverter CI4 is activated, and the logic level of the sensed signal is latched.</p><p>The select gates SG1 and SG2 and the word lines WL1 to WL4 are reset to 0V at time t5. Signal BLC1 becomes "L" at time t6, signal PRE1 becomes "H" at time t7, and the bit line BLi is reset to 0V at time t7.</p><p>The signal PRO2 becomes "L" (t10), and the operation of detecting whether the threshold of the memory cell M is 2.4 V or more ends. Only when the memory cell stores data "3", the second read sub data of the second sub data circuit becomes "0". In other cases, the second read sub data is "1".</p><p>Then, an operation of detecting whether or not the threshold of the memory cell M is equal to or greater than 0.0V is entered. First, the signal PRE1 becomes "L" and BLC1 becomes "H", and the bit line BLi is selected.</p><p>The signal PREC turns to VCC and the signal BIAS turns to 2V, and the bit line BLi is charged to 1V (t13). The signal BIAS turns to 0V, and the charging of the bit line BLi is finished (t14).</p><p>Next, the signal PREC turns to 0V, and the charging of the node Nsense ends (t15). The select gates SG1, SG2 and unselected word lines WL1, WL3, and WL4 of the selected block are set to 4V, and the selected word line WL2 remains at 0.0V (t15).</p><p>When the selected word line WL2 is 0.0 V, the bit line BLi remains at 1 V when the memory cell stores "1", "2" or "3" data. When the memory cell stores "0" data, the bit line BLi becomes 0.7V or less.</p><p>After a certain period (t15 to t16) has elapsed, the signal BIAS is set to 1.8V. When the memory cell stores "1", "2" or "3" data, the node Nsense remains at 2V. When the memory cell stores "0" data, the Nsense is 0.8V or less.</p><p>Again, after the signal BIAS turns to 0V and the bit lines BLi and Nsense are separated, the signals SEN1 and LAT1 turn to "L", and the clock synchronous inverters CI1 and CI2 are deactivated (t17).</p><p>At the same time, only when the signal VRFY2 becomes VCC and the second read sub data of the second sub data circuit is "0", the node Nsense becomes 0 V (t17). When the signal PRO1 turns to "H" (t18) and the signal SEN1 turns to "H" (t19), the clock synchronous inverter CI1 is activated, and the potential of the node Nsense is sensed. When the signal LAT1 becomes "H" (t20), the clock synchronous inverter CI2 is activated, and the logic level of the sensed signal is latched.</p><p>The select gates SG1 and SG2 and the word lines WL1 to WL4 are reset to 0V at time t16. The signal BLC1 becomes "L" at time t17, the signal PRE1 becomes "H" at time t18, and the bit line BLi is reset to 0V at time t18.</p><p>The signal PRO1 turns to "L" (t21), and the operation of detecting whether or not the threshold of the memory cell M is 0.0 V or more ends. The first read sub data of the first sub data circuit becomes "1" only when the memory cell stores "0" or "3" data. In other cases, the first read sub data is "0".</p><p>Then, an operation of detecting whether or not the threshold of the memory cell M is 1.2V or more is entered. First, the signal PRE1 becomes "L" and BLC1 becomes "H", and the bit line BLi is selected.</p><p>The signal PREC turns to VCC and the signal BIAS turns to 2V, and the bit line BLi is charged to 1V (t24). The signal BIAS turns to 0V, and the charging of the bit line BLi is finished (t25).</p><p>Next, the signal PREC turns to 0V, and the charging of the node Nsense ends (t26). The selection gates SG1 and SG2 and the unselected word lines WL1, WL3, and WL4 of the selected block are set to 4V, and the selected word line WL2 is set to 1.2V (t26).</p><p>When the selected word line WL2 becomes 1.2V, the bit line BLi remains at 1V when the memory cell stores "2" or "3" data. When the memory cell stores "0" or "1" data, the bit line BLi becomes 0.7V or less.</p><p>After a certain period (t26 to t27) has elapsed, the signal BIAS is set to 1.8V. When the memory cell stores "2" or "3" data, the node (Nsense) remains at 2V. When the memory cell stores "0" or "1" data, the Nsense is 0.8V or less.</p><p>Again, after the signal BIAS turns to 0V and the bit line BLi and Nsense are disconnected, the signals SEN2 and LAT2 turn to "L", and the clock synchronous inverters CI3 and CI4 are deactivated (t28).</p><p>When the signal PRO2 turns to "H" (t29) and the signal SEN2 turns to "H" (t30), the clock synchronous inverter CI3 is activated, and the potential of the node Nsense is sensed. When the signal LAT2 becomes "H" (t31), the clock synchronous inverter CI4 is activated, and the logic level of the sensed signal is latched.</p><p>The select gates SG1 and SG2 and the word lines WL1 to WL4 are reset to 0V at time t27. The signal BLC1 goes to "L" at the time t28, the signal PRE1 goes to "H" at the time t29, and the bit line BLi is reset to 0V at the time t29.</p><p>The signal PRO2 becomes "L" (t32), and the operation of detecting whether or not the threshold of the memory cell M is 1.2V or more ends. Only when the memory cell stores "0" or "1" data, the second read sub data of the second sub data circuit becomes "1". In other cases, the second read sub data is "0".</p><p>As described above, the operation in which the data of the memory cell M is stored as read data by the data storage circuit 10 in the procedure shown in Figs. 7 to 9 is completed.</p><p>After that, when the signals CSLi and CSLi+1 become "H", the first read sub data is output to the data input/output line IOL and the second read sub data is output to the data input/output line IOU, and the data output buffer 4 ) is outputted from the data input/output terminal 5 to the outside.</p><p>Table 2 shows the relationship between the quaternary data of the memory cell and the first and second read sub data.</p><p><tables id="2"><table id="2" cols="3"><row><entry he="130" wi="2735" rb="1" re="1" cb="1" ce="1" al="c">memory cell data</entry><entry he="130" wi="3233" rb="1" re="1" cb="2" ce="2" al="c">first read sub data</entry><entry he="130" wi="3233" rb="1" re="1" cb="3" ce="3" al="c">second read sub data</entry><row><entry he="127" wi="2735" rb="2" re="2" cb="1" ce="1" al="c">0</entry><entry he="127" wi="3233" rb="2" re="2" cb="2" ce="2" al="c">1</entry><entry he="127" wi="3233" rb="2" re="2" cb="3" ce="3" al="c">1</entry><row><entry he="127" wi="2735" rb="3" re="3" cb="1" ce="1" al="c">1</entry><entry he="127" wi="3233" rb="3" re="3" cb="2" ce="2" al="c">0</entry><entry he="127" wi="3233" rb="3" re="3" cb="3" ce="3" al="c">1</entry><row><entry he="127" wi="2735" rb="4" re="4" cb="1" ce="1" al="c">2</entry><entry he="127" wi="3233" rb="4" re="4" cb="2" ce="2" al="c">0</entry><entry he="127" wi="3233" rb="4" re="4" cb="3" ce="3" al="c">0</entry><row><entry he="130" wi="2735" rb="5" re="5" cb="1" ce="1" al="c">3</entry><entry he="130" wi="3233" rb="5" re="5" cb="2" ce="2" al="c">1</entry><entry he="130" wi="3233" rb="5" re="5" cb="3" ce="3" al="c">0</entry></row></row></row></row></row></table></tables></p><p>10 shows a write operation. Here, the bit lines BL0, BL2, ... , BLi, , BL4222 is selected (BLi is represented as representative), and the word line WL2 is selected. Here, it is an example of 4-value memory. If the memory level is limited to three levels, three-value memory can be easily performed.</p><p>Prior to writing, initial setting of control data into the data storage circuit 10 is performed. The initial setting of the control data to the data storage circuit 10 provided in the bit line BLi is performed as follows.</p><p>The initial sub data of the first sub data circuit is transferred to the data input/output line IOL, the initial sub data of the second sub data circuit is transferred to the data input/output line IOU, and the signals CSLi and CSLi+1 become "H". Initial sub data is stored in the first and second sub data circuits.</p><p>Initial control data is set in an arbitrary number of data storage circuits 10 by changing the selection of the signal CSL. At this time, the relationship between the initial control data and the initial sub data is shown in Table 3 below.</p><p><tables id="3"><table id="3" cols="3"><row><entry he="263" wi="2735" rb="1" re="1" cb="1" ce="1" al="c">initial control data</entry><entry he="263" wi="3375" rb="1" re="1" cb="2" ce="2" al="c">Initial sub data of the first sub data circuit </entry><entry he="263" wi="3445" rb="1" re="1" cb="3" ce="3" al="c">Initial sub data of the second sub data circuit </entry><row><entry he="127" wi="2735" rb="2" re="2" cb="1" ce="1" al="c">0</entry><entry he="127" wi="3375" rb="2" re="2" cb="2" ce="2" al="c">0</entry><entry he="127" wi="3445" rb="2" re="2" cb="3" ce="3" al="c">0</entry><row><entry he="127" wi="2735" rb="3" re="3" cb="1" ce="1" al="c">1</entry><entry he="127" wi="3375" rb="3" re="3" cb="2" ce="2" al="c">1</entry><entry he="127" wi="3445" rb="3" re="3" cb="3" ce="3" al="c">0</entry><row><entry he="127" wi="2735" rb="4" re="4" cb="1" ce="1" al="c">2</entry><entry he="127" wi="3375" rb="4" re="4" cb="2" ce="2" al="c">1</entry><entry he="127" wi="3445" rb="4" re="4" cb="3" ce="3" al="c">1</entry><row><entry he="130" wi="2735" rb="5" re="5" cb="1" ce="1" al="c">3</entry><entry he="130" wi="3375" rb="5" re="5" cb="2" ce="2" al="c">0</entry><entry he="130" wi="3445" rb="5" re="5" cb="3" ce="3" al="c">1</entry></row></row></row></row></row></table></tables></p><p>Here, it is preferable to set the signal PRST to "H" and to preset the control data of all data storage circuits 10 to "0" before setting all the initial control data. As will be explained later, since the state of the memory cell M is not changed by the control data "0", the initial control data is set from the outside only in the desired memory circuit 10 in the 2112 data storage circuits 10. Do it.</p><p>Of course, the initial control data may be externally set in all of the 2112 data storage circuits 10 . Signal SEN1 is "H", LAT1 is "H", VRFY1 is "L", SEN2 is "H", LAT2 is "H", VRFY2 is "L", potential VREG is 0V and PREC remains 0V. 10 is omitted.</p><p>In the write operation, first, the signal PRE1 becomes "L", and the bit line BLi and the potential BL1 are separated (t2). At the same time, the signal BLC1 turns to 6V, and the bit line BLi is selected (t2).</p><p>Further, the signals BIAS and PRE2 also become 6V (t2). The potential VBL2 becomes VCC (3 V here), and the unselected bit line BLi+1 is charged to VCC via the n-channel MOS transistor Qn18 (t3 to t4).</p><p>Further, the signal PRO1 becomes 3V, and the selection bit line BLi is charged in accordance with the first sub data (t3 to t4). At this time, the bit line BLi is charged to VCC when the control data is "0" or "3", and becomes 0V when the control data is "1" or "2".</p><p>Further, when the selection gate SG1 and the word line WL4 become 6V (t3 to t4), the selection gate SG1 turns to VCC when the potential VCC of the bit line is transferred (t4). The word line WL3 remains at 0V. The word lines WL1 and W12 become VCC. The select gate SG2 remains at 0V.</p><p>Thereafter, the signal PRO2 becomes 2.2 V, and the potential of the selected bit line BLi is changed according to the second sub data (t5). When the second sub data is "0", the bit line BLi, which was previously 0V, is charged to 1.2V, which is lower than 2.2V by the threshold value (1V) of the n-channel MOS transistor Qn10.</p><p>When the second sub data is "0", the bit line BLi, which was previously VCC, remains at VCC because the n-channel MOS transistor Qn10 is non-conductive. When the second sub data is "1", the bit line BLi is 0V because the n-channel MOS transistor Qn10 is conductive.</p><p>As a result, the bit line BLi turns to VCC when the control data is "0", 1.2V when the control gate is "1", 0V when the control data is "2", and the control data is "3". In this case, it becomes 0V.</p><p>The selected word line WL2 becomes 1.6 V, and WL1 and WL4 of the unselected word lines become 10 V, and electron injection into the floating gate of the memory cell starts according to the control data (t6 to t7).</p><p>When the bit line BL is 0V, the potential difference between the channel of the memory cell and the word line is 16V, and electron injection occurs. When the bit line BL is 1.2 V, electron injection occurs with a potential difference of 14.8 V between the channel and the word line of the memory cell, but is smaller than the case where the potential difference between the channel and the word line of the memory cell is 16 V.</p><p>When the bit line BL is VCC, the word line WL1 becomes 10V and WL2 becomes 16V, so that the channel of the selected memory cell rises above VCC (for example, 6V), and between the channel of the memory cell and the word line Since the potential difference is small, electron injection practically does not occur.</p><p>After the signal PRO2 is reset to 0 V (t7), the word lines WL1 to WL4 are 0 V, the potential VBL2 is 0 V, the signal PRE1 is "H", the signal PRE2 is "H", the signal BLC1 is "L", the signal BIAS is "" L" (t8), and the write operation is terminated.</p><p>As shown in Fig. 11, the potential of the selected word line WL2 between times t3 to t6 is not VCC, but may be set to the same 6V as that of the unselected word line WL4. This is because a channel is formed even when the threshold of the selected memory cell is high. This is because the bit line potential can be reliably transferred from the selected memory cell to the memory cell on the common source side.</p><p>Fig. 12 is a modification of the write operation shown in Fig. 10; Here, the timing at which the word line WL4 that is not adjacent to the common source side of the selected word line WL2 becomes 10 V is set to t5. This is because the memory cells located on the adjacent common source side of the selected memory cells are reliably made non-conductive.</p><p>FIG. 13 is a modification of the write operation shown in FIG. 11 . Here, the timing at which the word line WL4 which is not adjacent to the common source side of the selected word line WL2 becomes 10V is set to t5. This is because, as in the case of Fig. 12, the memory cells located on the adjacent common source side of the selected memory cells are reliably made non-conductive.</p><p>14, 15, and 16 show a write verification operation for detecting the write state of the memory cell after the write operation shown in FIG. 10, 11, 12 or 13 .</p><p>Here, the case where the bit lines BL0, BL2, ..., BL4222 are selected (BLi is indicated as a representative) and the word line WL2 are selected is shown. Here, it is an example of 4-value memory. If the memory level is limited to three levels, three-value memory can be easily performed.</p><p>Further, since the potentials VBL1 and VBL2 remain at 0 V, the signal BLC2 at "L", PRE2 at "H", and the bit line BLi+1 at 0 V, the display in Figs. 14 to 16 is omitted. are doing In addition, since the signal PRST remains "L", CSLi is "L", and CSLi+1 remains "L", the display in Figs. 14 to 16 is omitted.</p><p>First, the signal PRE1 becomes "L" and BLC1 becomes "H", and the bit line BLi is selected. The signal PREC turns to VCC and the signal BIAS turns to 2V, and the bit line BLi is charged to 1V (t2). The signal BIAS turns to 0V, and the charging of the bit line BLi is finished (t3).</p><p>Then, the signal PREC turns to 0V, and the charging of the node Nsense ends (t4). The selection gates SG1, SG2 and unselected word lines W11, W13, and WL4 of the selected block turn to 4V, and the selected word line WL2 turns to 2.8V (t4).</p><p>When the selected word line WL2 becomes 2.8 V, the bit line BLi becomes 1 V when the memory cell corresponding to the data storage circuit storing the "3" control data reaches a state of storing the "3" data. there is</p><p>If the memory cell corresponding to the data storage circuit storing the "3" control data does not reach the state storing the "3" data, the bit line BLi becomes 0.7V or less.</p><p>Since the memory cell corresponding to the data storage circuit storing the "2" or "1" control data does not reach the state storing the "3" data, the bit line BLi becomes 0.7V or less.</p><p>After a certain period of time (t4 to t5) has elapsed, the signal BIAS is set to 1.8V. When the memory cell corresponding to the data storage circuit storing the control data "3" reaches the state storing the data "3", the node Nsense remains at 2V. If the memory cell does not store the "3" data, the Nsense becomes 0.8V or less.</p><p>Again, after the signal BIAS becomes 0V and the bit line BLI and Nsense are separated, the signal VRFY2 becomes VCC (t6). Only when the second sub data of the second sub data circuit is "0", the Nsense becomes 2V by the n-channel MOS transistors Qn11 and Qn12. At this time, the potential VREG is VCC (t5 to t6).</p><p>Signals SEN2 and LAT2 become "L", and clock synchronous inverters CI3 and CI4 are deactivated (t8). When the signal PRO2 turns to "H" (t9) and the signal SEN2 turns to "H" (t10), the clock synchronous inverter CI3 is activated, and the potential of the node Nsense is sensed.</p><p>When the signal LAT2 becomes "H" (t11), the clock synchronous inverter CI4 is activated, and the logic level of the sensed signal is latched.</p><p>The select gates SG1 and SG2 and the word lines WL1 to WL4 are reset to 0V at time t5. Signal BLC1 goes to "L" at time t6, signal PRE1 goes to "H" at time t7, and bit line BLi is reset to 0V at time t7.</p><p>When the signal PRO2 becomes "L" (t12), it is detected whether the memory cell corresponding to the data storage circuit 10 storing the control data "3" has reached the state of storing the "3" data. (verification read with data "3") ends.</p><p>At this point, only when it is detected that the memory cell corresponding to the data storage circuit storing the "3" control data has reached the state of storing the "3" data, only when the "3" control data is stored. The control data of the data storage circuit is changed to "0" data, otherwise the control data is maintained (not changed).</p><p>Next, an operation of detecting whether or not the memory cell corresponding to the data storage circuit storing the control data of "2" has reached the state of storing the "2" data begins.</p><p>First, the signal PRE1 becomes "L" and BLC1 becomes "H", and the bit line BLi is selected. The signal PREC turns to VCC and the signal BIAS turns to 2V, so that the bit line BLi is charged to 1V (t15). The signal BIAS turns to 0V, and the charging of the bit line BLi is finished (t16).</p><p>Next, the signal PREC turns to 0V, and the charging of the node Nsense ends (t17). The selection gates SG1 and SG2 and the unselected word lines WL1, WL3, and WL4 of the selected block are set to 4V, and the selected word line WL2 is set to 1.6V (t17).</p><p>When the selected word line WL2 becomes 1.6 V, if the memory cell corresponding to the data storage circuit storing the "2" control data has reached the state storing the "2" data, the bit line BLi becomes 1 V stays If the memory cell corresponding to the data storage circuit storing the "2" control data has not reached the state storing the "2" data, the bit line BLi becomes 0.7V or less.</p><p>Since the memory cell corresponding to the data storage circuit storing the "1" control data has not reached the state of storing the "2" data, the bit line BLi becomes 0.7V or less. After a certain period (t7 to t18) has elapsed, the signal BIAS is set to 1.8V. When the memory cell corresponding to the data storage circuit storing the "2" control data reaches the state storing the "2" data, the node Nsense remains at 2V.</p><p>If the memory cell corresponding to the data storage circuit storing the "2" control gate has not reached the state storing the "2" data, the node Nsense becomes 0.8V or less. Since the memory cell corresponding to the "1" control data is stored and the data storage circuit does not reach the state in which the "2" data is stored, the node Nsense is 0.8V or less.</p><p>Again, after the signal BIAS becomes 0V and the bit line BLi and Nsense are separated, the signal VRFY1 becomes VCC (t19). At this time, since the potential VREG is 0V, when the first sub data is "0", the node Nsense is set to 0V by the n-channel MOS transistors Qn5 and Qn6.</p><p>After this, the signal VRFY2 becomes VCC (t21). Only when the second sub data of the second sub data circuit is "0", the Nsense becomes 2V by the n-channel MOS transistors Qn11 and Qn12. At this time, the potential VREG is VCC (t21 to t23).</p><p>Signals SEN2 and LAT2 become "L", and the clock synchronous inverters CI3 and CI4 are deactivated (t23). When the signal PRO2 becomes "H" (t24) and the signal SEN2 becomes "H" (t25), the clock synchronous inverter CI3 is activated, and the potential of the node Nsense is sensed. When the signal LAT2 becomes "H" (t26), the clock synchronous inverter CI4 is activated, and the logic level of the sensed signal is latched.</p><p>The select gates SG1 and SG2 and the word lines W11 to W14 are reset to 0V at time t18. The signal BLC1 becomes "L" at the time t19, the signal PRE1 becomes "H" at the time t20, and the bit line BLi) is reset to 0V at the time t20.</p><p>When the signal PRO2 becomes "L" (t27), it is detected whether the memory cell corresponding to the data storage circuit storing the control data "2" has reached the state storing the data "2" (data "2"). Verification read of ") ends. At this point, if it is detected that the memory cell corresponding to the data storage circuit storing the control data of "3" has reached the state of storing the data "3", the control data of the data storage circuit 10 is " It is changed to 0" data.</p><p>Only when it is detected that the memory cell corresponding to the data storage circuit storing the "2" control data has reached the state storing the "2" data, the control data of the data storage circuit 10 is the "1" data has been changed to In other cases, the control data is maintained (not changed).</p><p>Next, an operation of detecting whether or not the memory cell corresponding to the data storage circuit storing the control data of "1" has reached the state of storing the "1" data begins.</p><p>First, the signal PRE1 becomes "L" and BLC1 becomes "H", and the bit line BLi is selected. The signal PREC turns to VCC and the signal BIAS turns to 2V, and the bit line BLi is charged to 1V (t30). The signal BIAS turns to 0V, and the charging of the bit line BLi is finished (t31).</p><p>Next, the signal PREC turns to 0V, and the charging of the node Nsense ends (t32). The selection gates SG1, SG2 and unselected word lines WL1, WL3, and WL4 of the selected block are set to 4V, and the selected word line WL2 is set to 0.4V (t32).</p><p>When the selected word line WL2 becomes 0.4V, the bit line BLi remains at 1V if the memory cell corresponding to the data storage circuit storing the "1" control data is in the state storing the "1" data. . If the memory cell corresponding to the data storage circuit storing the "1" control data has not reached the state storing the "1" data, the bit line BLi becomes 0.7V or less.</p><p>After a certain period (t7 to t18) has elapsed, the signal BIAS is set to 1.8V. If the memory cell corresponding to the data storage circuit storing the "1" control data has reached the state storing the "1" data, the node Nsense remains at 2V.</p><p>If the memory cell corresponding to the data storage circuit storing the "1" control data has not reached the state storing the "1" data, the node Nsense is 0.8V or less. Again, the signal BIAS turns to 0V, and after the bit lines BLi and Nsense are separated, the signal PRO2 turns to 1.3V (t34).</p><p>At this time, when the second sub data is "1", the node Nsense is set to 0V by the n-channel MOS transistor Qn10. At this time, when the second sub data is "0", the node Nsense is only 0.3V by the n-channel MOS transistor Qn10.</p><p>Originally, when Nsense is 0.3V or more, since Qn10 is non-conductive, the potential of Nsense does not change. Thereafter, the signal VRFY1 becomes VCC (t36). Only when the first sub data of the first sub data circuit is "0", Nsense becomes 2V by the n-channel MOS transistors Qn5 and Qn6. At this time, the potential VREG is VCC (t36 to t38).</p><p>Signals SEN1 and LAT1 become "L", and the clock synchronous inverters CI1 and CI2 are deactivated (t38). When the signal PRO1 becomes "H" (t39) and the signal SEN1 becomes "H" (t40), the clock synchronous inverter CI1 is activated, and the potential of the node Nsense is sensed.</p><p>When the signal LAT1 becomes "H" (t41), the clock synchronous inverter CI2 is activated, and the logic level of the sensed signal is latched.</p><p>The selection gates SG1 and SG2 and the word lines WL1 to WL4 are reset to 0V at time t33. The signal BLC1 becomes "L" at the time t34, the signal PRE1 becomes "H" at the time t35, and the bit line BLi is reset to 0V at the time t35.</p><p>When the signal PRO1 becomes "L" (t42), an operation of detecting whether or not the memory cell corresponding to the data storage circuit storing the control data of "1" has reached the state of storing the data of "1" ( Verification read of data "1") is finished.</p><p>At this point, it is detected that the memory cell corresponding to the data storage circuit storing the control data "3" has reached the state storing the data "3", and the data storing the control data "2" When it is detected that the memory cell corresponding to the memory circuit has reached the state storing "2" data, and when it is detected that the memory cell corresponding to the data storage circuit storing the control data "1" stores data "1" Only when it is detected that the current state is reached, the control data of the data storage circuit is changed to "0" data; otherwise, the control data is maintained (not changed).</p><p>The write verification operation is performed in the order shown in Figs. 14, 15, and 16. Figs.</p><p>In the write verification operation, the control data stored in the data storage circuit 10 in the write state of the memory cell is changed as shown in Table 4.</p><p><tables id="4"><table id="4" cols="3"><row><entry he="263" wi="2594" rb="1" re="1" cb="1" ce="1" al="c">memory cell write state</entry><entry he="263" wi="2594" rb="1" re="1" cb="2" ce="2" al="c">Control data before write verification</entry><entry he="263" wi="2594" rb="1" re="1" cb="3" ce="3" al="c">Control data after write verification</entry><row><entry he="127" wi="2594" rb="2" re="2" cb="1" ce="1" al="c">0, 1, 2 or 3</entry><entry he="127" wi="2594" rb="2" re="2" cb="2" ce="2" al="c">0</entry><entry he="127" wi="2594" rb="2" re="2" cb="3" ce="3" al="c">0</entry><row><entry he="127" wi="2594" rb="3" re="3" cb="1" ce="1" al="c">less than 1</entry><entry he="127" wi="2594" rb="3" re="3" cb="2" ce="2" al="c">1</entry><entry he="127" wi="2594" rb="3" re="3" cb="3" ce="3" al="c">1</entry><row><entry he="127" wi="2594" rb="4" re="4" cb="1" ce="1" al="c">1</entry><entry he="127" wi="2594" rb="4" re="4" cb="2" ce="2" al="c">1</entry><entry he="127" wi="2594" rb="4" re="4" cb="3" ce="3" al="c">0</entry><row><entry he="127" wi="2594" rb="5" re="5" cb="1" ce="1" al="c">less than 2</entry><entry he="127" wi="2594" rb="5" re="5" cb="2" ce="2" al="c">2</entry><entry he="127" wi="2594" rb="5" re="5" cb="3" ce="3" al="c">2</entry><row><entry he="127" wi="2594" rb="6" re="6" cb="1" ce="1" al="c">2</entry><entry he="127" wi="2594" rb="6" re="6" cb="2" ce="2" al="c">2</entry><entry he="127" wi="2594" rb="6" re="6" cb="3" ce="3" al="c">0</entry><row><entry he="127" wi="2594" rb="7" re="7" cb="1" ce="1" al="c">less than 3</entry><entry he="127" wi="2594" rb="7" re="7" cb="2" ce="2" al="c">3</entry><entry he="127" wi="2594" rb="7" re="7" cb="3" ce="3" al="c">3</entry><row><entry he="130" wi="2594" rb="8" re="8" cb="1" ce="1" al="c">3</entry><entry he="130" wi="2594" rb="8" re="8" cb="2" ce="2" al="c">3</entry><entry he="130" wi="2594" rb="8" re="8" cb="3" ce="3" al="c">0</entry></row></row></row></row></row></row></row></row></table></tables></p><p>The write operation shown in Figs. 10, 11, 12 or 13 and the write verify operation shown in Figs. 14 to 16 are repeated until all control data becomes "0", and the data into the memory cell M is Writing (program) is performed. Whether or not all the control data has become "0" can be known by detecting whether the signal PT is conducting with the ground level.</p><p>That is, the semiconductor memory device in the present invention has a memory cell M, a bit line BL connected to the memory cell M, a gate electrode, a source electrode, and a drain electrode, and the source electrode is connected to the bit line. A MOS transistor Qn14 to be used and a switch element Qn13 connected to a drain electrode are provided, and the bit line BL is charged by applying a first potential to the gate electrode by conducting the switch element Qn13, and thereafter The gate electrode is at a second potential different from the first potential to amplify the potential of the bit line BL, which varies according to the data of the memory cell M.</p><p>Further, preferred embodiments of the present invention include the following.</p><p>The switch element Qn13 becomes non-conductive while the second potential is applied to the gate electrode of the MOS transistor Qn14. The MOS transistor Qn14 is an n-channel MOS transistor, and the first potential is higher than the second potential. The correction capacitance of the bit line BL is greater than the capacitance connected to the drain electrode.</p><p>Further, the semiconductor memory device in the present invention is a NAND type memory cell unit in which a predetermined number of memory cells M having a MOS transistor structure are connected in series between first and second selection transistors S having a MOS transistor structure. In the following, the first electrode is applied to the gate electrode of the selected memory cell M, and a second potential is applied to the gate electrode of the memory cell M adjacent to the selected memory cell on the second selection transistor side, and the remaining memory Writing is performed by applying a third potential to the gate electrode of the cell M, wherein the first potential is set higher than the third potential, and the third potential is set higher than the second potential.</p><p>Further, preferred embodiments of the present invention include the following.</p><p>The first selection transistor S is connected to the bit line BL, and the second selection transistor S is connected to the source line SRC. Writing is sequentially performed from the memory cell side adjacent to the second selection transistor S to the memory cell side adjacent to the first selection transistor S.</p><p>A fourth potential is applied to the gate electrode of the memory cell M on the side of the second selection transistor S rather than the selected memory cell M among the remaining memory cells M, and the selected memory cell M among the remaining memory cells M is applied. A fifth potential is applied to the gate electrode of the memory cell M on the side of the first selection transistor S rather than M) to charge the channel of the memory cell M in advance, and then writing is performed.</p><p>A fourth potential is applied to the gate electrode of the memory cell M on the side of the second selection transistor S rather than the selected memory cell M among the remaining memory cells M, and the selected memory cell among the remaining memory cells M is applied. A fifth potential is applied to the gate electrode of the memory cell M on the side of the first selection transistor S than (M), and a fourth potential is applied to the gate electrode of the selected memory cell M, so that the memory cell M Write is performed after filling the channel of in advance.</p><p>A fourth potential is applied to the gate electrode of the memory cell M on the side of the second selection transistor S rather than the selected memory cell M among the remaining memory cells M, and the selected memory cell (M) among the remaining memory cells M A fifth potential is applied to the gate electrode of the memory cell on the side of the first selection transistor S rather than M), and the fifth electrode is applied to the gate electrode of the selected memory cell M to pre-select the channel of the memory cell M. After charging to , writing is performed.</p><p>The memory cell M has an n-channel MOS transistor structure. The fourth and fifth potentials are lower than the third potential, and the fourth potential is higher than the fifth potential.</p><p>Among the remaining memory cells M, after a third potential is applied to the gate electrode of the memory cell M on the side of the second selection transistor S rather than the selected memory cell M, the selected memory cell among the remaining memory cells M A third potential is applied to the gate electrode of the memory cell M on the side of the first selection transistor S rather than (M).</p><p>Among the remaining memory cells M, a third potential is applied to the gate electrode of the memory cell M on the side of the second selection transistor S rather than the selected memory cell M, and then a selected memory among the remaining memory cells M A third potential is applied to the gate electrode of the memory cell M on the side of the first selection transistor S rather than the cell M, and a first potential is applied to the gate electrode of the selected memory cell M.</p><p>As described above, the semiconductor memory device according to the present invention generates the channel potential of the memory cell at the time of writing "0" data without depending on the threshold value of the memory cell into which data is written. Thereby, it is possible to realize a semiconductor memory device capable of generating a sufficiently stable channel potential of the memory cell at the time of writing "0" data.</p><p>Further, in the semiconductor memory device according to the present invention, after the bit line is charged with the MOS transistor, the gate potential of the MOS transistor is changed. Thereby, the MOS transistor can be made non-conductive in a short time after the bit line is charged. Accordingly, it is possible to realize a semiconductor memory device capable of detecting the write state of a memory cell with high accuracy and high speed.</p><p>In addition, this invention is not limited to embodiment mentioned above. In addition, it can carry out with various deformation|transformation in the range which does not deviate from the summary of this invention.</p>

<p>The semiconductor memory device according to the present invention generates the channel potential of the memory cell when "0" data is written without depending on the threshold value of the memory cell into which data is written. Thereby, it is possible to realize a semiconductor memory device capable of sufficiently stably generating the channel potential of the memory cell at the time of writing "0" data.</p><p>Further, the semiconductor memory device according to the present invention changes the gate potential of the MOS transistor after the bit line is charged with the MOS transistor. Thereby, the MOS transistor can be made non-conductive in a short time after the bit line is charged. Accordingly, it is possible to realize a semiconductor memory device capable of detecting the write state of a memory cell with high accuracy and high speed.</p>