Semiconductor memory device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a semiconductor storage device, and is particularly used for a multi-value flash memory, a multi-value EEPROM, and a multi-value EPROM.

【0002】

[Conventional technology]

A MOSFET structure having a floating gate (charge storage layer) and a control gate on a semiconductor substrate is well known as one of the memory cells of a flash memory.

【0003】

Normally, one memory cell of a flash memory stores 1-bit data, that is, data 0 or 1. Further, whether the data of the memory cell is "0" or "1" can be identified by the amount of electric charge stored in the floating gate.

【0004】

On the other hand, in recent years, in order to secure a large data capacity, the development of a multi-value storage method for storing multi-bit data in one memory cell has been promoted. For example, in the quaternary storage method, data "0", "1", "2" or "3" is stored in one memory cell.

【0005】

In the multi-value storage type flash memory, which data is stored in the memory cell is determined by the amount of electric charge stored in the floating gate.

【0006】

Hereinafter, the storage state of the data, that is, the relationship between the data and the amount of electric charge in the floating gate will be described by taking a quadrature storage type flash memory as an example.

【0007】

First, the data "0" corresponds to the erased state.

【0008】

The erased state is a state in which a positive charge is stored in the floating gate. That is, in the erased state, the floating gate is positively charged with respect to the neutral state in which the amount of charge in the floating gate is zero.

【0009】

The erasing state is obtained, for example, by applying a high potential (about 20V) to the semiconductor substrate, setting the control gate to the ground potential (0V), and moving a positive charge from the semiconductor substrate to the floating gate.

【0010】

Next, the data "1", "2" and "3" correspond to the writing state.

【0011】

The writing state is a state in which a negative charge is stored in the floating gate. However, the amount of negative charge in the floating gate in the state of data "2" is larger than the amount of negative charge in the floating gate in the state of data "1", and the data " The amount of negative charge in the floating gate in the state of 3 is set to be larger than the amount of negative charge in the floating gate in the state of data 2 .

【0012】

In the writing state, the floating gate is negatively charged with respect to the neutral state in which the amount of charge in the floating gate is zero.

【0013】

In the writing state, for example, the semiconductor substrate, the source, and the drain are set to the ground potential (0V), a high potential (about 16V) is given to the control gate, and a negative charge is applied from the semiconductor substrate to the floating gate. Obtained by moving to.

【0014】

For memory cells that want to maintain data 0 during the write operation, the source, drain and channel are set to 5V. In this case, a high potential (about 16V) is given to the control gate, and even if the substrate is set to the ground potential (0V), the positive charge is retained in the floating gate, so the data " 0 is maintained.

【0015】

From the above, four types of write states (0, 1, 2, 3) can be realized by one memory cell.

【0016】

A flash memory having a NAND type memory cell unit is known.

【0017】

This memory cell unit includes a memory cell sequence composed of a plurality of (for example, four) memory cells, a first-select transistor connected between one end of the memory cell sequence and a bit line, and the memory cell sequence. It consists of a second-choice transistor connected between the end and the source line.

【0018】

The source line is common to all memory cell units.

【0019】

In a flash memory having a NAND memory cell unit, when writing data 0, the bit line is the power supply potential VCC (for example, 3V), the gate of the first selection transistor is the power supply potential VCC, and the selection memory. Set the cell control gate to the first high potential (for example, 16V) and the control gate of the non-selected memory cell to the second high potential (for example, 10V), and store it in the floating gate of the selected memory cell. Holds the charged charge.

【0020】

At this time, since the channel of each memory cell of the NAND memory cell unit is connected to the bit line via the first selection transistor, the potential of the channel of each memory cell drops the so-called threshold value of the first selection transistor. Considering the above, the initial potential is a predetermined potential of the power supply potential VCC (for example, 3V) or less.

【0021】

After that, when the first-select transistor becomes non-conducting, the potential of the channel of each memory cell of the NAND memory cell unit rises due to the capacitance generated between the control gate and the channel. For example, if the capacitance coupling ratio is 50%, the channel potential will be about 5V.

【0022】

However, when negative charges are accumulated in the floating gate of the memory cell, the threshold value of the memory cell becomes high. Along with this, the channel potential of each memory cell during the writing operation of the data 0 becomes lower as the threshold value of the memory cell becomes higher, and the reliability for maintaining the data 0 is maintained. Sex is reduced.

【0023】

However, when the threshold value of the memory cell is -1V, the potential of the channel is about 1V when the potential of the control gate is about 0V, and the potential of the channel is about 10V when the potential of the control gate is about 10V. Is about 6V (coupling ratio 50%).

【0024】

When the threshold value of the memory cell is 3V, the potential of the channel is about 0V when the potential of the control gate is about 1V, and the potential of the channel is about 10V when the potential of the control gate is about 10V. It becomes about 4.5V (bonding ratio 50%).

【0025】

In a flash memory having a NAND type memory cell unit, the data of the memory cell gives a predetermined read potential to the control gate, and the memory cell is turned on or off according to the data of the memory cell. At this time, it can be read by detecting the cell current flowing through the channel of the memory cell.

【0026】

Here, if three types of read potentials are prepared, four types of writing states (types and amounts of charges in the floating gate, that is, states having different threshold values) can be discriminated.

【0027】

Further, since the NAND type memory cell unit has a configuration in which a plurality of memory cells are connected in series, it is characterized in that the cell current during the read operation is small (for example, about 1 μA).

【0028】

Regarding the read time, for example, assuming that the bit line capacitance connected to the selected memory cell is about 5 pF, it takes about 5 μsec for the potential of the bit line to fluctuate by 1 V depending on the cell current.

【0029】

In order to read the data of the memory cell at high speed with a small cell current, for example, connect an N-channel MOS transistor between the bit line and the read circuit, and apply a potential of about 2V to the gate of this MOS transistor. , Precharge the bit line.

【0030】

In this case, assuming that the threshold value of the N-channel MOS transistor is about 1V, the bit line is precharged to about 1V in consideration of the so-called threshold drop of the MOS transistor.

【0031】

When the bit wire is precharged, the N-channel MOS transistor gradually becomes high resistance and then goes into a non-conducting state. However, the bit line pre-charging is not continued until the N-channel MOS transistor is completely non-conducting, considering the effective pre-charging time.

【0032】

During the read operation, when the cell current flows through the selected memory cell and the potential of the bit line drops, the channel resistance of the N-channel MOS transistor connected to the bit line decreases. It is possible to sense the change in the potential of the (memory cell data).

【0033】

The change in the channel resistance of the N-channel MOS transistor can be detected by comparing the resistance value of the channel resistance of the MOS transistor with the resistance value of the so-called reference resistance. Therefore, a current path is provided in the reference resistor, the N-channel MOS transistor, and the memory cell.

【0034】

However, in such a read operation, when reading the data of a plurality of selected memory cells at the same time, a large current flows through the source line common to all the cell units according to the threshold value of each selected memory cell. Or, conversely, it doesn't flow at all.

【0035】

For example, when the cell current flows through most of the selected memory cells, that is, when the data of most of the selected memory cells is "0", a large current flows through the source line and the source line is used. -The potential of the memory cell fluctuates. Fluctuations in the potential of the source line create a state in which the data of the selected memory cell cannot be read accurately.

【0036】

[Problems to be Solved by the Invention]

As described above, for example, when the data 0 is written, if the threshold value of the memory cell in the memory cell unit is high, the channel potential of the memory cell does not rise sufficiently, so that the data is set to the selected memory cell. There is a risk that data "1" will be written instead of data "0".

【0037】

Further, at the time of reading, it takes a very long time to detect the state of the memory cell having a small cell current, but there is a drawback that the state of the memory cell cannot be detected accurately when trying to detect the state of the memory cell at high speed. ..

【0038】

The present invention has been made to solve one of these problems, and an object of the present invention is to detect the state of a memory cell at high speed and accurately at the time of reading.

【0039】

[Means for solving problems]

In order to solve the above problems, the semiconductor storage device of the present invention has a memory cell, a bit line connected to the memory cell, a read circuit including a precursor circuit, and between the bit line and the read circuit. A first transistor to be connected is provided, and the bit wire is pre-charged by the pre-charging circuit when a first potential is applied to the gate of the first transistor, and the read-out circuit is When a second potential lower than the first potential is applied to the gate of the first transistor, a change in the potential of the bit line is sensed.

【0040】

The pre-charge circuit is composed of a second transistor connected between the first transistor and a power supply terminal, and the second transistor is applied with the second potential to the gate of the first transistor. During that time, it is set to the non-conducting state.

【0041】

In a desirable embodiment of the present invention, the first and second transistors are n-channel MOS transistors, and the capacitance of the bit line is larger than the capacitance of the connection portion between the first transistor and the readout circuit. This is the case.

【0042】

According to the semiconductor storage device of the present invention, a MOS transistor is connected between the bit line and the read circuit, the first potential is applied to the gate of the MOS transistor at the time of precharging the bit line, and the MOS transistor is read at the time of reading. A second potential lower than the first potential is applied to the gate.

【0043】

Therefore, after precharging the bit wire, the MOS transistor can be made non-conducting in a short time, so that the potential change of the bit wire can be sensed without using a reference resistor, etc., and the speed and accuracy can be increased. The write status of the memory cell can be detected.

【0044】

【0045】

【0046】

【0047】

【0048】

【0049】

【0050】

【0051】

【0052】

【0053】

【0054】

【0055】

【0056】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the semiconductor storage device of the present invention will be described in detail with reference to the drawings.

【0057】

FIG. 1 shows the configuration of a multi-value storage type NAND flash memory according to the embodiment of the present invention.

【0058】

The memory cell array 1 includes a plurality of NAND memory cell units, a plurality of bit lines, a plurality of word lines, and a source line. The NAND type memory cell unit is composed of a memory cell sequence composed of a plurality of memory cells connected in series and selection transistors connected to both ends of the memory cell sequence. The source line is common to all memory cell units.

【0059】

The bit line control circuit 2 reads the data of the memory cell via the bit line of the memory cell array 1, detects the state of the memory cell via the bit line, and controls writing to the memory cell via the bit line. A voltage is applied to write to the memory cell.

【0060】

The bit line control circuit 2 includes a plurality of data storage circuits. The data storage circuit is provided for the column of the memory cell array 1. The memory cell data read by the data storage circuit selected by the column recorder 3 is read out from the data input / output terminal 5 via the data input / output buffer 4. ..

【0061】

Further, the write data input to the data input / output terminal 5 from the outside passes through the data input / output buffer 4 and is initially stored in the data storage circuit selected by the column recorder 3. Latched as control data. The control data of the data storage circuit controls the write control voltage applied to the selected memory cell of the memory cell array 1 via the bit line.

【0062】

The word wire control circuit 6 selects one of the plurality of word wires of the memory cell array 1, and the one word wire is required for a read operation, a write operation, or an erase operation. Gives a predetermined potential.

【0063】

The operations of the memory cell array 1, the bit line control circuit 2, the column recorder 3, the data input / output buffer 4, and the word line control circuit 6 are controlled by the control signal and the control potential generation circuit 7, respectively.

【0064】

Further, the control signal and the control potential generation circuit 7 operate based on the control signal applied to the control signal input terminal 8 from the outside.

【0065】

FIG. 2 shows an example of the configuration of the memory cell array 1 and the bit line control circuit 2 of FIG.

【0066】

The NAND type memory cell unit includes a memory cell sequence consisting of four memory cells M connected in series with each other, a selection transistor S connected between one end of the memory cell sequence and the bit line BL, and the memory cell sequence. It consists of a selection transistor S connected between the end and the source line SRC.

【0067】

The control gate of the memory cell M is connected to the word line WLm (m is one of 1 to 4), and the selection transistor S on the bit line side is connected to the selection gate SG1. The selection transistor S on the source line side is connected to the selection gate SG2.

【0068】

A plurality of memory cells M sharing one word line WLm constitute a unit called a page, and in this example, one block is composed of four pages. Further, in this example, only two blocks are shown, but in reality, the memory cell array 1 is composed of an arbitrary number of blocks (for example, 1024 blocks). The number of bit lines BL0, BL1, ... BL4223 is 4224 in this example, but may be any number (for example, 2112).

【0069】

The bit line control circuit 2 includes a plurality of data storage circuits 10. In this example, one data storage circuit 10 is provided for two bit lines BLi, BLi + 1 (i is 0 or an even number), but any number, for example, one, is provided. One may be provided for four, six, or nine bit wires.

【0070】

The column selection signals CSL0, CSL1, ... CSL4223 are output signals of the column decorator. The column selection signals CSLi and CSLi + 1 are input to the data storage circuit 10 connected to the bit lines BLi and BLi + 1.

【0071】

At the time of reading, the data of the memory cell latched in the data storage circuit 10 selected by the column selection signals CSLi and CSLi + 1 is guided to the data input / output buffer as the reading data.

【0072】

Further, prior to writing, a control device for controlling the write control voltage applied to the memory cell at the time of writing to one of the bit lines BLi and BLi + 1 based on the column selection signals CSLi and CSLi + 1 is used. The data is initially transferred.

【0073】

When detecting the write state, the write state of the memory cell connected to either one of the bit line BLi and BLi + 1 is detected.

【0074】

FIG. 3 shows the structure of the memory cell M and the selection transistor S of FIG.

【0075】

An n-type diffusion layer 12 serving as a source or drain is formed on the surface of the p-type semiconductor substrate 11.

【0076】

The memory cell M is an n-type diffusion layer 12 in the semiconductor substrate 11, a gate insulating film 13 on the semiconductor substrate 11, a floating gate 14 on the gate insulating film 13, and a floating gate 14. The insulating film 15 and the control gate (word wire) 16 on the insulating film 15 are included. The selective transistor S includes an n-type diffusion layer 12 in the semiconductor substrate 11, a gate insulating film 17 on the semiconductor substrate 11, and a selective gate 18 on the gate insulating film 17.

【0077】

When a potential equal to or higher than the threshold value of the memory cell M is applied to the control gate 16 of the memory cell M, a channel is formed on the surface of the semiconductor substrate 11 immediately below the floating gate 14.

【0078】

For example, the capacitance between the control gate 16 and the floating gate 14 is 1fF, the capacitance between the floating gate 14 and the channel is 1fF, the capacitance between the channel and the semiconductor substrate 11 is 0.25fF, and n-type diffusion. Assuming that the capacitance between the layer 12 and the semiconductor substrate 11 is 0.25 fF, the capacitance coupling ratio between the control gate 16 and the channel and the capacitance coupling ratio between the control gate 16 and the n-type diffusion layer 12 are 50%, respectively. Is.

【0079】

In this case, when the channel and the n-type diffusion layer 12 are in a floating state, when the control gate 16 rises by 1 V, the potential of the channel and the n-type diffusion layer 12 rises by 0.5 V.

【0080】

FIG. 4 shows the structure of the NAND memory cell unit of FIG.

【0081】

A memory cell row is composed of four memory cells M, one end of the memory cell row is connected to the source line SRC via the selection transistor S, and the other end of the memory cell row passes through the selection transistor S. Is connected to the bit line BL.

【0082】

In the erasing operation, the potential Vsub of the semiconductor substrate is set to about 20V, the potentials of the selection gate SG1, SG2, source line SRC, and bit line BL are set to about 20V, and block erasing (all memory in the block). Set the potential of the word lines WL1 to WL4 of the selected block to be performed (erasing the cell data at the same time) to 0V.

【0083】

At this time, negative charges (electrons) move from the floating gate to the channel, and the floating gate is positively charged with respect to the neutral state (state in which no charge exists), so that all in the selected block. The threshold value of the memory cell M becomes negative (data 0 state).

【0084】

In the non-selected block where the block is not erased, the potentials of the word lines WL1 to WL4 are set to about 20V. As a result, the data of each memory cell retains the state before executing the erase operation.

【0085】

In the write operation, the potential of one selected word line of the selected block is set to about 16 V, and the potentials of the three non-selected word lines of the selected block are set to a potential lower than the write potential, and the selection is performed. Set the gate SG1 to the power potential VCC, set the selected gate SG2 to 0 V, and set the potentials of all ward wires and all selected gates of the non-selected block to 0 V.

【0086】

For example, to explain the case of the four-value storage method, the potential of the bit line BL is set to 0V when writing the data 1, 2, 3. At this time, in the selected memory cell, electrons are injected into the floating gate, and the threshold value becomes positive.

【0087】

When writing the data 0, the bit line BL is set to the power supply potential VCC. At this time, since the potential of the selective gate SG1 is the power supply potential VCC, the selective gate S on the bit line side is in a non-conducting state, and the channel of the memory cell and the n-type diffusion layer are floated. It becomes a state.

【0088】

The potential of the channel is increased by the capacitive coupling between the channel and the control gate. Assuming that the potential less than the write potential applied to each control gate is about 10 V, the potential of the channel is about 5 V if the coupling ratio of the capacitive coupling is 50%. However, the higher the threshold value of the memory cell, the lower the channel potential of the memory cell when writing the data 0.

【0089】

This is because, for example, when the threshold value of the memory cell is about 1V, the channel is not formed until the potential of the control gate reaches about 1V.

【0090】

That is, when the threshold value of the memory cell is about 1V, the potential of the channel is about 0V when the potential of the control gate is about 1V, so when the potential of the control gate is about 10V, the potential of the channel is , Approximately 4.5V (coupling ratio 50%).

【0091】

On the other hand, when the threshold value of the memory cell is about -1V, the potential of the channel can be charged to about 1V even if the potential of the control gate is about 0V. That is, when the control gate reaches about 10V, the channel potential becomes about 6V.

【0092】

In the present invention, when writing data 0, a non-selected word line (for example, WL2) adjacent to the source line side with respect to the selected word line (for example, WL2) in the selected block is used. The potential of WL3) is set to about 0V in particular, and the remaining unselected word wires (eg, WL1, WL4) in the selection block are given a potential of about 10V.

【0093】

In addition, the order of writing data "0" in the memory cell unit is the memory cell that is connected to the word line WL4 closest to the source line at the beginning, and is connected to the word line on the bit line side. The memory cells are sequentially transferred, and the last is the memory cell connected to the word line WL1 closest to the bit line.

【0094】

That is, in the memory cell unit, all the data of the memory cell existing on the bit line side of the memory cell connected to the selected word line is erased, that is, the data "0" is written. There is. In other words, the threshold value of the memory cell existing on the bit line side of the memory cell connected to the selected word line is in a negative state.

【0095】

On the other hand, since the control gate of the memory cell adjacent to the source line side with respect to the selected memory cell connected to the selected word line is 0V, the potentials of the source and drain of this adjacent memory cell When increases due to capacitive coupling between the control gate of the memory cell and the channel, the adjacent memory cell becomes non-conducting.

【0096】

Therefore, the channel potential of the selected memory cell rises integrally with the selected memory cell and the erased memory cell existing on the bit line side of the selected memory cell. Therefore, the channel potential of the selected memory cell is always secured to be, for example, about 6 V or more at all times. That is, no electrons are injected into the floating gate, and data "0" can be written.

【0097】

For example, when the selected word line is WL4, the potentials of the non-selected word lines WL1 to WL3 are set to about 10V. When the selected word line is WL3, the potential of the non-selected word lines WL1 and 2 is set to about 10V, and the potential of the non-selecting word line WL4 is set to 0V.

【0098】

However, when the selected word line is WL3, the memory cell connected to the non-selected word line WL4 does not have a memory cell on the source line side, so the memory connected to the non-selected word line WL4 Sometimes it is not possible to make a cell non-conducting. However, there is no problem because there are more memory cells on the bit line side than the memory cells connected to the non-selected word line WL4.

【0099】

When the selected word line is WL3, the potential of the non-selected word line WL4 may be set to about 10 V. When the selected word line is WL1, the potential of the non-selected word lines WL3 and 4 is about 10 V, and the potential of the non-selected word line WL2 is about 0 V.

【0100】

The point to be noted here is that the non-selected word line existing on the bit line side with respect to the selected word line must not be set to 0V. For example, when the word line WL2 is selected, the word line WL1 must not be set to 0V. This is because when the word line WL1 is set to 0V, the memory cells connected to the word line WL1 become non-conducting.

【0101】

Further, the potential of the bit line when writing the data 1, 2, 3 does not have to be 0V. For example, the potential of the bit line may be set to 1.2V when writing the data 1, and the potential of the bit line may be set to 0V when writing the data 2 and 3.

【0102】

This is because the amount of electrons injected into the floating gate of the memory cell M to store the data 1 is the floating charge of the memory cell M to store the data 2 and 3. -This is because it may be less than the amount of electrons injected into the memory.

【0103】

Further, the potentials of the bit lines when writing the data 1, 2, 3 may be different from each other. For example, the potential of the bit line when writing data "1" is about 2.4V, the potential of the bit line when writing data "2" is about 1.2V, and the potential of data "3" is written. The potential of the bit line at the time may be 0V.

【0104】

In the case of the 4-value storage method, for example, the threshold value of the memory cell corresponding to the data "0" is 0 V or less, the threshold value of the memory cell corresponding to the data "1" is 0.4 V to 0.8 V, and the data " Set the threshold of the memory cell corresponding to "2" to 1.6V to 2.0V, and the threshold of the memory cell corresponding to data "3" to 2.8V to 3.2V.

【0105】

At the time of reading, the potential of the selection word line WL2 of the selection block is set to Vread. The potentials of the non-selection word lines WL1, WL3, WL4 of the selection block are set to, for example, about 4V. The potentials of the selection gates SG1 and SG2 of the selection block are also set to, for example, about 4V. The potentials of all ward wires and all-select gate SGs in the non-selected block are 0 V. The source wire SRC is connected to the grounding point via a parasitic resistor.

【0106】

If the potential of the source wire does not rise due to parasitic resistance, (1) When the potential Vread of the selected word line is 0V, if the selected memory cell stores data 1, 2 or 3, the bit line is precharged to 1V. At the same time, it remains at 1V even after it is in a floating state. If the selected memory cell stores data 0, the bit line is precharged to 1V and drops to 0.5V after entering the floating state.

【0107】

(2) When the potential Vread of the selected word line is 1.2V, if the selected memory cell stores data "2" or "3", the bit line is precharged to 1V. , It remains 1V even after the floating state. If the selected memory cell stores data "0" or "1", the bit line is precharged to 1V and drops to 0.5V after being in the floating state.

【0108】

(3) When the potential Vread of the selected word line is 2.4V and the selected memory cell stores data 3, the bit line is precharged to 1V and floated. Even after the state is reached, it remains at 1V. If the selected memory cell stores data "0", "1" or "2", the bit line is precharged to 1V and drops to 0.5V after entering the floating state.

【0109】

As described above, the data stored in the memory cell M is read out using the three types of read potentials.

【0110】

FIG. 5 shows a more specific configuration example of the memory cell array 1 and the data storage circuit 10 shown in FIG. Here, a configuration example of a quadrature storage flash memory is shown as an example.

【0111】

The clock synchronous inverters CI1 and CI2, and the n-channel MOS transistors Qn4, Qn5, and Qn6 form the first subdata circuit. Further, the clock synchronous inverters CI3 and CI4, and the n-channel MOS transistors Qn10, Qn11, and Qn12 form a second subdata circuit.

【0112】

The first and second sub-data circuits store the first and second sub-data at the time of writing, respectively. The first and second sub-data circuits store the first and second read sub-data at the time of reading, respectively.

【0113】

When the memory Nai in the first subdata circuit is at the H level, the first read subdata with the first subdata circuit being 1 or the first subdata with 1. -It is in a state of remembering the circuit.

【0114】

Also, when the mode Nai + 1 in the second subdata circuit is at the H level, the second subdata circuit is the second read subdata of 1 or 1. It is a state in which the second subdata is memorized.

【0115】

When the memory Nai in the first subdata circuit is at the L level, the first read subdata with the first subdata circuit being 0 or the first subdata with 0. -It is in a state of remembering the ta.

【0116】

When the code Nai + 1 in the second subdata circuit is at the L level, the second read subdata with the second subdata circuit being 0 or the second with 0. It is a state in which the sub-data of is memorized.

【0117】

The n-channel MOS transistors Qn1 and Qn7 are for setting the subdata of "0" in the first and second subdata circuits when the signal PRST becomes "H".

【0118】

The n-channel MOS transistors Qn2 and Qn8 are for electrically connecting the first and second sub-data circuits and the data input / output lines IOL and IOU, respectively. Each gate electrode is given the outputs CSLi and CSLi + 1 from column decoder 3, respectively.

【0119】

For example, when CSLi becomes H, the first sub-data circuit of the data storage circuit 10 provided in the bit line BLi and BLi + 1 and the data input / output line IOL are electrically connected. .. The data input / output lines IOL and IOU are connected to the data input / output buffer 4, and subdata can be set in the first or second subdata circuit. Alternatively, the read subdata of the first or second subdata circuit can be output to the data input / output buffer 4.

【0120】

The n-channel MOS transistors Qn3 and Qn9 detect whether or not the subdata of the first subdata circuit and the second subdata circuit are all 0. Since there are 2112 data storage circuits 10 in this example, if the 2112 first subdata and the 2112 second subdata are all "0", the common signal line PT and the ground line Is detected as non-conducting.

【0121】

Capacitor C1 is for amplifying the change of bit line potential together with n-channel MOS transistors Qn13 and Qn14. As will be described in detail later, the signal PREC is the power supply potential VCC (for example, 3V), the signal BIAS is 2V, and the bit line is charged.

【0122】

Assuming that the threshold value of the n-channel MOS transistor is 1V, the bit line is charged to near 1V. Since it takes time to charge the bit line until the n-channel MOS transistor Qn14 becomes non-conducting, the signals PREC and BIAS are set to 0V after a predetermined time has passed.

【0123】

When detecting the bit line potential, the signal BIAS is set to, for example, 1.8V. If there is no change in the bit line potential, this potential of 1.8V is set so that the n-channel MOS transistor Qn14 becomes non-conducting. If there is a change in the bit line potential and it is 0.8V, the n-channel MOS transistor Qn14 becomes conductive.

【0124】

When conducting, the potential of the throat Nsense drops. For example, if the bit line capacitance is 5 pF and the capacitor C1 is smaller, for example 0.5 pF, the change in the bit line potential has a large effect on the change in the node Nsense. Therefore, the bit line potential can be amplified with high sensitivity.

【0125】

For example, when the bit line goes from 1V to 0.7V, the throat Nsense goes from 2V to about 0.73V. Even if the bit line changes from 1V to 0.9V, Nsense remains at 2V. Therefore, the change in Nsense is about 1.27V for the change of 0.2V in the bit line.

【0126】

The n-channel MOS transistors Qn15 and Qn17 control the electrical connection between the first and second subdata circuits and the bit line BLi or BLi + 1. If the signal BLC1 is H and BLC2 is L, the first and second sub-data circuits and the bit line BLi are electrically connected.

【0127】

If the signal BLC1 is L and BLC2 is H, the first and second subdata circuits and the bit line BLi + 1 are electrically connected. The n-channel MOS transistors Qn16 and Qn18 control the electrical connection between the bit line BLi and the potential VBL1 and the electrical connection between the bit line BLi + 1 and the potential VBL2.

【0128】

If the signal PRE1 is H, the bit line BLi and the potential VBL1 are electrically connected. If the signal PRE2 is H, the bit line BLi + 1 and the potential VBL2 are electrically connected.

【0129】

A signal indicating the data or write state of the memory cell M is transferred via the bit line BLi or BLi + 1. In the first sub-data circuit, the clock-synchronous inverter CI1 and in the second sub-data circuit, the clock-synchronous inverter CI3 also works as a sense amplifier that senses the logic level of the bit line BL signal. ..

【0130】

In this example, the clock synchronous inverter senses the absolute value of the potential of the bit line BL as a logic level, but a differential type (differential) sense amplifier or the like may be used, in which case, a reference (reference) is used. The difference from the potential is detected as a logical level.

【0131】

The specific configuration of the clock synchronous inverter CI is shown in FIG.

【0132】

The input terminal of the inverter circuit composed of the n-channel MOS transistor Qn19 and the p-channel MOS transistor Qp2 is IN and the output terminal OUT. An n-channel MOS transistor Qn20 and a p-channel MOS transistor Qp1 are provided to activate or deactivate this inverter circuit by the signal CLOCK and its inverting signal CLOCKB. The signal CLOCK is activated with "H" and CLOCKB is activated with "L", and the signal CLOCK is deactivated with "L" and CLOCKB is deactivated with "H".

【0133】

Signals SEN1, LAT1, SEN2, LAT2, PRO1, PRO2, BLC1, BLC2, PRE1, PRE2, VRFY1, VRFY2, PRST, potentials VBL1, VBL2, VREG, BIAS, PREC, PT are the control signals and control potential generation circuit 7. It is an output signal and is common to all the data storage circuits 10 seen in FIG. The potential VCC is the power supply potential, for example, 3V.

【0134】

The first and second sub-data circuits store "0" or "1" sub-data, and each is a "1" sub-data stored in response to the "H" level of the bit line signal. It is configured to change the data to a "0" subdata and retain the "0" subdata.

【0135】

Regardless of the specific configuration of this embodiment, it can be similarly carried out using various circuits having the above-mentioned functions. In the sub-data circuit of this embodiment, the first or second signal PRO1 or PRO2 becomes H and the potential level of the bit line BL is sensed by the clock synchronous inverter CI1 or CI3. Depending on the subdata, the potential level of the bit line BL is adjusted by the n-channel MOS transistor Qn5,6 or Qn11,12.

【0136】

Only when the first or second subdata is 0, the potential level of the bit line BL is set to H. When the signal PRO1 or PRO2 becomes H and the H level of the bit line is transferred to the input terminal of the clock synchronous inverter CI1 or CI3, the node Nai or Nai + 1 becomes H. It is set to L "level.

【0137】

Furthermore, the subdata of "0" is stored by the clock synchronous inverter CI2 or CI4. Therefore, the originally stored "0" subdata is not changed. When the originally stored subdata is "1", when the bit line BL level is "H", it is changed to the "0" subdata and stored, and the bit line BL level is "L". Holds the subdata of when "1".

【0138】

Figures 7, 8 and 9 show the read operation of the quaternary data stored in the memory cell.

【0139】

Here, the bit line BL0, BL2, ..., BLi, ..., BL4222 is selected (BLi is shown as a representative), and the word line WL2 is selected. Is an example of.

【0140】

If the memory level is limited to 3 levels, ternary memory can be easily performed. Here, the potentials VBL1 and VBL2 are 0V, BLC2 is L, PRE2 is H, PREST is L, bit line BLi + 1 is 0V, CSLi and CSLi + 1 are 0V, and potential VREG is 0V. Since it remains as it is, the display in Figures 7, 8 and 9 is omitted.

【0141】

First, the signal PRE1 becomes L and BLC1 becomes H, and the bit line BLi is selected. When the signal PREC becomes VCC and the signal BIAS becomes 2V, the bit line BLi is charged to 1V (t2). The threshold value of the n-channel MOS transistor Qn is set to 1V unless otherwise specified.

【0142】

When the signal BIAS becomes 0V, charging of the bit line BLi ends (t3). Then, the signal PREC becomes 0V, and charging of the throat Nsense is completed (t4). The selected gates SG1 and SG2 of the selected block, and the non-selected word lines WL1,3,4 are set to 4V, and the selected word lines WL2 are set to 2.4V (t4).

【0143】

Table 1 shows the relationship between the data stored in the memory cell M and the threshold value.

【0144】

[table 1]

<img file="JPP3481817B2_D0001.tif" />【0145】

When the selected word line WL2 reaches 2.4V, the bit line BLi remains 1V only if the memory cell stores "3" data. In other cases, the bit line BLi is 0.7V or less. After a certain period (t4 ~ t5), the signal BIAS is set to 1.8V. The node Nsense remains at 2V only if the memory cell is storing "3" data.

【0146】

Otherwise, Nsense will be below 0.8V. After the signal BIAS becomes 0V again and the bit lines BLi and Nsense are cut off, the signals SEN2 and LAT2 become L and the clock synchronous inverters CI3 and CI4 are deactivated (t6).

【0147】

When the signal PRO2 becomes H (t7) and the signal SEN2 becomes H (t8), the clock synchronous inverter CI3 is activated and the potential of the node Nsense is sensed. When the signal LAT2 becomes H (t9), the clock synchronous inverter CI4 is activated and the logic level of the sensed signal is latched.

【0148】

The selected gates SG1, SG2, and word lines WL1 to WL4 are reset to 0V at time t5. The signal BLC1 becomes L at time t6, the signal PRE1 becomes H at time t7, and the bit line BLi is reset to 0V at time t7.

【0149】

The signal PRO2 becomes L (t10), and the operation of detecting whether the threshold value of the memory cell M is 2.4V or more ends. Only when the memory cell stores "3" data, the second read subdata of the second subdata circuit becomes "0". Otherwise, the second read subdata is 1.

【0150】

Then, the operation of detecting whether or not the threshold value of the memory cell M is 0.0V or more is started. First, the signal PRE1 becomes L and BLC1 becomes H, and the bit line BLi is selected.

【0151】

When the signal PREC becomes VCC and the signal BIAS becomes 2V, the bit line BLi is charged to 1V (t13). The signal BIAS becomes 0V and the charging of the bit line BLi ends (t14).

【0152】

Then, the signal PREC becomes 0V, and charging of the throat Nsense is completed (t15). The selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1,3,4 are set to 4V, and the selection word line WL2 is left at 0.0V (t15).

【0153】

If the selected word line WL2 is 0.0V, the bit line BLi remains 1V if the memory cell stores "1", "2" or "3" data. When the memory cell stores "0" data, the bit line BLi is 0.7V or less.

【0154】

After a certain period (t15 ~ t16), the signal BIAS is set to 1.8V. If the memory cell stores "1", "2" or "3" data, the throat Nsense remains at 2V. If the memory cell stores "0" data, Nsense will be 0.8V or less.

【0155】

Again, after the signal BIAS becomes 0V and the bit lines BLi and Nsense are cut off, the signals SEN1 and LAT1 become L and the clock synchronous inverters CI1 and CI2 are deactivated (t17). ..

【0156】

At the same time, the node Nsense is set to 0V only when the signal VRFY2 becomes VCC and the second read subdata of the second subdata circuit is 0 (t17). When the signal PRO1 becomes H (t18) and the signal SEN1 becomes H (t19), the clock synchronous inverter CI1 is activated and the potential of the node Nsense is sensed. When the signal LAT1 becomes H (t20), the clock synchronous inverter CI2 is activated and the logic level of the sensed signal is latched.

【0157】

The selected gates SG1, SG2, and word lines WL1 to WL4 are reset to 0V at time t16. The signal BLC1 becomes L at time t17, the signal PRE1 becomes H at time t18, and the bit line BLi is reset to 0V at time t18.

【0158】

The signal PRO1 becomes L (t21), and the operation of detecting whether the threshold value of the memory cell M is 0.0V or more ends. Only when the memory cell stores "0" or "3" data, the first read subdata of the first subdata circuit is "1". Otherwise, the first read subdata is 0.

【0159】

Then, the operation of detecting whether the threshold value of the memory cell M is 1.2 V or more is started. First, the signal PRE1 becomes L and BLC1 becomes H, and the bit line BLi is selected.

【0160】

When the signal PREC becomes VCC and the signal BIAS becomes 2V, the bit line BLi is charged to 1V (t24). The signal BIAS becomes 0V and the charging of the bit line BLi ends (t25).

【0161】

Then, the signal PREC becomes 0V, and charging of the throat Nsense ends (t26). The selected gates SG1 and SG2 of the selected block, and the non-selected word lines WL1,3,4 are set to 4V, and the selected word lines WL2 are set to 1.2V (t26).

【0162】

When the selected word line WL2 reaches 1.2V, the bit line BLi remains 1V if the memory cell stores "2" or "3" data. When the memory cell stores "0" or "1" data, the bit line BLi is 0.7V or less.

【0163】

After a certain period (t26 to t27), the signal BIAS is set to 1.8V. If the memory cell stores "2" or "3" data, the throat Nsense remains at 2V. If the memory cell stores "0" or "1" data, the Nsense will be 0.8V or less.

【0164】

Again, after the signal BIAS becomes 0V and the bit lines BLi and Nsense are cut off, the signals SEN2 and LAT2 become L and the clock synchronous inverters CI3 and CI4 are deactivated (t28). ..

【0165】

When the signal PRO2 becomes H (t29) and the signal SEN2 becomes H (t30), the clock synchronous inverter CI3 is activated and the potential of the node Nsense is sensed. When the signal LAT2 becomes H (t31), the clock synchronous inverter CI4 is activated and the logic level of the sensed signal is latched.

【0166】

The selected gates SG1, SG2, and word lines WL1 to WL4 are reset to 0V at time t27. The signal BLC1 becomes L at time t28, the signal PRE1 becomes H at time t29, and the bit line BLi is reset to 0V at time t29.

【0167】

The signal PRO2 becomes L (t32), and the operation of detecting whether the threshold value of the memory cell M is 1.2V or more ends. The second read subdata of the second subdata circuit is "1" only when the memory cell stores "0" or "1" data. Otherwise, the second read subdata is 0.

【0168】

As described above, the operation of storing the data of the memory cell M in the data storage circuit 10 as the read data is completed in the order shown in FIGS. 7 to 9.

【0169】

After that, when the signals CSLi and CSLi + 1 become H, the first read subdata becomes the data input / output line IOL, and the second read subdata becomes the data input / output line IOU. Is output to the outside from the data input / output terminal 5 via the data output buffer 4.

【0170】

Table 2 shows the relationship between the memory cell quadrature data and the first and second read subdata.

【0171】

[Table 2]

<img file="JPP3481817B2_D0002.tif" />【0172】

FIG. 10 shows the writing operation. Here, the case where the bit lines BL0, BL2, ..., BLi, ..., BL4222 are selected (BLi is shown as a representative) and the word line WL2 is selected is shown. Here is an example of quaternary memory. If the memory level is limited to 3 levels, ternary memory can be easily performed.

【0173】

Prior to writing, the control data is initially set in the data storage circuit 10. The initial setting of the control data to the data storage circuit 10 provided in the bit line BLi is performed as follows.

【0174】

The initial subdata of the first subdata circuit is transferred to the data input / output line IOL, and the initial subdata of the second subdata circuit is transferred to the data input / output line IOU, and the signals CSLi and CSLi + 1 becomes H and the initial subdata is stored in the first and second subdata circuits.

【0175】

The initial control data is set in an arbitrary number of data storage circuits 10 by changing the selection of the signal CSL. At this time, the relationship between the initial control data and the initial sub data is shown in Table 3 below.

【0176】

[Table 3]

<img file="JPP3481817B2_D0003.tif" />【0177】

Here, it is desirable to set the signal PRST to H and preset the control data of all the data storage circuits 10 to 0 before setting all the initial control data. As will be explained later, the state of the memory cell M cannot be changed by the control data 0. Therefore, out of the 2112 data storage circuits 10, only the desired data storage circuit 10 is initially selected from the outside. All you have to do is set the control data.

【0178】

Of course, initial control data may be set externally in all 2112 data storage circuits 10. The signal SEN1 is H, LAT1 is H, VRFY1 is L, SEN2 is H, LAT2 is H, VRFY2 is L, the potential VREG is 0V, and PREC remains 0V. The display to is omitted.

【0179】

In the writing operation, first, the signal PRE1 becomes L and the bit line BLi and the potential VBL1 are separated (t2). At the same time, the signal BLC1 becomes 6V and the bit line BLi is selected (t2).

【0180】

The signals BIAS and PRE2 are also 6V (t2). The potential VBL2 becomes VCC (here, 3V), and the non-selective bit line BLi + 1 is charged to VCC via the n-channel MOS transistor Qn18 (t3 to t4).

【0181】

In addition, the signal PRO1 becomes 3V, and the selection bit line BLi is charged according to the first subdata (t3 to t4). At this time, the bit line BLi is charged to VCC when the control data is 0 or 3, and is set to 0V when the control data is 1 or 2.

【0182】

In addition, the selective gate SG1 and the word line WL4 are set to 6V (t3 to t4), and the selected gate SG1 is set to VCC when the bit line potential VCC is transferred (t4). The word line WL3 remains at 0V. Word lines WL1 and 2 are set to VCC. The selection gate SG2 remains at 0V.

【0183】

After this, the signal PRO2 becomes 2.2V and the potential of the selected bit line BLi is changed according to the second subdata (t5). When the second subdata is 0, the bitline BLi, which was previously 0V, is charged to 1.2V, which is n-channel MOS transistor Qn10 threshold (1V) lower than 2.2V.

【0184】

When the second subdata is 0, the bit line BLi, which was previously VCC, remains VCC because the n-channel MOS transistor Qn10 is non-conducting. When the second subdata is 1, the bit line BLi is 0V because the n-channel MOS transistor Qn10 is conductive.

【0185】

As a result, the bit line BLi is set to VCC when the control data is 0, 1.2V when the control data is 1, and 0V when the control data is 2. -If the value is "3", it will be 0V.

【0186】

The selected word line WL2 is set to 1.6V, and the non-selected word lines WL1 and 4 are set to 10V, and electron injection into the floating gate of the memory cell starts according to the control data (t6 to t7). ).

【0187】

When the bit line BL is 0V, electron injection occurs when the potential difference between the memory cell channel and the word line is 16V. When the bit line BL is 1.2V, electron injection occurs when the potential difference between the memory cell channel and the word line is 14.8V, but it is smaller than when the potential difference between the memory cell channel and the word line is 16V.

【0188】

When the bit line BL is VCC, the word line WL1 becomes 10V and WL2 becomes 16V, so that the channel of the selected memory cell rises above VCC (for example, 6V), and between the memory cell channel and the word line. Since the potential difference is small, electron injection does not occur substantially.

【0189】

After the signal PRO2 is reset to 0V (t7), the word lines WL1 ~ 4 are 0V, the potential VBL2 is 0V, the signal PRE1 is H, the signal PRE2 is H, the signal BLC1 is L, and the signal. BIAS is reset to L (t8) and the write operation ends.

【0190】

As shown in FIG. 11, the potential of the selective word line WL2 during the time t3 to t6 may be 6V, which is the same as that of the non-selective word line WL4, instead of VCC. This is because channels are formed even if the threshold value of the selected memory cell is high. In addition, the bit line potential can be reliably transferred from the selected memory cell to the memory cell on the common source side.

【0191】

FIG. 12 is a modified example of the writing operation shown in FIG. Here, the timing at which the non-adjacent word line WL4 on the common source side of the selected word line WL2 is set to 10V is set to t5. This is to ensure that the memory cells located on the adjacent common source side of the selected memory cells are non-conducting.

【0192】

FIG. 13 is a modified example of the writing operation shown in FIG. Here, the timing at which the non-adjacent word line WL4 on the common source side of the selected word line WL2 is set to 10V is set to t5. This is to ensure that the memory cells located on the adjacent common source side of the selected memory cells are non-conducting, as in the case of FIG.

【0193】

FIGS. 14, 15 and 16 show the write verification operation for detecting the write state of the memory cell after the write operation shown in FIGS. 10, 11, 12 or 13.

【0194】

Here, the case where the bit lines BL0, BL2, ..., BLi, ..., BL4222 are selected (BLi is shown as a representative) and the word line WL2 is selected is shown. Here is an example of quaternary memory. If the memory level is limited to 3 levels, ternary memory can be easily performed.

【0195】

The potentials VBL1 and VBL2 are 0V, the signal BLC2 is L, the PRE2 is still H, and the bit line BLi + 1 is still 0V, so the display in FIGS. 14 to 16 is omitted. Moreover, since the signal PRST is L, CSLi is L, and CSLi + 1 is still L, the display in FIGS. 14 to 16 is omitted.

【0196】

First, the signal PRE1 becomes L and BLC1 becomes H, and the bit line BLi is selected. When the signal PREC becomes VCC and the signal BIAS becomes 2V, the bit line BLi is charged to 1V (t2). When the signal BIAS becomes 0V, charging of the bit line BLi ends (t3).

【0197】

Then, the signal PREC becomes 0V, and charging of the throat Nsense is completed (t4). The selected gates SG1 and SG2 of the selected block, and the non-selected word lines WL1,3,4 are set to 4V, and the selected word lines WL2 are set to 2.8V (t4).

【0198】

When the selected word line WL2 reaches 2.8V, the memory cell corresponding to the data storage circuit that stores the control data of "3" reaches the state of storing the "3" data. If so, the bit line BLi remains at 1V.

【0199】

If the memory cell corresponding to the data storage circuit that stores the "3" control data has not reached the state of storing the "3" data, the bit line BLi will be 0.7V or less. ..

【0200】

The bit line BLi is 0.7V because the memory cell corresponding to the data storage circuit that stores the control data of "2" or "1" does not reach the state of storing the "3" data. It becomes as follows.

【0201】

After a certain period (t4 ~ t5), the signal BIAS is set to 1.8V. If the memory cell corresponding to the data storage circuit that stores the "3" control data has reached the state where it stores the "3" data, the node Nsense remains at 2V. Is. Unless the memory cell is storing "3" data, Nsense will be 0.8V or less.

【0202】

Again, after the signal BIAS becomes 0V and the bit lines BLi and Nsense are cut off, the signal VRFY2 becomes VCC (t6). Only when the second subdata of the second subdata circuit is 0, the Nsense becomes 2V by the n-channel MOS transistors Qn11 and Qn12. At this time, the potential VREG is VCC (t5 to t8).

【0203】

The signals SEN2 and LAT2 become L and the clock synchronous inverters CI3 and CI4 are deactivated (t8). Signal PRO2 becomes H (t9). When the signal SEN2 becomes H (t10), the clock synchronous inverter CI3 is activated and the potential of the node Nsense is sensed.

【0204】

When the signal LAT2 becomes H (t11), the clock synchronous inverter CI4 is activated and the logic level of the sensed signal is latched.

【0205】

The selected gates SG1, SG2, and word lines WL1 to WL4 are reset to 0V at time t5. The signal BLC1 becomes L at time t6, the signal PRE1 becomes H at time t7, and the bit line BLi is reset to 0V at time t7.

【0206】

A state in which the signal PRO2 becomes L (t12) and the memory cell corresponding to the data storage circuit 10 that stores the control data of 3 stores the 3 data. Detection of whether or not the value has been reached (verification reading of data 3) is completed.

【0207】

Only when it is detected at this point that the memory cell corresponding to the data storage circuit storing the "3" control data has reached the state of storing the "3" data. , The control data of the data storage circuit that stores the control data of "3" is changed to "0" data, and in other cases, the control data is retained (changed). Not done).

【0208】

Then, in the operation of detecting whether or not the memory cell corresponding to the data storage circuit storing the "2" control data has reached the state of storing the "2" data. enter.

【0209】

First, the signal PRE1 becomes L and BLC1 becomes H, and the bit line BLi is selected. When the signal PREC becomes VCC and the signal BIAS becomes 2V, the bit line BLi is charged to 1V (t15). The signal BIAS becomes 0V and the charging of the bit line BLi ends (t16).

【0210】

Then, the signal PREC becomes 0V, and charging of the throat Nsense is completed (t17). The selected gates SG1 and SG2 of the selected block, and the non-selected word lines WL1,3,4 are set to 4V, and the selected word lines WL2 are set to 1.6V (t17).

【0211】

When the selected word line WL2 reaches 1.6V, the memory cell corresponding to the data storage circuit that stores the control data of 2 reaches the state of storing the 2 data. If so, the bit line BLi remains at 1V. If the memory cell corresponding to the data storage circuit that stores the "2" control data has not reached the state of storing the "2" data, the bit line BLi will be 0.7V or less. ..

【0212】

Since the memory cell corresponding to the data storage circuit that stores the control data of "1" does not reach the state of storing the "2" data, the bit line BLi becomes 0.7V or less. After a certain period (t7 ~ t18), the signal BIAS is set to 1.8V. If the memory cell corresponding to the data storage circuit that stores the "2" control data has reached the state where it stores the "2" data, the node Nsense remains at 2V. Is.

【0213】

If the memory cell corresponding to the data storage circuit that stores the "2" control data has not reached the state that stores the "2" data, the node Nsense will be 0.8V or less. Become. The memory cell corresponding to the data storage circuit that stores the control data of "1" does not reach the state of storing the "2" data, so the node Nsense becomes 0.8V or less. ..

【0214】

Again, after the signal BIAS becomes 0V and the bit lines BLi and Nsense are cut off, the signal VRFY1 becomes VCC (t19). At this time, the potential VREG is 0V, so when the first subdata is 0, the node Nsense is set to 0V by the n-channel MOS transistors Qn5 and Qn6.

【0215】

After this, the signal VRFY2 becomes VCC (t21). Only when the second subdata of the second subdata circuit is 0, the Nsense becomes 2V by the n-channel MOS transistors Qn11 and Qn12. At this time, the potential VREG is VCC (t21 to t23).

【0216】

The signals SEN2 and LAT2 become L and the clock synchronous inverters CI3 and CI4 are deactivated (t23). Signal PRO2 becomes H (t24). When the signal SEN2 becomes H (t25), the clock synchronous inverter CI3 is activated and the potential of the node Nsense is sensed. When the signal LAT2 becomes H (t26), the clock synchronous inverter CI4 is activated and the logic level of the sensed signal is latched.

【0217】

The selected gates SG1, SG2, and word lines WL1 to WL4 are reset to 0V at time t18. The signal BLC1 becomes L at time t19, the signal PRE1 becomes H at time t20, and the bit line BLi is reset to 0V at time t20.

【0218】

The signal PRO2 becomes L (t27), and the memory cell corresponding to the data storage circuit that stores the control data of 2 stores the 2 data. The detection of whether or not the data has been reached (verification reading of data "2") is completed. At this point, if it is detected that the memory cell corresponding to the data storage circuit that stores the "3" control data has reached the state of storing the "3" data, The control data of the data storage circuit 10 has been changed to "0" data.

【0219】

Data only when it is detected that the memory cell corresponding to the data storage circuit storing "2" control data has reached the state of storing "2" data. The control data of the storage circuit 10 has been changed to "1" data. Otherwise, the control data is retained (unchanged).

【0220】

Next, the operation of detecting whether or not the memory cell corresponding to the data storage circuit storing the "1" control data has reached the state of storing the "1" data is started. ..

【0221】

First, the signal PRE1 becomes L and BLC1 becomes H, and the bit line BLi is selected. When the signal PREC becomes VCC and the signal BIAS becomes 2V, the bit line BLi is charged to 1V (t30). The signal BIAS becomes 0V and the charging of the bit line BLi ends (t31).

【0222】

Then, the signal PREC becomes 0V, and the charging of the throat Nsense is completed (t32). The selected gates SG1 and SG2 of the selected block, and the non-selected word lines WL1,3,4 are set to 4V, and the selected word lines WL2 are set to 0.4V (t32).

【0223】

When the selected word line WL2 reaches 0.4V, the memory cell corresponding to the data storage circuit that stores the control data of 1 reaches the state of storing the 1 data. If so, the bit line BLi remains at 1V. If the memory cell corresponding to the data storage circuit that stores the "1" control data has not reached the state of storing the "1" data, the bit line BLi will be 0.7V or less. ..

【0224】

After a certain period (t7 ~ t18), the signal BIAS is set to 1.8V. If the memory cell corresponding to the data storage circuit that stores the "1" control data has reached the state where it stores the "1" data, the node Nsense remains at 2V. is there.

【0225】

If the memory cell corresponding to the data storage circuit that stores "1" control data does not reach the state that stores "1" data, the node Nsense will be 0.8V or less. Become. After the signal BIAS becomes 0V again and the bit lines BLi and Nsense are cut off, the signal PRO2 becomes 1.3V (t34).

【0226】

At this time, when the second subdata is 1, the node Nsense is set to 0V by the n-channel MOS transistor Qn10. At this time, when the second subdata is 0, the node Nsense is only set to 0.3V at most by the n-channel MOS transistor Qn10.

【0227】

Originally, when Nsense is 0.3V or higher, the potential of Nsense does not change because Qn10 is non-conducting. After this, the signal VRFY1 becomes VCC (t36). Only when the first subdata of the first subdata circuit is 0, the Nsense becomes 2V by the n-channel MOS transistors Qn5 and Qn6. At this time, the potential VREG is VCC (t36 to t38).

【0228】

The signals SEN1 and LAT1 become L and the clock synchronous inverters CI1 and CI2 are deactivated (t38). When the signal PRO1 becomes H (t39) and the signal SEN1 becomes H (t40), the clock synchronous inverter CI1 is activated and the potential of the node Nsense is sensed.

【0229】

When the signal LAT1 becomes H (t41), the clock synchronous inverter CI2 is activated and the logic level of the sensed signal is latched.

【0230】

The selected gates SG1, SG2, and word lines WL1 to WL4 are reset to 0V at time t33. The signal BLC1 becomes L at time t34, the signal PRE1 becomes H at time t35, and the bit line BLi is reset to 0V at time t35.

【0231】

The signal PRO1 becomes L (t42), and the memory cell corresponding to the data storage circuit that stores the control data of 1 stores the 1 data. The operation of detecting whether or not the data has been reached (verification reading of data 1) ends.

【0232】

At this point, when it is detected that the memory cell corresponding to the data storage circuit that stores the control data of "3" has reached the state of storing the "3" data. , When it is detected that the memory cell corresponding to the data storage circuit that stores the control data of "2" has reached the state of storing the "2" data, and "1" Data storage circuit only when it is detected that the memory cell corresponding to the data storage circuit that stores the control data of "1" has reached the state of storing "1" data. The control data of is changed to 0 data, otherwise the control data is retained (not changed).

【0233】

The write verification operations are performed in the order shown in FIGS. 14, 15 and 16.

【0234】

In the write verify operation, the control data stored in the data storage circuit 10 is changed from the write state of the memory cell as shown in Table 4.

【0235】

[Table 4]

<img file="JPP3481817B2_D0004.tif" />【0236】

The write operation shown in FIGS. 10, 11, 12 or 13 and the write verify operation shown in FIGS. 14 to 16 are repeated until all the control data becomes 0, and the data to the memory cell M is repeated. Writing (program) is performed. Whether or not all the control data has become "0" can be known by detecting whether or not the signal PT is conducting with the ground level.

【0237】

That is, the semiconductor storage device in the present invention has a memory cell M, a bit wire BL connected to the memory cell M, a gate electrode, a source electrode, and a drain electrode, and the bit wire in the source electrode. The MIS transistor Qn14 connected to the switch element Qn14 and the switch element Qn13 connected to the drain electrode are provided, and the bit wire BL is charged by conducting the switch element Qn13 and applying the first potential to the gate electrode. After that, the gate electrode is set to a second potential different from the first potential and amplifies the potential of the bit line BL which fluctuates according to the data of the memory cell M.

【0238】

Further, as a desirable embodiment of the present invention, the following can be mentioned.

【0239】

The switch element Qn13 is made non-conducting while the second potential is applied to the gate electrode of the MIS transistor Qn14. The MIS transistor Qn14 is an n-channel MIS transistor, and the first potential is higher than the second potential. The capacitance of the bit wire BL is larger than the capacitance connected to the drain electrode.

【0240】

Further, the semiconductor storage device in the present invention is a NAND type memory cell unit in which memory cells M having a predetermined number of MIS transistor structures are connected in series between the first and second selection transistors S having the MIS transistor structure. A first potential is applied to the gate electrode of the selected memory cell M, a second potential is applied to the gate electrode of the memory cell M adjacent to the selected memory cell on the second selection transistor side, and the remaining memory A third potential is applied to the gate electrode of the cell M to perform writing, and the first potential here is set higher than the third potential, and the third potential is set higher than the second potential. ing.

【0241】

Further, as a desirable embodiment of the present invention, the following can be mentioned.

【0242】

The first-choice transistor S is connected to the bit line BL, and the second-choice transistor S is connected to the source line SRC. Writing is sequentially performed from the memory cell side adjacent to the second selection transistor S to the memory cell side adjacent to the first selection transistor S.

【0243】

Of the remaining memory cells M, a fourth potential is applied to the gate electrode of the memory cell M on the second selection transistor S side of the selected memory cell M, and of the remaining memory cells M, from the selected memory cell M. A fifth potential is applied to the gate electrode of the memory cell M on the first-select transistor S side to charge the channel of the memory cell M in advance before writing.

【0244】

Of the remaining memory cells M, a fourth potential is applied to the gate electrode of the memory cell M on the second selection transistor S side of the selected memory cell M, and of the remaining memory cells M, from the selected memory cell M. A fifth potential is applied to the gate electrode of the memory cell M on the first selection transistor S side, and a fourth potential is applied to the gate electrode of the selected memory cell M to preliminarily set the channel of the memory cell M. Write after charging.

【0245】

Of the remaining memory cells M, the fourth potential is applied to the gate electrode of the memory cell M on the second selection transistor S side of the selected memory cell M, and among the remaining memory cells M, the second from the selected memory cell M. 1 Apply the 5th potential to the gate electrode of the memory cell on the selection transistor S side, apply the 5th potential to the gate electrode of the selected memory cell M, and charge the channel of the memory cell M in advance. Write from.

【0246】

The memory cell M has an n-channel MIS transistor structure. The 4th and 5th potentials are lower than the 3rd potential, and the 4th potential is higher than the 5th potential.

【0247】

Of the remaining memory cells M, after the third potential is applied to the gate electrode of the memory cell M on the second selection transistor S side of the selection memory cell M, the selection memory cell M of the remaining memory cells M A third potential is applied to the gate electrode of the memory cell M on the first selection transistor S side.

【0248】

Of the remaining memory cells M, after the third potential is applied to the gate electrode of the memory cell M on the second selection transistor S side of the selection memory cell M, the selection memory cell M of the remaining memory cells M A third potential is applied to the gate electrode of the memory cell M on the side of the first selection transistor S, and the first potential is applied to the gate electrode of the selected memory cell M.

【0249】

As described above, the semiconductor storage device according to the present invention generates the channel potential of the memory cell at the time of writing 0 data independently of the threshold value of the memory cell in which the data is written. As a result, it is possible to realize a semiconductor storage device capable of sufficiently stably generating the channel potential of the memory cell at the time of writing 0 data.

【0250】

Further, in the semiconductor storage device according to the present invention, after charging a bit wire with a MOS transistor, the gate potential of the MOS transistor is changed. As a result, the MOS transistor can be made non-conducting in a short time after charging the bit wire. Therefore, it is possible to realize a semiconductor storage device that can detect the writing state of the memory cell at high speed and with high accuracy.

【0251】

The present invention is not limited to the above-described embodiment. In addition, various modifications can be made without departing from the gist of the present invention.

【0252】

[Effect of the invention]

The semiconductor storage device according to the present invention generates the channel potential of the memory cell at the time of writing 0 data independently of the threshold value of the memory cell in which the data is written. As a result, it is possible to realize a semiconductor storage device capable of sufficiently stably generating the channel potential of the memory cell at the time of writing 0 data.

【0253】

Further, in the semiconductor storage device according to the present invention, after charging a bit wire with a MOS transistor, the gate potential of the MOS transistor is changed. As a result, the MOS transistor can be made non-conducting in a short time after charging the bit wire. Therefore, it is possible to realize a semiconductor storage device that can detect the writing state of the memory cell at high speed and with high accuracy.

[Simple explanation of drawings]

[Figure 1]

The figure which shows the semiconductor storage device which concerns on embodiment of this invention.

[Figure 2]

The figure which shows the structure of the memory cell array and the data storage circuit of FIG.

[Fig. 3]

The figure which shows the structure of the memory cell and the selection transistor of FIG.

[Fig. 4]

The figure which shows the structure of the memory cell unit.

[Fig. 5]

The figure which shows the specific structural example of the data storage circuit which concerns on embodiment of this invention.

[Fig. 6]

The figure which shows the specific structure of the clock synchronous type inverter.

[Fig. 7]

The figure which shows the reading operation of the semiconductor storage device of embodiment of this invention.

[Fig. 8]

The figure which shows the reading operation of the semiconductor storage device of embodiment of this invention.

[Fig. 9]

The figure which shows the reading operation of the semiconductor storage device of embodiment of this invention.

[Fig. 10]

The figure which shows the 1st writing operation of the semiconductor storage device of embodiment of this invention.

[Fig. 11]

The figure which shows the 2nd writing operation of the semiconductor storage device of embodiment of this invention.

[Fig. 12]

The figure which shows the 3rd writing operation of the semiconductor storage device of embodiment of this invention.

[Fig. 13]

The figure which shows the 4th writing operation of the semiconductor storage device of embodiment of this invention.

[Fig. 14]

The figure which shows the write verification operation of the semiconductor storage device of embodiment of this invention.

[Fig. 15]

The figure which shows the write verification operation of the semiconductor storage device of embodiment of this invention.

[Fig. 16]

The figure which shows the write verification operation of the semiconductor storage device of embodiment of this invention.

[Explanation of symbols]

1: Memory cell array, 2: Bit line control circuit, 3: Column decorator, 4: Data I / O buffer, 5: Data input / output terminal, 6: Word line control circuit, 7: Control signal and control potential generation circuit, 8: Control signal input / output terminal, 10: Data storage circuit, 11: p-type semiconductor substrate, 12: n-type diffusion layer, 13,17: Gate insulating film, 14: Floating gate, 15: Insulating film, 16: Control gate, 18: Selection gate, M : Memory cell, S: Selective transistor, WL: Word line, BL: Bit line, SG: Select gate, SRC: Source line, Qn: n-channel MOS transistor, Qp: p-channel MOS transistor, VCC: Power potential, CI: Clock synchronous inverter.