Untitled record

[Detailed Description of the Invention]

Technical field The present invention relates to the peripheral equipment controller of a data processing system including the transmission means which carries out interconnection of a processing unit suitable for generating two or more circumference commands (command word), and transmitting to a peripheral equipment controller, a processing unit, and the peripheral equipment controller. The background of an invention In a certain kind of data processing system, a main processing unit has a thing with processing speed required to perform required calculation and control of an I/O device which Listen is as for nothing. It is known that it can be made to decrease by forming the secondary processing unit which the load of a main processing unit is controlled by a main processing unit, and performs processing required for an I/O device as one solution of this problem about data processing capacity. They are such a secondary processing unit a peripheral equipment controller and Call after this. In the system of conventional technology, a main processing unit sends a high-level command to a peripheral equipment controller typically, and a peripheral equipment controller performs control needed for an I/O device, in order to execute a command. As a peripheral equipment controller, the controller by the microprocessor or a micro program has been used conventionally. One circumference Patent Publication which comprises the micro-program-ized controller Showa 59-36282 Many I/O devices are controllable by a device control machine. If a microprogram control machine breaks down, the group of I/0 device can be used with a data processing system. It is I or intermediary To have that the method of using one microprocessor for every peripheral equipment controller dies well in the application as which a demand of reliability is low and conservativeness is seldom required. There is no such demand at many data processing systems. However, the demand conditions of the reliability of a system like an electric communications system and conservativeness are not such. If the present invention is followed, this problem contains the 1st timer circuit by which the circumference unit controller was connected to the 1st subprocessor and the 1st subprocessor, The 1st timer circuit generates the 1st timer completion signal after the predetermined time after [ 1st ] generating of the 1st timer control signal following the 1st timer start signal, The 1st subprocessor generates the 1st timer start signal following the 1st thing of the circumference commands received from the transmission means with the halt condition, and goes into a halt condition, The 1st confirmation message is transmitted to a processing unit via a transmission means following the 1st timer completion signal between halt conditions, The 2nd subprocessor has a halt condition, goes into a halt condition following the 2nd thing of the circumference commands which are connected to the 1st timer circuit and received from the transmission means, and receives the 1st timer completion signal between the halt condition, Synchronous operation is started between the 1st subprocessor, the 2nd confirmation message is transmitted to the processing unit via the transmission means, and it is solved by the method as which the 1st and 2nd confirmation messages display the synchronous operation of a subprocessor by this. The abstract of an invention The Nobuyori Taka peripheral equipment controller which has the synchronous subprocessor doubled in the data processing system according to the present invention to the advantageous thing and a timer circuit used for starting synchronous operation is provided. In order to start the synchronous operation of two subprocessors, the main controller of a system directs the circumference command (command word) which puts two subprocessors into operation. The 1st thing of a subprocessor puts a timer into operation following a circumference command, and both subprocessors go into a halt condition following a circumference command. A timer generates a timer completion signal after predetermined time, and both sub this 1st timer circuit generates an initialization timer completion signal at the predetermined time after reception of a timer initialization signal following the timer initialization signal, The 1st and 2nd microprocessor devices follow the initial timer completion signal between the halt condition. A peripheral equipment controller, wherein it starts synchronous operation and; and the 1st microprocessor device transmit the confirmation message which shows the synchronous operation of a microprocessor device to the processing unit following the initial timer completion signal further. in a peripheral equipment controller given in the 1st paragraph of the range of 3 claims -- : -- the 1st subprocessor, It consists of the 1st microprocessor device 300,301,302,304 and 2nd microprocessor device 307,308,309,311, and is the 1st timer circuit 100-a, It has the 1st output terminal that is connected to the 1st and 2nd microprocessor devices, and generates the 1st timer completion signal following the 1st timer starting signal, and the 2nd output terminal connected to the 1st microprocessor device, It consists of 1st subtimer 303 that generates a timer completion signal in the 2nd output terminal following the timer control signal from the 1st microprocessor device, and is the 1st timer circuit, A peripheral equipment controller by which 2nd subtimer 310 that has the output terminal connected to the 2nd microprocessor device, and generates a timer completion signal in the output terminal following the timer control signal from the 2nd microprocessor device further being included. in a peripheral equipment controller given in the 1st paragraph of the range of 4 claims -- : -- each of the 1st and 2nd subprocessors, It consists of bus means 214,215 which carries out interconnection of the memory device of relation at micro computer 200,204, related memory device FIFO2Ol, FIFO2O5, and each micro computer and it, Intermediary ing [ as ] which performs a function defined by a data word which each of the micro computer generated a memory read-out signal, and was memorized by memory device of relation. Each of a storage device transmits the data word which expresses the function to the micro computer of relation following the memory read-out signal from micro pair Utah of relation, The peripheral equipment controller includes interconnection means 220 which carries out interconnection of a memory device of the 1st subprocessor, and the memory device of the 2nd subprocessor further, While a memory device of the 1st subprocessor memorizes one of the data words specified by the circumference command following a circumference command. An intermediary cage [ as ] which transmits the address selection signal over a memory device of the 2nd subprocessor through generating and the interconnection means of an address selection signal, And a peripheral equipment controller, wherein the memory device of the 2nd subprocessor operates so that a data word specified by circumference command following the selection signal may be memorized. In a peripheral equipment controller given in the 4th paragraph of the range of 5 claims, it is each of; this memory device, It consists of devices 519 and 520,521,522,523 which resemble memory measure 532, and first in / the first out method and Recovery means 501 and 502,516,517,518, therefore access the memory measure, The memory device of the 2nd subprocessor contains control flip flop 505 which has the 1st and 2nd stable states further, And the peripheral equipment controller operating so that a data word may be memorized in the memory measure, when the flip flop is in the 1st stable state following the address selection signal. in a peripheral equipment controller given in the 1st paragraph of the range of 6 claims -- : -- the 1st subprocessor, The 1st microprocessor 300 and 2nd microprocessor 307; 1st clock generator means 801 for generating Twins stable means 506; which has the 1st and 2nd stable states, and the 1st oscillation output signal is included, The 2nd subprocessor includes 2nd oscillator means 801 for generating the 2nd oscillation output signal, and is the 1st subprocessor, It is means 802,803,804 connected to the 1st and 2nd oscillator means, and is Then, When the 1st oscillation output signal is followed and this Twins stable means is in the 1st bistable state or the time of only the 1st oscillation output signal existing -- the 1st oscillation output signal -- therefore, the time of generating the 1st clock signal, following the 2nd oscillation output signal, and this Twins stable means being in the 2nd stable state or -- the time of only the 2nd oscillation output signal existing -- the 2nd oscillation output signal -- therefore, the peripheral equipment controller characterized by the 1st microprocessor following the 1st clock signal by that cause including means 802,803,804 to generate the 1st clock signal. in a peripheral equipment controller given in the 6th paragraph of the range of 7 claims --; -- the 1st subprocessor, the time of only the 1st oscillation output signal existing, when it is connected to the 1st and 2nd clock generator means 801 and this Twins stable means is in the 1st stable state following the 1st oscillation output signal -- the 1st oscillation output signal -- therefore -- generating the 2nd clock signal the time of only the 2nd oscillation output signal existing, when this Twins stable means is in the 2nd stable state following the 2nd oscillation output signal -- the 2nd oscillation output signal -- therefore -- including 2nd means 901,902,903 to generate the 2nd clock signal The peripheral equipment controller characterized by the 2nd micro Prosser's following the 2nd clock signal by that cause. 8 It is Used with Transmission Means 102 Which Carries Out Interconnection of Processing Unit 101 Which Generates Two or More Circumference Commands and Transmits to Then and the Peripheral Equipment Controller 100 with Peripheral Equipment Controller of Data Processing System and the Processing Unit 101, and the Peripheral Equipment Controller 100, It consists of the 1st, 2nd subprocessor 100-B and lOO-d, 1st, and 1st timer circuit 100-a that were connected to the 2nd subprocessor, The 1st timer circuit generates the 1st timer completion signal in the 1st predetermined period after generating of the 1st timer starting signal following the 1st timer starting signal from the 1st subprocessor, While the 1st subprocessor generates the 1st timer starting signal following the circumference command received from the transmission means It went into the halt condition, and the 1st confirmation message was transmitted via the transmission means to the processing unit following the 1st timer completion signal from the 1st timer circuit between the halt condition, and the 1st subprocessor has transmitted initialization information to the 2nd subprocessor, The 2nd subprocessor 100-d goes into a halt condition following the circumference command received from the transmission means, Synchronous operation with the 1st subprocessor is started following having received the 1st timer completion signal from the 1st timer circuit between the halt condition, The 2nd confirmation message is transmitted to the processing unit via the transmission means, in the intermediary To have peripheral equipment controller [ as ] transmission of the 1st and 2nd confirmation messages indicates the synchronous operation of a subprocessor to be by this -- : -- 2nd timer circuit 100-c connected to the 2nd subprocessor 100-d is further included The 2nd timer completion signal is generated at the 2nd predetermined time after generating of the 2nd larger timer starting signal than the 1st predetermined time following the 2nd timer starting signal from subProsa of the 2nd timer circuit 2, The 2nd subProsa generates the 2nd timer starting signal further following a circumference command, and the 1st timer completion signal does not exist between the halt condition. The peripheral equipment controller transmitting the 3rd confirmation message to the processing unit following having produced the 2nd timer completion signal, and displaying the asynchronous operation of a subprocessor. 9 It is Used with Transmission Means 102 Which Carries Out Interconnection of Processing Unit 101 Which Generates Two or More Circumference Commands and Transmits to Then and the Peripheral Equipment Controller 100 with Peripheral Equipment Controller of Data Processing System and the Processing Unit 101, and the Peripheral Equipment Controller 100, It consists of the 1st, 2nd subprocessor 100-B and lOO-d, 1st, and 1st timer circuit 100-a that were connected to the 2nd subprocessor, The 1st timer circuit generates the 1st timer completion signal in the 1st predetermined period after generating of the 1st timer starting signal following the 1st timer starting signal from the 1st subprocessor, While the 1st subprocessor generates the 1st timer starting signal following the circumference command received from the transmission means It went into the halt condition, and the 1st confirmation message was transmitted via the transmission means to the processing unit following the 1st timer completion signal from the 1st timer circuit between the halt condition, and the 1st subprocessor has transmitted initialization information to the 2nd subprocessor, The 2nd subprocessor 100-d goes into a halt condition following the circumference command received from the transmission means, Synchronous operation with the 1st subprocessor is started following having received the 1st timer completion signal from the 1st timer circuit between the halt condition, The 2nd confirmation message is transmitted to the processing unit via the transmission means, Transmission of the 1st and 2nd confirmation messages should show the synchronous operation of a subprocessor by this. in an intermediary To have peripheral equipment controller --; -- bus means 100-m which carries out interconnection of the 2nd subprocessor to the 1st [ the ] is further included --; -- the 1st subprocessor follows a circumference command A peripheral equipment controller, wherein it transmits a subprocessor command to the 2nd subprocessor via the bus means and the 2nd subprocessor goes into a halt condition following a subprocessor command and a circumference command. Technical field The present invention relates to the peripheral equipment controller of a data processing system including the transmission means which carries out interconnection of a processing unit suitable for generating two or more circumference commands (command word), and transmitting to a peripheral equipment controller, a processing unit, and the peripheral equipment controller. The background of an invention In a certain kind of data processing system, a main processing unit has a thing with processing speed required to perform required calculation and control of an I/O device which Listen is as for nothing. It is known that it can be made to decrease by forming the secondary processing unit which the load of a main processing unit is controlled by a main processing unit, and performs processing required for a /O device as one solution of this problem about data processing capacity. Such a secondary processing unit is called a peripheral equipment controller after this. In the system of conventional technology, typically, a main processing unit sends a high-level command to a peripheral equipment controller, and in order to execute peripheral equipment controller Instruction, it performs control needed for an I/O device. As a peripheral equipment controller, the controller by the microprocessor or a micro program has been used conventionally. Many I/O devices are controllable by one peripheral equipment controller which comprises the micro-program-ized controller. If a microprogram control machine breaks down, the group of I/0 device can be used with a data processing system. It is I or intermediary To have that the method of using one microprocessor for every peripheral equipment controller dies well in the application as which a demand of reliability is low and conservativeness is seldom required. There is no such demand at many data processing systems. However, the demand conditions of the reliability of a system like an electric communications system and conservativeness are not such. If the present invention is followed, this problem contains the 1st timer circuit by which the circumference unit controller was connected to the 1st subprocessor and the 1st subprocessor, The 1st timer circuit generates the 1st timer completion signal after the predetermined time after [ 1st ] generating of the 1st timer control signal following the 1st timer start signal, The 1st subprocessor generates the 1st timer start signal following the 1st thing of the circumference commands received from the transmission means with the halt condition, and goes into a halt condition, The 1st confirmation message is transmitted to a processing unit via a transmission means following the 1st timer completion signal between halt conditions, The 2nd subprocessor has a halt condition, goes into a halt condition following the 2nd thing of the circumference commands which are connected to the 1st timer circuit and received from the transmission means, and receives the 1st timer completion signal between the halt condition, Synchronous operation is started between the 1st subprocessor, the 2nd confirmation message is transmitted to the processing unit via the transmission means, and it is solved by the method as which the 1st and 2nd confirmation messages display the synchronous operation of a subprocessor by this. the abstract of an invention -- the Nobuyori Taka peripheral equipment controller which has the synchronous subprocessor doubled in the data processing system according to the present invention to the advantageous thing and a timer circuit used for starting synchronous operation is provided. In order to start the synchronous operation of two subprocessors, the main controller of a system directs the circumference command (command word) which puts two subprocessors into operation. The 1st thing of a subprocessor puts a timer into operation following a circumference command, and both subprocessors go into a halt condition following a circumference command. A timer generates a timer completion signal after predetermined time, and both subprocessors start synchronous operation and transmit a confirmatory order (check word) to a main controller. It will be shown that two subprocessors are carrying out synchronous operation of both confirmatory orders having been received by the main controller. installing the 2nd timer in a peripheral equipment controller -- the 2nd subprocessor -- therefore, intermediary Stomach [ as ] which generates a timer control signal is also good. The 2nd timer generates the 2nd timer completion signal that occurs after a time timer control signal longer than the time of the 1st timer following the timer control signal of the 2nd subprocessor. When the 1st timer completion signal does not exist, the 2nd subprocessor transmits the confirmatory order which displays asynchronous operation following the 2nd timer completion signal to a main processing unit. Interconnection of the two more subprocessors is carried out, and following the 1st circumference command, to the 2nd subprocessor, the 1st subprocessor generates a special instruction and may transmit. The 2nd subprocessor goes into a halt condition next following a special instruction and the 2nd circumference command. Two microprocessor systems to Be complete of each of two subprocessors which synchronizes and operates is also good. A microprocessor system synchronizes by the initialization command from a main processing unit, by this, both microprocessor devices go into a halt condition, and both start synchronous operation following an initial timer completion signal. Therefore, the circumference controller according to the present invention comprises one pair which comprises the pair of the microprocessor system by which each of it synchronized of subprocessors which synchronized. If other features of the present invention are followed, each of two timer circuits relevant to the doubled subprocessor is divided into two subtimers. One subtimer generates the timer completion signal for initialization, and gives this signal to the microprocessor system of both subprocessors. Both subtimers are used by a microprocessor system, and give a timeout signal to a microprocessor system related between normal operations. Each doubled microprocessor of a subprocessor is called a micro computer, and the memory of first-in first-out (FIFO) relates to each micro computer. It is used for FIFO memorizing the data word received from the main processing unit which specifies the function which should be performed by the microprocessor. If one feature of the present invention is followed, interconnection of the FIFO memory of two micro computers will be carried out by the bus and the memory decoder circuit, and the data word transmitted from the central processing unit will be memorized by FIFO of both micro pair Utah. Thus, it will be guaranteed that become the same [ the data word memorized by the FIFO memory ], and the same function is performed by the micro computer of :A. The system which follows an advantageous thing at the present invention has a clock circuit and a control flip flop in each subprocessor. As for each of the clock circuit, the oscillator of each clock circuit is connected to the selection circuit and selection circuit of the clock circuit of another side including the oscillator and the selection circuit. The selection circuit of each clock circuit has a flip flop relevant to it in one state, That is, if it is shown that the oscillator which generates the clock output from the oscillator relevant to it and in which a related flip flop changes Then relation into the state of another side is immobility Tsukuru when the Klopp circuit of another side is immobility Tsukuru, the clock signal from the clock circuit of another side will be generated. Each clock circuit connects to a slave the oscillator connected with a slave clock when a control flip flop is [ the clock circuit of Then another side ] immobility Tsukuru at one state, To open -- the circuit which operates so that a slave may be connected to the oscillator of the clock circuit of another side, when it is shown that the oscillator in which a flip flop changes Then relation into the state of another side is immobility Tsukuru is included. A control flip flop is applicable to communication between input/output devices again, By this, an input/output device follows the input-and-output command from the 1st subprocessor, when a flip flop is in one state, and when a flip flop is in the state of another side, it comes to follow the input-and-output command from the 2nd subprocessor. Intermediary To have [ as ] which two subprocessors usually operate in instep mode, and an input-and-output command is compared by the matcher in that case, mistakes this when disagreement arises, and generates a signal. If other features of the present invention are followed, data can be transmitted to the 2nd subprocessor from the 1st subprocessor by the memory data transfer circuit of the 1st and 2nd subprocessors. The memory data transfer circuit of the 1st subprocessor, A data word is read in the memory relevant to it under control of the micro computer relevant to it, the data word is transmitted to the memory data transfer circuit of the 2nd subprocessor, and this is written in the data memory of the 2nd subprocessor by This X.

[Brief Description of the Drawings]

It seems that the present invention is more completely understood by the detailed explanation which referred to the attached drawing. Drawing 1 -- 1 of the present invention -- an example -- block diagram [ of a data processing system ]; -- Plock figure [ of the peripheral equipment controller with which Drawing 2 follows the present invention ]: -- one detail view [ of the micro computer with which the peripheral equipment controller doubled Drawing 3 ]: -- Guillotine memory access whose Drawing 4 is an element of a peripheral equipment controller (DMA) circuit: -- Drawing 5 -- detail view [ of the first in / first out memory (FIFO) circuit of Drawing 2 ]: -- timing diagram: which shows the relation of the signal with which Drawing 6 is used by the data input series of FIFO -- the details of the signal with which Drawing 7 is generated by the data output series of FIFO Shown timing diagram: Drawing 8 -- detail view; of the master clock circuit of Drawing 3 -- Drawing 9 -- detail view; of the slave clock circuit of Drawing 3 -- Drawing 10 -- detail view; of the input-and-output interface of Drawing 2 -- Drawing 11 -- detail view [ of the Strobe control circuit of Drawing 3 ]: -- Drawing 12 is one Plock figure of the microprocessor of Drawing 3. Plock 100 of Drawing 1 shows one example of the peripheral equipment controller according to the detailed explanation present invention. For explanation, the peripheral equipment controller is shown in the drawing as some communications systems containing processing unit 101, memory 103, and circumference bus system 102 which are shown in Drawing 1. Intermediary To have [ as ] which processing unit 101 runs the program in memory 103, and transmits a circumference command to peripheral equipment controller 100 via circumference bus system 102. Peripheral equipment controller 100 interprets a circumference command about each circumference command, and it sends a series of input-and-output commands to input/output device 105 or input/output device 106 through input-and-output bus system 0,104 or input-and-output bus system 1,107. Peripheral equipment controller 100 receives data from an input/output device via input-and-output bus system 0,104 or input-and-output bus system 1,107, and returns the result of circumference operation to processing unit 101 via circumference bus system 102. The arbitrary peripheral equipment which can receive and transmit data following the circumference command from peripheral equipment controller 100 may be sufficient as input/output devices 105 and 106. Peripheral equipment controller 100 is a device with high reliability which uses subprocessor 100-b and 100-d which can synchronize and can execute a command, and which were doubled. While both subprocessors synchronize and the command is executed, the subprocessor is operating in duplex mode. While only one subprocessor is executing the command which realizes the function of peripheral equipment controller 100, the subprocessor will operate in simplex mode. Timer circuit 100-a and 100-c by which each was connected to the subprocessor and which were doubled give a synchronized signal to a subprocessor. It will be specified that one of subprocessors turns into a master subprocessor with processing unit 101, and the subprocessor of the other will be specified by this as a slave. Two subprocessors communicate mutually via bus 100-m. The following examples show how to synchronize between initialization of peripheral equipment controller 100 by processing unit 101 by initializing between subprocessor 100 1b and subprocessor 100-d. In order to initialize a controller, processing unit 101 specifies subprocessor, for example, subprocessor, 100-b as a master subprocessor, and specifies another side, for example, subprocessor, 100-d as a slave subprocessor. Processing unit 101 transmits a circumference command to a master subprocessor via circumference bus system 102, and a master subprocessor starts execution of the function of a peripheral equipment controller in simplex mode by this. Using the circumference command of Additive, processing unit 101 sends an input-and-output state required to perform the function of a peripheral equipment controller, and control information, and a master subprocessor memorizes this state and control information in an internal memory. Processing unit 101 sends a circumference command to a slave subprocessor, and a slave subprocessor becomes maintenance mode by this. When it becomes maintenance mode, a slave subprocessor will run a maintenance program. In order to start a synchronous process, processing unit 101 sends a circumference command to a slave subprocessor, and it prepares it so that it may go into duplex mode. After performing a certain kind of initialization routine, a slave subprocessor scans cable 100-m, and looks for a subprocessor command. This subprocessor command is called again the microcomputer command from a master subprocessor by This X. Next, processor 101 sends the circumference command which starts a synchronous process to a master subprocessor. The next step for a synchronization is transmitting the input-and-output state control information memorized by the internal memory of the master subprocessor to the internal memory of a slave subprocessor. ing with the memory data transfer circuit where each subprocessor accesses the internal memory of a subprocessor. A memory transmission circuit transmits data among these selves via cable 100-m. A master subprocessor starts transmission by transmitting the information word of a micro computer command and the beginning. After the internal memory of slave Subbed Setusa is updated completely, a master subprocessor Set timer 100-a to 5 milliseconds, and executes a cease and desist order. A slave subprocessor Set timer 100-c to 7 milliseconds, and executes a cease and desist order. The completion signal of timer 100-a is combined with both a master and the subprocessor of a slave via conductor 100-f. If timer 100-a sends a completion signal to both subprocessors, this will start a synchronization mutually and will transmit the confirmatory order which is a confirmation message which indicates that operation is normal to processing unit 101. A slave subprocessor stops the timing sequence of timer 100-c. If timer 100-c transmits a completion signal to a slave subprocessor, it will be shown that mistake this completion signal since timer 100-a does not time out correctly, and a state exists. Although a master subprocessor is Up X of a halt condition, a slave subprocessor sends out a confirmatory order to processing unit 101. It tells that, as for this confirmatory order, Running does not have a master subprocessor to processing unit 101. A slave subprocessor performs simplex operation of a peripheral equipment controller. As this result, peripheral equipment controller 100 operates in the mode of a simplex or duplex. Peripheral equipment controller 100 is shown in Drawing 2 in detail. Each subprocessor contains a microcomputer, scanning machine response latch circuitry, a first-in first-out (FIFO) memory, a direct memory access (DMA) circuit, and random access memory (RAM). The memory data transfer circuit of a subprocessor is DMA relevant to it. Each micro computer contains programmable ROM (PROM) which memorizes the program one pair of microprocessors which synchronize and operate, and for microprocessors so that it may mention below in relation to Drawing 3. RAM2O3 and 207 memorize the input-and-output condition data which specifies the operation which arises in relation to the input/output device connected to input-and-output bus system 0,104 and input-and-output bus system 1,107. RAM2O3 and 207 may be formed with the element by which arbitrary numbers are marketed. Circumference bus system 102 comprises peripheral equipment bus 208 and scanning machine response bus 209. Next, Drawing 2 is explained in full detail about a Use synchronous process. It is necessary to realize a synchronization between microcomputer 200 and micro computer 204 in two subprocessors. If the circumference command for which processing unit 101 makes subprocessor 100-b simplex mode to subprocessor 100-b specified as the master subprocessor is produced, A circumference command is given to FIFO2Ol through peripheral equipment bus 208, and is read from FIFO2Ol by micro computer 200. Transmission of the circumference command for which processing unit 101 makes subprocessor 100-d maintenance mode to subprocessor 100-d specified as slave Sub nail Seta will transmit a circumference command through peripheral equipment bus 208, FIFO2O5, and bus 215. although internal state memory of subprocessor 100-b is RAM2O3 and this was made the function of the peripheral equipment controller with micro computer 200 -- an intermediary -- it is updated so that the right input-and-output state information may be memorized. In order for micro computer 204 to be able to synchronize with micro computer 200, the information included in RAM2O3 must be copied to RAM2O7. This data transfer is realized by DMA2l.2, DMA2l.3, and bus 217. Before performing data transfer, micro computers 200 and 204 must initialize the number and start address of a data word which should be transmitted, respectively by each of DMA2l.2 and 213. DMA provides the means for transmitting a micro pair Utah command between [ other than the function of data transfer ] micro computers for micro pair Utah. When subprocessor 100-d receives the circumference command which makes preparations included in duplex mode, micro computer 204 scans DMA2l.3 and searches for the micro computer command from micro computer 200. If a circumference command for subprocessor 100-d to start a synchronous process is received, micro computer 200 initializes DMA2l.2 and sends out a micro computer command to micro computer 204. If the micro computer command from micro computer 200 is received, micro computer 204 will initialize DMA2l.3, will read a word from DMA2l.2, and will memorize these words to RAM2O7. ing which waits to take out the RAM2O3 to 1st word and, as for DMA2l.2, for DMA2l.3 to read this word from the suitable register in DMA2l.2 since DMA2l.2 is already initialized by micro computer 200. Two DMA continues this operation until RAM2O3 to RAM2O7 is updated completely. If RAM2O7 is completely updated from RAM2O3, micro computer 200 will set up timer 100-a to clock 5 milliseconds, and will execute a cease and desist order. Micro computer 204 is set up to clock 7 milliseconds timer 100-c, and executes a cease and desist order. It is connected with conductor 100-f to a micro computer, and the timer completion signal of timer 100-a which occurs in 5 milliseconds produces interruption to both micro computers. If timer 100-a produces interruption in both micro computers, this starts a synchronization to Mutually and transmits the confirmatory order which shows that operation is normal to processing unit 101. These confirmatory orders are transmitted by a micro computer using scanning machine response Latchch 206 and 202. Micro computer 204 carries out Reset of the timer 100-c, and it keeps interruption from timer 100c from producing it. Since interruption from timer 100-c shows that timer 100-a did not time out correctly, it shows that an error exists. At this time, micro pair Utah 204 transmits again the confirmatory order which shows that micro computer 200 broke down to processing unit 101. Micro computer 200 and micro computer 204 will synchronize and execute a command by This X. In order to maintain a synchronization, the data read from peripheral equipment bus 208 and input-and-output bus systems 104 and 107 must be simultaneously read by both micro computers. The data in which an input/output device should be read from an input/output device in read-out at the time of Line intermediary To have is given to both input-and-output bus systems 104 and 107. About the data on peripheral equipment bus 208 in which a buffer is carried out by FIFO2Ol and FIFO2O5, the micro computer must read the same circumference command in both FIFO simultaneously. This is solved by writing simultaneously the arbitrary circumference commands currently written to FIFO of a master micro computer in FIFO of a Slave micro computer from peripheral equipment bus 208. FIFO2Ol and the internal data operation of 205 synchronize and operate. It is judged whether the micro computer synchronizes when some input-and-output commands are sent to an input/output device. As for all the commands sent to the input/output device, coincidence is taken by data matchers 211 and 219. If one of matchers shows disagreement, it means that micro computers 200 and 204 synchronize and this is not executing the command. If disagreement arises, both micro computers 200 and 204 go into maintenance mode. If permanent failure is found in maintenance mode, micro pair Utah of a direction which is not out of order will serve as simplex mode, and the micro computer of another side will serve as Up X in maintenance mode. If permanent failure is not found, the specified master micro computer serves as simplex mode, and becomes the specified slave microcomputer Maintenance mode. Micro computer 200 is illustrated in detail in Drawing 3. Micro computer 204 is not shown in detail in the drawing, in order are structurally equivalent to micro computer 200 and to make a drawing brief. Each micro computer contains the master microprocessor (microprocessor 300) and the slave micromicro processor (microprocessor 307) regardless of the specification. Microprocessor 300 is mentioned below in relation to Drawing 12. Microprocessor 300 expresses the micro computer which operates self-containedly with PROM3O4, master clock 301, PIC(priority interruption circuit) 302, local RAM3O5, transceiver 306, and bus 314. The microprocessor synchronizes and operates and the output is adjusted by matcher 319. If a microprocessor synchronizes and is not operating, matcher 319 is mistaken in both PIC3O2 and PIC3O9, sends out a signal, and produces interruption in the microprocessor relevant to each by this. If interruption is received, microprocessor 300 and microprocessor 307 will be tried so that it may re-synchronize. The purpose of master clock 301 is to generate the basic clock pulse demanded by microprocessor 300. Master clock 301 chooses the output of the crystal oscillator of itself, or clock 11 signal of conductor 318. Clock 11 signal is generated by the master clock circuit of the micro computer of another side of Drawing 2. By the function which chooses either of internal clock oscillator [ of itself of master clock 301 ], or clock 11 signals, also when one of the sources of a clock pulse breaks down, a clock pulse can be generated to micro pair Utah 300. Although slave clock 308 resembles master clock 301, it is the following point, and it is different intermediary To have. this does not have an internal crystal oscillator -- clock 11 signal on conductor 318 -- or a conductor -- either of clock 10 signals of the 317 ground is chosen. The guided clock pulse is transmitted to microprocessor 307. PROM3O4 can consist of memory devices of arbitrary numbers of marketing. PROM3ll is equivalent to PROM3O4. PROM3ll includes the program which should be run by microprocessor 300. Local RAM3O5 can consist of elements of marketing of an arbitrary number. Local RAM3l.2 is the same as that of mouth-Cal RAM3O5, and the purpose is to give memory to microprocessor 300 temporarily between execution of a diagnostic program. PIC3O2 is a priority interruption circuit with a mask function of microprocessor 300. PIC3O2 comprises an element of arbitrary numbers of marketing. The function of PIC3O2 is producing interruption to microprocessor 300, when an input signal is received. Microprocessor 300 reads PIC3O2 and it judges which input produced interruption. Microprocessor 300 sends a word for an input not to produce interruption to PIC3O2. PIC3O9 is the same as that of PIC3O2. Subtimer 303 is an element of arbitrary numbers of marketing which has three independent counters. Each counter has each completion signal output terminal. The time which should be clocked is determined by the word which microprocessor 300 writes in the timer via bus 314. Subtimer 303 is a device in which an address is possible for microprocessor 300. One of the outputs of subtimer 303 is signal RSTOUTL-0 on conductor 320, and this is connected to input terminal 12 of PIC3O2. RSTOUTL-0 is transmitted to the micro computer of another side of Drawing 2 again. Microprocessor 300 uses subtimer 303, in order to clock the fixed time. After the counter of subtimer 303 is Declination(ed) by O, a suitable output terminal will be in a *1" state, and will produce interruption to microprocessor 300 via PIC3O2. The point that subtimer 310 does not produce the signal similar to RSTOUTL-0 although subtimer 310 is the same as subtimer 303 is different intermediary To have. Instead, RSTOUTL-0 signal of subtimer 303 is connected to PIC3O9 via conductor 100-f. It seems that it becomes clear from explanation as to how a synchronization is realized between microprocessor 300 and microprocessor 307 which carry out such distinction and which carry out reason Will be described later. If it writes in and transceiver 306 gives the capability of read-out to microprocessor 300 to bus 214, it comprises an element of various marketing for which what kind of thing may be used. If transceiver 313 gives the capability to read bus 214 to microprocessor 307, it comprises an element of good various marketing anything. While microprocessor 300 and microprocessor 307 are synchronizing and operating, matcher 319 compares bus 314, and the data signal and HACKL signal on 315, and performs error detection. If disagreement is detected, matcher 319 will interrupt to microprocessor 300 via input 15 of PIC3O2, and will interrupt by carrying out a microprocessor 307VC pair via input 15 of PIC3O9. Any microprocessor can de-energize this interruption using the mask function of suitable PIC. Matcher 319 is a standard comparison machine which generates the signal on intermediary conductor 324 in AND of the output and the suitable control signal from a microprocessor. The process of carrying out micro computers 200 and 204 the same term was explained with reference to Drawing 2. Before synchronizing a micro computer, each pair of a microprocessor must synchronize. A process synchronous [ this ] is explained about microprocessors 300 and 307. Between initialization of peripheral equipment controller 100, processing unit 101 transmits RESET-0 signal to micro pair Utah 200 via peripheral equipment bus 208 and conductor 224, and carries out Reset of the microprocessor in micro computer 200 by this. 2theta Reset of the microprocessor 300 is carried out, and the diagnostic routine which checks the completeness is performed, and as this Set counter 2 of subtimer 303 and produces 5-millisecond interruption, it executes a cease and desist order next. Microprocessor 307 performs the same operation. When subtimer 303 applies interruption to microprocessors 300 and 307, this starts synchronous operation. Microprocessor 300 Set counter 2 to 5 milliseconds by carrying out the address of the subtimer 303 via bus 321, and writing in the suitable word for counter 2. The decrease part of the counter 2 is carried out, at the time of Noodle, this sends out *1" to conductor 100-f, and this is given to input 12 of PIC3O2 0. Conductor 100-f is connected to PIC3O9 again. When *1 * exists on conductor 100-f, PIC3O2 and PIC3O9 produce interruption to microprocessors 300 and 307. If subtimer 303 Kapi 1 *'' is produced, microprocessors 300 and 30r synchronize, and start operation, microprocessor 300 returns a confirmatory order to processing unit 101, and it is shown that the synchronization is realized. This confirmatory order is executed through bus 314, buffer 306, bus 214, scanning machine response Latchch 202 (Drawing 2), and scanning machine response bus 209 (Drawing 2). Operation of DMA2l.2 of Drawing 2, DMA2l.3, and bus 217 is explained in full detail next. The purpose of these circuits is to transmit data between RAM2O3 and RAM2O7 as a part of synchronization of micro computer 200 and micro computer 204. When transmitting data to RAM2O3 to RAM2O7, micro computer 200 accesses data from RAM2O3, and in order to transmit this data to DMA2l.3 via bus 217, it initializes DMA2l.2. Micro computer 204 initializes DMA2l.3, receives information from DMA2l.2 (going via bus 217), and writes this information in RAM2O7. As a part of initialization, each micro computer sends the information which indicates it to be a start address of the data which should be transmitted to DMA (a micro computer controls), and the number of the words which should be transmitted whether operation is read-out or it is writing. After It was which initialize and waits by carrying out DMA in order that micro computer 200 may read RAM2O3, DMA2l.2 requires the right of control of bus 214 from micro computer 200. 1) MA2l.2 obtains the data accessed from RAM2O3 via bus 214, and it resends this to DMA2l.3 via bus 217. DMA2l.3 requires the right of control of bus 215 from micro computer 204. Micro computer 204 receives DMA(going via bus 215)2l.3, ing in which DMA2l.3 has a right of control of bus 215 -- if things are told, DMA2l.3 will transmit an address, the data received from bus 217, and the write-in control signal of RAM2O7 to RAM2O7. After the writing to RAM2O7 is completed, DMA2l.3 sends a completion signal to DMA2l.2 via bus 217. After receiving the completion signal from DMA2l.3, DMA2l.2 accesses other words of RAM2O3. This process is continued until DMA2l.2 will access a number of words specified by micro computer 200 at the time of initialization. If information is transmitted to RAM2O3 to RAM2O7, like usual, DMA2l.2 becomes a master and DMA2l.3 becomes a slave. DMA circuit 212 is shown in Drawing 4 in detail. Since DMA2l.3 is the same as that of the structure of DMA2l.2, in order to make a drawing brief, it is not explained in full detail on a drawing. Micro computer 200 of Drawing 2 performs three operations about DMA2l.2. The 1st operation is reading and writing of the e-mail pox which are output register 402 and input register 403. These two registers are used for communication between two micro computers by micro computers 200 and 204. Output register 402 sends out the contents to DMA2l.3 through conductor 421, and input register 403 receives the data from DMA2l.3 via conductor 422. ing with the input register in which DMA2l.3 receives the data from conductor 421, and the output register which transmits data via conductor 422. Output register 402 is written in by micro computer 200 which executes a write-in command, and this produces the sequence of the following signals. 11 * * on conductor 417 which is the address and WL signal of FD23l.6 on conductor 214-a is sent out. The data on conductor 214-b is aligned and taken out to a clock by this transmission by the output of NAND gate 414 at output register 402. This address is decoded by functional decoder 400 which sends out *1" to conductor 423. When *1 * is received to both conductors 423 and 417, NAND gate 413 sends out *0 * * to NAND gate 414, and it makes it NAND gate 414 produce a clock in output register 402. Although used for the same address reading input register 403, micro computer 200 executes a memory read-out command. Becoming RL Signal 1 * on conductor 418 by execution of a read-out memory command, input register 403 will transmit the information to conductor 214-b by this. This address is decoded by functional decoder 400 and this sends out *1 * on conductor 423. if 1F * is received to both conductors 423 and 418, AND gate 415 will come out to 0R gate 416, and will send out 1", and the output will energize input register 403. Next, a micro computer reads the signal on conductor 214-b. The 2nd command executed is initialization of DMA controller 401. The element of arbitrary marketing may be sufficient as DMA controller 401. Micro computer 200 initializes DMA controller 401, and gives the number and command data of a start address and the word which should be transmitted. DMA controller 401 memorizes all of these pieces of information to the inside. By command data, DMA controller 401 determines the type of the operation which it should perform, and determines the internal state of itself so that it may be common to the DMA controller of this form. A start address shows the 1st address that should be accessed. DMA controller 401 carries out the decrease part of this start address until it finishes accessing all the words specified by the number of the words which should be transmitted. Micro computer 200 sends information to DMA controller 401 by executing a memory write-in command. When CS command of DMA controllers 4.01 is 61'', DMA controller 401 memorizes the information on conductor 214-b inside. When micro computer 200 executes the memory write-in command to DMA2l.2, 8 bits of the higher rank of an address are decoded by functional decoder 400, and this energizes DMA controller 401 via CS input through conductor 424 next. DMA controller 401 decodes 8 bits of the low rank read from the AD input, and judges the form of the information on conductor 214-b. An address bit is transmitted via conductor 434, transceiver 411, and conductor 214-a. Operation of the 3rd of DMA2l.2 is transmission and reception of the data between RAM2O3. The juniper which is transmission of as opposed to [ for explanation by This k ] DMA2l.3 in DDMA2l.2 of data. By Set(ing) flip flop 453, micro computer 200 specifies that DMA2l.2 transmits data to DMA2l.3, and starts transmission by Set(ing) D flip flop 454. When micro computer 200 executes a memory write-in command with the data of the address of FDO4l.6, and 0816, flip flop 453 is Set(ed) by the following sequence. When functional decoder 400 detects the address of FDO4l.6, and the data of 0816, this sends out *1* to conductor 425. between execution of a memory write-in command, micro computer 200 comes out to conductor 417, and sends out 1 * (WL signal). It lets NAND gate 456 pass and flip flop 453 is Set(ed) by *1" of both conductor 417 and conductor 425. When micro computer 200 executes a memory write-in command in the address of FDOl6, DMA demand D flip flop 454 is Set(ed) by the following sequence. The address of FDOO operates function decoder 400, *1" is sent out to conductor 427, and this gives a signal next to D input of D flip-flop 454. As for D flip flop 454, the output of NAND gate 444 is Set(ed) by the Noodle output in the end of a write-in command at *1 *. Since both conductors 443 and 427 have sent out *1 *, the outputs of NAND gate 444 are The [ between memory write-in commands ] O", and intermediary To have. The output of flip flop 454 is sent out to the DREQO input terminal of DMA controller 401 with conductor 428. If the output of flip flop 454 becomes *ゞ1'', DMA controller 401 will start transmission of Plock of the data from RAM2O3. DMA controller 401 sends out a HREQL signal (*1 *) to conductor 429 first. Micro computer 200 sends out a HACKL signal as *1" on conductor 430 following this, and cuts itself from bus 214. DMA controller 401 acts as Strobe of these bits by sending out 8 A bit of the higher rank of address A bit on bus 434, and sending out *1 * to conductor 436 (this is connected to the ADSTB output terminal). DMA controller 401 sends out 8 bits of the low rank of an address on (1) bus 434, (2) Make an AEN output terminal into *1*, by this, energize the output and Latchch 410 of transceiver 411 and connect with address conductor 214-a, (3) Make into *1 * the MEMR output terminal connected to conductor 432, and return this via buffer 412 with conductor 418 (RL signal). With these signals, RAM2O3 reads the memory site specified by the address on conductor 214-a, and it gives the accessed data to conductor 214-b. By making an IOW output terminal into *1 *, DMA controller 401 writes this data in output register 402. This signal is sent out to output register 402 with conductor 437 via NAND gate 414. Output register 402 transmits this information to conductor 421 next. Since flip flop 453 is Set(ed) previously, the signal on 437 Set flip flop 405 via data selector 445. When flip flop 453 is Set(ed), it makes the A input choose it as data selector 445. If flip flop 405 is Set(ed), it sends out *1 * to DMA2l.3 via conductor 438. Conductor 437 has sent out *O *, and when conductor 439 (CKL signal) has sent out *O", flip flop 405 beam Set is carried out by NOR gate 406. When DMA2l.3 answers by *0 * (PRIVRDY-1 signal) on conductor 409, flip flop 404 is Set(ed). When conductor 437 has transmitted *0 *, flip flop 404 beam Set is carried out. If flip flop 404 is Set(ed), this will transmit 11 * to the Ready input terminal of DMA controller 401 via conductor 440. If a Ready input terminal becomes *1 *, DMA controller 401 will access other words of RAM2O3. If DMA controller 401 is slave DMA, data will be written in RAM2O3 through conductor 214-b from input register 403. This operation is the same as that of the operation previously described except for a MEMW output terminal (this is connected to 431) and an IOR output terminal (this is connected to conductor 441) being used. Flip flop 453 is not Set(ed). Therefore, data selector 445 chooses conductor 441 (IOR output terminal). FIFO2Ol of Drawing 2 is shown in Drawing 5 in detail. The structure of FIFO2O5 is the same as the structure of FIFO2Ol, and since it is easy, it is not shown in a drawing in detail. Data is moved to the input of register 531 through conductor 551 via data selector 530 by control of timing generator 519 from either PUB2 or PUBl. As for data, data is transmitted to RAM532 via conductor 552 from input register 531. Micro pair Utah 200 empties register 533, and after It was which wait by carrying out, from RAM532, timing generator 519 transmits information to output register 533, and Set flip flop 539. When flip-flop 539 is Set(ed), it is shown that data can be further used by output register 533. It is shown that micro computer 200 took out information from output register 533 by carrying out Reset of the flip flop 539. Peripheral equipment bus 208 contains data bus PUB2538 and data bus PUBl537 further. Both data buses 538 and 537 transmit 24-bit data. It is specified whether by transmitting "1 *'' to conductor 507 (energization 0) or conductor 509 (energization 1), processing unit 101 is using either data bus PUBl537 or data bus PUB2538. For the object of explanation, I will assume processing unit 101 to have sent out information to data bus PUBl537. Processing unit 101 sends out data to conductor 537. Processing unit 101 sends out *1 * to conductor 507 again, and flip flop 501 is Set(ed) by this. Data selector 530 chooses data bus PUBl537. This is for the output of flip flop 501 to operate data selector 530 via 0R gate 516 and conductor 549, and to choose conductor 537. The output of flip flop 501 makes the ENAL signal of conductor 551 *O * via gates 516 and 518, and this starts the input sequence timing generator 519 was further indicated to be to Drawing 6. The ENAL signal is shown as line 602 of Drawing 6. Timing generator 519 sends out ENWH signal *1 * to conductor 547, and this energizes input register 531. Input register 531 contains SR flip flop previously Set(ed) by 0. It is transmitted to conductor 551 through data selector 530, and the data bit of the data bus PUBl537 ground is Set(ed) in register 531. Timing generator 519 chooses the address of input counter 520 as the address conductor of RAM532 through conductor 534 and data selector 523. This selection is performed by making the MSL signal on conductor 526 into *0 *, as shown in line 608 of Drawing 6. Input counter 520 contains the address of the position in RAM532 which should write in there the data which will seemingly be new. Timing generator 519 writes in RAM532 by making signal WFL of conductor 528 into *O *, as shown in line 604. Next, timing generator 519 carries out the increment of the input counter 520 by giving the pulse of *1 * to signal 11CL on conductor 524, as shown in line 605. Timing generator 519 carries out Reset of the input register 531 by giving the pulse of *1 * to the IRRH signal of conductor 548, as shown in (1) line 606, (2) Carry out Reset of the flip flop 501 by giving the pulse of *O" to the ENRL signal of conductor 508, as shown in line 607. It tells that timing generator 519 moves the information from RAM532 specified by output counter 522 to output register 533, Set flip flop 539, and a word is in output register 533 to micro computer 200. The sequence of the timing signal used for this operation is shown in Drawing 7. (1) If 0PPL signal of conductor 544 shown in line 704 became "1 *, the ENAL signal of conductor 551 shown in (2) line 706 became *1" and (3) subtraction machine 521 has transmitted 8F" to conductor 525, Timing generator 519 makes ''1 * pulse signal BCH on conductor 529, as shown in line 701. As for the output of RAM532, signal BCH is given to output register 533 in the front tip of a BCH signal at the time of the pulse of *1 *, and Noodle. When an ENAL signal becomes *1 *, it is shown that processing unit 101 is not trying to write information in input register 531. "1" on conductor 525 shows that the word which should move to output register 533 from RAM532 exists. Timing generator 519 carries out the increment of the output counter 522 by giving the pulse of the IOCL signal which is *1 * to conductor 527, as line 703 shows. Becoming MSL signal (shown by line 705) The 1 * on conductor 526, this operates data selector 523 and gives the output of output counter 522 on conductor 535 to conductor 536 as an address to RAM532. flip-flop 539 is shown in line 702 -- as -- a conductor -- timing generator 519 which generates the pulse of the 542 ground Set. By Set of flip Floppe 539, flip Floppe 539 makes *0 * 0PPL signal on conductor 544, as shown in line 704. Micro computer 200 reads the word of 24 A bit from output register 533 as three data bytes who continued. A micro computer performs three memory read-out operations using address FCOOl6, FCOll6, and FCO2l.6. Address decoder 541 chooses the right byte from output register 533 by choosing data selector 540 appropriately and giving information to conductor 214-b. Micro computer 200 makes the output of flip flop 539 *1 * by making pulse signal RODPL on conductor 543 into *1 *. Flip flop 505 is a Die pose flip-flop, and this deals with ENABLEO-1 and ENABLEl-1 (it comes from FIFO2O5 via bus 220), when it Set by the same method as the output of flip flops 501 and 502. The circuit of Drawing 5 showing FIFO2Ol generates ENABLEO-0 and ENABLEl-0, it is transmitted to FIFO2O5 via bus 220, and this is dealt with in a similar way. When flip flop 505 is Set(ed), the circumference command transmitted to FIFO2O5 is received by FIFO2Ol, and is memorized by RAM532 synchronizing with FIFO2O5. Since these must receive the circumference command simultaneously from each of the FIFO, the synchronization with micro computers 200 and 204 is an important function. When Reset of the flip flop 505 is carried out by the Die pose reset signal on conductor 513, FIFO2Ol becomes independent of FIFO2O5. FIFO2O5 has the same flip-flop as flip flop 505 which determines whether this is operating independently with FIFO2Ol. Flip flops 506 are a master / slave flip-flop, this is Set(ed) by the master Set signal on conductor 514, and Reset is carried out by the master reset signal on conductor 515. The output of flip flop 506 is a MASTERO signal on conductor 553. The directions of a MASTERO signal are explained in detail in relation to a clock circuit, I/O interface 210, and matcher 211. The purpose of the MASTERO signal about 1 / O device is to determine whether to be ing in which which micro computer has a right of control of I/0 device. ing in which two microprocessors of both micro computer 200 and micro computer 204 have a clock circuit of itself in order to improve reliability. There are four clock circuits by all jams. When micro computers 200 and 204 synchronize and it is operating, In order to improve reliability, when the specified oscillator breaks down, the clock circuit must enable it to change to the oscillator of another side automatically, although the clock circuit must be driven with the same oscillator. ing in which micro computer 200 or the master clocks (master clock circuit 301 of Drawing 3) of 204 have an oscillator. The oscillator in which FIFO2Ol and the master flip flop of 205 are used is specified. Next, an automatic change when the specified oscillator breaks down is described. Master clock 301 of Drawing 3 is shown in Drawing 8 in detail. Data selector 804 chooses clock 10 signal and clock 11 signal so that it may be specified to the 1st table. It is detected whether single stable flip-flops 802 and 803 (as for this, it is advantageous considering it as a 74LS123 type re-trigger possible single stable integrated circuit) in which a re-trigger is possible have an active clock signal. It is 200% size from the cycle of clock 10 signal on conductor 318 during the timing of single stable flip flop 803 in which a re-trigger is possible. If oscillator 801 stops generating clock 10 signal on the right frequency, flip flop 802 in which a re-trigger is possible times out, makes the Q output *1 *, and this is transmitted to data selector 804 with conductor 805. Data selector 804 operates, as shown in the 1st table. ~ which wants to be cautious of not Q but Q output being used although single stable flip flop 803 in which a re-trigger is possible operates similarly Slave clock 308 is shown in Drawing 9 in detail. In the circuit of Drawing 9, it is different intermediary To have that oscillator 801 does not exist although it operates like the circuit of Drawing 8. It is indicated in Drawing 10 as input-and-output interface 210 and the input-and-output matcher of Drawing 2 in detail. Input-and-output interface 218 and matcher 219 are the same. Input-and-output interface 210 comprises elements 1001 thru/or 1006, and ON appearance Kachatya 211 comprises elements 1007-1008, 1015, and 1016. Micro computer 200 performs read-out and the writing from an input/output device by executing read-out and a memory command of writing. Address decoder 1001 and decoder 1003 decode these read-out and a memory command of writing, and act as Strobe of the suitable Energetic-Do on control bus 222. The input-and-output data of input-and-output data bus 0221 is compared with the information on input-and-output data 1 bus 223 about a command of each read-out and writing. In a write-in command, micro computer 200 transmits an address at conductor 214-a, transmits data to conductor 214-b, and gives the pulse of *0 * to WL lead. An address is decoded by address decoder 1001 and this makes the signal on conductor 1009 *1 *. If the MASTERO signal on conductor 553 is *1", AND gate 1002 will give WL signal to the output via NAN[gate 1004. The output of AND gate 1002 acts as Strobe of the decoder 1003. 6 bits of the low rank of the address of decoder 1003 Conductor 214-a are decoded. It is condition To be dashed so that data may be given to input-and-output data 0 bus 221 by *1 * of conductors 1009 and 1012 as for transceiver 1005. If conductor 554 is in a *1 * state, the output of inverter 1015 will give conditions to gate 1016, and then AND gate 1002 will give a clock to flip-flop 1007. Flip flop 1007 carries out the sample of the output of comparison machine 1008, and this will display an error, when input-and-output data 0 bus 221 and input-and-output data 1 bus 223 do not contain the same data. boil flip flop 1007 micro computer 200 -- Reset is carried out by the ICL signal on conductor 1013 which can give the pulse of 0 * * by One. The output (error signal on conductor 1014) of flip flop 1007 is given to the interruption mechanism of micro pair Utah 200. The Strobe control 328 of Drawing 3 is shown in Drawing 11 in detail. The Strobe control 328 operates by each output with an address peculiar on bus 314-a of decoder 1106. If address decoder 1101 detects one of these addresses, and WL signal on bus 314-c, decoder 1106 will give the pulse of *O" to the suitable output. It is determined which output decoder 1106 gives a pulse by decoding bus 314-a again. If both the outputs of the output of address decoder 1101 and inverter 1103 are *1 *, it will become Output 1 * of AND gate 1105, and this will give relevant conditions to decoder 1106. Data selector 1107 performs the same operation as decoder 1106 except this reading data via bus 314-b. When the suitable address for bus 314a exists and *1 * * is transmitted on RL signal of bus 314-c, data selector 1107 gives the state of conductor 544 to bus 314-b. Microprocessor 300 of Drawing 3 is shown in Drawing 12 in detail. Microprocessor 307 has the same structure as microprocessor 300, and it is not shown in a drawing in detail for conciseness. Microprocessor 1201 is like a throat among commercial various elements. Latch 1202 is like a throat among commercial versatility. Microprocessor 1201 receives input x1 (this is received through line 331) to a basic clock input from the master clock of Drawing 8. Microprocessor 1201 gives address information to bus 314-a, and gives data information to bus 314-b. Bus 314-c transmits and receives required control information. The above-mentioned composition should understand that other various composition is considered by the person skilled in the art, without deviating from that it is only a mere example of application of the principle of the present invention, and the soul and the range of the present invention.