Method for forming packet control list for controlling dma machine in packet data communication system, and format therefor

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Related patent specification]

This specification assigns a channel number to a received data packet, filed April 26, 1996 as U.S. Patent Specification Serial Number (TI-22691), a provisional patent specification, also referenced herein. "Methods, Devices and Systems for", a continuation of the current US Patent No.

【0002】

[Technical field to which the invention belongs]

The present invention generally relates to the field of electronic devices, more specifically to communication interface devices, and more specifically to control DMA machines in platform-designated communication interfaces compliant with IEEE standard 1394 and similar communication interface standards. For packet control list formats and methods for forming packet control lists.

【0003】

[Conventional technology]

Not only processing speed is important for many multimedia applications, I / O bandwidth is also a significant factor limiting applications on personal computers. To overcome this limitation, the IEEE1394 standard provides high-performance multimedia connections for camcorders, televisions, stereos, CD exchangers, set-top boxes, mixing consoles and music keyboards, as well as traditionally. It is possible with personal computer equipment. Known as the "FireWire" standard, IEEE1394 provides a bus interface standard for portable and desktop computer environments. The IEEE1394 standard serves as an important link technology between consumers and the computer market, describing serial buses driven by advanced communication protocols. The IEEE1394 serial bus is designed to provide the data transfer rates required for high performance peripheral buses at a low system cost.

【0004】

The IEEE1394 standard, developed by the Institute of Electrical and Electronics Engineers (IEEE) and its member computer companies, is a serial bus interface that enables low-cost, high-speed digital data transfer and communication. Transfer rates between devices can reach up to 400 megabits per second (mbps) and can be achieved via both asynchronous and equi-time interval data transfer modes. The IEEE1394 standard interface is itself suitable for video applications because it operates in a time-division system. For example, if the system were configured to output one frame every 1/15 second, it should be present in every packet that outputs at least one frame. The result is a smooth video. For this reason, the IEEE1394 standard interface is highly compatible with technologies such as Asynchronous Transfer Mode (ATM), which also operates in equi-time interval modes.

【0005】

The advantage of the IEEE1394 standard is the real-time transfer of data, which provides the ideal advantage for interconnecting multimedia applications. By using small, durable and flexible cables and cable connectors, the IEEE1394 standard saves money and eliminates the requirement for certain cable specifications. The IEEE1394 standard provides a general purpose I / O interconnect, which integrates I / O ports while consolidating printed circuit board space. In addition, the IEEE1394 standard provides a peer-to-peer communication structure, which allows peripherals to communicate directly with each other without imposing a load on the host device.

【0006】

The IEEE1394 standard provides a high-speed serial bus, which uses packetized data including headers. The header contains routing information. In addition, the packetized data includes payload data. The physical characteristics of the medium need not be designed for long-distance transmission. The IEEE1394 standard is designed for short distances, such as local area networks operating on desk buses. The distance is often longer than just a desk, but the IEEE1394 standard is not intended to be used in local area network operations. Therefore, basically the IEEE1394 standard provides serial and parallel buses for various media types such as audio, video and text to access devices such as workstations, home computers, televisions, VCRs and camcorders. Provides a fast interconnect to replace.

【0007】

When controlling a platform-designated IEEE1394 standard bus interface device, there is a demand to ensure that the data structure for directly controlling the memory access machine is optimized. There is a demand to minimize the number of PCI accesses in order to obtain the maximum amount of information while transferring data from one location to another. However, existing data transfer control schemes are unacceptable, because they fail to operate the associated DMA engine in an optimal manner that requires excessive I / O to memory. A control structure that minimizes the number of times the control information is accessed in order to reduce the number of memory accesses, and thus the amount of real time required to acquire the control structure, as opposed to the data actually transferred. Need to be adopted. The control structure that controls data transfer is an overhead item in data transfer and is not counted in data transfer or data transfer efficiency.

【0008】

[Problems to be Solved by the Invention]

Due to the above limitations, there is a need for methods and systems to specify the format of the data structures that will allow the DMA engine to operate in an optimal manner.

【0009】

There is a need for a method and system that can directly control the memory access engine while minimizing the number of I / O accesses to the data transfer device memory.

【0010】

In addition, there is a need for a mechanism that optimizes the amount of bandwidth that the direct memory access mechanism can support.

【0011】

In addition, there is a need for methods and systems that eliminate the need to load and unload source and destination addresses as well as control structures.

【0012】

INDUSTRIAL APPLICABILITY According to the present invention, a method and a system for generating a packet control list for controlling a direct memory access machine of an interface device conforming to IEEE standard 1394 or a similar communication standard are provided, which have been conventionally developed. It basically eliminates or mitigates the shortcomings and problems associated with methods and systems for controlling direct memory access machines.

【0013】

As one feature of the present invention, there is provided a method and a system for controlling the transfer of a data packet between a plurality of transmission locations and a plurality of reception locations, each of which is associated with a data transfer device. The method and system include procedures, circuits and instructions for allocating a predetermined space inside the memory and associating it with a data packet transfer device. Determining the next program list address for constructing the program control list from it is the next feature of the present invention. Yet another feature of the present invention is to construct or program a program control list for controlling a data packet transfer device when transferring a data packet from one of a plurality of transmission locations to one of a plurality of destination locations. Functions and structures for listing controls. The present invention further controls the operation of data packet transfer based on the program control appearing on the program control list.

【0014】

A technical feature of the present invention is to provide a method of specifying a format for a data packet transfer structure that acts directly on the memory access engine in an optimal manner.

【0015】

A feature of the present invention is to provide control of a direct memory access engine that minimizes the number of input / output accesses to the data transfer device memory.

【0016】

Another technical feature of the present invention is to provide a method of grouping data packets with each other, which can minimize the number of accesses to the data transfer device memory using a control language or format. Is.

【0017】

Yet another technical feature of the present invention is to provide a package control list formatting mechanism, which minimizes the intervention of the host processor in controlling the transfer of data from the source location to the destination location.

【0018】

Yet another technical feature of the present invention is a sequence of linked or pre-built control instructions that minimizes the access of the host processor to the memory of a bus interface device that complies with the IEEE1394 standard or similar communication standards. Is to be able to build.

【0019】

Another technical feature of the present invention is to allow the construction of linked or pre-built columns of packet control lists containing control instructions. This also minimizes access to the interface device memory of the host processor.

【0020】

Another technical feature of the present invention is to provide a method for further extending a program control list to autonomously and programmatically control data transfer within an interface device.

【0021】

Yet another technical feature of the present invention is to provide an optimal mechanism that requires a minimum amount of overhead to obtain an instruction to transfer data from a source location to a destination location.

【0022】

The present invention and its features will be more fully understood than the following description given with reference to the accompanying drawings. The same reference number in the attached drawings indicates the same event.

【0023】

BEST MODE FOR CARRYING OUT THE INVENTION

Submitted examples of the present invention are illustrated in the accompanying drawings, where the same numbers refer to the same corresponding parts across the various drawings.

【0024】

FIG. 1 conceptually illustrates the personal computer environment 10, which includes the personal computer 12 shown in the dotted box 12 and the associated peripherals shown in the dotted box 14. Various buses and nodes exist inside the personal computer 12 to control the operation of the personal computer. For example, the interface bus 16 supports communication between the 3-port physical layer interface 18 and the interface device 20 according to the present invention. The serial EPROM 22 supports the operation of the PCI interface device 20. The PCI interface device 20 further interfaces the PCI bus 24 with the auxiliary port local bus 26. In addition, the local bus 28 and the PCI handling devices 30 and 32 also communicate via the PCI bus 24. The PCI host bridge 34 performs the host bridge function between the local bus 28 and the PCI bus 24. Auxiliary port local bus 26 is a flash PROM (or RPL) Communicates with ROM) 36, direct memory access (DMA) channel control static RAM (SRAM) 38, user-defined function (AUX) 40, and zoom video (ZV) port 42 for video input / output. The host local bus 28 communicates with the host CPU 44 and the local memory 46.

【0025】

Peripheral devices 14 that communicate with the physical layer interface 18 include a CD ROM device 48, a laser printer 50, a desktop camera 52, and a digital videocassette recorder (VCR) 54 that interfaces with a video cable set-top box 56. ..

【0026】

In FIG. 1, the PCI interface ASIC20 transmits data packets between a device operating in an environment that supports the PCI bus 24 and a device operating in a high-speed I / O peripheral device environment established by, for example, the IEEE1394-1995 standard environment. Performs basic control functions. The PCI interface ASIC20 of this embodiment conforms to IEEE standard 1394-1995 and PCI specification version 2.0. In addition, the PCI interface ASIC20 performs the functions of the cycle master, especially in the IEEE1394-1995 environment, and has the ability to detect lost cycle start messages. The PCI interface ASIC20 generates a 32-bit Cyclic Redundancy Check (CRC) signal for IEEE1394 standard packet transmission, and also performs a 32-bit CRC check when receiving an IEEE1394 packet. The PCI interface ASIC 20 supports an equidistant barrier between the PCI interface ASIC 20 and the physical layer interface 18. In addition, the PCI interface ASIC20 supports IEEE1394 standard transmission speeds of 100, 200 and 400 mbps, as well as three sizes of programmable FIFOs (eg asynchronous transmission, equi-time interval transmission, and general reception).

【0027】

As described below, the PCI interface ASIC20 implements programmable channel address comparator logic on the received input data packets and assigns DMA channels to them. The present invention provides five scatter-gather DMA channels in at least one embodiment, where the data packet manipulation of each channel is (1) asynchronous packet transmission, (2) etc. It is programmed to support time-spaced packet transmission, (3) asynchronous packet reception, and (4) equi-time-spacing packet reception.

【0028】

The PCI interface ASIC20 also provides a PCI master bus function to support DMA operations, as well as a PCI slave function to provide read and write access to internal registers. To implement a 32-bit PCI address data path, the PCI interface ASIC20 provides not only PCI address data parity checking, but also software control over interrupt events. The PCI interface ASIC20 provides a programmable external local bus to provide a dedicated path to external logic. In addition, the PCI interface ASIC20 provides an 8-bit or 16-bit interface to the zoom video (ZV) port to transfer video data directly to an external motion video memory carrier.

【0029】

FIG. 2 presents block diagram 58, which shows the functional division of the PCI interface ASIC20 of the present invention. The logic in the PCI interface ASIC 20 includes the PCI bus logic 60, which includes the serial EPROM interface 62 for communicating with the serial EPROM 22. PCI master logic 64 and PCI slave logic 66, as well as PCI configuration control and status register 68, provide the logic needed to communicate with the PCI bus 24. The local bus interface logic 70 provides the control logic required to interface with the auxiliary port local bus 26.

【0030】

The DMA logic 72 in the PCI interface ASIC 20 includes a DMA engine 74 and a DMA control as well as a status register 76 to control the operation and communication between the PCI bus logic 60 and the FIFO logic 78. FIFO logic 78 includes general purpose receive FIFO 80, asynchronous transmit FIFO 82, equal time interval transmit FIFO 84, pointer address mapping logic 86, and FIFO control and status register 88.

【0031】

The link layer control logic 90 includes a control as well as a status register 92, which controls all functions in the link layer control logic 90 and reports the status. The packet transmission control logic 98 and the packet reception control logic 102 work together with the logic, the cycle timer 94 and the cycle monitor 96. The physical link interface logic 104 includes parallel / serial conversion as well as serial / parallel conversion functions.

【0032】

In FIG. 2, the PCI bus logic 60 executes the interface logic between the PCI interface ASIC 20 and the PCI bus 24. PCI Slave Logic 66 provides external PCI handling equipment with read and write capabilities to slave interface control logic, allowing PCI interface 20 control and status registers 68, 76, 88, 92 to be evaluated. These are required when application software controls the PCI interface ASIC20 and monitors its operating status. The PCI master logic 64 provides the DMA logic 72 with a function to start data transmission on the PCI bus 24 as a master device. The PCI configuration control and status register 68 can be used in the personal computer system 12 application software for configuring and programming the PCI interface ASIC20. It contains the controls and basic registers required by PCI, as well as interrupt controls and status signals for the PCI interface ASIC20 as well as other controls and status registers. Local Bus Interface Logic 70 includes RAM, ROM, auxiliary functions, a zoom video port, and auxiliary ports for interfacing and controlling four GPIO interfaces. Further, the serial EPROM interface 62 provides some configuration data required by PCI and certain system control register information after power-on.

【0033】

The serial EPROM interface 62 provides communication between the PCI interface ASIC20 and the serial EPROM22 (Figure 1). When the power is turned on, the serial EPROM interface 62 initializes a small part of the PCI configuration register 68 from the serial EPROM 22. Serial EPROM state All PCI slave access inputs are terminated in a retry state while the machine is accessing the serial EPROM22.

【0034】

The serial EPROM 22 also contains configuration data for PCI configuration control as well as status register 68. This information is read and written by the host CPU44, which emulates the 2-wire serial bus protocol through the control register for serial EPROM22. This 2-wire serial bus is manipulated by the host CPU44 to set the serial EPROM22 output enable bit to a value of "1", followed by data and clock bits to emulate the 2-wire serial bus protocol. to access. The PCI configuration control as well as the status register 68 includes a timer bit, which provides a time reference for timing a 2-wire serial bus protocol event.

【0035】

The PCI master logic 64 executes the control necessary for the PCI interface ASIC20 to operate the PCI bus 24 as a master device. This logic allows memory read, memory write, memory read line, memory write line, and write invalid instruction operations. Regarding the memory read function, as a result of the DMA read operation of the PCI interface ASIC20, the memory is read by the memory read line instruction on the PCI bus. Regarding the memory write operation, the PCI memory write is performed as a result of the PCI interface ASIC20 DMA write operation, or a memory write line instruction or a memory write invalid instruction is issued on the PCI bus.

【0036】

The PCI slave logic 66 executes the control logic required for the PCI interface ASIC20 to operate the PCI bus as a slave device. When enabled, the PCI slave function 66 responds to memory read or write instructions in the PCI memory address range specified by the basic address register contained in 68. The PCI slave logic 66 executes slave burst transfer when enabled by the slave burst bits in other control registers. The PCI slave logic 66 executes a destination-specified write operation when enabled by the control bits in other control registers.

【0037】

The PCI configuration control and status register 68 provides the system and application software with the ability to perform the PCI arithmetic configuration of the PCI interface ASIC20.

【0038】

Local bus interface logic 70 provides a special I / O port group that shares common logic. These ports are accessible from either the PCI bus 24 or the DMA engine 74. External devices on these ports cannot function as master devices. These ports connect the PCI interface ASIC20 to an external device or interface, allowing automatic data transfer to and from such devices. All local bus interfaces except the zoom video bus interface are synchronized to the local clock, which is provided by the PCI clock. The ZV port clock is programmed based on a PCI clock, an IEEE1394 clock, or an external clock.

【0039】

Local Bus Interface Logic 70 provides a shared local address bus, which in the present invention is a 16-bit address bus, shared 8-bit or 16-bit read or write data bus, with programmable wait states and ready conditions. Is. The local bus address and data bus are shared within the ROM, RAM, AUX, and zoom port functions. The ZV output port provides horizontal sync, vertical sync data enable, and ZV-PIXEL.CLR. Other inputs and outputs for Local Bus Interface Logic 70 include four general purpose I / O (GPIO) pins, which provide programmable directional and polar functions. Other signals in this embodiment of the local bus interface logic 70 include a local bus clock output, a reset output, an interrupt input, and an external ready input. The PCI configuration control and status register 68 provide the control instructions and information necessary to configure the operation of the local bus interface logic 70.

【0040】

The PCI interface ASIC20 includes a remote program load (RPL) read-only memory (ROM), which provides the personal computer 12 with the ability to read the boot code from the included RPL ROM. This allows the system to boot from an IEEE1394 device, even if the system loses a particular IEEE1394 boot code on power reset. Furthermore, the ROM interface is generalized and RPL It can also provide other functions than just accessing the ROM. Local Bus Interface Logic 70 supports PCI slaves and internal DMAs with read / write access to devices such as flash PROM36, SRAM38 and other RAM equivalents shown in Figure 1. Access to the ROM is controlled by PCI configuration control and status register 68, and is enabled by writing 1 to the least significant bit of the ROM basic address register. The ROM interface is either 8-bit or 16-bit wide data and can be configured as a specified number of wait states or similar functions. ROM options are configured via serial EPROM22 at power reset and are input via PCI slave access.

【0041】

The RAM interface is accessed through PCI configuration control and a register based on the second PCI memory in status register 68. This memory can be used as a DMA control structure or data buffer or as a shared memory interface to other functions such as digital signal processing equipment. The RAM interface is either 8-bit or 16-bit wide data and can be configured as a specified number of wait states or external ready paces.

【0042】

The auxiliary interface is a general purpose I / O port, which is accessed through PCI configuration control as well as the third PCI memory base address register in status register 68. This port is used to provide fast data paths to external dedicated resources such as compression / decompression logic or video processors / framebuffers. If a ZV port is enabled, one port in the AUX address space will be mapped to that ZV port. Otherwise, this space is available as part of the auxiliary address base of the submitted examples. In this embodiment, the auxiliary interface is either 8-bit or 16-bit wide data and can be configured as a specified number of wait states or external ready steps.

【0043】

The FIFO logic is designed around a single 256x33 clocked dual port RAM in the submitted examples and is split into three logical FIFOs. Each FIFO is programmed with a size of 0 to 256 words. For a given FIFO size combination, the sum of the three FIFO sizes must be 256 words or less.

【0044】

The general purpose receive FIFO (GRF) 80 contains a pair of read and write pointers and is used to access the FIFO dual port RAM. Each pointer counts in the range 0 minus its fifo_size_value. The FIFO RAM addressing range for each pointer is set by the logic that generates the offset value. Add that offset to the pointer value so that it maps to a unique range of RAM addresses. A working DMA channel uses a read pointer to read asynchronous or equi-time-spaced packets from the PCI side of RAM and write them into host memory. The write pointer is used by the IEEE1394 receiver to write asynchronous or equi-time interval packets received on the IEEE1394 bus to the link side of the FIFO RAM. The two pointers are communicated through the synchronization logic on both sides of the FIFO RAM because both sides of the FIFO dual-port RAM are in different clock regions.

【0045】

Asynchronous transmit FIFO 82 contains a pair of read and write pointers to access the FIFO dual port RAM. Each pointer counts in the range 0 minus its fifo_size_value. The FIFO RAM addressing range for each pointer is set by the logic that generates the offset value. Add that offset to the value of the pointer so that it maps to a unique range of addresses. A working DMA channel uses a write pointer to read an asynchronous packet from host memory and write it into the PCI side of RAM. The read pointer is used by an IEEE1394 transmitter, which uses the read pointer to read an asynchronous packet from the link side of the FIFO RAM and send it over the IEEE1394 bus. The two pointers are communicated through the synchronization logic on both sides of the FIFO RAM because both sides of the FIFO dual port RAM are in different clock regions.

【0046】

The equi-time interval transmit FIFO 84 contains a pair of read and write pointers to access the FIFO dual port RAM. Each pointer counts in the range 0 minus its fifo_size_value. The FIFO RAM addressing range for each pointer is set by the logic that generates the offset value. Add that offset to the value of the pointer so that it maps to a unique range of addresses. The operating DMA channel uses a write pointer to read equi-time-interval packets from host memory and write them into the PCI side of the FIFO RAM. The IEEE1394 transmitter uses a read pointer to read packets at equal time intervals from the link side of the FIFO RAM and transmits them on the IEEE1394 bus. Read and write pointers are communicated through the synchronization logic on both sides of the FIFO RAM because both sides of the FIFO dual port RAM are in different clock regions.

【0047】

The pointer dual-port address mapping logic 86 uses three size values from the FIFO size register to map each pair of FIFO read-write pointers to a unique address range in the FIFO dual-port RAM. The pointer address mapping function is generated based on the formula shown in the table below.

[table 1]

<img file="JPH1069456A_D0001.tif" />【0048】

FIFO control and status register 88 executes control of FIFO logic 78 and status register set. The FIFO control as well as the status register 88 includes a FIFO size register for setting the size of each logical FIFO. This register has parameters of three sizes and programs the sizes of equichronous transmit FIFO84, asynchronous transmit FIFO82 and general purpose receive FIFO80. This register is accessed via a PCI slave 66 read or write operation. The PCI side FIFO pointer write / read port is provided with a PCI slave 66 write / read port for software, which is for capturing or writing the current value of the PCI side pointer. The link-side FIFO pointer write-read port provides a PCI slave read port for software, which is used to capture or write the current value of the link-side pointer. The general purpose receive FIFO pop push port receives a 32-bit slave write and is pushed to the beginning of the GRF80 as a data quadlet (data). quadlet). A 32-bit slave read from this port pops off the data quadlet from the beginning of the GRF80. Asynchronous transmit FIFO pop-push port is a data quadlet that receives 32-bit slave writes to this port and is pushed to the beginning of the asynchronous transmit FIFO. A 32-bit slave read from this port pops off the data quadlet from the beginning of the asynchronous transmit FIFO 82. The equi-time-spacing transmit FIFO pop-push port is a data quadlet that receives 32-bit slave writes to this port and is pushed to the beginning of the equi-time-spacing transmit FIFO 84. A 32-bit slave read from this port pops off the data quadlet from the beginning of the equi-time-spaced transmit FIFO 84. The FIFO Control Token State Read Port provides a slave read and returns the value of bit 33 of the last data quadlet popped from one of the three previously accessed FIFOs. The FIFO diagnostic test and control register include a PCI slave read / write port for software, and construct the FIFO logic for controlling the diagnostic test and its operation. In addition, the transmit FIFO threshold register is provided with a PCI slave read / write port for software, and sets a transmission threshold for asynchronous and equichronically spaced transmit FIFOs.

【0049】

The CRC logic 100 executes logic that performs various functions, including the generation of a 32-bit automatic DIN CRC error code on the header portion of the packet data stream generated by the transmitter logic. The transmitter inserts this code into the data stream at the end of the header. For data packets with a data payload, CRC Logic 100 generates a 32-bit automatic DIN CRC error code on top of the data payload portion of the packet stream generated by the transmitter logic. The transmitter inserts this code at the end of the packet stream. CRC logic 100 generates a 32-bit automatic DIN CRC error code above the header part of the input packet data stream. If the calculated code is equal to the header CRC code sent with the packet, the receiver determines that the header is correct. In addition, CRC Logic 100 is a 32-bit automatic DIN Generate a CRC error code on top of the payload portion of the input packet data stream. If the calculated code is equal to the data CRC code sent with the packet, the receiver determines that the data payload is correct.

【0050】

The 1394 Link Layer Logic 90 executes the IEEE 1394 Link Layer Control Logic (LLC) as specified by the IEEE 1394-1995 standard. This feature controls the transmission and reception of IEEE1394 packet data between FIFO Logic 78 and other devices on the IEEE1394 bus.

【0051】

The 1394 link layer control and status register 92 executes the control and status register logic required by the application software to control the operation of the LLC and monitor the operation. The 1394 bus number / node number register provides an interface for application software to program the bus and node numbers. The 1394 link layer control register provides an interface for application software to control the operating mode of LLC. The 1394 link layer interrupt state register provides an interface for application software to decode the cause of the interrupt generated by LLC and a mechanism for canceling this interrupt state. The 1394 link-layer interrupt enable register provides an interface for application software to selectively enable the state bits in the interrupt state register to generate an LLC interrupt or disable the generation of an LLC interrupt. The 1394 cycle timer register provides an interface for application software to program the initial value of the cycle timer or read its current value. When LLC is operating as a cycle master, this timer is used to time the period at which packets are started to be sent every 125 microseconds. The 1394 physical layer access register provides an interface for application software to control the physical layer interface 18 as well as write or read data from the state register.

【0052】

The 1394 Diagnostic Test Control Register provides an interface for application software to perform diagnostic tests on 1394 LLC logic. The 1394 link layer control and status register 92 also includes a DMA channel 4-0 word 0 received packet comparison value register. The DMA channel comparator logic function is assigned to each register. The DMA channel comparator matches the set of bit positions selected in the comparison value register with the corresponding bit position of the first data quadlet (word 0) of the input packet. The bit position to match is specified by the mask value contained in the word 0 received packet comparison mask register. DMA Channel 4-0 Word 0 Received Packet Comparison The mask register is assigned to the corresponding DMA channel comparator. The DMA channel comparison logic uses the mask value in this register to select a bit position in word 0, which matches the corresponding bit position in the word 0 receive comparison value register. DMA channel 4-0 word 1 Receive packet comparison value register is assigned to the DMA channel comparator logic function. The DMA channel comparator matches the set of bit positions selected in the comparison value register with the corresponding bit position of the second data quadlet (word 1) of the input packet. The bit position to match is specified by the mask value contained in the word 1 received packet comparison mask register. Also, the DMA channel 4-0 word 1 received packet comparison mask register is assigned to the corresponding DMA channel comparator. The DMA channel comparison logic uses the mask value in this register to select a bit position in word 1, which matches the corresponding bit position in the word 1 receive comparison value register.

【0053】

In addition, the 1394 link layer control and status register 92 includes a busy retry count register, which contains the number of times the 1394 transmitter should retry asynchronous packet transmission when a busy affirmative confirmation is received from the destination node. It is specified. This register is read and written by PCI slave access from the application software. The busy retry time interval register contains a time interval that the transmitter should delay between subsequent retries when a busy affirmative confirmation signal is received for each attempt. This register is read and written from the application software via PCI slave access. There is also a state machine vector register, which gives the software the ability to monitor the state vector of each state machine built into LLC. In addition, the FIFO error counter counts the under-runs that occur in the asynchronous and equi-periodically transmitted FIFOs 82 and 84 during packet transmission and the over-runs that occur in the GRF80 during packet reception.

【0054】

The packet receiver control logic 102 executes the logic required to receive the incoming IEEE1394 packet. The receiver control logic meets the detailed functional requirements specified by IEEE1394-1995. They include the following features for using the bus and node ID registers and / or the DMA channel receive packet comparator to determine whether to receive an input asynchronous or equi-time interval packet. The CRC logic function checks the header CRC to confirm that the input packet is received correctly. If the packet has a payload, the data CRC is checked and if the packet passes the addressing and CRC checks, the received packet is loaded into the GRF80. The packet receiver control logic 102 generates an affirmative confirmation on the asynchronous received packet.

【0055】

The periodic timer logic 96 executes the logic for executing the periodic timer function. The periodic timer logic 96 meets the requirements of the periodic timer function specified in the IEEE1394-1995 standard. The periodic timer includes a periodic counter and a periodic offset timer. The offset timer is either free timekeeping, reloaded from low to high on the selected signal pin, or takes a reload value from the receiver, which is the cycle master in the 1394 LLC control and status register 92 and Selected based on the state of the periodic source bits. Periodic timers are used to support equal time interval data transfer. The cycle time is 32 bits wide. In this embodiment, the lower 12 bits are counted as a modulo 3072 counter modulo 3072, which is updated every 24.576 MHz clock period, or (40.69 nanoseconds). The next higher 13 bits count 8khz (or 125 microseconds) and the highest 7 bits count in seconds.

【0056】

The periodic monitoring logic 94 executes the logic for executing the periodic monitoring function. The periodic monitoring logic 94 supports equichronous data transfer, monitors LLC operations, and handles schedules of equichronous operations. When the cycle monitoring logic 94 receives or sends a cycle start packet, the cycle monitoring logic 94 indicates the occurrence of these events by generating a cycle start or cycle receive interrupt. The cycle monitoring logic 94 also detects the loss of the cycle start packet and generates a cycle loss interrupt. When the equi-time interval cycle is completed, the cycle monitoring logic 94 issues a cycle completion interrupt. The cycle monitoring logic 94 sends a signal to the transmitter to send a cycle start packet, when the cycle master enable bit is emitted in the 1394 LLC control as well as in the status register 92.

【0057】

The 1394 packet transmission control logic executes logic for controlling the movement for transmitting an IEEE 1394 packet from either the asynchronous transmission FIFO 82 or the equi-time interval transmission FIFO 84 to the physical link interface logic 104 on the IEEE 1394 bus. The transmission control logic 98 meets the functional requirements specified in the IEEE1394-1995 standard. The packet transmission control logic 98 formats the transmission packet format.

【0058】

The 1394 packet transmission control logic 98 pulls the quadlets from the asynchronous transmission FIFO 82 and correctly formats them into a 32-bit parallel 1394 asynchronous packet stream. The control logic 98 pulls from the equi-time-interval transmit FIFO 84 and correctly formats them into a 32-bit parallel 1394 equi-time-interval packet stream. The CRC logic is used to calculate the CRC code for the header and payload portion of the packet, and the control logic 98 inserts the CRC code into the time slot of the packet stream as required by the format of the packet being sent. The 1394 packet transmission control logic 98 inputs a parallel packet stream into the physical link interface logic and converts it from parallel to a serial data stream format for transmission to the physical interface.

【0059】

The 1394 packet transmission control logic 98 transmits a cycle start packet when the LLC is programmed to operate as a cycle master. The 1394 packet transmission control logic 98 transmits a 1394 transmission bus request to the physical interface. The physical interface layer arbitrates the bus and sends instructions to the transmitter to initiate transmission when the bus permission is received. The 1394 packet transmission control logic 98 executes retry transmission using the single-phase retry X protocol specified in the IEEE1394-1995 standard when a busy confirmation is returned in response to an asynchronous transmission packet. Further, the 1394 packet transmission control logic 98 sets the packet transmission speed.

【0060】

The physical link interface logic 104 executes the logic to interface the PCI interface ASIC20 to the physical layer chip. The physical link interface logic 104 meets the requirements of the link physical interface specification within the IEEE1394-1995 standard. This feature provides the PCI interface ASIC20 with access to physical layer services. The physical link interface logic 104 uses the packet velocity code from the transmitter to select the number of serial data streams to generate. If the speed code is set to 100 mbps, the parallel data streams are converted into two serial data streams, each sending at 50 mbps. If the speed code is set to 200 mbps, the parallel data streams are converted into four serial data streams, each sending at 50 mbps. The physical link interface logic 104 uses the speed display received by the physical interface to convert the input serial data stream from the physical interface into a parallel data stream of input to the receive control logic. For any input packet, the physical interface will generate two serial data streams to the PCI interface ASIC20 if the packet is received at 100 mbps and four serial data streams if received at 200 mbps. Generate. Each serial data stream is clocked at 50MHz. The physical link interface logic 104 receives serial state responses from the physical interface and converts them to parallel format. The state response carries the physical interface interrupt display and / or return data in response to a physical interface register read access request. The physical link interface logic 104 detects and receives serial affirmative confirmation packets and converts them to parallel format. In addition, the physical link interface logic 104 is a transmitter package. Receives send requests or read / write access requests to the physical interface register and formats them into a serial request stream for transmission to the physical interface. In addition, the physical link interface logic 104 optionally acts as an electrical equi-time interval barrier between the physical interface and the PCI-LYNX device.

【0061】

The DMA logic 72 uses the PCI master logic 64 to acquire the PCI bus 24 and functions as a master device. The DMA logic 72 includes a DMA engine 74, which includes a common state machine that is time-division-multiplexed. The DMA engine also includes arbitration logic for operating channels based on assigned priority levels. Further, the DMA control and the status register 76 provide data path control together with the PCI slave 66 for each DMA channel, and access these registers from the PCI interface ASIC 20.

【0062】

The DMA engine 74 executes state machine logic and fetches control parameters and data buffer pointers from the PCL. State machine logic or packet processing equipment uses these parameters to control data transfer between data buffers.

【0063】

FIG. 3 illustrates the header comparison logic contained within the 1394 packet receive logic 102, which receives the 32-bit packet data stream 106 from the physical link interface logic 104. The 32-bit packet data stream 106 enters the IEEE1394 packet receiver logic 102 and the header comparison logic indicated by reference number 110. The PCI slave 66 also provides 32-bit read / write access to the comparator control register contained in number 110. Line 117 shows the header comparison match output for DMA channel 0. Line 119 shows a header comparison match for DMA channel 1. Line 121 shows a header comparison match for DMA channel 2. Line 123 shows a header comparison match for DMA channel 3. Each of these outputs enters the priority encoder 128 and the OR circuit 129. The priority encoder 128 produces a DMA channel output 130, which enters the 1394 receiver logic 102. The logical OR circuit 129 provides a comparator match signal to the receiver control logic, where 0 indicates no match, or 1 indicates there is a match on line 132, which enters 1394 receiver logic 102.

【0064】

The DMA engine 74 is depicted as having five (5) or more independent DMA channels, all of which operate simultaneously. In practice, one main control state machine is used and the DMA channels are time-division-multiplexed. The time interval logic such as priority monitoring continuously examines the current contents of all channels and assigns the highest priority to the channel having the operation pending execution for the state machine.

【0065】

FIG. 4 illustrates the general concept described in FIG. 3 in more detail. In FIG. 4, the received data 106 includes header data 108 having words WD0, WD1. Words WD0 and WD1 are provided in each of the N DMA channel header comparison blocks of logic 110 (for example, the four channels 0 to 3 in FIG. 3). The DMA header comparison register for each DMA channel in logic 110 contains instructions in the circuit, which compares the match of header WD0 at 108 with select register content 120 and control value logic 122. Similarly, WD1 at 109 is compared with the contents of register 124 and the contents of select register 126 using a comparison instruction as shown in the figure. The output of the DMA header comparison register and logic is expressed as channel selection [0] to channel selection [N-1]. FIG. 4 further illustrates how the priority encoder 128 receives the channel selection output, generates a channel number on the DMA channel selection line 130, and outputs the address matching output 132. As illustrated in FIG. 3 and the accompanying text, the DMA channel selection output 130 and the address matching output 132 flow to the IEEE1394 packet receiver logic 102.

【0066】

The DMA header comparison register and logic 110 as well as the priority encoder 128 perform the logic necessary to determine if the incoming packet should be received and loaded into the GRF80. FIG. 3 shows four DMA channels, and five or more DMA channels are also within the scope of the present invention. Each DMA header comparison register and logic 110 is assigned to take charge of one DMA channel. One comparator contains the WD0 field selection register 122, the WD1 selection register 126, the WD0 comparison value register 120, the WD1 comparison value register 124, and the comparison equal time interval logic. The two field selection mask registers identify the bitfields in WD0 and WD1 of the input packet, which are matched by the expected values and the comparator logic. The two comparison value registers identify the expected bit pattern, which is matched against the selected bit fields in word 0 and word 1 of the input packet. The priority encoder 128 collects the DMA channel match indication from each DMA header comparison register and logic 110 and generates a bitcode for mapping the input packet to a particular DMA channel. The OR logic circuit 129 combines the DMA header comparison register and the selection display from logic 110 to generate a single comparator matching display for IEEE1394 receiver logic 102. The IEEE1394 receiver logic uses the DMA channel number and the comparator match display to determine if an input packet should be accepted into the GRF80.

【0067】

In this embodiment, the DMA packet processor operates as an independent DMA channel in which all are executed simultaneously. In the actual realization, one main control state machine is used, which divides the time into multiple DMA channels (for example, 5 DMA channels). The priority monitoring superisochronous logic continuously examines the current content of all channels, assigns the highest priority of the pending functions to that channel, and causes the state machine to perform it. To. The DMA channel is initialized to a static state after reset, and in this state waits for a valid PCL pointer to be written to the packet control list start address register, as well as channel enablement and link bits to be set in the DMA control register. The valid PCL pointer is determined by the bit zero state of the packet control list start address register. 1 indicates an invalid address and 0 indicates a valid address. The DMA then goes to the address indicated by the packet control list start address register, fetches a new address, and if valid, starts execution with this as the current PCL address.

【0068】

If this address is invalid, the link bit is cleared in the DMA control register, a DMA stop interrupt is generated for this channel with the associated state in the interrupt state register, and the channel is in the stopped state. This mechanism provides a sanity check on the PCL memory structure, as well as a relatively easy way to continue channel PCL execution if the next address link is lost. When a valid next PCL address is detected, DMA sets a BUSY bit in the DMA control register and fetches the first control word of the PCL offset section. Then, a check is performed to determine whether the instruction is received or transmitted, whether it is directed to the PCL or the local bus, or whether it is an auxiliary instruction. From the priority encoder 128, the channel with the highest priority with the match identifies the particular DMA channel to be selected, depending on which DMA channel is matched.

【0069】

FIG. 5 shows further details of the operation of the designated DMA channel header comparison logic 120 based on this embodiment. For example, the received data including the words WD0 and WD1 enters the header comparison logic 120. It contains the code segment 134 of word WD0, which is sent to the destination ID comparison logic 136. Part 138 of WD0 is sent to transfer code comparison logic 140. Part 142 of WD0 is sent to comparison logic 144, where WD0 bits 15: 6 and 3: 0 are compared. In addition, the comparison logic 146 receives bits 31:16, which is shown as part 148 of WD1. Comparison logic output from destination ID comparison logic 136, transfer code comparison logic 140, comparison logic 144 acting on WD0 bits 3: 0 and WD0 bits 15: 6, as well as comparison logic 146 output for WD1 bits 31:16 are AND functions. Entered in 150. The output of the AND function 150 is the channel selection output [x], which is the channel selection [0] to the channel selection [N-1], which the priority encoder 128 receives as described above. Then, the DMA channel selection signal 130 and the address matching signal 132 are generated.

【0070】

Figures 6, 7, 8 and 9 show details of the received data bits sent to the DMA channel header comparison logic 120. In particular, FIG. 6 shows the transfer code 160 including the asynchronous header 162 [7: 4]. Similarly, the transfer code bit 164 forms the bit [7: 4] of the equi-time interval header 166. In the designated DMA channel, the matching data set 168 includes a WD0 matching data header 170 corresponding to header WD0162 and a selected matching data set 172 corresponding to header 166. As shown in FIG. 6, the [7: 4] comparison bit 174 is changed by the [7: 4] bit 176 of the comparison selection WD0172 to determine the match result for the receive header WD0 bit [7: 4]. The output of this comparison equal time interval is ANDed with the other partial comparison equal time interval results to determine the match value 117 for the particular DMA channel.

【0071】

Figure 6 shows a possible target data value array for a particular field. The present invention attempts to capture received data in one field at a time and set a comparison word and a selection word to show possible ways to receive a particular result. In particular, Figure 6 shows a simultaneous comparison for the transfer code 160 field. One of the transfer code 160 or transfer code 164 provides an arithmetic code, which identifies the data type on the received data bus 16 and 1394 serial data as equichronous or asynchronous data. In the example shown in FIG. 6, the transfer code exists in the same field. This simultaneous comparison works equally well for both asynchronous and equi-time-spaced headers. There may be different ways to decode equichronous and asynchronous headers. They may be as illustrated or may be integrated with each other. The actual coding will vary, but the behavior is similar in that it will eventually be compared or not.

【0072】

Figure 7 highlights [3: 0] bits 178 and [15: 8] bits 180 in the asynchronous header 162, as well as [3: 0] synchronization bits 182 and [15: 8] channel bits 184 in the equi-time interval header 166. doing. Either the [3: 0] bits in the header WD0, the primary bits 178 or the synchronization bits 182 are modified by the [3: 0] bits 188 of the comparison selection WD0 shown by 172, and the [3: 0] bits of WD0 shown by 170. ] Compared to bit 186. Further, either the [15: 7] bits of the header WD0 indicated by 170, the [15: 7] bits 180 of the asynchronous header 162, or the [15: 7] bits 184 of the equi-time interval header 166 are the comparison selection WD0 indicated by 172. Compared to the [15: 7] bit 190 of the comparison WD0 shown by 170, modified by the [15: 7] bit of. The results of these match determinations that occur in FIG. 7 correspond to the WD0 bits [3: 0] and [15: 7] of the comparison logic 144 of the circuit 110.

【0073】

FIG. 8 shows yet another simultaneous comparison, which corresponds to the destination ID comparison logic 136 of the DMA channel comparison logic 110. Asynchronous header 162 contains a destination ID bit [31:15], which is represented by reference number 200. These identical bit positions, the [31:16] bits of the header WD0 indicated by 166, include the data length bits [31:16], which are represented by reference number 202 for equichronically spaced data packets. Similarly, the bits [31:16] of the individual link layer control registers 92, here indicated by reference number 204, include node number and bus number data. Figure 8 shows whether the asynchronous receive header WD0 shown in 162 or the equi-time interval receive header WD0 shown in 166 matches the [31:16] bits of the dataset 170 bits 206 modified according to the dataset 172 bits 208. The comparison is illustrated. Matching dataset 210 contains bits [15:11] as destination ID set bits 212. Based on the simultaneous comparison performed in FIG. 8, the DMA channel number is derived in logic block 146, which is sent to the AND function 150 of the DMA channel comparison logic 110.

【0074】

The high-order bits [31:16] of the asynchronous header WD0 can have a special meaning because the IEEE1394 standard handles destination identifiers. For example, IEEE1394 coding specifies broadcast-formatted messages in different headers. For the receiver header, compares the word 0 and bits election if there is a-option word 0, whereby it is possible to select a specific receive header word. In addition, each bit in comparison selection word 1 [15:11] 212 individually selects a specific destination ID simultaneous comparison expression.

【0075】

Figure 9 shows the asynchronous header 162, which contains the source ID bit [31:16] in 220. These bit positions 222 in the equi-time interval header 166 are part of the variable data. Within the WD1 comparison logic 146, the DMA channel 120 represents the bits 16-31 of the matching dataset 170 modified based on the comparison selection word 1 bit [31:16] indicated by 226 as the header WD1 bit [22 or 222. 31:16] and compare.

【0076】

FIG. 10 shows a register write circuit 250 for writing an arbitrary number of data register bits in a single register write operation. Circuit 250 illustrates one of any number of similar circuits. Each circuit controls one particular bit of any number of data bits. In the register write circuit 250, the general purpose I / O (GPIO) write data input 252 is connected to the data flip-flop 254. The data flip-flop 254 also receives the clock signal 256 and the writable input 258 from the AND function 260. The AND function 260 inputs a GPIO address approval signal 262, a write standard signal 264, and a GPIO address bit input 266. The AND function 260 supplies a writable output 258 to the writable bits 268 of the data flip-flop 254. Each GPIO write data 252 is written only to the flip-flop 254 whose individual specified address bits 266 are a1.

【0077】

The register write circuit 250 allows writing to only the bits that must be changed in the register, and saves the previous values of the remaining bits. The register write circuit 250 also allows software to change important bits without having to read, specify, or manipulate register bits that are not relevant to a particular operation.

【0078】

If the register address exists, writable bits 258, 1 to 4 GPIOs are written to it based on the address field.

[GPIO] Ax in the address number input 266 represents the address bit that is the basis of this writing, and determines whether to write to this bit. Write Strobe 264 tells you this is a write operation. GPIO address approval 262 is a basic address decoding signal for all registers. The writable input 258 to the flip-flop 250 is the output of the AND function. When writable is active, the input write data 252 is written to the flip-flop 254 and appears at the flip-flop output 270.

【0079】

Figure 11 shows the address field 272, which contains the GPIO register address bit 274 and the individual bit selection fields 276 address bits A0, A1, A2, and A3, which are the values of the associated bits in the address field 272, 0 or. Based on 1. The last two bits 278 of the address field 272 are usually considered to be zero values. The lowest 2 bits of address 272 are assumed to be zero, which is a requirement of the bus architecture. The following 4 bits designated as A0, A1, A2, and A3 allow 4-bit addressing individually or in different combinations. The higher or most significant bit is the individual address specific or assigned to this individual function. Therefore, there is a fixed bit pattern combination, which specifies the address of the given GPIO address value and selects a specific address. As a result, the entire array of addresses from 0000 to 1111 (ie, 16 different possible combinations) can be addressed.

【0080】

The DMA priority selector is responsible for activating the contents of the channels that have the most urgent need for PCI data movement. The DMA is configured as a main state machine (dma_fsm.v), which performs the state of the selected channel. The selected channel has a stored condition number of any one point at the same time. These stored conditions are called their context. Part of the channel's context is its current state running on the main state machine.

【0081】

State The machine has several idle states, in which it must wait until certain conditions are met that allow the channel to continue running. One obvious case is when the channel is idle or waits until the valid PCL address is loaded, the channelable bit is set, and the link bit is set. Another time is when the receive channel waits for data in the receive FIFO. If one channel is waiting for received data and the other channel is ready to transfer data to the transmit FIFO, we need to have that transfer done. This type of scenario occurs in many cases.

【0082】

One of these idle states represents an "opportunity window", where processing of another channel is performed. The priority selector monitors all these possible idle states and selects which state and channel has the highest priority at that time.

【0083】

FIG. 12 shows an example of a DMA instruction processed in the environment 300. In FIG. 12, the PCI register write data 302 is input to the multiplexer 304. DMA register write data 306 is also input to the multiplexer 304. The appropriate data source is selected in 308 based on the operation being performed. The output of the multiplexer 304 is input to the DMA register 310 and is shown in the figure to include 6 channels from channel 0 to channel 5 as an example. For each channel, the DMA field includes the previous address or provisional field 312, the current PCI address field 314, the data buffer address 316, the state 320, the instruction 322, the current state 324, and the ready bit 326. The DMA register write arbitration selection circuit 328 also provides an input to the DMA register 310, which responds to a PCI slave signal 330, a PCI master signal 332, a DMA PCI master periodic input 334, and a slave end input 336. The DMA channel arbitrator 340 receives the lock channel input 342 and provides an input to the multiplexer 346. The slave register read address input 348 controls the operation of the multiplexer 344. The DMA register read data output 350 returns the DMA register data to the PCI interface. The multiplexer 346 provides its output to the DMA state machine next state logic 352. The DMA status machine next status value 354 is written back to the status register and other output registers via the multiplexer 304. The output from the DMA instruction processing environment 300 includes FIFO read, write, and selection signals 356 as well as numerous signals.

【0084】

The DMA channel arbitrator 340 controls which channel should be executed. This arbitration is from FIFO 358, for example, "FIFO operating channel requests data" and "FIFO operating channel" as well as which FIFO is ready for data transfer and which channel is enabled and operating. It is based on the signal.

【0085】

The DMA register 310 executes control and sets the status register to control each DMA channel and monitor the status. The DMA register 310 supports many functions of each DMA channel. For example, the last packet control list start address / provisional register 312 provides registers that are updated by the DMA engine 74 when queuing during asynchronous transfer. It is also used as a temporary save register when auxiliary instructions load and store data. The packet control list start address register 314 is initialized by the application software and specifies the start point of the first (dummy) PCL in the PCL chain. The DMA engine 74 uses the next address loaded in this PCL to link to the first real PCL. The packet control list start address register 314 is updated by the operating DMA channel when the PCL is processed. The DMA buffer start address register 316 is loaded with the data buffer pointer fetched from the PCL when the operating DMA channel processes the PCL. The DMA status register 320 stores the ongoing count value of the number of bits transferred in this PCL, and also includes the completion status of the transfer. After the PCL processing is complete, the operating DMA channel writes the state information of this register back to the offset 0xC location in the PCL.

【0086】

The DMA control register 322 contains control bits that allow application software to enable or disable the operation of the DMA channel and reuptake the next address of the PCL for linking. The DMA control register 322 stores the data buffer transfer control, the transfer bit count value, and the instruction fetched from the PCL. The least significant bit of the DMA ready register 326 can wait until the DMA channel is ready before continuing to execute the XMT, RCV, LOAD, STORE, STORE0 or STORE1 instructions. This ready state is selected by the PCL control word (s). The least significant bit of the DMA ready register 326 allows conditional branching of the DMA channel during execution of the BRANCH instruction. This condition is selected by the PCL control word (s). The current DMA status register 324 stores the status vector of the DMA channel. This register is updated during the operating time of the DMA channel and holds the last state vector generated just before the channel stopped.

【0087】

The DMA register 310 can also include a received packet count value register (not shown), which includes the currently received packet count value. The DMA engine 74 loads this register with the received packet count value that has passed through the GRF80 token word. This count is decremented each time the data is transferred to the PCI bus 24. It is also possible to include a DMA global register (not shown), which includes a state flag that the state machine uses to track the execution of asynchronous transfer packets. This DMA global register stores the lower bound bit used with the cache line size register and determines the burst size required by the PCI master.

【0088】

FIG. 21 shows how the DMA channel is initialized after being reset to rest in section 135. Each DMA register 310 waits for a valid PCL pointer to be written to the packet control list start address register 314, and channel enablement and link bits are set in the DMA control register. The valid PCL pointer is determined by the 0th bit of the current packet control list (PCL) address register. A value of 1 represents an invalid address, and a value of 0 represents a valid address. The DMA then goes to the address specified in the current PCL address register start address register, fetches the next PCL address, and if valid, starts execution with this as the current PCL address. If this address is invalid, the link bit in the DMA control register is erased and a DMA stop interrupt is generated for this channel, and at the same time a related state is generated in the interrupt state register for this channel. It will be stopped. This mechanism provides a sanity check of the PCL memory structure, while at the same time providing a relatively easy way to continue channel PCL execution if the next address link is lost (ie disabled). When the DMA engine 74 finds a valid next PCL address, the DMA engine 74 sets the BSY bit inside the DMA control and status register 76 and fetches the appropriate PCL word. A check is then performed to determine whether the instruction is in the direction of receive, transfer, PCI or local bus, or an auxiliary instruction.

【0089】

FIG. 21 subsequently illustrates in section 137 how the DMA engine 74 operates to receive equidistant and asynchronous data within the GRF80. The DMA engine 74 performs a check to see if a standby state exists. If the standby state no longer exists, the processor enters the data transfer phase. Here, the DMA engine 74 enters the loop and checks whether the transfer count value is currently zero. In that case, a check is made to see if this is the final data buffer in the PCL buffer list. If this is the final buffer and the packet boundaries are not displayed by the link layer control logic 90 by writing the special control token word into the GRF80, an error will occur but this will result in more packets that the buffer can hold. This is because the data will be transferred. In this case, PKT The ERR bit is set in the DMA control and status register 76, and the DMA engine 74 flows the remaining data to the packet boundary. If the transfer count is currently reduced to zero and another buffer exists in the PCL list, the DMA engine 74 acquires a new buffer address and transfer count and executes the transfer.

【0090】

While moving the data from the GRF80 to the PCI interface logic 70, the DMA engine 74 waits until the GRF80 has enough data before making a transfer execution request to the PCI bus master. This transfer threshold is reached when one or two conditions are met. The DMA engine 74 makes a transfer request to the PCI master when the number of bits in the receive FIFO reaches the "high water level mark". This high water mark is greater than or equal to the cache line register or equal to the lower bound field of the DMA global register.

【0091】

The DMA obtains information on the data size of the packet from the link, when the packet was first written into the GRF 80 by the link layer control logic 90. This transfer count is used to determine if the data in the GRF80 is the rest of the data in the packet, and if so, the transfer count is the rest. Request a transfer of PCI master logic 64 equal to. While the DMA engine 74 transfers data, the data buffer start address register and data buffer transfer length bit in the DMA control and state register 76 are updated to reflect the current state of the transfer.

【0092】

When the link layer control logic 90 encounters the end of the packet, as shown in Section 139 of FIGS. 22 and 23, it writes a special control token word to the GRF80 to mark the end of the packet. Built into this control word is the state bit, which indicates the completion status of the packet on the bus. The DMA engine 74 uses the end mark of this packet to end the data transfer from the GRF 80 to the PCI bus 24. If the end-of-packet sign indicates the presence of an IEEE1394 busy affirmative confirmation signal, the DMA engine 74 reacquires the PCL's initial buffer address and transfer count and initiates the transfer of the entire packet. .. If the busy affirmative status is not displayed from the end mark of the packet, the DMA control and status register 76 loads the affirmative state passed from the link layer control logic 90 into the end mark of the packet, and the packet completion bit. Is set. The packet completion state is then written to the memory in the PCL state word, an interrupt signal is issued and latched into the corresponding bit in the interrupt state register. If the instruction was a receive and update instruction, the remaining transfer counts and next buffer address are written to the appropriate PCL offset.

【0093】

FIG. 13 illustrates Table 360 and shows the operation of the DMA channel arbitration circuit 340. Table 360 shows that if a channel is currently running on an IEEE standard 1394 bus, it has the highest priority in the DMA channel execution schedule. Otherwise, the channel priority is in channel number order, with 0 having the highest priority. The value "X" is assigned to the "ignore" value in 362 parts. This means that the currently running channel has the highest priority, regardless of the other values. That is, channels are scheduled on a first-come, first-served basis.

【0094】

The operation of DMA instruction processing is shown in the following example. Suppose the DMA is currently operating on channel 3. Therefore, all registers for channel 3 are selected via multiplexer 346 in DMA. DMA selects individual slices of registers to appear in the current and next state logics on the DMA state machine.

【0095】

FIG. 14 shows a simplified diagram of the personal computer environment 12 of the present invention, which includes an autoboot function 370. Pin 370 of the PCI interface ASIC20 provides a direct input to the autoboot PCI interface ASIC20. As a result, the PCI interface ASIC20 operates as a host device for PCI device # 1 with reference number 30 and PCI device # 2 with reference number 31 through the PCI bus 24. Autonomous operation instructions for PCI interface ASIC20 should use RPL ROM36 and SRAM38. Further, the PCI interface ASIC 20 communicates with the physical layer interface 18 through the interface bus 16.

【0096】

The automatic boot mode of the present invention is selected while the automatic boot pin 370 is operating (ie, when lifted). The automatic boot mode allows many features, which makes the PCI interface ASIC20 function autonomously. Autonomous operation uses DMA channel 0 to capture the address of the first packet control list after a power reset, including the following features: Also, after a power reset, the automatic boot mode allows the DMA master to access the external RPL ROM. In addition, after a power reset, automatic boot mode allows the DMA master to access the internal link registers.

【0097】

Once enabled as a master on the PCI bus 24, the PCI interface ASIC20 issues PCI configurations, inputs / outputs, and memory read and write instructions to the PCI bus 24 to give the appropriate address to control the packet control list. Specify the range. The external PCI address space is limited to 30 bits while operating in auto boot mode. The value of the most significant two address bits is always 0. Internally, these two bits are used to select PCI instructions.

【0098】

The state of auto boot pin 370 can be read from special bits in other control registers for diagnostic purposes. Using the selected automatic boot mode and external ROM, the present invention operates the PCI interface ASIC20 as a local processor, sets up all internal PCI interface ASIC20 registers, initializes other equipment on the PCI bus 24, and It is possible to build and connect multiple other PCLs. Various DMA channels can execute these PCLs to transfer data over the IEEE1394 bus.

【0099】

By adding the external local bus RAM to the PCI interface ASIC20, a PCI slave memory can be provided in the device on the PCI bus 24, control information can be acquired, and a local memory for data transfer can be provided. The PCL program can transfer device control / data to other systems via IEEE1394. Therefore, the environment that employs the automatic boot mode of the present invention can be used in peripheral devices that cannot use an appropriate processing device that manages the PCI interface environment.

【0100】

The circuit of FIG. 14 provides another mode of operation for the chip via an external pin. The effect is to enable and pre-specify part of the memory map to ensure sufficient resources accessible to the DMA engine 74 at power up so that all required functions work sufficiently effectively. is there. The effect is to change the operation of the DMA engine 74 so that when the DMA machine is in a specific mode, the machine stops operating and instead requests a new instruction from the dedicated ROM.

【0101】

The DMA engine 74 goes live and acquires an address to get an instruction. This makes it possible for the PCI interface ASIC20 to operate in a stand-alone independent mode. It also allows the generation of PCI memory instructions and all input / output instructions from the PCI interface ASIC20.

【0102】

By using the automatic boot pin 370, the present invention allows the power-on memory map to be reconfigured by allowing access and initialization of address registers based on ROM and RAM. This allows the DMA machine to have read and write access after power on. Further, the present invention modifies the behavior of the DMA engine 74 when the automatic boot mode is selected. This makes it possible to acquire new instructions from the dedicated ROM address when the power is turned on. The initial access address is exactly 0 in this embodiment. The present invention also provides a method of generating bus instructions and protocols that are not required in a normal environment.

【0103】

The DMA engine 74 can acquire and execute instructions from the RPL ROM 36 when the auto boot option is selected. This allows the DMA engine 74 to generate the instructions required to operate as a master device on the external PCI bus to configure, initialize and manage other PCI devices on this external bus.

【0104】

Table 380 in FIG. 15 shows a mapping of the internal PCI address bus [31:30] bits to the instructions on the PCI bus when the autoboot input 370 is activated. For example, when the value of bit 31 is 0 and bit 30 is an arbitrary value, the PCI memory instruction is operated. After that, when the value of the address bit 31 becomes 1 and the value of the address bit 30 becomes 0, a PCI input / output instruction is generated. When the value of the address bit 31 is 1 and the value of the address bit 30 is 1, the PCI configuration instruction is sent to the PCI interface ASIC20.

【0105】

FIG. 16 shows a diagram of the local bus interface block 390 based on one feature of the present invention. The local bus interface block 390 includes a local bus configuration register 392 and a zoom video (ZV) decoding interface block 394 that communicates with the ZV machine 396. The packed / unpacked state machine 398 contains an address / data / bit enable hold register 398. The local bus interface block 390 also includes a local bus interface state machine 400 and a slave affirmative interrupt block 402.

【0106】

The ZV port in Fig. 2 is an output-only port for transferring data from the IEEE1394 standard bus to an external device on the PCI interface ASIC20. When properly programmed, the ZV interface logic provides a way to receive an IEEE1394 digital camera packet and transfer its payload to an external ZV-compliant device with the appropriate control signal.

【0107】

The ZV decoding circuit 394 is accessed via a subset of third PCI memory compliant address registers. When the ZV decoding circuit 394 is enabled, the auxiliary addresses between 0xF000 and 0xFFFF are mapped to the ZV port. The ZV port is enabled when one of the six available clock sources 395 is selected as the ZV pixel clock. If none of the six clocks are selected, the ZV port is disabled and the auxiliary interface requires full address space. When the ZV port is disabled, all ZV-related outputs are neutral except for the data bus, which is driven during auxiliary, RAM and ROM access.

【0108】

A vertical sync signal is generated when the ZV port detects that the IEEE1394 equi-time interval packet header sync field is equal to 0x1. In this embodiment, the data bit 24 includes important synchronization field data. When this vertical sync bit is detected, a vertical sync output is generated. For the rest of the frame, a horizontal sync output is generated each time a special address is accessed when transferring video data to the zoom port. With proper programming of the packet control list, all IEEE1394 digital camera packets can be forwarded via the ZV port.

【0109】

FIG. 17 shows one embodiment of the synchronization detection circuit 405 of the present invention, which is for generating the vertical synchronization detection signal 407 and the horizontal synchronization detection signal 409. When the value of the PCI slave address bit [15: 0] is assumed to be 0xF000 and the slave data bit 28 is assumed to be the binary value 1, the comparison circuits 411 and 413 send a signal to the AND gate 415. This produces a vertical sync detection signal on line 407. Similarly, when the slave address bit [15: 0] sends 0XF004 to the comparison circuit 417, a horizontal sync detection signal appears on line 409.

【0110】

FIG. 18 shows one video scan line for a packet zoom port address map 410 according to the present invention. The zoom port address map 410 includes an equi-time-spaced packet header 412 starting at address 0XF000 and an equi-time-spaced packet data space starting at addresses 0XF004 and ending at 0XFFFF, detailed at reference numbers 414-424. Each equi-time interval packet is forwarded into the zoom port address space with a header quadlet forwarded to address 0XF000, the first data payload quadlet 428 is forwarded to address 0XF004, and the remaining quadlets in the packet are in order. The end of the packet payload data is forwarded to the address of until the address (0XF000 + (N-1)) in the case of packet N quadlet length is reached.

【0111】

FIG. 18 shows that the present invention can autonomously display a video image display in a window managed by hardware without the assistance of software. The present invention allows raw data to be sent over an IEEE1394 bus and flow into a zoom port in a format compatible with input data to a video controller chip. This makes it possible to display data autonomously while maintaining horizontal and vertical frame synchronization.

【0112】

During operation, the zoom video port is mapped into an address space. The header contains frame synchronization information or signals. By constructing the correct control structure, the header packet data is forwarded to a specific address based on the address where the logic looks for a field. For Sony cameras that meet the IEEE P1394 digital camera specifications, the bits in the equi-time interval header synchronization field indicate the start position of the video frame. A vertical sync signal is generated by decoding this particular equi-time interval header sync field bit. This information can be used to synchronize the reception of zoom port data to the zoom port.

【0113】

There are two ways to achieve this, one is horizontal sync and the other is vertical sync. For vertical synchronization, a specific address and a specific equal time interval header synchronization bit are required for decoding. Horizontal synchronization is generated by decrypting another specific address.

【0114】

The video zoom function of the present invention provides a function of autonomously extracting control information such as a horizontal or vertical synchronization signal from packetized data including embedded control information such as encoded video. .. Simultaneous comparison logics 411 and 413 detect a transfer to the destination address specified by the particular data value.

【0115】

The present invention also provides software or hardware control structures for designating appropriate destinations for different segments of packet data. The DMA architecture allows specific packets to be collected or delivered by breaking them down into different lengths to different destination addresses. Therefore, the present invention can write the header field to a specific address and the data field to another address. Utilizing this feature, the present invention can control which part of the PCI interface device sees which address.

【0116】

The present invention also provides a programmable counter, which is used to generate basic control signals for multiple access to specific address locations and / or data patterns. This gives the option of giving multiple packets per horizontal scan line or during horizontal synchronization by using a counter. Therefore, a horizontal synchronization signal is generated immediately after the vertical synchronization. This makes it possible to count the number of times the system passes a particular address. The system can, for example, generate another horizontal sync signal only after repeating that address four times. This makes it possible to combine four packets into a horizontal scan line according to a specific camera, resolution, etc.

【0117】

FIG. 19 shows a procedure for mapping a single video packet to multiple video scan lines using the zoom port address map 410. The zoom port address map 410 includes an equi-time interval packet header 412, which is adjacent to the equi-time interval packet data 414. The memory spaces 416 to 424 are similar to those described in FIG. The zoom video equi-time interval packet 440 contains header quadlet 0, which should include the frame start bit in the equi-time interval header synchronization field. Quadlet 1 is the first video data payload quadlet, which contains the start of video scan A. The horizontal sync signal is generated by writing this quadlet to address 0XF004. Similarly, writing the data quadlet 442 to address 0XF004 marks the beginning of video scan A + 1 by generating a horizontal sync. Writing data starting at 0XF000 and continuing to [0XF000 + (N-1)] is the actual data output through the zoom video port, i.e. zoom data. The header is removed and is not part of the data field.

【0118】

Therefore, in this case, vertical synchronization and horizontal synchronization are generated for the first packet of the video frame. Subsequent packets mean subsequent scan lines that fill the rest of the video frame header, but these headers do not contain synchronization fields. The data flow is the same for all packets, starting at point 0XF000 where each header is present, and if the sync bit is not present in the header, the vertical sync bit is not set. A horizontal sync is generated if written to F004. This produces the start of the scan line, which causes the rest of the data to flow out as part of the scan line.

【0119】

Furthermore, there are situations in which multiple scanning lines exist for each packet. A packet control list is used to handle this.

【0120】

The DMA engine 74 of the present invention is controlled by a data structure called a packet control list or PCL. PCL contains instruction information, which DMA retrieves from memory as needed. These instructions tell the DMA the source and destination of the data, as well as how many bytes will be transferred. Some instructions move chunks of data between the IEEE1394 transfer FIFO and the PCI bus 24, or between the general purpose receive FIFO 80 and the PCI bus 24. Another instruction moves data between the PCI bus 24 and the auxiliary port local bus 26. Other instructions are secondary functions and are called auxiliary instructions. These auxiliary instructions allow the DMA to snoop and tweak the quadlet of the specified data for any PCI address, and also allow conditional branching using PCL. Its intended use is to allow DMA to perform special data movement control and to function as a stand-alone processing device that can build a PCL with an automatic boot sequence. The full scope of this feature is not systematized, and other uses of DMA will be developed in the future.

【0121】

The application software of the present invention programs the operation of the DMA channel using the PCL data structure existing in the host memory. The application software is responsible for building the PCL and allocating the memory to the storage device. The PCL is organized as a contiguous set of memory arrays, which contains instructions, control parameters, and data buffer pointers, which are used when the DMA channel transfers one IEEE1394 data packet, or the data is transferred to the PCI bus 24 and the auxiliary port. It is required when traveling to and from the local bus 26, or when executing one or more auxiliary instructions. The total number of memory arrays required by the PCL is generally limited to 32 quadlets in this implementation.

【0122】

As a minimum requirement, the PCL start address is lined up at the quadlet border. For optimal DMA performance, it is recommended that the PCL start address be a line on the cache line boundary. Data buffer pointers can be arranged on any byte boundary. In order to optimize the DMA performance, the data buffer pointers are arranged on the cache line boundary in the present invention. If this is not possible, the next best option is to arrange the data buffer pointers on the quadlet boundaries. The total data buffer size specified by the PCL is limited to approximately 1 kilobit when the IEEE1394 bit rate is 100 mbps, or approximately 2 kilobits when the IEEE1394 bit rate is 200 mbps.

【0123】

In this embodiment, the operating DMA channel takes in instructions and control parameters from the PCL, constructs the channel itself using these, and executes the transfer instruction.

【0124】

An application software program allows a DMA channel to forward multiple IEEE1394 data packets by chaining multiple packet control lists in a PCL list queue. The present invention comprises this queue by setting the next address field of each PCL to indicate the start address in the memory of the next PCL. The PCL at the end of the queue can be programmed to stop DMA processing, return to the beginning of the queue, or point to a new queue. A PCL containing ancillary instructions can be incorporated anywhere in the PCL queue, but not both at the same time. The PCL queue can be a mixture of receive and transmit or auxiliary instructions; however, the asynchronous transfer instruction must be next to another asynchronous transfer instruction, because it does the transfer of the pipeline structure. This is also because there is a possibility that the packet will be retried. On the other hand, this request is eliminated by setting the "wait state" bit in the asynchronous transfer instruction.

【0125】

FIG. 20 illustrates an example of a linked list of a plurality of packet control lists based on an embodiment of the present invention. In FIG. 20, the PCI queue 450 starts at the start address 452. The processing flow from the start address 452 enters the dummy packet control list 454. The dummy packet control list 454 sends the processing flow to the transfer instruction packet control list 456. In the transfer instruction packet control list 0, the data buffer counting instruction and the data buffer address information go to, for example, the data buffer 460, the data buffer 462, and the data buffer 464, and 14 data buffers are used in this example.

【0126】

The forwarding instruction packet control list 0 indicated by reference number 456 includes the following list address 466, which is connected to the auxiliary instruction packet control list 1 indicated by reference number 470. The auxiliary instruction packet control list 1, indicated by reference number 470, includes the load instruction 472, the source address in 474, and the store instruction and position 476. Load instruction 472 is connected to data register 478, which supplies DMA register 480. The store 1 instruction 476 provides the input to the memo position 482. The auxiliary instruction packet control list 1 indicated by the reference number 470 also includes the destination address 484 when the condition is satisfied, which sends PCI process control to the transfer instruction packet control list 2 indicated by the reference number 486 according to the condition. .. The forwarding instruction packet control list 2 indicated by reference number 486 contains the following list address 488, which is for connecting to another PCL as indicated by reference number 490, while the data counting and data buffer address 492 is , Connected to data buffer 494, and so on. If the destination address 484 when the condition is satisfied controls the processing flow of the PCI queue, the next list address 468 is connected to the transfer instruction packet control list 2 indicated by the reference number 486. This information is then sent from the following list address to another PCI, as indicated by reference number 490, and the data buffer 0 address and counting instruction information is sent to data buffer 1, and so on.

【0127】

Typically, when the host CPU44 operates, it arranges the memory to build the packet control list and the dummy next PCL address, because the previous PCL did not exist. The dummy's next PCL address provides the memory location, which is the start pointer of the first full PCL, or PCL0. The host processor then builds a list of required PCLs and causes it to perform either a data transfer or auxiliary instruction type, for example, an auxiliary instruction operation that actually issues an instruction equivalent to the processor.

【0128】

The space within the next PCL address contains the error address, reserved location, and state. The next pair is the control state and the transfer count value. One of them is the data buffer address. These two long words make up a data transfer to one instruction or one data buffer. A transfer example is a buffer address that indicates a data buffer location in memory, to which the data is transferred or transferred from there. If data is transferred continuously, this embodiment makes it possible to form a large control loop for continuous data transfer.

【0129】

The operation of the receive, transmit, or auxiliary operation between PCI and the port local bus of the present invention will be described with reference to FIGS. 21 to 30 and the following description. In the receiving operation, as shown in FIG. 21, the processing flow is started by checking whether or not a waiting state exists for the equi-time interval and asynchronous data in the GRF80. As shown in FIG. 27, for equichronous transmission, if the channel enablement is equal to 1, the transmission function is ready, the cycle start bit is accepted, and there is no waiting state. The wait state is determined by the wait selector bit of the data buffer control word zero. When the wait state no longer exists, the processor enters the data transfer phase. At this point, a loop is entered and it is confirmed whether the current transfer count value is zero. If it is zero, a check is made to see if it is the last data buffer in the PCL buffer list. If that data buffer is the last data buffer and the link layer control GRF a special control token word If the packet boundaries are not displayed by writing in the FIFO, an error occurs because more packet data is being transferred than the buffer can hold. In this case, the packet error bit is set in the DMA status register, and the DMA pushes the remaining data to the packet boundary. If it is determined that the current transfer count has been reduced to zero and another buffer exists in the PCL list, DMA acquires a new buffer address and transfer count and continues the transfer.

【0130】

While moving data from the receive FIFO in the PCI interface, the DMA waits until the FIFO has enough data before making a transfer execution request to the PCI bus master. This transfer threshold is reached when one or two conditions are met. The DMA requires the transfer of the PCI master whenever the number of bytes in the receive FIFO reaches the "high water level mark". This high water mark is equal to the upper bound of the cache line size register or the lower bound field of the DMA global register. DMA gets information about the data size of a packet from the link when the packet is first written into the FIFO by the length layer control. It uses this transfer count to determine if the data in the FIFO is the remaining data in the packet, and if so, if its size is less than the high water mark, its transfer count is equal to the rest. Request a transfer from the PCI master. While the DMA transfers data, the data buffer start address register in the data buffered by the transfer length bits in the DMA control register is updated to reflect the current status of the transfer.

【0131】

When the link layer control reaches the end of the packet, it writes a special control token word in the FIFO to mark the end of the packet. Built into this control word is a state bit that represents the completion state of the packet on the bus. DMA uses this packet termination marker to terminate the transfer of data from the FIFO to the PCI bus. If the packet end marker represents an IEEE1394 busy affirmative confirmation, the DMA reacquires the PCL's first buffer address and the transfer count value and restarts the packet transfer. If the busy status is not displayed from the packet end marker, the positive confirmation status sent from the link layer control into the packet end marker is loaded in the DMA status register, and the packet completion is set. It is then written to memory in the PCL state word along with the number of bits transferred to this PCL. If the INT bit is set for a data buffer control / byte count instruction in the PCL, an interrupt signal is issued and the corresponding DMA in the interrupt status register. Latched into the PCL bit. If the instruction is a receive and update instruction, the remaining transfer count value and the next buffer address are written to the PCL. The DMA then determines if another PCL is linked to the current PCL by fetching the next list address field of the current PCL. If a linked PCL exists, DMA will continue to run with that linked PCL as the current PCL. If another PCL is not linked to the current PCL, a DMA stop interrupt is generated in the interrupt state register with the state associated with this channel, and that channel is in the idling state.

【0132】

For DMA asynchronous transfer operations, asynchronous transfer is determined after a valid PCL pointer has been written to the packet control list start address register, channel enabled and the link bit set, as shown in FIGS. 24-26. The ultimate goal of the asynchronous packet processor is to leave one more packet than the current packet forwarded from the FIFO to the IEEE1394 bus by the link layer controller. From a DMA point of view, this packet on the bus is the last packet. All states reported by the link layer control are believed to be related to this last packet; however, by setting the "wait state" bit into the "data buffer / byte count / instruction" in the PCL. This pipeline operation is prevented. The DMA holds the address of the previous packet control list start address in the previous packet control list start address / provisional register. A flag called "last PCL valid" is held by DMA in the DMA global register and records whether it is the stored valid address. The transfer operation on the asynchronous channel is performed while checking whether the waiting state exists. The wait state is determined by the wait selection bit of "data buffer control / byte count / instruction" in the PCL. A flag called "retry" is held by DMA in the DMA global register. DMA uses this flag to keep track of these wait states being evaluated so that they are ignored during retries.

【0133】

When the wait state no longer exists, the DMA writes a control token representing the beginning of the packet to the FIFO and enters the data transfer phase. At this point, a loop is entered and the current transfer count value is checked to see if it has reached zero. If so, a check is made to see if this is the final data buffer in the PCL buffer list. If another buffer exists in the PCL, the DMA acquires a new buffer address and a transfer count value to carry out the transfer. While transferring data from the PCI interface into an asynchronous transfer FIFO, the DMA waits until the FIFO has enough free space before requesting the PCI bus master to perform a read transfer. DMA requires the transfer of a PCI master with a bit count value equal to the high water level mark defined for the DMA receive operation. While the DMA transfers data, the data buffer start address register and the data buffer transfer link bit in the DMA control register are updated to reflect the current state of the transfer.

【0134】

The DMA reached the end of the packet when the last bit of data was transferred from the buffer to the asynchronous transfer FIFO and the buffer was at the end of the PCL list, as indicated by the last buffer bit in the control / byte count PCL word. Know that. If the last packet address is valid, DMA delays the state check until all packets are packed into the forwarding FIFO. In this case, the return state is always for the previous packet, unless the state wait bit is set. If only one packet is forwarded, the previous and current packets are the same. If the last packet address is valid, DMA checks the packet counter. When the packet has been transferred to the IEEE1394 bus by the link layer controller and the state of this packet is valid, the link layer controller decrements the packet counter. The DMA idles and waits until the packet counter reaches zero, indicating that the valid state can be applied to the previous packet. If the state indicates that the previous packet should be retried, the DMA makes a FIFO flush request to the link layer controller, which removes the retry indication to complete the FIFO flush. Wait until you indicate that you have done so. The DMA then "returns" to the previous packet and initiates the entire transfer. If no retries occur, the DMA updates the DMA status register with the affirmative state sent from the link-layer control, sets the packet completion, and then puts the completion state in memory in the previous PCL state word. , Write with the number of bits transferred to the currently running PCL, which should not be related to the previous PCL. If the interrupt bit is set in the PCL, an interrupt signal is emitted and latched into the corresponding interrupt state register bit.

【0135】

After checking the status, the DMA writes a special control token to the forwarding FIFO to mark the end of the packet. The packet count is decremented to 1 to indicate to the link layer control that the end of the packet was written by DMA. The current PCL address is saved as the last PCL address, and the last packet control list start address register and the "last valid" flag are set in the DMA global register. The DMA then determines if another PCL is linked to the current PCL by fetching the next list address value. If it is valid, DMA will use this as the current PCL address and continue execution. If it is not valid or the state wait bit is set, the DMA waits for the current packet to be forwarded by the link layer control. If a valid state is found, as indicated by the packet counter being reduced to zero, the DMA checks to see if the packet should be retried as shown in the IEEE1394 busy state. If so, the FIFO is swept away and the transfer is attempted again as described above.

【0136】

If the transfer time expires, the retry is exceeded, or the FIFO is not reached as indicated by the link layer control, a packet error bit is sent to the DMA status register with a positive confirmation status. This state is updated within the PCL. In case of transfer time out or retry excess, it could be possible that the target node no longer responds. DMA solves this situation by allowing the PCLs that form the stream of data to this particular node to be skipped. The software can be set by designating the entry point of the PCL's next PCL stream as the first PCL for the next stream of transfer data (ie the next asynchronous transfer to another 1394 node). If the next PCL stream address is valid, DMA will continue to run on this PCL. If this address is not valid, the DMA channel goes into an idling state, as it would have encountered if the next PCL address was marked as invalid. If this next stream content is not used, this value should be set to the same value as the next list address. If the DMA stops, it notifies the DMA stop interrupt state and invalidates the introduction of the next PCL stream, so the next PCL stream needs to be rewritten because the DMA is in the next stream acquisition state and the DMA sets the next list address. This is to ignore it. Therefore, it is always necessary to set the "next list address" and "next PCL stream" to the same address if the contents of the next stream are not used, which is all asynchronous transfers that carry out the next PCL stream introduction. This is to prevent the channel from hanging around due to an error.

【0137】

FIGS. 28 and 29 show the same flow chart as described in the asynchronous and equichronically spaced transfer operations described above, but are applied to the auxiliary operation of the DMA engine 74.

【0138】

As shown in FIG. 30, the transfer operation from PCI to the local bus and from the local bus to PCI controls the data transfer between the PCI bus and the local bus. The PCI address and the number of bits transferred are derived from the PCL data buffer control / bit count / instruction word in the PCL, as well as other transfer instructions such as transfer. The difference is that the destination or source of the transfer is a local bus rather than a FIFO. Its local bus address is generated from the AUX_ADR register (see hardware register definition).

【0139】

The operation between PCI and LOCAL is performed by performing a check to confirm whether or not a waiting state exists. The wait state is determined by the wait selection bit of buf0ctl / bit cnt / cmd with a PCL offset of 0x18. If the wait state no longer exists, the DMA goes into a loop where a check is made to see if the current transfer count has reached zero. If so, check to see if this is the final data buffer in the PCL buffer list. If another buffer exists in the PCL list, the DMA acquires a new buffer address and a transfer count value to carry out the transfer. While the DMA transfers data, the data buffer start address register and data buffer transfer length bit in the DMA control register are updated to reflect the current state of the transfer.

【0140】

If the last bit of data from the buffer is transferred between the local bus and the buffer, and the buffer is at the end of the PCL list as indicated by the last buffer bit of the control / bit counting PCL word, then the DMA is in the transfer. Know that you have reached the end. DMA updates the DMA status register with 0x0001, PKT CMP is set, and is written with the number of bytes transferred to the PCL status word at offset 0xC in PCL. When the INT bit is set to buf0ctl / bit cnt / cmd with a PCL offset of 0x18, an interrupt signal is issued and latched into the corresponding (DMA_PCL [x]) bit in the interrupt status register.

【0141】

Next, DMA determines whether another PCL is linked to the current PCL by taking in the next list address (PCL offset 0x00). If it is valid, indicated by bit 0 = 0, DMA continues execution with this as the current PCL address, as shown in the figure. If another PCL is not currently PCL linked, it is displayed by bit 0 = 1, the link and busy bits are cleared in the DMA control register, and a DMA stop interrupt is associated with this channel (DMA_HLT [ It is generated in the interrupt state register together with x]), and the channel is in the idling state.

【0142】

Figures 31 and 32 show FIFO high-level function blocks Figure 500, which illustrate FIFO operations for GRF80, asynchronous transmit FIFO 82, and equi-time interval transmit FIFO 84. The FIFO logic of the present invention includes a link side clock area 502 and a PCI side clock area 504. The PCI side clock area 504, FIFO control and status register 88 are written in real time by the PCI bus interface logic. The FIFO controller status register 88 also provides an input to the pointer address mapping logic 86. The pointer address mapping logic 86 generates a RAM address mapping offset for the FIFO read / write pointer.

【0143】

The dual port RAM 501 serves as a data storage unit for the GRF 80, the asynchronous transmission FIFO 82, and the equi-time interval transmission FIFO 84, and is deployed at the boundary between the link side clock area 502 and the PCI side clock area 504. One PCI side clock area 504, clock area pointer translation logic 506 generates an input to the DMA FIFO occupied state logic 508. The DMA FIFO occupied state logic 508 generates a FIFO state for the DMA logic signal 510. One link-side clock region 502, clock region pointer translation logic 512, provides inputs to the 1394 FIFO transmitter and receiver occupancy state logic 514, which generate a FIFO state for the 1394 transmit / receive logic signal 516.

【0144】

The dual port RAM501 receives address input from the multiplexer 518 and multiplexer 520. The multiplexer 518 receives input from the general-purpose receive-write pointer 522, the asynchronous transmit-read pointer 524, and the equi-time-spaced transmit-read pointer 526. The general-purpose receive / write pointer 522 is controlled by a 1394 receiver and address mapping logic. The asynchronous transmit read pointer 524 and the equichronically transmit read pointer 526 are controlled by the 1394 receiver and the address mapping logic. All output from the general-purpose receive-write pointer 522, the asynchronous transmit-read-pointer 524, and the equi-time-spaced transmit-read-pointer 526 is sent to the transmitter and receiver-occupied state logic 514, the clock region pointer translation logic 506, and the multiplexer 518.

【0145】

The general-purpose receive pointer 528, the asynchronous transmit / write pointer 530, and the equichronically spaced transmit / write pointer 532 are all controlled by the DMA logic and the address mapping logic. The general-purpose receive pointer 528, the asynchronous transmit write pointer 530, and the equi-time interval transmit write pointer 532 all provide output to the DMA FIFO state logic 508, the clock region pointer translation logic 512, and the multiplexer 520.

【0146】

The dual port RAM501 also receives data input from the 1394 receive logic via the 33-bit data bus 534, a link clock 25 MHz signal 536, and control from the 1394 transmit / receive logic via line 538. Further, the control from the 1394 transmission / reception logic 538 is sent to the link side address multiplexer 518. Bytepack logic 540 receives DMA read data from host memory via control from DMA logic and provides output on the 33-bit data bus 542, which sends it to the PCI side data input of dual port RAM501. Be done. The byte unpack logic 544 receives the data output from the dual port RAM501 PCI side data output 33 bit bus 546 and provides DMA write data to the host memory. Also, control from the DMA logic is sent to the byte unpack logic 544, multiplexer 520 and dual port RAM 501. Zero to 33MHz PCI clock signals are sent to dual port RAM501.

【0147】

In connection with the description given in FIG. 2 and the related description, a more detailed description of the functions of the FIFO, GRF80, asynchronous transmission FIFO 82, and equi-time interval transmission FIFO 84 is given below.

【0148】

FIFO state logics 514 and 516 execute the logic needed to generate an occupied state for each logical FIFO. When calculating the FIFO state on the PCI side, the translation logic from the link to the PCI clock area samples the current value of each pointer on the link side of the FIFO, and based on these samples, the link clock area to the PCI clock area. Translate to. Each translated link-side pointer is compared to its corresponding PCI-side pointer and an occupied state of each FIFO is generated. This state is used in DMA logic to pace the data transfer between the host memory and the FIFO. Similarly, when calculating the link-side FIFO state, the PCI-to-link clock region translation logic samples the current value of each pointer on the FIFO's PCI side and from the PCI clock region to the link clock region of these samples. Translate. Each translated PCI-side pointer is compared to its corresponding link-side pointer and the occupancy state of each FIFO is calculated. This state is used in 1394 transmit / receive logic, which paces the data transfer between the 1394 bus and the FIFO.

【0149】

Bytepack Logic 540 executes logic that aggregates all quadlet data reads from host memory over byte-aligned addresses via the operating DMA channel. This logic preferably includes four 8-bit width registers and four 8-to-1 multiplexers. Each register-multiplexer pair corresponds to a single byte sequence. The input of each register is connected to an input byte string, which is switched to host memory by the operating DMA channel. The output of each multiplexer is connected to a sequence of output bytes, which drives the FIFO. For each 8-to-1 multiplexer, the four inputs are connected to each register output in a one-to-one correspondence. The remaining four inputs have a one-to-one correspondence and are connected to each register input. This configuration makes it possible to switch the bit array DMA read data from the four input byte sequences to the four output byte strings in a different order. Control of the byte sequence multiplexer is performed on the DMA read channel during operation.

【0150】

The byte unpacking logic 544 provides the logic needed to disassemble the quadlet data read from the FIFO to individual selectable bytes to write over the running DMA channel on the byte-ordered addresses in host memory. Execute. This logic consists of four 8-bit wide registers and four 8-to-1 multiplexers. Each register-multiplexer pair corresponds to a single byte sequence. The input of each register is connected to the input byte sequence, which is driven from the FIFO. The output of each multiplexer is connected to a string of output bytes, which is switched to host memory by the DMA channel. Four inputs are connected to each register output in a one-to-one correspondence for each 8-to-1 multiplexer. The remaining four inputs have a one-to-one correspondence and are connected to each register input. This configuration allows quadlet reads from the FIFO to be switched on the output byte sequence in a different order. Control of the byte sequence multiplexer is performed by the DMA write channel during operation.

【0151】

Having described the invention in detail, it should be understood that various modifications, substitutions and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims.

【0152】

The following sections are further disclosed with respect to the above description. (1) A method for controlling data packet transfer between at least one source location and at least one destination location, each of which is associated with a data packet transfer device: said at least one source. Linking multiple data packet transfer control instructions in a packet control list that includes multiple logical functions to control logical operations related to data packet transfer from location to at least one destination location; and data packet transfer equipment The method including the above procedure, which controls the operation of the above based on a plurality of data packet transfer control instructions on the packet control list.

【0153】

(2) The method according to paragraph 1, further comprising associating an auxiliary packet control instruction with the packet control list.

【0154】

(3) The method according to paragraph 1, further comprising storing a plurality of receive and multiple transmit instructions in the packet control list.

【0155】

(4) The method according to paragraph 1, further comprising associating a plurality of receptions and a plurality of auxiliary instructions within the packet control list.

【0156】

(5) The method according to paragraph 1, further comprising a procedure of linking a plurality of the packet control lists to each other.

【0157】

(6) The method according to paragraph 1, further comprising a procedure of looping the packet control list on itself in order to continuously execute the data packet transfer control instruction.

【0158】

(7) The method according to paragraph (1), wherein the asynchronous transmission instruction further includes an asynchronous transmission instruction in the packet control list, and the asynchronous transmission instruction includes a state waiting bit.

【0159】

(8) The method according to paragraph 1, further comprising a procedure for associating the next PCL address instruction in the packet control list.

【0160】

(9) The method according to paragraph 1, further comprising a procedure of associating an address instruction of the next stream in the packet control list.

【0161】

(10) The method according to paragraph 1, further comprising associating a set of data packet control instructions with a single data packet in a one-to-one correspondence.

【0162】

(11) A data packet control list for controlling data packet transfer between at least one source location and at least one destination location, each associated with a data packet transfer device: at least 1 above. With multiple data packet transfer control instructions associated within a sequential list containing multiple logical functions to control the logical operations associated with data packet transfer from one source location to the at least one destination location; The data packet control list including instructions for controlling the operation of the data packet transfer device according to the plurality of data packet transfer control instructions.

【0163】

(12) The data packet control list according to paragraph 11, further comprising an instruction for associating an auxiliary packet control instruction with the packet control list.

【0164】

(13) The data packet control list according to paragraph 11, further comprising instructions for associating a plurality of receive and multiple transmit instructions within the packet control list.

【0165】

(14) The data packet control list according to paragraph 11, wherein the data packet control list further includes an instruction that associates a plurality of receive and a plurality of auxiliary instructions within the packet control list.

【0166】

(15) The data packet control list according to paragraph 11, further comprising an instruction for linking a plurality of the packet control lists to each other.

【0167】

(16) The data packet control according to paragraph 11, further comprising an instruction to loop the packet control list on itself in order to continuously execute the data packet transfer control instruction. list.

【0168】

(17) The data packet control list according to paragraph 11, wherein the data packet control list further includes an instruction for storing an asynchronous transmission instruction in the packet control list, and the asynchronous transmission instruction includes a state wait bit.

【0169】

(18) The data packet control list according to paragraph 11, further comprising an instruction for associating the next PCL address instruction within the packet control list.

【0170】

(19) The data packet control list according to paragraph 11, further comprising an instruction in the packet control list that associates an address instruction of the next stream.

【0171】

(20) The data packet control list according to paragraph 11, wherein the data packet control list further includes an instruction that associates a set of data packet control instructions with a single data packet in a one-to-one correspondence.

【0172】

(21) Packet Control List 456 controls data packet transfer between at least one source location 452 and at least one destination location 460, each associated with the data packet transfer device 20. Packet control list 456 associates multiple data packet transfer control instructions 454 within sequential list 466, which controls the logical operations associated with forwarding data packets from at least one source location 452 to at least one destination location 460. Includes multiple logical functions 472 for. Instruction 486 controls the operation of the data packet transfer device 20 based on the instruction 486.

[Simple explanation of drawings]

[Figure 1]

The operation schematic diagram of the personal computer environment which incorporates this invention is illustrated.

[Figure 2]

The general operation schematic diagram of the functional logic of this invention is shown.

[Fig. 3]

The conceptual diagram of the comparison logic of this invention is illustrated.

[Fig. 4]

A more detailed conceptual expression of the comparison logic of the present invention is shown.

[Fig. 5]

Further details of the header comparison function of the packet receiver logic of the present invention are illustrated.

[Fig. 6]

Data values that can be considered as matching dataset fields that apply to the present invention are illustrated.

[Fig. 7]

Data values that can be considered as matching dataset fields that apply to the present invention are illustrated.

[Fig. 8]

Data values that can be considered as matching dataset fields that apply to the present invention are illustrated.

[Fig. 9]

Data values that can be considered as matching dataset fields that apply to the present invention are illustrated.

[Fig. 10]

An embodiment of a programmable selective writable data flip-flop of the present invention is illustrated.

[Fig. 11]

An example of an address field for realizing the programmable bit selection function of the present invention is shown.

[Fig. 12]

A diagram of a direct memory access and multiple channel environment in which time division multiplexing is performed is shown, and the DMA instruction processing operation of the present invention is illustrated.

[Fig. 13]

The table which illustrates the priority assignment based on the channel currently operating is shown.

[Fig. 14]

A part of the interface device structure of the present invention applicable to the automatic boot function is shown.

[Fig. 15]

A table of PCI master bus instructions corresponding to bits 31 and 30 of the internal PCI address bus when the automatic boot pin of FIG. 14 is set to the operating state is shown.

[Fig. 16]

The local bus interface of the present invention is shown in block diagram format.

[Fig. 17]

The logic of the interface device of the present invention for detecting horizontal and vertical sync signals is shown graphically.

[Fig. 18]

Another function of the invention, including the operation of directing a single data packet to a single scan line, is illustrated.

[Fig. 19]

The operation of this embodiment for mapping a single data packet to a multiple video scanning line is shown.

[Fig. 20]

The packet control list data structure used in the DMA packet processing apparatus of the present invention and the memory map of the data buffer are illustrated.

[Fig. 21]

The partial flow diagram of the DMA machine is shown, and the operation of the packet processing apparatus of this invention is illustrated.

[Fig. 22]

The partial flow diagram of the DMA machine is shown, and the operation of the packet processing apparatus of this invention is illustrated.

[Fig. 23]

The partial flow diagram of the DMA machine is shown, and the operation of the packet processing apparatus of this invention is illustrated.

[Fig. 24]

A partial flow diagram of the DMA machine is shown, and the asynchronous transmission operation of the present invention is illustrated.

[Fig. 25]

A partial flow diagram of the DMA machine is shown, and the asynchronous transmission operation of the present invention is illustrated.

[Fig. 26]

A partial flow diagram of the DMA machine is shown, and the asynchronous transmission operation of the present invention is illustrated.

[Fig. 27]

A partial flow chart of the DMA machine is shown, and the equichronous transmission operation of the present invention is illustrated.

[Fig. 28]

An example of the auxiliary function flow chart of the present invention is shown.

[Fig. 29]

An example of the auxiliary function flow chart of the present invention is shown.

[Fig. 30]

A partial flow diagram of the DMA machine is shown, and the local bus / PCI bus intercommunication operation of the present invention is illustrated.

[Fig. 31]

It is a conceptual diagram at a high level of the function generated in the FIFO circuit of this invention.

[Fig. 32]

It is a conceptual diagram at a high level of the function generated in the FIFO circuit of this invention.

[Explanation of symbols]

10 Personal computer environment 12 personal computer 14 Peripherals 16 Interface bus 18 3-port physical layer interface 20 PCI interface ASIC 22 Serial EPROM 24 PCI bus 26 Auxiliary port local bus 28 local bus 30, 31 address bits 34 PCI Host Bridge 36 Flash PROM 38 (DMA) Channel Control Static RAM (SRAM) 40 User-defined function (AUX) 42 Zoom video (ZV) port for video input / output 46 local memory 48 CD ROM device 50 laser printer 52 desktop camera 56 Video Cable Set Top Box 60 PCI bus logic 62 Serial EPROM interface 64 PCI master logic 66 PCI Slave Logic 68 PCI configuration control and status register 70 Local Bus Interface Logic 72 DMA logic 74 DMA engine 76 DMA control and status register 78 78 FIFO logic 80 General purpose receive FIFO 82 Asynchronous transmission FIFO 84 Equal time interval transmission FIFO 86 Pointer address mapping logic 88 FIFO control and status register 90 Link layer control logic 92 Control and status register 94 Periodic monitoring logic 96-cycle timer logic 98 Packet transmission control logic 100 CRC logic 102 Packet receiver control logic 104 Physical link interface logic 106 Received data 110 DMA header comparison register and logic 120 DMA channel header comparison logic 128 Priority Encoder 129 Logical OR circuit 136 Destination ID comparison logic 140 Transfer code comparison logic 144, 146 Comparison logic 150 AND function 160 transfer code 162 async header 164 Transfer code bit 166 Equal time interval header 250 register write circuit 252 General Purpose I / O (GPIO) Write Data Input 254 Data flip-flop 256 clock signal 258 Writable input 260 AND function 262 GPIO address approval signal 264 write standard signal 266 GPIO address bit input 300 DMA instruction processing environment 302 PCI register write data 304 multiplexer 306 DMA register write data 310 DMA register 312 Last address or provisional field 314 Packet control list start address register 316 DMA buffer start address register 320 DMA status register 322 DMA control register 324 Current DMA status register 326 Ready bit 328 DMA register write arbitration selection circuit 330 PCI slave signal 332 PCI master signal 334 DMA PCI master periodic input 336 Slave end input 340 DMA channel arbitrator 342 Lock channel input 344 multiplexer 346 multiplexer 348 Slave register read address input 350 DMA register read data output 370 auto boot input 390 Local bus interface block 392 Local Bus Configuration Register 394 Zoom Video (ZV) Decoding Interface Block 396 ZV machine 398 Address / Data / Bit Enablement Hold Register 400 Local Bus Interface State Machine 402 Slave Confirmation Positive Interrupt Block 410 Zoom port address map 412 Equal time interval packet header 414 Equal time interval packet data 416 memory space 440 Zoom video equal time interval packets 450 PCI queue 452 Start address 454 Dummy packet control list 456 Forwarding instruction packet control list 466 Sequential list 472 Logical function 480 DMA register 484 Destination address when the condition is met 501 dual port RAM 502 Link side clock area 504 PCI side clock area 506 Clock region pointer translation logic 508 DMA FIFO Occupied State Logic 510 DMA logic signal 512 Clock Region Pointer Translation Logic 514 Transmitter and receiver occupancy logic 516 1394 transmit / receive logic signal 518 multiplexer 520 multiplexer 522 General-purpose receive / write pointer 524 Asynchronous send read pointer 526 Current time interval send read pointer 528 General-purpose receive pointer 530 Asynchronous send write pointer 532 Current time interval send write pointer 536 link clock 25MHz signal 538 1394 Send / receive logic 540 byte pack logic 542 33-bit data bus 546 PCI side data output 33-bit bus