Clock control circuit

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a control circuit that uses a delay array to control the timing of an external clock generated by a CPU and the timing of an internal clock used inside a memory (IC).

【0002】

[Conventional technology]

An increasing number of recent memories achieve high-speed data transfer by transferring data in synchronization with a clock. For example, in a clock-synchronized DRAM such as a synchronous DRAM, data is exchanged with a block such as a CPU by synchronizing the clocks with 100 MHz and 250 MHz, respectively.

【0003】

In a system that exchanges data between blocks in synchronization with such a clock, there is a slight timing between the external clock given to the memory from a block such as the CPU and the internal clock generated inside the memory. The problem is that the deviation, that is, the occurrence of skew.

【0004】

For example, when an external clock of 100 MHz is used, one cycle is 10 nsec (nanoseconds), so if a deviation of 1 nsec occurs between the external clock and the internal clock, this deviation is equivalent to 10% of the one cycle time. However, it interferes with high-speed synchronous control.

【0005】

In particular, when transferring data from memory to another block, the external clock and internal clock skew directly affect the data output time of the memory and slow down the data transfer time.

【0006】

FIG. 48 shows an example of a system for synchronous control using a high-speed clock. Further, FIG. 49 shows the relationship between the external clock and the internal clock in the system of FIG. 48.

【0007】

An external clock CK generated by, for example, the CPU 12 is input to the memory (clock synchronous DRAM such as synchronous DRAM) 11. The external clock CK is converted to the internal clock CLK by the buffer 13, and the internal clock CLK is supplied to the input circuit 14, the output circuit 15, the write / read circuit 16, and the like to control the input / output operation of the data.

【0008】

Since the internal clock CLK is generated by the buffer 13 triggered by the external clock CK, there is inevitably a skew between the external clock CK and the internal clock CLK.

【0009】

Since it is the internal clock CLK that controls the operation inside the memory 11, when data is exchanged between the memory 11 and other blocks (CPU12, etc.), the external clock CK and the internal clock CLK are used. It is necessary to set the timing in anticipation of the skew between.

【0010】

However, as described above, the timing setting in anticipation of the skew delays the data transfer rate.

【0011】

Therefore, recently, the development of a technique for eliminating this skew has been promoted. Hereinafter, two examples of the technology at present will be described.

【0012】

The first is a technology that uses a PLL (Phase Locked Loop). In this technique, the width of the skew is detected by the PLL and the skew is set to zero. Further, since this technique feeds back the internal clock, it is effective when the external clock given to the memory always has a constant frequency and is not interrupted.

【0013】

The second is a technique for constructing a circuit that generates a corrected internal clock that matches the external clock based on a predetermined principle. This technology is very promising because it can immediately match the external clock and the internal clock even if the frequency of the external clock changes or the external clock is interrupted. There is.

【0014】

Therefore, the latter technique will be described in detail below.

【0015】

First, the principle of this technique will be described with reference to FIG.

【0016】

Let D1 be the skew width (delay amount) of the external clock CK and the internal clock CLK, and let T be the period of the external clock CK and the internal clock CLK.

【0017】

Here, the delayed imitation pulse FCL is generated when time A elapses from the time when the first pulse of the internal clock CLK is generated (the time when it rises). In this case, the time from the time when the delayed imitation pulse FCL is generated to the time when the second pulse of the internal clock CLK is generated is Δ.

【0018】

Further, this time Δ is copied so that the delayed imitation pulse RCL is generated when the time (2 × Δ) elapses from the time when the delayed imitation pulse FCL is generated. Then, the time point at which time A elapses from the time point at which the delayed imitation pulse RCL is generated coincides with the time point at which the third pulse of the internal clock CLK is generated.

【0019】

However, (A + W) <T. W is the width of the delayed imitation pulses FCL and RCL.

【0020】

Here, assuming that the time from the time when the delayed imitation pulse RCL is generated to the time when the third pulse of the external clock CK is generated is D2, if the delayed imitation pulse RCL is delayed by the time D2, the external clock CK A corrected internal clock CK ́ that matches the timing is obtained.

【0021】

In other words, if a delay circuit that generates delay amounts A, (2 × Δ), D2 is formed and the internal clock CLK is delayed by the time A + (2 × Δ) + D2, the correction internal that matches the timing of the external clock CK The clock CK ́ will be obtained.

【0022】

As is clear from FIG. 50, since there is a relationship of A = D1 + D2, the delay amount D2 can be obtained from A and D1.

【0023】

Further, since it is assumed that the period T of the external clock CK and the internal clock CLK is not constant, the time Δ also does not have a constant value. Therefore, the delay circuit that generates the time (2 × Δ) must be configured so that the time (2 × Δ) can be accurately generated according to the period T of the external clock CK and the internal clock CLK. ..

【0024】

According to such a principle, the first pulse of the correction internal clock can always be matched with the third pulse of the external clock CK regardless of the period T of the external clock CK and the internal clock CLK. In addition, after the third pulse of the external clock CK, the timing of the external clock CK and the timing of the correction internal clock CLK match, so even if the external clock CK is interrupted, this is immediately done. Correspondingly, it becomes possible to match the external clock and the internal clock.

【0025】

Next, a circuit configuration for matching the timing of the external clock and the internal clock based on the above principle will be examined.

【0026】

FIG. 51 shows an example of the circuit configuration.

【0027】

The external clock CK is input to the input buffer 22 via the input terminal 21. The internal clock CLK is output from the input buffer 22. Here, since the input buffer 22 has a delay amount D1, a skew for a delay amount D1 is generated between the external clock CK and the internal clock CLK.

【0028】

The internal clock CLK is input to the forward delay array 24 via the delay circuit 23 having the delay amount A. The forward delay array 24 is composed of a plurality of delay circuits 25-1, 25-2, ~ 25-n having a delay amount d.

【0029】

The Mira-control circuit 26 has a number of control elements 27-1,27-2, ~ 27-n corresponding to the number of delay circuits 25-1,25-2, ~ 25-n. The Mira-control circuit 26 has a function of determining the delay amount Δf in the forward delay array 24 and making the delay amount Δb in the reverse delay array 28 equal to the delay amount Δf.

【0030】

Like the forward delay array 24, the reverse delay array 28 is composed of a plurality of delay circuits 29-1, 29-2, to 29-n having a delay amount d.

【0031】

The clock output from the reverse delay array 28 becomes the correction internal clock CK ́ having a timing that matches the timing of the external clock CK by passing through the delay circuit 30 having the delay amount D2.

【0032】

In the circuit having the above configuration, the configuration of the forward delay array 24 and the configuration of the reverse delay array 28 are the same, and the delay amount Δf of the forward pulse is copied as it is to obtain the delay amount Δb of the reverse pulse, and 2Δ (Δf = Δb = Δ). ) Is obtained.

【0033】

However, the circuit having the above configuration has a drawback that it is difficult to completely match the delay amount Δf of the forward pulse and the delay amount Δb of the reverse pulse due to the fact that the forward pulse has a constant pulse width. ..

【0034】

This drawback will be described.

【0035】

FIG. 52 shows the circuit state of FIG. 51 at the time point t in FIG. 50 (that is, the time point in which the delay amounts Δf and Δb are determined).

【0036】

Here, the state in which the forward pulse is input to the delay circuit of the forward delay array is defined as the active state (indicated by diagonal lines), and the state in which the forward pulse is not input to the delay circuit of the forward delay array is defined as the inactive state. .. In this case, for example, when a forward pulse is input to the delay circuit 25-k, the delay circuit 25-k becomes active and the other delay circuits become inactive.

【0037】

When a pulse of the internal clock CLK is generated after the forward pulse is input to the delay circuit 25-k, the delay circuit 29-k of the reverse delay array is activated, and the delay circuit 29-k generates the reverse pulse.

【0038】

That is, since the forward pulse and the internal clock CLK pulse are input to the kth control element 27-k from the beginning of the delay array, the control element 27-k activates the delay circuit 29-k of the reverse delay array. In the state, the delay circuit 29-k generates a reverse pulse.

【0039】

However, in this case, the position from the beginning of the delay circuit 29-k to which the forward pulse is input and the position from the beginning of the delay circuit 29-k to generate the backward pulse are the same.

【0040】

Therefore, the front F1 of the forward pulse that determines the delay amount Δf and the front F2 of the reverse pulse that determines the delay amount Δb are inevitably the delay amount for one stage of the delay circuit (for example, the pulse width W of the forward pulse). ) Will be different. That is, in the circuit having the configuration of FIG. 51, the delay amount Δb has a drawback that the delay amount Δb is shorter than the delay amount Δf by the delay amount for one stage of the delay circuit at the maximum.

【0041】

[Problems to be Solved by the Invention]

As described above, conventionally, in the technique of constructing a circuit for generating a corrected internal clock that matches the external clock based on a predetermined principle, it is not possible to construct a circuit that accurately copies a predetermined delay amount. Therefore, it was difficult to completely match the correction internal clock with the external clock.

【0042】

The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to accurately obtain a predetermined delay amount in a technique for constructing a circuit that generates a corrected internal clock that matches an external clock based on a predetermined principle. It is to configure a circuit that can be copied to and make the correction internal clock exactly match the external clock.

【0043】

Another object of the present invention is to provide a circuit that generates a corrected internal clock having a constant phase relationship with respect to an external clock, that is, having a phase delayed by a predetermined amount from the external clock, based on a predetermined principle. It is to be.

【0044】

[Means for solving problems]

In order to achieve the above object, the delay array of the present invention is composed of a plurality of delay units connected in series, and each delay unit transmits a forward pulse by a certain delay amount to a subsequent delay unit. The forward pulse delay circuit, the reverse pulse delay circuit that delays the reverse pulse by the fixed amount of delay and transmits it to the delay unit in the previous stage, and the forward pulse when the pulse of the internal clock is not input to the plurality of delay units. Is set to the set state when is input, and is composed of a state holding unit which is set to the reset state when the reverse pulse is input when the pulse of the internal clock is input to the plurality of delay units. , The forward pulse is input to the delay unit of the first stage, and the front edge of the reverse pulse is the most of the delay units whose state holding unit is in the reset state when the pulse of the internal clock is input to the plurality of delay units. It is formed by a delay unit close to the first stage delay unit, and the reverse pulse is output from the first stage delay unit.

【0045】

Further, the edges other than the front edge of the reverse pulse are delayed closest to the delay unit of the first stage among the delay units whose state holding unit is in the reset state when the pulse of the internal clock is no longer input to the plurality of delay units. Formed in units.

【0046】

The clock control circuit of the present invention has the delay array, a delay amount D1, a buffer that generates an internal clock based on an external clock, and delays the pulse of the internal clock by a delay amount A to obtain the delay as a forward pulse. It is composed of a first delay circuit that supplies the delay unit of the first stage of the array and a second delay circuit that delays the reverse pulse output from the delay unit of the first stage by the delay amount D2 and outputs it as a correction internal clock. The amount D1, the delay amount D2, and the delay amount A have a relationship of A = D1 + D2.

【0047】

Further, in the clock control circuit of the present invention, the plurality of internal clock pulses are input within a period from when the pulse of the internal clock is input to the plurality of delay units of the delay array until the forward pulse is supplied to the delay unit of the first stage. It is equipped with a control pulse generation circuit that generates a control pulse for initializing the forward pulse delay circuit of the delay unit.

【0048】

Further, the clock control circuit of the present invention cuts off the reverse pulse output from the delay unit of the first stage when the forward pulse is output from the delay unit of the final stage of the delay array, and replaces the reverse pulse with the reverse pulse. A means for controlling the pulse of the internal clock to be output from the second delay circuit is provided.

【0049】

The means initializes the second delay circuit based on the reverse pulse output from the delay unit of the first stage after the pulse of the internal clock is output from the second delay circuit.

【0050】

The delay array is arranged between the position where the buffer is arranged and the position where the second delay circuit is arranged. The pattern of the first delay circuit is the same pattern as the pattern of the buffer and the wiring from the buffer to the delay array, and the second delay circuit and the second delay circuit from the delay array. It is laid out so that the pattern of the wiring up to is composed of a combination with the same pattern.

【0051】

The memory circuit of the present invention includes a memory cell array, a write / read circuit for writing or reading data to the memory cell array, an input circuit for inputting the data from a bus, and the above. It is composed of an output circuit for outputting data to the bus and the clock control circuit, and the operation of the write / read circuit is controlled by an internal clock output from the buffer of the clock control circuit. The operation of the input circuit or the output circuit is controlled by at least the correction internal clock output from the second delay circuit of the clock control circuit.

【0052】

The clock control system of the present invention has a bus, a control block that transfers data to and from the bus and generates an external clock, and the memory circuit, and exchanges data to and from the bus. A memory block for receiving the external clock is provided.

【0053】

The delay array of the present invention is composed of a plurality of first and second delay units connected in series. Each first delay unit delays the forward pulse by a certain delay amount and transmits it to the delay unit in the subsequent stage, and delays the first reverse pulse by the fixed delay amount and transmits it to the delay unit in the previous stage. The first reverse pulse delay circuit and the pulse of the internal clock are set to the first state when the forward pulse is input when the pulse of the internal clock is not input to the plurality of first delay units, and the pulse of the internal clock is said. It is composed of a state holding unit that is set to the second state when the first reverse pulse is input when the first delay unit is input to a plurality of first delay units. Each second delay unit is composed of a second reverse pulse delay circuit that delays the second reverse pulse by the fixed amount of delay and transmits the second reverse pulse to the delay unit in the previous stage. The forward pulse is input to the first delay unit of the first stage, and the front edge of the first reverse pulse is in the second state of the state holding unit when the pulse of the internal clock is input to the plurality of first delay units. The first delay unit is formed by the first delay unit closest to the first delay unit in the first stage, and the first reverse pulse is output from the first delay unit in the first stage. The front edge of the second reverse pulse is formed by a second delay unit corresponding to the first delay unit forming the front edge of the first reverse pulse, and the second reverse pulse is from the second delay unit of the first stage. It is output. The delay amount of the first reverse pulse delay circuit and the delay amount of the second reverse pulse delay circuit are the same.

【0054】

The edge other than the front edge of the first reverse pulse is the first stage of the first delay unit whose state holding unit is in the second state when the pulse of the internal clock is no longer input to the plurality of first delay units. It is formed by the first delay unit, which is close to the first delay unit.

【0055】

The number of the first delay units and the number of the second delay units are different from each other. It is effective that the number of the second delay units is smaller than the number of the first delay units.

【0056】

One first block is composed of j consecutive first delay units among the plurality of first delay units, and the first one is composed of k consecutive second delay units among the plurality of second delay units. The k pieces of the second block are based on the control pulses that form one second block corresponding to the blocks and control the operation of k of the j first delay units of the first block. Controls the operation of the second delay unit. However, j and k are coprime natural numbers and j> k.

【0057】

The first delay unit constitutes r (r is a natural number) blocks, the total number of the first delay units is n (= r × j), and the second delay unit is also r. When the block is composed and the total number of the second delay units is m (= r × j) and the delay amount of the first reverse pulse is Δ, the delay amount of the second reverse pulse is (m / n) × Δ.

【0058】

The clock control circuit of the present invention has the above-mentioned delay array, the delay amount D1, the buffer that generates the internal clock based on the external clock, and the forward pulse by delaying the pulse of the internal clock by the delay amount A. The first delay circuit supplied to the first delay unit of the first stage and the first reverse pulse output from the first delay unit of the first stage are delayed by the delay amount (j-1) × D1 + j × D2. 1st correction 2nd correction by delaying the 2nd delay circuit output as the internal clock and the 2nd reverse pulse output from the 2nd delay unit of the first stage by the delay amount (k-1) × D1 + k × D2. It is equipped with a third delay circuit that outputs as an internal clock. However, j and k are coprime natural numbers and j> k.

【0059】

The delay amount D1, the delay amount D2, and the delay amount A have a relationship of A = j × (D1 + D2).

【0060】

The clock control circuit of the present invention has the above-mentioned delay array, a delay amount k × D1, a buffer that generates the internal clock based on the external clock, and the pulse of the internal clock is delayed by the delay amount A. The first delay circuit supplied to the first delay unit of the first stage as a forward pulse and the first reverse pulse output from the first delay unit of the first stage are delayed by a delay amount (jk) × D1 + j × D2. The second delay circuit output as the first correction internal clock and the second reverse pulse output from the second delay unit of the first stage are delayed by the delay amount k × D2 and output as the second correction internal clock. It has a circuit. However, j and k are coprime natural numbers and j> k.

【0061】

The delay amount D1, the delay amount D2, and the delay amount A have a relationship of A = j × (D1 + D2).

【0062】

In the clock control circuit of the present invention, the plurality of internal clock pulses are input to the plurality of first delay units within a period from the time when the forward pulse is supplied to the first stage delay units. A control pulse generation circuit for generating a control pulse for initializing the forward pulse delay circuit of the first delay unit is further provided.

【0063】

The number of the first delay units and the number of the second delay units are different from each other. It is effective that the number of the second delay units is smaller than the number of the first delay units.

【0064】

One first block is composed of j consecutive first delay units among the plurality of first delay units, and the first one is composed of k consecutive second delay units among the plurality of second delay units. The k pieces of the second block are based on the control pulses that form one second block corresponding to the blocks and control the operation of k of the j first delay units of the first block. Controls the operation of the second delay unit.

【0065】

The first delay unit constitutes r (r is a natural number) blocks, the total number of the first delay units is n (= r × j), and the second delay unit is also r. The block is composed, and the total number of the second delay units is m (= r × j).

【0066】

The second reverse pulse delay circuit generates a delay amount of m / n (= k / j) of the delay amount generated by the first reverse pulse delay circuit.

【0067】

The j is 2 and the k is 1, and the second reverse pulse delay circuit of the second delay unit is half the delay amount generated by the first reverse pulse delay circuit of the first delay unit. Generate a delay amount.

【0068】

The k is 1, and the second reverse pulse delay circuit of the second delay unit generates a delay amount of 1 / j of the delay amount generated by the first reverse pulse delay circuit of the first delay unit. To do.

【0069】

The memory system of the present invention has the same input capacity as the input capacity of the plurality of memories with respect to a plurality of memories, a controller for controlling the plurality of memories, and an external clock output from the controllers. The damage memory to be included, the delay time of the external clock from the controller to the plurality of memories, and the delay time of the external clock from the controller to the damage memory are arranged so as to be equal to each other. A data bus that guides data from one of the plurality of memories to the controller based on one wiring and an internal clock having a constant phase relationship with the external clock, and the damage memory. It is provided with a second wiring that returns the external clock given to the controller as a return clock again to the controller.

【0070】

Further, the delay time of the data from one of the plurality of memories to the controller is equal to the delay time of the return clock from the damage memory to the controller, and The controller captures the data based on the return clock.

【0071】

The clock control circuit of the present invention includes a first delay circuit that outputs a forward pulse after an internal clock delayed by D1 with respect to an external clock is input and a delay time A elapses after the internal clock is input. A second delay circuit that outputs a reverse pulse after delaying the forward pulse by 2 × Δ, and a delay time (j-1) × D1 + j × after the reverse pulse is input and the reverse pulse is input. After D2 has elapsed, it is provided with a third delay circuit that outputs a corrected internal clock whose phase is the same as that of the external clock. However, j is a natural number, Δ is the time from the generation of the forward pulse to the first generation of the pulse of the internal clock, and A is j × (D1 + D2).

【0072】

The clock control circuit of the present invention is a first delay circuit that outputs a forward pulse after an internal clock delayed by m × D1 with respect to the external clock is input and a delay time A elapses after the internal clock is input. , The second delay circuit that outputs the reverse pulse after delaying the forward pulse by 2 × Δ, and the delay time (jk) × D1 + j × after the reverse pulse is input and the reverse pulse is input. After D2 has elapsed, it is provided with a third delay circuit that outputs a corrected internal clock whose phase is the same as that of the external clock. However, j and k are coprime natural numbers, j k and Δ are the time from the generation of the forward pulse to the first generation of the internal clock pulse, and A is j × (D1 + D2). ).

【0073】

The clock control circuit of the present invention includes a first delay circuit that outputs a forward pulse after an internal clock delayed by D1 with respect to the external clock is input and a delay time A elapses after the internal clock is input. After delaying the forward pulse by Δ + (k / j) × Δ, the second delay circuit that outputs the reverse pulse and the reverse pulse are input, and the delay time (k-1) after the reverse pulse is input. ) × D1 + k × D2 is elapsed, and then a third delay circuit for outputting a correction internal clock whose phase is delayed by (k / j) × T with respect to the external clock is provided. However, j and k are coprime natural numbers, j k and Δ are the time from the generation of the forward pulse to the first generation of the internal clock pulse, and A is j × (D1 + D2). ), T is the period of the external clock.

【0074】

The clock control circuit of the present invention includes a first delay circuit that outputs a forward pulse after an internal clock delayed by k × D1 with respect to the external clock is input and a delay time A elapses after the internal clock is input. , A second delay circuit that outputs a reverse pulse after delaying the forward pulse by Δ + (k / j) × Δ, and a delay time k × after the reverse pulse is input and the reverse pulse is input. After D2 has elapsed, it is provided with a third delay circuit that outputs a corrected internal clock whose phase is delayed by (k / j) × T with respect to the external clock. However, j and k are coprime natural numbers, j k and Δ are the time from the generation of the forward pulse to the first generation of the internal clock pulse, and A is j × (D1 + D2). ), T is the period of the external clock.

【0075】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the clock control circuit of the present invention will be described in detail with reference to the drawings.

【0076】

FIG. 1 shows an example of a synchronous control system including a memory block having a clock control circuit of the present invention.

【0077】

An external clock CK generated by, for example, the CPU 12 is input to the memory (clock synchronous DRAM such as synchronous DRAM) 11. The external clock CK is converted to the internal clock CLK by the buffer 13. The internal clock CLK is supplied to the write / read circuit 16 and controls the write / read operation of the data.

【0078】

Since the internal clock CLK is generated by the buffer 13 triggered by the external clock CK, there is inevitably a skew between the external clock CK and the internal clock CLK.

【0079】

The clock control circuit 31 generates a corrected internal clock CK ́ that matches the timing of the external clock based on the internal clock CLK. The correction internal clock CK ́ is supplied to the input circuit 14 and the output circuit 15 and controls the input / output operation of the data.

【0080】

FIG. 2 shows the configuration of the clock control circuit 31 in the memory 11 of FIG.

【0081】

The external clock CK is given to the input terminal 30 of the memory. The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A, and the delay circuit 32 outputs the forward pulse FCL1 (delay imitation pulse CL).

【0082】

The internal clock CLK and the inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 are input to n delay units 33-1, 33-2, ... 33-n, respectively.

【0083】

The n delay units 33-1, 33-2, ... 33-n are connected in series with each other. The forward pulse FCL1 is input to the first-stage delay unit 33-1, and the reverse pulse RCL1 is output from the first-stage delay unit 33-1.

【0084】

The reverse pulse RCL1 becomes the correction internal clock CK ́ by passing through the delay circuit 34 having the delay amount D2.

【0085】

FIG. 3 shows in detail the configuration of the delay unit of FIG.

【0086】

The delay unit 33-i is composed of three parts: a forward pulse delay circuit, a state holding circuit, and a reverse pulse delay circuit.

【0087】

The forward pulse delay circuit is composed of three inverters 41 to 43. The inverters 41 and 42 are connected in series, the output signal FCLi of the delay unit in the previous stage is input to the inverter 41, and the inverter 42 outputs the output signal FCLi + 1 to the delay unit in the subsequent stage. .. The operation of the inverter (clocked inverter) 41 is controlled by the control pulse / P. For example, when the control pulse / P is 1, the inverter 41 is in the active state.

【0088】

Further, the output end of the inverter 43 is connected to the input end of the inverter 42, and a potential of "0" (for example, a ground potential) is always applied to the input end of the inverter 43. The operation of the inverter (clocked inverter) 43 is controlled by the control pulse P. For example, when the control pulse P is 1, the inverter 43 is in the active state.

【0089】

The reverse pulse delay circuit is composed of three inverters 44 to 46. The inverters 44 and 45 are connected in series, the output signal RCLi + 1 or the internal clock CLK of the delay unit in the subsequent stage is input to the inverter 44, and the inverter 45 outputs the output signal to the delay unit in the previous stage. Output RCLi. The operation of the inverter (clocked inverter) 44 is controlled by the control pulse Q. For example, the inverter 44 is activated only when the control pulse Q is 1.

【0090】

Further, the output end of the inverter 46 is connected to the input end of the inverter 45, and the internal clock CLK is always input to the input end of the inverter 46. The operation of the inverter (clocked inverter) 46 is controlled by the control pulse / Q. For example, when the control pulse / Q is 1, the inverter 46 is in the active state.

【0091】

The state-holding circuit is composed of a state-holding unit 47 and NAND circuits 48 and 49. The output signal FCLi and the inverted internal clock / CLK of the delay unit in the previous stage are input to the NAND circuit 48, and the output signal of the inverter 45 and the internal clock CLK are input to the NAND circuit 49.

【0092】

The output signal of the NAND circuit 48 is the set input / S of the state holding unit 47, and the output signal of the NAND circuit 49 is the reset input / R of the state holding unit 47. Therefore, when the output signal (set input) / S of the NAND circuit 48 becomes 0, the state holding unit 47 becomes the set state, and the output signal (reset input) / R of the NAND circuit 49 becomes 0. At that time, the state holding unit 47 is in the reset state.

【0093】

The state holding unit 47 is also configured to output control pulses Q, / Q. The control pulse Q is 1 when the state holding unit 47 is in the set state, and the control pulse / Q is 1 when the state holding unit 47 is in the reset state.

【0094】

FIG. 4 shows an example of the configuration of the state holding unit of FIG.

【0095】

The P-channel MOS transistor 51 and the N-channel MOS transistors 53 and 54 are connected in series with each other, and high-potential VDD and low-potential VSS are applied to both ends thereof, respectively.

【0096】

Similarly, the P-channel MOS transistors 52 and the N-channel MOS transistors 55 and 56 are connected in series with each other, and high-potential VDD and low-potential VSS are applied to both ends thereof, respectively.

【0097】

The set input / S is input to the gates of MOS transistors 51 and 54, and the reset input / R is input to the gates of MOS transistors 52 and 56.

【0098】

The gate of the MOS transistor 53 is connected to the drain of the MOS transistor 52, and the gate of the MOS transistor 55 is connected to the drain of the MOS transistor 51.

【0099】

The control pulse Q is output from the drain of the MOS transistor 51, and the control pulse / Q is output from the drain of the MOS transistor 52.

【0100】

FIG. 5 shows an example of the configuration of the control pulse P, / P generation circuit.

【0101】

The internal clock CLK is input to one input end of the NOR circuit 58 via the delay circuit 57 having a delay amount A ́, and the inverted internal clock / CLK is input to the other input end of the NOR circuit 58. The NOR circuit 58 outputs the control pulse P. Further, the control pulse P becomes a control pulse / P by passing through the inverter 59.

【0102】

The pulse width of the control pulses P and / P is determined by the delay amount A ́ of the delay circuit 57. However, this delay amount A ́ is set smaller than the delay amount A of the delay circuit 32 that outputs the delay imitation pulse. This is because it is necessary to initialize the forward delay circuits of all delay units before the forward pulse is input to the delay unit of the first stage.

【0103】

Next, the principle of the present invention will be confirmed with reference to FIG.

【0104】

Let D1 be the skew width (delay amount) of the external clock CK and the internal clock CLK, and let T be the period of the external clock CK and the internal clock CLK.

【0105】

The delayed imitation pulse FCL1 is generated when time A elapses from the time when the first pulse of the internal clock CLK is generated (when it rises). In this case, the time from the time when the delayed imitation pulse FCL1 is generated to the time when the second pulse of the internal clock CLK is generated is Δf.

【0106】

In addition, this time Δf is copied to create Δb so that the delayed imitation pulse RCL1 is generated when the time 2 × Δ (however, Δf = Δb = Δ) elapses from the time when the delayed imitation pulse FCL1 is generated. To. Then, the time point at which time A elapses from the time point at which the delayed imitation pulse RCL1 is generated coincides with the time point at which the third pulse of the internal clock CLK is generated. However, (A + W) <T. W is the width of the delayed imitation pulses FCL and RCL.

【0107】

Assuming that the time from the time when the delay imitation pulse RCL1 is generated to the time when the third pulse of the external clock CK is generated is D2, if the delay imitation pulse RCL1 is delayed by the time D2, it matches the timing of the external clock CK. The corrected internal clock CK ́ is obtained.

【0108】

In other words, if a delay circuit that generates delay amounts A, (2 × Δ), D2 is formed and the internal clock CLK is delayed by the time A + (2 × Δ) + D2, the correction internal that matches the timing of the external clock CK The clock CK ́ will be obtained.

【0109】

Since there is a relationship of A = D1 + D2, the delay amount D2 can be obtained from A and D1. Further, the control pulse P is for initializing the forward delay circuits of all the delay units before the forward pulse is input to the delay unit of the first stage.

【0110】

Next, the operation of the clock control circuit of FIGS. 2 to 5 will be described.

【0111】

1. State of timing chart in Fig. 7 at time a As shown in Fig. 8, the internal clock CLK becomes 1 (rises). Therefore, the output signals of the control pulse generation circuit 60 are P = 1 and / P = 0, and control pulses P and / P having a pulse width determined by the delay amount A ́ are generated, and each delay is generated. Input to units 33-1, 33-2, ~ 33-n.

【0112】

In each delay unit 33-1, 33-2, ~ 33-n, P = 1 and / P = 0, so that the inverter 43 is in the active state and the inverter 41 is inactive. It becomes a state. Therefore, the input / output signals FCL1 to FCLn of the forward pulse delay circuits of all the delay units 33-1, 33-2, to 33-n are all "0", and the line through which the forward pulse is transmitted is initialized.

【0113】

After that, in each delay unit 33-1, 33-2, ~ 33-n, when P = 0 and / P = 1, the inverter 41 becomes active and the inverter 43 becomes non-active. It becomes active. That is, the forward pulse delay circuits of the delay units 33-1, 33-2, to 33-n are electrically connected to each other, and the input end of the forward pulse delay circuit of the delay unit 33-1 is connected to the delay circuit 32. It is electrically connected and ready to transmit the forward pulse.

【0114】

It is essential that the pulse widths of the control pulses P and / P (the period when P is 1 and / P is 0) are shorter than the period determined by the delay amount A of the delay circuit 32. is there. Forward pulse (delay imitation pulse) Before FCL1 is input to delay unit 33-1, it is necessary to initialize the transmission lines of forward pulses of all delay units 33-1, 33-2, ~ 33-n. Because there is.

【0115】

2. State of timing chart in Fig. 7 at point b As shown in FIG. 9, the internal clock CLK becomes 0 and the inverted internal clock / CLK becomes 1. Since the internal clock CLK and the inverted internal clock / CLK are common to all delay units 33-1, 33-2, ~ 33-n, all delay units 33-1, 33-2, ~ 33- One input of the NAND circuit 48 of n becomes 1.

【0116】

On the other hand, the state holding units 47 of the delay units 33-1, 33-2, to 33-n are in the reset state R, and the control pulse output from the state holding unit 47 is Q = 0, / Q = 1.

【0117】

Therefore, the inverter 46 of each delay unit 33-1, 33-2, ~ 33-n becomes active, the inverter 44 becomes inactive, and all delay units 33-1, 33-2, ~ The input / output signals RCL1 to RCLn of the reverse pulse delay circuit of 33-n are all "0".

【0118】

3. State of timing chart in Fig. 7 at time c As shown in FIG. 10, the forward pulse (delay imitation pulse) FCL1 is output from the delay circuit (delay amount A) 32 and input to the delay unit 33-1. The sum of the pulse width of the forward pulse (period of "1") and the period determined by the delay amount A needs to be set to be shorter than the period T of the internal clock CLK.

【0119】

When the forward pulse FCL1 (= 1) is input to the delay unit 33-1, the other input of the NAND circuit 48 of the delay unit 33-1 becomes 1 and the output of the NAND circuit 48 (set input / S). ) Becomes "0". Therefore, the state of the state holding unit 47 changes to the set state S.

【0120】

In the delay unit 33-1 in which the state holding unit 47 is in the set state S, the control pulse output from the state holding unit 47 becomes Q = 1 and / Q = 0, so that the inverter 44 Becomes active and Inverter 46 becomes inactive.

【0121】

Four. State of timing chart in Fig. 7 at time d and e As shown in FIG. 11, the forward pulse travels through the delay units 33-1, 33-2, ~ 33-n in sequence.

【0122】

In the delay unit 33-1 where the forward pulse has passed, the other input of the NAND circuit 48 becomes 0 again, and the output (set input / S) of the NAND circuit 48 becomes 1, but the state holding unit 47 The state is maintained in the set state S.

【0123】

Similarly, when the forward pulse is input to the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 changes to the set state S. Even if the forward pulse passes through the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 maintains the set state S.

【0124】

When the internal clock CLK becomes 1 again and the inverted internal clock / CLK becomes 0, the internal clock CLK and the inverted internal clock / CLK is input.

【0125】

Therefore, one input of the NAND circuit 48 of all the delay units 33-1, 33-2, to 33-n becomes "0", and one input of the NAND circuit 49 becomes "1".

【0126】

Further, in the delay units 33-1 and 33-2 in which the state holding unit 47 is in the set state S, Q = 1 and the inverter 44 is in the active state, so that the output signals RCL1 and the reverse pulse delay circuit are in the active state. RCL2 maintains the state of "0", but in the delay units 33-3 to 33-n where the state holding unit 47 is in the reset state R, / Q = "1" and the inverter 46 is in the active state. Therefore, the output signals RCL3 to RCLn of the reverse pulse delay circuit are 1.

【0127】

As a result, the front edge F2 of the reverse pulse is formed.

【0128】

Here, the front edge F2 of the reverse pulse is the first-stage delay unit 33- among the delay units 33-3 to 33-n whose state holding unit is in the reset state R when the internal clock CLK becomes 1. It is formed by delay units 33-3 located on one side.

【0129】

At this time, since the front edge F1 of the forward pulse is considered to be located immediately before the delay unit 33-3, the front edge F1 of the forward pulse and the front edge F2 of the reverse pulse coincide with each other.

【0130】

Therefore, the time Δf from the time when the forward pulse (delayed imitation pulse) FCL1 is generated to the time when the pulse of the internal clock CLK is generated, and the reverse after the pulse of the internal clock CLK is generated (after the backward pulse is generated). The time Δb between the output of the pulse RCL1 and the input to the delay circuit 34 becomes equal.

【0131】

After that, as shown in FIG. 12, the output signal of the control pulse generation circuit 60 becomes P = 1, / P = 0, and the control pulse P having a pulse width determined by the delay amount A ́, / P is generated and input to each delay unit 33-1, 33-2, ~ 33-n.

【0132】

In each delay unit 33-1, 33-2, ~ 33-n, P = 1 and / P = 0, so that the inverter 43 is in the active state and the inverter 41 is inactive. It becomes a state. Therefore, the input / output signals FCL1 to FCLn of the forward pulse delay circuit of all delay units 33-1, 33-2, ~ 33-n are all "0", the forward pulse disappears, and the line through which the forward pulse is transmitted disappears. Is initialized.

【0133】

On the other hand, when the front of the reverse pulse (= 1) is input to the delay unit 33-1, in the delay unit 33-2, both inputs of the NAND circuit 49 become 1, so the NAND circuit 49 Output (reset input / R) becomes 0, and the state holding unit 47 changes (initializes) to the reset state R.

【0134】

Initialization of the state holding unit 47 of each delay unit (setting to the reset state R) is performed only during the period when the internal clock CLK is 1. That is, when the internal clock CLK is 1 and a reverse pulse (= 1) is input, both of the two inputs of the NAND circuit 49 become 1.

【0135】

Since the state holding section 47 of each delay unit is initialized only during the period when the internal clock CLK is 1, the state holding section 47 of all delay units can be initialized, that is, reset to the reset state R. It may not be possible, but there is no particular problem. This is because it is clear that the next forward pulse will pass through the uninitialized delay unit 33-1.

【0136】

Five. State of timing chart in Fig. 7 at time f As shown in FIG. 13, the internal clock CLK becomes 0 and the inverted internal clock / CLK becomes 1. The internal clock CLK and the inverted internal clock / CLK are input to all delay units 33-1, 33-2, ~ 33-n.

【0137】

In each delay unit 33-1, 33-2, ~ 33-n, P = 0 and / P = 1, so that the inverter 41 is in the active state and the inverter 43 is not. It becomes active. That is, the forward pulse delay circuits of the delay units 33-1, 33-2, to 33-n are electrically connected to each other, and the input end of the forward pulse delay circuit of the delay unit 33-1 is connected to the delay circuit 32. It is electrically connected and ready to transmit the forward pulse.

【0138】

On the other hand, in the delay units 33-2 to 33-n in which the state holding unit 47 is in the reset state R, / Q = 1 and the inverter 46 is in the active state. Therefore, when the internal clock CLK becomes 0, the output signals RCL2 to RCLn of the delay units 33-2 to 33-n in the reset state R of the state holding unit 47 become 0, and the back edge of the reverse pulse is formed. Will be done.

【0139】

Therefore, the pulse width of the reverse pulse is the same as or shorter than the period corresponding to the delay amount for one stage of the delay unit (delay amount for two stages of the inverter).

【0140】

If it is desired to make the pulse width of the reverse pulse longer than the delay amount for one stage of the delay unit, as shown in FIG. 17, the other input of the NAND circuit 49 of the delay circuit 33-n is set to the delay circuit of the previous stage. The output RCLn-1 of 33- (n-1) may be used. In this case, the maximum pulse width of the reverse pulse is a period corresponding to the delay amount for two stages of the delay unit (delay amount for four stages of the inverter).

【0141】

In the delay unit 33-1 in which the state holding unit 47 is in the set state S, Q = 1 and the inverter 44 is in the active state. Therefore, the preparation for guiding the reverse pulse to the delay circuit 34 via the delay unit 33-1 is completed.

【0142】

6. State of timing chart in Fig. 7 at time g As shown in FIG. 14, the forward pulse (delay imitation pulse) FCL1 is output from the delay circuit (delay amount A) 32 and input to the delay unit 33-1. When the forward pulse FCL1 (= 1) is input to the delay unit 33-1, the other input of the NAND circuit 48 of the delay unit 33-1 becomes 1 and the output of the NAND circuit 48 (set input / S). ) Becomes "0".

【0143】

Therefore, when the state holding unit 47 of the delay unit 33-1 is in the set state, the state holding unit 47 maintains the set state S, and when the state holding unit 47 is in the reset state R, the state holding unit 47 is in the reset state R. , Changes to the set state S.

【0144】

In the delay unit 33-1 in which the state holding unit 47 is in the set state S, the control pulse output from the state holding unit 47 becomes Q = 1 and / Q = 0, so that the inverter 44 Becomes active and Inverter 46 becomes inactive.

【0145】

On the other hand, the reverse pulse is input to the delay unit 33-1 of the first stage, receives a delay of two stages of the inverter, and is output from the delay unit 33-1 of the first stage.

【0146】

7. State of timing chart in Fig. 7 at time h As shown in FIG. 15, the forward pulse travels through the delay units 33-1, 33-2, ~ 33-n in sequence.

【0147】

In the delay unit 33-1 where the forward pulse has passed, the other input of the NAND circuit 48 becomes 0 again, and the output (set input / S) of the NAND circuit 48 becomes 1, but the state holding unit 47 The state is maintained in the set state S.

【0148】

Similarly, when the forward pulse is input to the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 changes to the set state S. Even if the forward pulse passes through the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 maintains the set state S.

【0149】

On the other hand, the reverse pulse is input to the delay circuit 34. The delay circuit 34 delays the reverse pulse by the delay amount D2 and generates a pulse of the correction internal clock CK ́. The pulse timing of this correction internal clock CK ́ coincides with the pulse timing of the external clock CK.

【0150】

8. 8. State of timing chart in Fig. 7 at time i As shown in FIG. 16, when the internal clock CLK becomes 1 again and the inverted internal clock / CLK becomes 0, each delay unit 33-1, 33-2, ~ 33-n has this internal. The clock CLK and the inverted internal clock / CLK are input.

【0151】

Therefore, one input of the NAND circuit 48 of all the delay units 33-1, 33-2, to 33-n becomes "0", and one input of the NAND circuit 49 becomes "1".

【0152】

Further, in the delay units 33-1 and 33-2 in which the state holding unit 47 is in the set state S, Q = 1 and the inverter 44 is in the active state, so that the output signals RCL1 and the reverse pulse delay circuit are in the active state. RCL2 maintains the state of "0", but in the delay units 33-3 to 33-n where the state holding unit 47 is in the reset state R, / Q = "1" and the inverter 46 is in the active state. Therefore, the output signals RCL3 to RCLn of the reverse pulse delay circuit are 1.

【0153】

As a result, the front F1 of the reverse pulse is formed.

【0154】

After that, the operations of FIGS. 12 to 16 are repeated.

【0155】

According to the clock control circuit having the above configuration, since each delay unit has a state holding unit, the time Δf from the generation of the delay imitation pulse (forward pulse) FCL1 to the generation of the pulse of the internal clock CLK can be accurately determined. It is possible to copy and form Δb, and input the reverse pulse RCL1 to the delay circuit 34 having the delay amount D2 after a time Δb (= Δf) after the pulse of the internal clock CLK is generated.

【0156】

Therefore, it is possible to generate a corrected internal clock CK ́ that is accurately synchronized with the CK to the external clock, and it is possible to achieve data transfer using a high-speed clock. Further, the present invention is effective for a memory such as a synchronous DRAM in which an internal clock may be temporarily interrupted and data is exchanged in synchronization with a high-speed clock whose frequency changes.

【0157】

FIG. 18 shows a modified example of the clock control circuit of FIG.

【0158】

This clock control circuit is different from the circuit of FIG. 2 in that a predetermined function is added to the delay circuit 34, and other configurations are the same as those of the circuit of FIG.

【0159】

That is, in the present embodiment, when the period T of the external clock CK or the internal clock CLK is longer than a predetermined value, the process of adjusting the timing of the internal clock CLK to the timing of the external clock CK is not performed, and the memory is input. The output circuit is controlled by the internal clock CLK, which has a constant skew.

【0160】

This is because when the frequency of the external clock CK is relatively low (the period is long), the skew itself does not matter much. Further, the number of delay units constituting the clock control circuit is not so large in relation to the occupied area on the memory chip.

【0161】

Hereinafter, the configuration of the circuit of this embodiment will be briefly described.

【0162】

The external clock CK is given to the input terminal 30 of the memory. The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A, and the delay circuit 32 outputs the forward pulse FCL1 (delay imitation pulse CL).

【0163】

The internal clock CLK and the inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 are input to n delay units 33-1, 33-2, ... 33-n, respectively.

【0164】

The n delay units 33-1, 33-2, ... 33-n are connected in series with each other. The forward pulse FCL1 is input to the first-stage delay unit 33-1, and the reverse pulse RCL1 is output from the first-stage delay unit 33-1.

【0165】

When the period T of the external clock CK is less than a predetermined value (high-speed clock), the reverse pulse RCL1 becomes the correction internal clock CK ́ by passing through the delay circuit 34 having the delay amount D2. The timing of this correction internal clock CK ́ coincides with the timing of the external clock CK.

【0166】

When the period T of the external clock CK is equal to or greater than a predetermined value, the reverse pulse RCL1 is input to the delay circuit 34 having the delay amount D2, but is not output from the delay circuit 34. Instead, the internal clock CLK is output from the delay circuit 34. In this case, the internal clock CLK naturally has a constant skew with respect to the external clock CK, but this skew is an amount that does not cause much problem with respect to the period of the external clock CK. There is.

【0167】

The control pulse generation circuit 61 is based on the output LST of the forward pulse delay circuit of the delay unit 33-n in the final stage and the output RCL1 of the reverse pulse delay circuit of the delay unit 33-1 in the first stage, and the control pulses L, / L. Is output. The control pulses L and / L determine whether to output the correction internal clock CK ́ or the internal clock CLK.

【0168】

FIG. 19 shows in detail the configuration of the delay circuit 34 of FIG.

【0169】

The output RCL1 of the delay unit 33-1 is input to one input end of the NAND circuit 64 via the delay circuit 62 and the inverter 63, and is directly input to the other input end of the NAND circuit 64. There is. The output signal of the NAND circuit 64 becomes the correction internal clock CK ́ by passing through the three inverters 65 to 67.

【0170】

The inverter 66 is a clocked inverter that is activated when the control clock / L is 1. That is, when the control clock / L is 1, the reverse pulse is delayed by a certain period of time to generate the correction internal clock CK ́, and when the control clock / L is 0, the reverse pulse is cut off.

【0171】

The internal clock CLK is input to the inverter 67 of the delay circuit 34 via the inverter 68. The inverter 68 is a clocked inverter that is activated when the control clock L is 1. That is, when the control clock L is 1, the internal clock CLK is guided to the inverter 67, and when the control clock L is 0, the internal clock CLK is cut off.

【0172】

FIG. 20 shows the configuration of the control pulse generation circuit 61 of FIG.

【0173】

The output LST of the forward pulse delay circuit of the delay unit 33-n in the final stage is input to one input end of the NOR circuit 69, and the output of the NOR circuit 72 is input to the other input end. The output of the NOR circuit 69 is input to one input end of the NOR circuit 72, and the output of the NOR circuit 71 is input to the other input end.

【0174】

In the NOR circuit 71, the output LST of the forward pulse delay circuit of the delay unit 33-n in the final stage and the output RCL1 of the reverse pulse delay circuit of the delay unit 33-1 in the first stage are inverted by the inverter 70, respectively. It has been entered.

【0175】

Further, the output of the NOR circuit 69 and the output delayed by the delay circuit 74 by the delay amount D3 are input to the NAND circuit 73, respectively. The output of the NAND circuit 73 becomes the control clock L, and the control clock L obtained by inverting this control clock L with the inverter 75 becomes the control clock / L.

【0176】

The NAND circuit 73 and the delay circuit 74 do not delay the start-up of the control clock L with respect to the output of the NOR circuit 69, but delay the start-up of the control clock L by the delay amount D3, and delay the reverse pulse in the delay circuit 34. It is for surely extinguishing and initializing.

【0177】

Next, the principle of the clock control circuit of FIGS. 18 to 20 will be briefly described with reference to FIG. 21.

【0178】

In Fig. 21, one cycle (cycle time) of the external clock CK is relatively long, and the maximum delay amount maxΔ by all delay units is the time from the time when the delay imitation pulse is generated to the time when the pulse of the internal clock CLK is generated. The timing clock when it becomes shorter than Δf is shown.

【0179】

Let D1 be the skew width (delay amount) of the external clock CK and the internal clock CLK, and let T be the period of the external clock CK.

【0180】

The delayed imitation pulse FCL1 is generated when time A elapses from the time when the first pulse of the internal clock CLK is generated (when it rises). In this case, the time from the time when the delayed imitation pulse FCL1 is generated to the time when the second pulse of the internal clock CLK is generated is Δf.

【0181】

However, the maximum amount of delay that can be formed by all delay units is maxΔ (<Δf). That is, since the maximum value of the delay amount that can be copied by the clock control circuit of the present invention is maxΔ, the delay imitation pulse RCL1 is generated when the time maxΔ elapses from the time when the second pulse of the internal clock CLK is generated. Therefore, the delay amount Δf cannot be copied accurately.

【0182】

Therefore, even if the correction internal clock CK ́ is generated when the time D2 elapses from the time when the delay imitation pulse RCL1 is generated, the timing of the correction internal clock CK ́ is different from the timing of the external clock CK. Moreover, this deviation may be larger than the originally existing skewer, which in turn deteriorates the performance of the memory.

【0183】

The present embodiment is conceived in order to avoid such a phenomenon. In the embodiment of FIG. 2, when the time from the generation of the pulse of the internal clock CLK to the generation of the delay imitation pulse is A, and the maximum delay amount by all the delay units is maxΔ, A + maxΔ It is necessary to satisfy T, but in the present embodiment, such a condition is not required.

【0184】

Next, the operation of the clock control circuit of FIGS. 18 to 20 will be described with reference to the timing chart of FIG.

【0185】

Since the operation when A + maxΔT is satisfied is the same as the timing chart shown in FIG. 7, only the operation when A + maxΔ> T will be described below.

【0186】

When the internal clock CLK becomes 1, P = 1 and / P = 0, and the input / output signals FCL1 of the forward pulse delay circuit of all delay units 33-1, 33-2, ~ 33-n. ~ FCLn becomes all "0", and the line through which the forward pulse is transmitted is initialized.

【0187】

After that, when P = 0 and / P = 1, the forward pulse delay circuits of the delay units 33-1, 33-2, to 33-n are electrically connected to each other, and the delay units are connected. The input end of the forward pulse delay circuit of 33-1 is electrically connected to the delay circuit 32, and the preparation for transmission of the forward pulse is completed.

【0188】

After the internal clock CLK becomes 0 and the inverted internal clock / CLK becomes 1, the forward pulse (delay imitation pulse) FCL1 is output from the delay circuit (delay amount A) 32 and sent to the delay unit 33-1. Entered.

【0189】

When the forward pulse FCL1 (= 1) is input to the delay unit 33-1, the state of the state holding unit 47 of the delay unit 33-1 becomes the set state S. Further, the forward pulse advances while sequentially passing through the delay units 33-1, 33-2, ~ 33-n. In the delay unit where the forward pulse has passed, the state of the state holding unit 47 is maintained in the set state S.

【0190】

After this, the forward pulse passes through all the delay units 33-1, 33-2, ~ 33-n, and is output from the delay unit 33-n as an output pulse LST (= 1).

【0191】

This output pulse LST is input to the control pulse generation circuit 61. As a result, the control pulse generation circuit 61 generates a path switching signal of L = 1 and / L = 0. That is, when the output pulse LST is output, L = 1, / L = 0, the delay circuit 34 is deactivated, and the delay circuit 34 has a correction internal that matches the timing of the internal clock CLK. Clock CK ́ is output.

【0192】

Further, when the time maxΔ elapses after the internal clock CLK becomes 1 again, the reverse pulse RCL1 is output from the delay unit 33-1. When this reverse pulse RCL1 is input to the control pulse generation circuit 61, the control pulse generation circuit 61 causes L = after the timing at which the reverse pulse RCL1 is output from the delay circuit 34, that is, after the reverse pulse RCL1 disappears. Generates a path switching signal of 0 , / L = 1 .

【0193】

That is, the delay circuit 34 is initialized (activated), and the delay circuit 34 changes to a state in which the output signal RCL1 of the delay unit 33-1 can be output.

【0194】

The delay circuit 62, the inverter 63, and the NAND circuit 64 determine the pulse width of the reverse pulse output from the delay unit 33-1. That is, when the internal clock CLK is used for memory input / output control, after the reverse pulse disappears in the delay circuit 34, L = 0 and / L = 1, and the delay circuit 34 is initialized (activated). ) To be configured.

【0195】

However, each delay amount of the delay circuits 34, 62, 74 is set so as to have a relationship of D3> D2 + D2 ́.

【0196】

According to the clock control circuit having the above configuration, it is possible to generate a corrected internal clock CK ́ that is accurately synchronized with the CK to the external clock, and it is possible to achieve data transfer using a high-speed clock.

【0197】

Further, in the present embodiment, it is possible to determine whether to use the internal clock CK as it is or to use the corrected internal clock CK ́ synchronized with the external clock CK, depending on the frequency of the external clock CK.

【0198】

In other words, when exchanging data in synchronization with a high-speed clock in which the skew of the external clock CK and the internal clock CLK becomes a problem, the corrected internal clock CK ́ synchronized with the external clock CK is used. When exchanging data in synchronization with a clock that does not cause a problem with the skewer, the internal clock CK is normally used.

【0199】

Whether to use the internal clock or the correction internal clock is determined by the number of delay units.

【0200】

Therefore, when the cycle (cycle time) of the external clock CK is long, the difference between the external clock CK and the correction internal clock CK ́ does not become large.

【0201】

FIG. 23 shows a layout when the clock control circuit of the present invention is arranged on the chip.

【0202】

When the clock control circuit of the present invention is actually incorporated into a syslem as an IC, it is necessary to consider the delay (wiring delay) caused by the wiring capacitance.

【0203】

Therefore, first, the array of delay units (hereinafter referred to as STBD, Synchronous Traced Backwards Delay) 80 has a distance (or wiring delay amount) from the input buffer 13 and a distance (or wiring delay amount) to the output buffer (delay circuit) 34. ) Are the same.

【0204】

Next, the input buffer 13 and the STBD80 are connected by wiring with a wiring length of L. Here, the actual skew-D1 is the sum of the delay amount due to the input buffer 13 and the delay amount due to the wiring of the wiring length L.

【0205】

Next, the delay circuit 32 having the delay amount A will be examined. The delay amount A is represented by D1 + D2 as described above (see, for example, FIG. 6). Further, the actual delay amount D2 of the delay circuit (output buffer) 34 is the sum of the delay amount due to the output buffer 34 and the delay amount due to the wiring having the wiring length L.

【0206】

Therefore, the delay circuit having the delay amount A is the same pattern as the pattern 82 that forms the delay amount D2 and the pattern 82 that is reversed left and right with respect to the pattern 81 that forms the skew D1. It is composed of 84.

【0207】

With such a layout, the delay amounts A, D1 and D2 can be determined in consideration of the wiring delay, so that the correction internal clock CK ́ can be synchronized with the external clock CK more accurately. It will be possible.

【0208】

As described above, the clock control circuit of the present invention has the following effects.

【0209】

Since each delay unit has a state holding unit, the time Δf from the generation of the delay imitation pulse (forward pulse) FCL1 to the generation of the pulse of the internal clock CLK is accurately copied to form Δb. The reverse pulse RCL1 can be input to the delay circuit having the delay amount D2 after a time Δb (= Δf) after the pulse of the internal clock CLK is generated.

【0210】

This situation is schematically shown in FIGS. 24 to 27.

【0211】

That is, in the initial state, as shown in FIG. 24, the forward pulse delay circuit and the reverse pulse delay circuit of the delay units 33-1 to 33-n are all in a state of outputting "0".

【0212】

Further, as shown in FIG. 25, when a forward pulse is input to the delay unit 33-4, the state holding portion of the delay unit 33-4 becomes the set state S, and then a pulse of the internal clock CLK is generated, the state is held. The delay units 33-5 to 33-n whose unit is in the reset state R output "1".

【0213】

That is, since the front F1 of the forward pulse and the front F2 of the reverse pulse coincide with each other, the delay amount Δf and the delay amount Δb are the same.

【0214】

After this, as shown in FIGS. 26 and 27, the delay unit 33-4 is initialized to the reset state R, a reverse pulse is further formed, and the reverse pulse passes through the delay units 33-3, 33-2. Is output from the delay unit 33-1.

【0215】

By such an operation, it is possible to generate a corrected internal clock CK ́ that is accurately synchronized with the CK to the external clock, and it is possible to achieve data transfer using a high-speed clock.

【0216】

Also, by monitoring the signal output from the final stage of the delay unit, whether to use the internal clock CK as it is or to use the correction internal clock CK ́ synchronized with the external clock CK according to the frequency of the external clock CK. Can be determined.

【0217】

In other words, when exchanging data in synchronization with a high-speed clock in which the skew of the external clock CK and the internal clock CLK becomes a problem, the corrected internal clock CK ́ synchronized with the external clock CK is used. When exchanging data in synchronization with a clock that does not cause a problem with the skewer, the internal clock CK is normally used.

【0218】

Whether to use the internal clock or the correction internal clock is determined by the number of delay units.

【0219】

Therefore, when the cycle (cycle time) of the external clock CK is long, the difference between the external clock CK and the correction internal clock CK ́ does not become large.

【0220】

Furthermore, paying attention to the point that the delay amount A is represented by (D1 + D2), and considering the wiring delay, the pattern of the delay amount A is the same as the pattern forming the delay amounts D1 and D2. It is formed by the pattern of.

【0221】

Therefore, with the simplified layout, it is possible to configure a system in the memory chip that accurately synchronizes the correction internal clock CK ́ with the external clock CK.

【0222】

The present invention is effective for a memory such as a synchronous DRAM in which an internal clock may be temporarily interrupted and data is exchanged in synchronization with a high-speed clock whose frequency changes.

【0223】

FIG. 28 shows the clock control circuit of FIG. 2 in a simplified manner.

【0224】

D1 is a delay circuit having a delay amount D1, D2 is a delay circuit having a delay amount D2, A is a delay circuit having a delay amount D1 + D2, and STBD (Synchronous Traced Backward Delay) is an array of delay units. .. STBD consists of FD (Forward Delay) and BD (Backward Delay).

【0225】

According to the clock control circuit having such a configuration, as described above, the phase of the external clock CK and the phase of the internal clock CK ́ are completely matched (the skew is eliminated). Therefore, the clock control circuit having the above configuration is effective when data is output at the rising edge of the external clock CK (at the time of transition from L to H).

【0226】

On the other hand, in recent years, when the period of the external clock CK is T, in addition to the internal clock CK ́ without skew, the internal clock CKD whose phase is delayed by (k / j) × T with respect to the external clock CK is added. It is required to be generated accurately (k and j are coprime natural numbers and j> k).

【0227】

For example, when data is output at the rising and falling edges of the external clock CK, the phase is T / with respect to the external clock CK together with the internal clock CK ́ whose phase is the same as that of the external clock CK. It is necessary to generate an internal clock CKD delayed by 2 (= π).

【0228】

In such a case, if the phase of the internal clock CKD is not exactly delayed by T / 2 (= π) with respect to the phase of the external clock, the data window (data) at the time of data output will be displayed. The fixed period) becomes shorter, and erroneous data may be output.

【0229】

Therefore, in the following, a clock control circuit capable of accurately generating an internal clock CKD whose phase is delayed by (k / j) × T with respect to the external clock CK will be described.

【0230】

FIG. 29 shows a first example of the configuration of the clock control circuit of the present invention.

【0231】

This clock control circuit generates an internal clock CKD whose phase is delayed by T / 2 (= π) with respect to the external clock CK together with an internal clock CK ́ whose phase is matched with respect to the external clock CK (T is External clock period).

【0232】

The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A, and the delay circuit 32 outputs the delay imitation pulse CL (forward pulse FCL1).

【0233】

The delay imitation pulse CL is input to the FD (Forward Delay) of STBD (Synchronous Traced Backward Delay). After the delay imitation pulse CL advances by the delay amount Δ in FD, a backward pulse is generated in BD (Backward Delay) and HBD (Half Backward Delay), respectively.

【0234】

The reverse pulse RCL in the BD is output from the BD after being moved backward by exactly the delay amount Δ. In addition, the reverse pulse HCL in the HBD is output from the HBD after being accurately moved backward by the delay amount Δ / 2 minutes.

【0235】

The internal clock CLK is input to BD and HBD and determines the timing of generation of the reverse pulse. The inverted internal clock / CLK, which is the inverted internal clock CLK by the inverter 35, is input to the FD and controls the period (delay amount) in which the forward pulse advances.

【0236】

The reverse pulse RCL becomes the corrected internal clock CK ́ that matches the phase of the external clock CK when passing through the delay circuit 34 having the delay amount D1 + (D2 × 2). Further, the reverse pulse HCL becomes an internal clock CKD whose phase is delayed by T / 2 (= 180 °) with respect to the external clock CK when passing through the delay circuit 36 having the delay amount D2.

【0237】

Here, the delay amount A of the delay circuit 32 is set to 2 × (D1 + D2).

【0238】

FIG. 30 shows a second example of the configuration of the clock control circuit of the present invention.

【0239】

This clock control circuit generates an internal clock CKD whose phase is delayed by T / j (= 2π / j) with respect to the external clock CK together with an internal clock CK ́ whose phase is matched with respect to the external clock CK. There is (T is the period of the external clock, j is a natural number).

【0240】

The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A, and the delay circuit 32 outputs the delay imitation pulse CL (forward pulse FCL1).

【0241】

The delay imitation pulse CL is input to the FD (Forward Delay) of STBD (Synchronous Traced Backward Delay). After the delay imitation pulse CL advances by the delay amount Δ in FD, a backward pulse is generated in BD (Backward Delay) and 1 / jBD (Backward Delay), respectively.

【0242】

The reverse pulse RCL in the BD is output from the BD after being moved backward by exactly the delay amount Δ. Further, the reverse pulse 1 / jCL in 1 / jBD is output from 1 / jBD after being backward by exactly the delay amount Δ / j.

【0243】

The internal clock CLK is input to BD and 1 / jBD and determines the timing of generation of the reverse pulse. The inverted internal clock / CLK, which is the inverted internal clock CLK by the inverter 35, is input to the FD and controls the period (delay amount) in which the forward pulse advances.

【0244】

The reverse pulse RCL becomes a corrected internal clock CK ́ that matches the phase of the external clock CK when passing through the delay circuit 34 having a delay amount (j-1) × D1 + j × D2. Further, the reverse pulse 1 / jCL becomes an internal clock CKD whose phase is delayed by T / j (= 360 ° / n) with respect to the external clock CK when passing through the delay circuit 36 having the delay amount D2.

【0245】

Here, the delay amount A of the delay circuit 32 is set to j × (D1 + D2).

【0246】

FIG. 31 shows a third example of the configuration of the clock control circuit of the present invention.

【0247】

This clock control circuit has an internal clock CK ́ whose phase is matched with respect to the external clock CK, and an internal clock whose phase is delayed by (k / j) × T (= 2π × k / j) with respect to the external clock CK. It generates a CKD (T is the period of the external clock, k and j are natural numbers that are in phase with each other, j> k).

【0248】

The external clock CK is input to the input buffer 13 having a delay amount k × D1. The input buffer 13 outputs an internal clock CLK having a skew of k × D1 with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A, and the delay circuit 32 outputs the delay imitation pulse CL (forward pulse FCL1).

【0249】

The delay imitation pulse CL is input to the FD (Forward Delay) of STBD (Synchronous Traced Backward Delay). After the delay imitation pulse CL advances by the delay amount Δ in FD, a backward pulse is generated in BD (Backward Delay) and k / jBD (Backward Delay), respectively.

【0250】

The reverse pulse RCL in the BD is output from the BD after being moved backward by exactly the delay amount Δ. Further, the reverse pulse k / jCL in k / jBD is output from k / jBD after being backward by exactly the delay amount Δ × (k / j).

【0251】

The internal clock CLK is input to BD and k / jBD and determines the timing of generation of the reverse pulse. The inverted internal clock / CLK, which is the inverted internal clock CLK by the inverter 35, is input to the FD and controls the period (delay amount) in which the forward pulse advances.

【0252】

The reverse pulse RCL becomes a corrected internal clock CK ́ that matches the phase of the external clock CK when passing through the delay circuit 34 having a delay amount (jk) × D1 + j × D2. Further, the reverse pulse k / jCL is delayed by T × (k / j) (= 360 ° × k / j) with respect to the external clock CK when passing through the delay circuit 36 having the delay amount k × D2. It becomes the internal clock CKD.

【0253】

Here, the delay amount A of the delay circuit 32 is set to j × (D1 + D2).

【0254】

FIG. 32 shows a fourth example of the configuration of the clock control circuit of the present invention.

【0255】

This clock control circuit has an internal clock CK ́ whose phase is matched with respect to the external clock CK, and an internal clock whose phase is delayed by T × (k / j) (= 2π × k / j) with respect to the external clock CK. It generates a CKD (T is the period of the external clock, k and j are natural numbers that are in phase with each other, j> k).

【0256】

The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A, and the delay circuit 32 outputs the delay imitation pulse CL (forward pulse FCL1).

【0257】

The delay imitation pulse CL is input to the FD (Forward Delay) of STBD (Synchronous Traced Backward Delay). After the delay imitation pulse CL advances by the delay amount Δ in FD, a backward pulse is generated in BD (Backward Delay) and k / jBD (Backward Delay), respectively.

【0258】

The reverse pulse RCL in the BD is output from the BD after being moved backward by exactly the delay amount Δ. Further, the reverse pulse k / jCL in k / jBD is output from k / jBD after being backward by exactly the delay amount Δ × (k / j).

【0259】

The internal clock CLK is input to BD and k / jBD and determines the timing of generation of the reverse pulse. The inverted internal clock / CLK, which is the inverted internal clock CLK by the inverter 35, is input to the FD and controls the period (delay amount) in which the forward pulse advances.

【0260】

The reverse pulse RCL becomes a corrected internal clock CK ́ that matches the phase of the external clock CK when passing through the delay circuit 34 having a delay amount (j-1) × D1 + j × D2. Further, the reverse pulse k / jCL has a phase of T × (k / j) (= 360 °) with respect to the external clock CK when passing through the delay circuit 36 having a delay amount (k-1) × D1 + k × D2. The internal clock CKD is delayed by × k / j).

【0261】

Here, the delay amount A of the delay circuit 32 is set to j × (D1 + D2).

【0262】

FIG. 33 shows a fifth example of the configuration of the clock control circuit of the present invention.

【0263】

This clock control circuit has a phase of T / 4 (= 90 °), T / 2 (= 180 °), and 3T / with respect to the external clock CK, together with an internal clock CK ́ that is in phase with the external clock CK. The internal clocks CKQ, CKH, and CK3Q delayed by 4 (= 270 °) are generated respectively.

【0264】

The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A, and the delay circuit 32 outputs the delay imitation pulse CL (forward pulse FCL1).

【0265】

The delay imitation pulse CL is input to the FD (Forward Delay) of the SAD (Synchronous Adjustable Delay). SAD includes STBD (Synchronous Traced Backward Delay) and so on.

【0266】

After the delay imitation pulse CL advances by the delay amount Δ in FD, a backward pulse is generated in BD (Backward Delay), QBD (Quarter Backward Delay), HBD (Half Backward Delay) and 3QBD (3 Quarters Backward Delay), respectively. ..

【0267】

The reverse pulse RCL in the BD is output from the BD after being moved backward by the delay amount Δ minutes (X delay elements). The reverse pulse QCL in the QBD is output from the QBD after moving backward by a delay amount of Δ / 4 minutes (delay element X / 4), and the reverse pulse HCL in the HBD has a delay amount of Δ / 2 minutes (delay amount Δ / 2 minutes). The reverse pulse 3QCL in 3QBD is output from 3QBD after moving backward by the delay amount of 3Δ / 4 minutes (delay element 3X / 4). To.

【0268】

The internal clock CLK is input to BD, QBD, HBD, and 3QBD, respectively, and determines the timing of generation of the reverse pulse. The inverted internal clock / CLK, which is the inverted internal clock CLK by the inverter 35, is input to the FD and controls the period (delay amount) in which the forward pulse advances.

【0269】

The reverse pulse RCL becomes a corrected internal clock CK ́ that matches the phase of the external clock CK when passing through the delay circuit 34 having a delay amount (D1 × 3 + D2 × 4).

【0270】

Further, the reverse pulse QCL becomes an internal clock CKQ whose phase is delayed by T / 4 (= 90 °) with respect to the external clock CK when passing through the delay circuit 36a having the delay amount D2.

【0271】

Further, the reverse pulse HCL becomes an internal clock CKH whose phase is delayed by T / 2 (= 180 °) with respect to the external clock CK when passing through the delay circuit 36b having a delay amount (D1 + D2 × 2).

【0272】

Furthermore, the reverse pulse 3QCL has an internal clock CKD whose phase is delayed by 3T / 4 (= 270 °) with respect to the external clock CK via the delay circuit 36c having a delay amount (D1 × 2 + D2 × 3). Become.

【0273】

Here, the delay amount A of the delay circuit 32 is set to 4 × (D1 + D2).

【0274】

FIG. 34 shows in detail the configuration of the clock control circuit of FIG. 32.

【0275】

The external clock CK is given to the input terminal 30 of the memory. The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A, and the delay circuit 32 outputs the forward pulse FCL1 (delay imitation pulse CL).

【0276】

The internal clock CLK and the inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 are input to n (n is a natural number) delay units 33-1, 33-2, ... 33-n, respectively. Will be done.

【0277】

The n delay units 33-1, 33-2, ... 33-n are connected in series with each other. The forward pulse FCL1 is input to the first-stage delay unit 33-1, and the reverse pulse RCL1 is output from the first-stage delay unit 33-1.

【0278】

The control pulses P and / P output by the control pulse generation circuit 60 are input to the n delay units 33-1, 33-2, ... 33-n. Further, the delay unit 33-i (i is 1 to n) outputs control pulses Qi, / Qi. The control pulses Qi, / Qi are input to k / jBD37.

【0279】

The reverse pulse RCL1 becomes the correction internal clock CK ́ by passing through the delay circuit 34 having the delay amount (j-1) × D1 + j × D2.

【0280】

The reverse pulse k / jCL has a phase of T × (k / j) (= 360 °) with respect to the external clock CK by passing through a delay circuit 36 having a delay amount (k-1) × D1 + k × D2. The internal clock CKD is delayed by × k / j).

【0281】

FIG. 35 shows in detail the first example of the configuration of the delay unit of FIG. 34.

【0282】

The delay unit Ui (i = 1 to n) is composed of three parts: a forward pulse delay circuit, a state holding circuit, and a reverse pulse delay circuit.

【0283】

The forward pulse delay circuit is composed of three inverters 41 to 43. The inverters 41 and 42 are connected in series, the output signal FCLi of the delay unit in the previous stage is input to the inverter 41, and the inverter 42 outputs the output signal FCLi + 1 to the delay unit in the subsequent stage. .. The operation of the inverter (clocked inverter) 41 is controlled by the control pulse / P. For example, when the control pulse / P is 1, the inverter 41 is in the active state.

【0284】

Further, the output end of the inverter 43 is connected to the input end of the inverter 42, and a potential of "0" (for example, a ground potential) is always applied to the input end of the inverter 43. The operation of the inverter (clocked inverter) 43 is controlled by the control pulse P. For example, when the control pulse P is 1, the inverter 43 is in the active state.

【0285】

The reverse pulse delay circuit is composed of three inverters 44 to 46. The inverters 44 and 45 are connected in series, the output signal RCLi + 1 or the internal clock CLK of the delay unit in the subsequent stage is input to the inverter 44, and the inverter 45 outputs the output signal to the delay unit in the previous stage. Output RCLi. The operation of the inverter (clocked inverter) 44 is controlled by the control pulse Qi. For example, the inverter 44 is activated only when the control pulse Qi is 1.

【0286】

Further, the output end of the inverter 46 is connected to the input end of the inverter 45, and the internal clock CLK is always input to the input end of the inverter 46. The operation of the inverter (clocked inverter) 46 is controlled by the control pulse / Qi. For example, when the control pulse / Qi is 1, the inverter 46 is in the active state.

【0287】

The state-holding circuit is composed of a state-holding unit 47 and NAND circuits 48 and 49. The output signal FCLi and the inverted internal clock / CLK of the delay unit in the previous stage are input to the NAND circuit 48, and the output signal of the inverter 45 and the internal clock CLK are input to the NAND circuit 49.

【0288】

The output signal of the NAND circuit 48 is the set input / S of the state holding unit 47, and the output signal of the NAND circuit 49 is the reset input / R of the state holding unit 47. Therefore, when the output signal (set input) / S of the NAND circuit 48 becomes 0, the state holding unit 47 becomes the set state, and the output signal (reset input) / R of the NAND circuit 49 becomes 0. At that time, the state holding unit 47 is in the reset state.

【0289】

The state holding unit 47 is also configured to output control pulses Q, / Q. The control pulse Q is 1 when the state holding unit 47 is in the set state, and the control pulse / Q is 1 when the state holding unit 47 is in the reset state.

【0290】

As the state holding unit 47, for example, one having a configuration as shown in FIG. 4 can be used.

【0291】

In the delay unit Ui through which the forward pulse has passed, the control pulse Qi becomes H and / Qi becomes L. On the other hand, in the delay unit Ui through which the reverse pulse has passed, the control pulse Qi becomes L and / Qi becomes H.

【0292】

FIG. 36 shows in detail a second example of the configuration of the delay unit of FIG. 34.

【0293】

The delay unit Ui (i = 1 to n) is composed of three parts: a forward pulse delay circuit fdi, a state holding circuit sri, and a reverse pulse delay circuit bdi.

【0294】

The forward pulse delay circuit fdi is composed of five inverters 91 to 95. The inverters 91 to 93 are connected in series, the output signal FCLi of the delay unit in the previous stage is input to the inverter 91, and the inverter 92 outputs the output signal FCLi + 1 to the delay unit in the subsequent stage. .. The operation of the inverter (clocked inverter) 91 is controlled by the control pulse / P. For example, when the control pulse / P is 1, the inverter 91 is in the active state.

【0295】

Further, the output end of the inverter 94 is connected to the output end of the inverter 91 and to the input ends of the inverters 92 and 95, and the input end of the inverter 94 is always 0. (For example, ground potential) is applied. The operation of the inverter (clocked inverter) 94 is controlled by the control pulse P. For example, when the control pulse P is 1, the inverter 94 is in the active state.

【0296】

The reverse pulse delay circuit bdi is composed of five inverters 96 to 100. The inverters 96 to 98 are connected in series, the output signal RCLi + 1 or the internal clock CLK of the delay unit in the subsequent stage is input to the inverter 96, and the inverter 97 outputs a signal to the delay unit in the previous stage. Output RCLi. The operation of the inverter (clocked inverter) 96 is controlled by the control pulse Qi. For example, the inverter 96 is activated only when the control pulse Qi is 1.

【0297】

Further, the output end of the inverter 99 is connected to the output end of the inverter 96 and the input end of the inverters 97 and 100, and the internal clock CLK is always connected to the input end of the inverter 99. It has been entered. The operation of the inverter (clocked inverter) 99 is controlled by the control pulse / Qi. For example, when the control pulse / Qi is 1, the inverter 99 is in the active state.

【0298】

The state holding circuit sri is composed of P-channel MOS transistors 101, 102, N-channel MOS transistors 103, 104, and an inverter 105.

【0299】

The P-channel MOS transistors 101 and 102 are connected in series between the power supply terminal and the node Z, and the N-channel MOS transistors 103 and 104 are connected in series between the ground terminal and the node Z.

【0300】

The clock signal / CLK in which the internal clock CLK is inverted is input to the gates of the MOS transistors 101 and 104, and the output signal / RCLi-3 of the delay unit Ui-3 is input to the gate of the MOS transistor 102. , The output signal FFCLi of the delay unit Ui-1 is input to the gate of the MOS transistor 103.

【0301】

The input end of the inverter 105 is connected to the node Z, and the control pulse Qi-2 is output from the output end of the inverter 105. The control pulse / Qi-2 is output from the throat Z.

【0302】

37 and 38 show an example of the configuration of k / jBD of FIG. 34.

【0303】

In this example, the case where k is 1 and j is 2, that is, the case where the phase is delayed by T / 2 with respect to the external clock will be described. In this case, k / jBD becomes HBD (Half Backward Delay).

【0304】

The HBD is composed of m (m is a natural number) delay units bdi (i = 1 to m) connected in series. The configuration of each delay unit bdi is the same as the configuration of the reverse pulse delay circuit bdi of the delay unit Ui of the SAD (Synchronous Adjustable Delay).

【0305】

Therefore, the ratio of the delay amount of the reverse pulse in BD to the delay amount of the reverse pulse in HBD is the ratio of the number of delay units in BD to the number of delay units in HBD, to be exact, the number of delay units of BD in one block. Equal to the ratio of the number of delay units in the HBD.

【0306】

Specifically, in this example, n delay units Ui (i = 1 to n) and m delay units bdi (i = 1 to m) are each divided into r (r is a natural number) block B ( It is evenly divided into 1), B (2), ... B (r).

【0307】

For example, block B (1) is composed of two delay units U1 and U2 and one delay unit bd1, and control pulses Q1, / Q1 for controlling the delay unit U1 and control pulses Q2, for controlling the delay unit U2. One of / Q2 is given to the delay unit bd1.

【0308】

Similarly, block B (r) is composed of two delay units Un-1, Un and one delay unit bdm, and has a control pulse Qn-1, / Qn-1 and a delay that control the delay unit Un-1. One of the control pulses Qn and / Qn that controls the unit Un is given to the delay unit bdm.

【0309】

That is, in this example, one delay unit of HBD is provided for two delay units of SAD. Therefore, in BD, the reverse pulse is delayed by Δ, whereas in HBD, the reverse pulse is delayed by Δ / 2.

【0310】

In the case of this example, r and m are equal and have a relationship of m = n / 2. Also, the relatively prime natural numbers j and k that often appear in the above explanation are j = 2 (equal to the number of delay units of SAD in one block) and k = 1 (delay of HBD in one block), respectively. Equal to the number of units).

【0311】

The total number of delay units n of SAD is j (2 in this example) × r, and the total number of delay units m of HBD is k (1) × r in this example.

【0312】

Further, the delay units bd1 to bdm of the HBD should be evenly arranged with respect to the delay units U1 to Un of the SAD. In other words, by associating one delay unit of HBD with two adjacent delay units of SAD, it is possible to generate a delay of Δ / 2 accurately.

【0313】

FIG. 39 shows an example of the configuration of the delay unit bdi in HBD.

【0314】

This example is an example when the delay unit Ui shown in FIG. 35 is used. That is, since the reverse pulse delay circuit of the delay unit Ui is composed of three inverters 44 to 46, the delay unit bdi in the HBD is also composed of three inverters 44 ́ to 46 ́.

【0315】

The inverter 44 ́, 45 ́ is connected in series, the output signal HCLi + 1 or the internal clock CLK of the delay unit in the subsequent stage is input to the inverter 44 ́, and the inverter 45 ́ is the delay in the previous stage. The output signal HCLi is output to the unit. The operation of the inverter (clocked inverter) 44 ́ is controlled by the control pulse Qi. For example, the inverter 44 ́ is activated only when the control pulse Qi is 1.

【0316】

Further, the output end of the inverter 46 ́ is connected to the input end of the inverter 45 ́, and the internal clock CLK is always input to the input end of the inverter 46 ́. The operation of the inverter (clocked inverter) 46 ́ is controlled by the control pulse / Qi. For example, when the control pulse / Qi is 1, the inverter 46 ́ is in the active state.

【0317】

FIG. 40 symbolizes the delay unit bdi of FIG. 39. Therefore, the circuit of FIG. 39 and the circuit of FIG. 40 show the same thing.

【0318】

FIG. 41 shows an example of the configuration of k / jBD of FIG. 34.

【0319】

In this example, the case where j is 3 and k is 1, that is, the case where the phase is delayed by T / 3 with respect to the external clock will be described.

【0320】

The 1 / 3BD is composed of m delay units bdi (i = 1 to m) connected in series. The configuration of each delay unit bdi is the same as the configuration of the reverse pulse delay circuit bdi of the delay unit Ui of the SAD (Synchronous Adjustable Delay).

【0321】

Therefore, the ratio of the delay amount of the reverse pulse in BD to the delay amount of the reverse pulse in 1/3 BD is the ratio of the number of delay units in BD to the number of delay units in 1/3 BD, to be exact, in one block. It is equal to the ratio of the number of BD delay units to the number of 1/3 BD delay units.

【0322】

Specifically, in this example, n delay units Ui (i = 1 to n) and m delay units bdi (i = 1 to m) are combined with r blocks B (1) and B (2). ), ... B (r) is evenly divided.

【0323】

For example, block B (1) is composed of three delay units U1 to U3 and one delay unit bd1, and control pulses Q1 and / Q1 for controlling the delay unit U1 are given to the delay unit bd1. However, instead of the control pulses Q1 and Q1, a control pulse for controlling the delay unit U2 or the delay unit U3 may be given to the delay unit bd1.

【0324】

That is, in this example, one 1/3 BD delay unit is provided for each of the three SAD delay units. Therefore, in BD, the reverse pulse is delayed by Δ3, whereas in 1/3 BD, the reverse pulse is delayed by Δ / 3.

【0325】

In the case of this example, r and m are equal and have a relationship of m = n / 3. Also, the relatively prime natural numbers j and k that often appear in the above explanation are j = 3 (equal to the number of delay units of SAD in one block) and k = 1 (delay of HBD in one block), respectively. Equal to the number of units).

【0326】

The total number of delay units n of SAD is j (3 in this example) × r, and the total number of delay units m of HBD is k (1) × r in this example.

【0327】

Also, it is preferable to arrange the 1/3 BD delay units bd1 to bdm evenly with respect to the SAD delay units U1 to Un. In other words, if one delay unit of 1/3 BD is associated with three adjacent delay units of SAD, a delay of Δ / 3 can be generated accurately.

【0328】

FIG. 42 shows an example of the configuration of k / jBD of FIG. 34.

【0329】

In this example, the case where k is 2 and j is 3, that is, the case where the phase is delayed by 2T / 3 with respect to the external clock will be described.

【0330】

The 2 / 3BD is composed of m delay units bdi (i = 1 to m) connected in series. The configuration of each delay unit bdi is the same as the configuration of the reverse pulse delay circuit bdi of the delay unit Ui of the SAD (Synchronous Adjustable Delay).

【0331】

Therefore, the ratio of the delay amount of the reverse pulse in BD to the delay amount of the reverse pulse in 2/3 BD is the ratio of the number of delay units in BD to the number of delay units in 2/3 BD, to be exact, the ratio of BD in one block. It is equal to the ratio of the number of delay units to the number of delay units of 2/3 BD.

【0332】

Specifically, in this example, n delay units Ui (i = 1 to n) and m delay units bdi (i = 1 to m) are combined with r blocks B (1) and B (2). ), ... B (r) is evenly divided.

【0333】

For example, block B (1) is composed of three delay units U1 to U3 and two delay units bd1 and bd2, and control pulses Q1 and / Q1 for controlling the delay unit U1 are given to the delay unit bd1 to give the delay unit bd1. The control pulses Q3 and / Q3 that control U3 are given to the delay unit bd2.

【0334】

However, the control pulses Q1, / Q1, Q2, / Q2 may be given to the delay units bd1, bd2 instead of the control pulses Q1, / Q1, Q3, / Q3, and the control pulses Q2, / Q2, Q3, / Q3 may be given to the delay units bd1 and bd2.

【0335】

That is, in this example, two delay units of 2/3 BD are provided for three delay units of SAD. Therefore, in BD, the reverse pulse is delayed by Δ, whereas in 2/3 BD, the reverse pulse is delayed by 2Δ / 3.

【0336】

In the case of this example, there is a relationship of m = 2n / 3. Also, the relatively prime natural numbers j and k that often appear in the above explanation are j = 3 (equal to the number of delay units of SAD in one block) and k = 2 (delay of HBD in one block), respectively. Equal to the number of units).

【0337】

The total number of delay units n of SAD is j (3 in this example) × r, and the total number of delay units m of HBD is k (2) × r in this example. Moreover, since m / n = k × r / j × r, there is a relationship of m / n = k / j.

【0338】

Also, it is preferable to arrange the 2 / 3BD delay units bd1 to bdm evenly with respect to the SAD delay units U1 to Un. In other words, if two delay units of 2 / 3BD are associated with three adjacent delay units of SAD, a delay of 2Δ / 3 can be generated accurately.

【0339】

FIG. 43 generally shows the configuration of the k / jBD of FIG. 34. FIG. 44 shows the configuration of k / jBD in one block B (i) of FIG. 43.

【0340】

The SAD is composed of r blocks B (1) to B (r). In SAD, each block contains j delay units. Similarly, k / jBD is composed of r blocks B (1) to B (r). In k / jBD, each block contains k delay units.

【0341】

j and k are coprime natural numbers and are generally set to j> k. Since there are r blocks, the total number n of delay units in SAD is r × j, and the total number m of delay units in k / jBD is r × k.

【0342】

The number of blocks in SAD and the number of blocks in k / jBD are equal. For example, SAD block B (1) corresponds to k / jBD block (1), SAD block B (2) corresponds to k / jBD block (2), and SAD block B (r). ) Corresponds to the k / jBD block (r).

【0343】

For example, the SAD block (1) is controlled by j sets of control pulses Q1, / Q1, Q2, / Q2, ... Qj, / Qj. Therefore, only k (<j) pairs of these j pairs of control pulses are selected, and these k pairs of control pulses are supplied to the block (1) of k / jBD.

【0344】

The k sets of control pulses are regularly and evenly selected from the j sets of control pulses Q1, / Q1, Q2, / Q2, ... Qj, / Qj.

【0345】

Also, the selected k sets of control pulses are regularly given to the corresponding k delay units in k / jBD. For example, when the control pulses Q1, / Q1, Q2, / Q2 are selected, the control pulses Q1, / Q1 are given to the delay unit bd1 of k / jBD (not given to bd2), and the control pulses Q2, / Q2 are given. Is given to the delay unit bd2 of k / jBD (not given to bd1).

【0346】

According to such a configuration, the ratio of the number of delay units of SAD to the number of delay units of k / jBD is always k / j = m / n regardless of the position of the delay unit reached by the forward pulse of SAD. Will meet. Therefore, the delay amount of k / jΔ can be accurately generated in k / jBD regardless of the position of the delay unit reached by the forward pulse.

【0347】

Next, the principle of the present invention (in the case of the example of FIG. 31) will be described with reference to FIG. 45.

【0348】

The skew width (delay amount) of the external clock CK and the internal clock CLK is k × D1, and the period of the external clock CK and the internal clock CLK is T.

【0349】

A delayed imitation pulse CL is generated when time A elapses from the time when the first pulse of the internal clock CLK is generated (when it rises). In this case, the time from the time when the delayed imitation pulse CL is generated to the time when the second pulse of the internal clock CLK is generated is Δf.

【0350】

In addition, this time Δf is copied to create Δb so that the delayed imitation pulse RCL is generated when the time 2 × Δ (where Δf = Δb = Δ) elapses from the time when the delayed imitation pulse CL is generated. To. Then, the time point at which time A elapses from the time point at which the delayed imitation pulse RCL is generated coincides with the time point at which the third pulse of the internal clock CLK is generated. However, (A + W) <T. W is the width of the delayed imitation pulses CL and RCL.

【0351】

Assuming that the time from the time when the delayed imitation pulse RCL is generated to the time when the third pulse of the external clock CK is generated is (jk) × D1 + j × D2, the delayed imitation pulse RCL is time (jk) × D1 + j. If the delay is made by × D2, the corrected internal clock CK ́ that matches the timing of the external clock CK can be obtained.

【0352】

That is, a delay circuit that generates delay amounts A, (2 × Δ), (jk) × D1 + j × D2 is formed, and the internal clock CLK is set to time A + (2 × Δ) + {(jk) × D1 + j. By delaying by × D2}, the corrected internal clock CK ́ that matches the timing of the external clock CK can be obtained.

【0353】

The delay amount (2 × Δ) is generated by the SAD, and the delay amount (jk) × D1 + j × D2 is generated by the delay element. The delay amount A is determined as follows.

【0354】

From the relationship in Fig. 45 k × D1 + A + Δ = T + k × D1 ... (1) k × D1 + A + 2Δ + (jk) × D1 + j × D2 = 2T ... (2) Can be guided.

【0355】

From equation (1), T = A + Δ ... (3) can be derived, and from equation (2), A + 2Δ + j (D1 + D2) = 2T ... (4) can be derived.

【0356】

From equations (3) and (4) A + 2Δ + j (D1 + D2) = 2 (A + Δ) A = j (D1 + D2) ... (5) Will be.

【0357】

The principle of generating the internal clock CKD delayed by (k / j) × T with respect to the external clock CK is as follows.

【0358】

A delay pulse k / j CL is generated when the time Δ + (k / j) × Δ elapses from the time when the time (k / j) × Δ (Δ = Δf = Δb) is created and the delay imitation pulse CL is generated. To do. In addition, the internal clock CKD is generated when the time k × D2 elapses from the time when the delay pulse k / jCL is generated.

【0359】

At this time, as is clear from FIG. 45, the internal clock CKD is different from the external clock CK. k × D1 + (k / j) × Δ + k × D2 ... (6) Will be late.

【0360】

When Eq. (6) is transformed, (k / j) × (j × D1 + Δ + j × D2) = (k / j) × {j (D1 + D2) + Δ} ... (7) Will be.

【0361】

Equation (7) is based on equations (3) and (5) above. (k / j) × T ... (8) Will be.

【0362】

That is, the internal clock CKD means that the phase is delayed by (k / j) × T with respect to the external clock CK.

【0363】

Therefore, a delay circuit that generates the delay amount A, Δ + (k / j) × Δ, k × D2 is formed, and the internal clock CLK is set to the time A + {Δ + (k / j) × Δ} + k × D2 only. If delayed, an internal clock CKD whose phase is delayed by (k / j) × T with respect to the external clock CK can be obtained.

【0364】

The delay amount Δ is generated by the FD of the SAD, and the delay amount k × D2 is generated by the delay element. The delay amount A is set to j (D1 + D2) by the above method as shown in Eq. (5).

【0365】

Next, the principle of the present invention (in the case of the example of FIG. 32) will be described with reference to FIG. 46.

【0366】

Let D1 be the skew width (delay amount) of the external clock CK and the internal clock CLK, and let T be the period of the external clock CK and the internal clock CLK.

【0367】

A delayed imitation pulse CL is generated when time A elapses from the time when the first pulse of the internal clock CLK is generated (when it rises). In this case, the time from the time when the delayed imitation pulse CL is generated to the time when the second pulse of the internal clock CLK is generated is Δf.

【0368】

In addition, this time Δf is copied to create Δb so that the delayed imitation pulse RCL is generated when the time 2 × Δ (where Δf = Δb = Δ) elapses from the time when the delayed imitation pulse CL is generated. To. Then, the time point at which time A elapses from the time point at which the delayed imitation pulse RCL is generated coincides with the time point at which the third pulse of the internal clock CLK is generated. However, (A + W) <T. W is the width of the delayed imitation pulses CL and RCL.

【0369】

If the time from the time when the delayed imitation pulse RCL is generated to the time when the third pulse of the external clock CK is generated is (j-1) × D1 + j × D2, the delayed imitation pulse RCL is the time (j-1). By delaying by × D1 + j × D2, a corrected internal clock CK ́ that matches the timing of the external clock CK can be obtained.

【0370】

That is, a delay circuit that generates delay amounts A, (2 × Δ), (j-1) × D1 + j × D2 is formed, and the internal clock CLK is set to time A + (2 × Δ) + {(j-1). By delaying by × D1 + j × D2}, the corrected internal clock CK ́ that matches the timing of the external clock CK can be obtained.

【0371】

The delay amount (2 × Δ) is generated by the SAD, and the delay amount (j-1) × D1 + j × D2 is generated by the delay element. The delay amount A is determined as follows.

【0372】

From the relationship shown in Fig. 46 D1 + A + Δ = T + D1 ... (9) D1 + A + 2Δ + (j-1) × D1 + j × D2 = 2T ... (10) Can be guided.

【0373】

From equation (9), T = A + Δ ... (11) can be derived, and from equation (10), A + 2Δ + j (D1 + D2) = 2T ... (12) can be derived.

【0374】

From equations (11) and (12) A + 2Δ + j (D1 + D2) = 2 (A + Δ) A = j (D1 + D2) ... (13) Will be.

【0375】

The principle of generating the internal clock CKD delayed by (k / j) × T with respect to the external clock CK is as follows.

【0376】

A delay pulse k / j CL is generated when the time Δ + (k / j) × Δ elapses from the time when the time (k / j) × Δ (Δ = Δf = Δb) is created and the delay imitation pulse CL is generated. To do. Further, the internal clock CKD is generated when the time (k-1) × D2 + k × D2 elapses from the time when the delay pulse k / jCL is generated.

【0377】

At this time, as is clear from FIG. 46, the internal clock CKD is different from the external clock CK. D1 + (k / j) × Δ + (k-1) × D1 + k × D2 ...(14) Will be late.

【0378】

When equation (14) is transformed, (k / j) × (j × D1 + Δ + j × D2) = (k / j) × {j (D1 + D2) + Δ} ... (15) Will be.

【0379】

Equation (15) is based on equations (11) and (12) above. (k / j) × T ... (16) Will be.

【0380】

That is, the internal clock CKD means that the phase is delayed by (k / j) × T with respect to the external clock CK.

【0381】

Therefore, a delay circuit that generates the delay amount A, Δ + (k / j) × Δ, k × D2 is formed, and the internal clock CLK is set to the time A + {Δ + (k / j) × Δ} + k × D2 only. If delayed, an internal clock CKD whose phase is delayed by (k / j) × T with respect to the external clock CK can be obtained.

【0382】

The delay amount Δ is generated by the FD of the SAD, and the delay amount k × D2 is generated by the delay element. The delay amount A is set to j (D1 + D2) by the above method as shown in Eq. (13).

【0383】

FIG. 47 shows the connection relationship between a controller that generates an external clock and receives data, and a memory that outputs data based on the internal clock generated from the external clock.

【0384】

In the above example, the technique of clearly determining the phase relationship between the external clock and the internal clock and outputting accurate data from the memory has been described. In this example, a technique capable of accurately receiving the accurate data read from such a memory by the controller will be described.

【0385】

In general, a memory system includes a controller (CPU) and a plurality of memories (ICs). In addition, it takes a certain amount of time for the external clock CK to reach the memories 1 and 2 from the controller. Therefore, first, the wiring lengths of the external clocks from the controller to each memory 1 and 2 are made equal.

【0386】

Further, the memory 1 or the memory 2 outputs data based on the internal clock having a constant phase relationship with the external clock CK. The data is guided to the controller via the data bus.

【0387】

The controller receives data from memory 1 or memory 2, but the data is output from memory 1 or memory 2 and input to the controller depending on the wiring length and wiring capacity of the data bus. It takes a certain amount of time.

【0388】

That is, in order for the controller to capture accurate data, it is necessary to capture the data at a timing that takes into consideration the propagation time of the data of the data bus.

【0389】

Therefore, a Dummy-Memory (IC) with an external clock input capacity equal to the memories 1 and 2 is prepared. The wiring length of the external clock from the controller to the damage memory is equal to the wiring length of the external clock from the controller to each memory 1 and 2.

【0390】

In addition, the external clock CK input to the Dami-IC is further returned to the controller, and this is used as the return clock.

【0391】

The return clock determines when the controller receives the output data of memory 1 or memory 2. Therefore, the wiring length of the return clock from the damage memory to the controller is equal to the data bus length from the memory 1 or the memory 2 to the controller.

【0392】

In this way, the controller receives data from memory 1 or memory 2 based on the return clock. Therefore, erroneous data is not input to the controller.

【0393】

[Effect of the invention]

As described above, the clock control circuit of the present invention has the following effects.

【0394】

It is possible to stably generate an internal clock that always has a constant phase relationship with the external clock, and even if the period of the external clock changes, it is internal to the external clock in the few cycles of the external clock. The clock will always have a constant phase relationship.

【0395】

Therefore, the present invention is most suitable for controlling a clock-synchronized DRAM data input / output circuit such as a so-called synchronous memory.

【0396】

In addition, when multiple data are output in one clock cycle by controlling to divide the clock cycle and output data, the phase is only a predetermined amount with respect to the external clock. Although a plurality of accurately deviated internal clocks are required, according to the present invention, such a plurality of internal clocks can be easily generated without using a complicated system such as a PLL.

[Simple explanation of drawings]

[Figure 1]

The figure which shows the main part of the system which provided the memory which has the circuit of this invention.

[Figure 2]

The figure which shows the structure of the clock control circuit in the memory of FIG.

[Fig. 3]

The circuit diagram which shows the delay unit in the circuit of FIG. 2 in detail.

[Fig. 4]

The circuit diagram which shows the state holding part in the delay unit of FIG. 3 in detail.

[Fig. 5]

The figure which shows the control pulse generation circuit in the circuit of FIG. 2 in detail.

[Fig. 6]

The figure which shows the principle of this invention.

[Fig. 7]

Timing diagram showing the operation of the circuits shown in FIGS. 2 to 5.

[Fig. 8]

The figure which shows the state of a of the timing diagram of FIG.

[Fig. 9]

The figure which shows the state b of the timing diagram of FIG.

[Fig. 10]

The figure which shows the state of c of the timing diagram of FIG.

[Fig. 11]

The figure which shows the state d of the timing diagram of FIG.

[Fig. 12]

The figure which shows the state of e of the timing diagram of FIG.

[Fig. 13]

The figure which shows the state of f of the timing diagram of FIG.

[Fig. 14]

The figure which shows the state of g of the timing diagram of FIG.

[Fig. 15]

The figure which shows the state of h of the timing diagram of FIG.

[Fig. 16]

The figure which shows the state of i of the timing diagram of FIG.

[Fig. 17]

The figure which shows the modification of the circuit of FIG.

[Fig. 18]

The figure which shows the modification of the circuit of FIG. [Fig. 19]

The figure which shows the delay circuit 34 in the circuit of FIG. 18 in detail.

[Fig. 20]

The figure which shows the control pulse generation extension circuit 61 in the circuit of FIG. 18 in detail. [Fig. 21]

The figure which shows the problem of the operation of the circuit of FIG.

[Fig. 22]

Timing diagrams showing the operation of the circuits of FIGS. 18 to 20.

[Fig. 23]

The figure which shows the layout when the circuit of this invention is incorporated in a chip.

[Fig. 24]

The figure which shows the operation of the circuit of FIG. 2 and FIG.

[Fig. 25]

The figure which shows the operation of the circuit of FIG. 2 and FIG.

[Fig. 26]

The figure which shows the operation of the circuit of FIG. 2 and FIG.

[Fig. 27]

The figure which shows the operation of the circuit of FIG. 2 and FIG.

[Fig. 28]

The figure which shows the schematic structure of the clock lock control circuit of FIG.

[Fig. 29]

The figure which shows the 1st example of the clock control circuit of this invention.

[Fig. 30]

The figure which shows the 2nd example of the clock control circuit of this invention.

[Fig. 31]

The figure which shows the 3rd example of the clock control circuit of this invention.

[Fig. 32]

The figure which shows the 4th example of the clock control circuit of this invention.

[Fig. 33]

The figure which shows the 5th example of the clock control circuit of this invention.

[Fig. 34]

The figure which shows the structure of the clock control circuit of FIG. 1 in detail.

[Fig. 35]

The figure which shows the structure of the delay unit Ui in the circuit of FIG. 34 in detail.

[Fig. 36]

The figure which shows the structure of the delay unit Ui in the circuit of FIG. 34 in detail.

[Fig. 37]

The figure which shows the 1st example of the structure of HBD.

[Fig. 38]

The figure which shows the 2nd example of the structure of HBD.

[Fig. 39]

The figure which shows the structure of the delay unit bdi of FIG. 37 or FIG. 38.

[Fig. 40]

The figure which shows the circuit of FIG. 39 as a symbol.

[Fig. 41]

The figure which shows the 1st example of the structure of 1/3 BD.

[Fig. 42]

The figure which shows the 2nd example of the structure of 1/3 BD.

[Fig. 43]

The figure which shows the structure of m / nBD.

[Fig. 44]

The figure which shows the structure of the block B (i) of FIG. 43.

[Fig. 45]

The figure which shows the principle of this invention.

[Fig. 46]

The figure which shows the principle of this invention.

[Fig. 47]

The figure which shows the structure of the memory system of this invention.

[Fig. 48]

The figure which shows the main part of the conventional system.

[Fig. 49]

A schematic showing a skew of the external and internal clocks of the system in Figure 48.

[Fig. 50]

The figure which shows the principle of the synchronization system which is the basis of this invention.

[Fig. 51]

The figure which shows an example of the circuit for achieving the principle of FIG.

[Fig. 52]

The figure which shows the state of determination of the delay amount Δf, Δb in the circuit of FIG. 51.

[Explanation of symbols]

11: Memory, 12: CPU, 13: Buffer, 14: Input circuit, 15: Output circuit, 16: Write / read circuit, 17: Memory cell array, 18: Data tapas, 21: Input terminal, 22: Input buffer, 23, 25-1 ~ 25-n, 29-1 ~ 29-n, 30: Delay circuit, 24: Forward delay array, 26: Mira-control circuit, 27-1 ~ 27-n: Control element, 28: Reverse delay array, 31: Clock synchronization delay control circuit, 32, 33-1 ~ 33-n, 34,57,62: Delay circuit, 41 ~ 46,59,63,66 ~ 68,70: Inverter, 47: State holding part, 48,49,64: NAND circuit, 51,52: P-channel MOS transistor, 53 ~ 56: N-channel MOS transistor, 58,69,71,72: NOR circuit, 60,61: Control pulse generation circuit, 73: NAND circuit, 74: Delay circuit, 75: Inverter, 81 ~ 84: Circuit pattern.