Clock control circuit

An external clock signal CK is input to a buffer (13), which generates an internal clock signal CLK having a skew of D1 with respect to the external clock signal CK. The internal clock signal is input first to a delay circuit (32) which has a delay time A, then to a delay array which provides a delay time D2, and finally to a delay circuit (34) which has a delay time of D2. The delay circuit (34) generates a corrected internal clock signal CK' which is synchronous with the external clock signal CK. The delay array is composed of delay units (33-1 to 33-n), each having a state-holding section. The state-holding section of any delay unit that has passed a forward pulse is set in a predetermined state. Once its state-holding section is set in the predetermined state, the delay unit provides a correct delay time of 2 × Δ.