Random number generation circuit

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention is provided for, for example, in the case of performing data transmission between a battery-powered portable electronic device equipped with a microcomputer and a device equipped with a microcomputer, each of these portable electronic devices and devices is provided. It relates to a random number generation circuit used for encrypting data to be transmitted from the viewpoint of confidentiality.

【0002】

[Conventional technology]

FIG. 2 is a schematic configuration diagram of a conventional random number generation circuit, and FIG. 3 is a diagram showing the encryption process of FIG. The random number generation circuit in FIG. 2 is a clock that divides an oscillation circuit (hereinafter referred to as OSC) 1 that oscillates at a constant frequency and the output signal of the OSC1 and outputs output data (that is, random number data) DA. It is composed of a self-propelled counter 2 such as. The output data DA of the self-propelled counter 2 is read by a central processing unit (hereinafter referred to as "CPU") (not shown), arithmetic processing is performed by the CPU, and the data to be transmitted is encrypted and transmitted to the outside. It has become like. In FIG. 3, it is shown that the CPU reads the output data DA of the self-propelled counter 2 at an arbitrary time. When power is supplied to the device equipped with the random number generation circuit shown in FIG. 2, the self-propelled counter 2 starts counting at any time when the power is supplied, and further, at any time when this device is used. Therefore, after a certain program processing by the CPU, the CPU outputs data DA (for example, D) of the self-propelled counter 2._{n + 1}) Is read to obtain random number data. The CPU performs arithmetic processing on the read random number data to encrypt the data to be transmitted, and sends the data to the outside from a transmission unit (not shown).

【0003】

[Problems to be Solved by the Invention]

However, the conventional random number generation circuit has the following problems, and it is difficult to solve them. (a) In the random number generation circuit of FIG. 2, in order to obtain random output data DA, that is, random number data, the OSC1 and the self-propelled counter 2 must be constantly supplied with power and operated. Therefore, when the device equipped with the random number generation circuit of FIG. 2 is driven by a battery, for example, there is a problem that the life of the battery is shortened, that is, the power consumption is large. (b) In order to reduce the power consumption in (a) above, for example, a method of supplying power supply power only when the device is in use can be considered. In the case of this method, the timing at which the CPU reads the output data DA has a certain regularity because the CPU performs a certain program process in preparation for reading from the time the power is turned on. In addition, the value of the output data DA of the self-propelled counter 2 also has a certain regularity after a certain period of time after the power is turned on. Therefore, the value of the output data DA read by the CPU has a certain regularity and does not become a sufficient random number. The present invention solves the problems of the prior art, and provides, for example, a random number generation circuit capable of obtaining highly reliable random number data while reducing power consumption by turning on the power only when in use. Is what you do.

【0004】

[Means for solving problems]

In order to solve the above problems, the first invention comprises an oscillating means (for example, an oscillating circuit) that oscillates at a constant frequency when a power is turned on in a random number generation circuit provided in various devices such as a data transmission device. A clock generation means (for example, composed of a plurality of stages of frequency dividing circuits or the like) that generates and outputs a clock signal having a jitter width larger than a half cycle of the output signal based on the output signal of the oscillation means, and the clock. With a sampling means (for example, a flip flop circuit or the like) that samples the output signal of the oscillation means by the jitter in the output signal of the generation means and outputs random data composed of logic signals (for example, 1 and 0). Is equipped. According to the second invention, in a random number generation circuit, a first oscillating means that oscillates at a constant frequency when a power is turned on and an oscillating means that oscillates at a frequency that is a non-infinite multiple of the first oscillating means when the power is turned on. A clock generation means that generates and outputs a clock signal having a jitter width larger than a half cycle of the output signal of the first oscillation means based on the output signals of the second oscillation means and the second oscillation means. The clock means is provided with a sampling means that samples the output signal of the first oscillation means by the jitter in the output signal of the clock generation means and outputs random data composed of a logic signal. The third invention includes a random number generation circuit of the first or second invention, and a scramble circuit that scrambles the output data of the sampling means and outputs the scrambled random number data.

【0005】

According to the first invention, since the random number generation circuit is configured as described above, when the power is turned on, the oscillating means oscillates at a constant frequency and the oscillating output signal is sent to the clock generating means and the sampling means. In the clock generation means, the output signal of the oscillating means is input, for example, a clock signal containing jitter is generated, and this jitter is amplified to generate a clock signal having a jitter width larger than half a cycle of the output signal. , Send to sampling means. In the sampling means, the output signal of the oscillating means is sampled by the jitter in the output signal of the clock generating means, and random data is output. According to the second invention, when the power is turned on, the first oscillating means and the second oscillating means oscillate asynchronously, and the output signal of the first oscillating means is sent to the sampling means, and the second oscillating means is sent. The output signal of the oscillating means is sent to the clock generating means. The clock generating means inputs the output signal of the second oscillating means, generates a clock signal having a jitter width larger than a half cycle of the output signal of the first oscillating means, and sends it to the sampling means. In the sampling means, the output signal of the first oscillation means is sampled by the jitter in the output signal of the clock generation means, and random data is output. According to the third invention, the output data output from the sampling means of the first or second invention is sent to the scramble circuit by turning on the power, the output data is scrambled by the scramble circuit, and the random number data is generated. It is output.

【0006】

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment FIG. 1 is a block diagram of a random number generation circuit showing the first embodiment of the present invention. This random number generation circuit includes an oscillating means (for example, OSC) 10 and a clock generating means (for example, a plurality of (n) stages of divided circuits) 20-1 to 20-n connected to the output side of the OSC10. , The OSC10 and a sampling means (for example, a D-type flip-flop circuit, hereinafter referred to as "D-FF") 30 connected to the output side of the final stage 2-dividing circuit 20-n. .. OSC10 is a circuit that oscillates at a constant frequency when the power is turned on and outputs the output signal S10, and is composed of a crystal oscillator circuit and the like. The n-stage dichotomy circuits 20-1 to 20-n constituting the clock generation means input the output signal S10 and generate a clock signal S20 having a jitter width larger than a half cycle of the output signal S10. It is a circuit given to D-FF30, and the two-division circuits 20-1 to 20-n of each stage are composed of the same circuit.

【0007】

For example, the first-stage 2-division circuit 20-1 uses a CR integrator circuit consisting of a resistor 21 and a capacitor 22 that integrates the output signal S10 in a triangular wave shape, and an integrator signal S22 output from the CR integrator circuit for waveform shaping. It is composed of a 2-division counter (for example, D-FF) 23 that divides the frequency by 2. The D-FF23 has a data input terminal D, a clock input terminal T, a data output terminal Q for outputting an output signal S23, and an inverting data output terminal Q /, and the clock input terminal T is connected to a resistor 21 and a capacitor 22. It is connected to a point, and the data input terminal D is connected to the inverting data output terminal Q /. The data output terminal Q of D-FF23 is connected to the resistor in the 2-stage frequency divider circuit 20-2 in the next stage. Similarly, other 2-divided circuits 20-3 to 20-n are connected in series, and the data output terminal of D-FF in this final stage 2-divided circuit 20-n is connected to D-FF30. .. The D-FF30 has a data input terminal D, a clock input terminal T, and a data output terminal Q, the data input terminal D is connected to the output side of the OSC10, and the clock input terminal T is divided into two in the final stage. It is a circuit that is connected to the data output terminal of D-FF in the circuit 20-n and outputs the output data (that is, random data) DA of "1" and "0" from the data output terminal Q.

【0008】

4 and 5 are operation waveform diagrams of the random number generation circuit shown in FIG. 1, and the operation of the random number generation circuit of FIG. 1 will be described with reference to these figures. When the power is turned on, the OSC10 starts oscillating, and the output signal S10 with a constant frequency is output from the OSC10 and sent to the D-FF30 and the first-stage 2-division circuit 20-1. In the first-stage dichotomy circuit 20-1, the input output signal S10 is integrated in a triangular wave shape by a CR integrator circuit including a resistor 21 and a capacitor 22, and the integrator signal S22 is output from the CR integrator circuit. In the CR integrator circuit, if the resistance value of the resistor 21 is increased and the capacitance value of the capacitor 22 is decreased, the impedance becomes large and it becomes easy to pick up ambient noise. Therefore, by integrating the output signal S10 with the resistor 21 and the capacitor 22 into a triangular wave-shaped integrated signal S22, a signal containing jitter due to ambient noise at the conversion point when viewed from the clock input terminal T of D-FF23. It becomes. D-FF23 divides the integrated signal S22 containing jitter by 2 for waveform shaping. As a result, the output signal S23 output from the data output terminal Q of the D-FF23 also becomes a signal containing jitter. This output signal S23 is sent to the 2-stage division circuit 20-2 in the next stage, and is output with further increased jitter in the same manner as the 2-division circuit 20-1 in the first stage, and is output in the 2-stage division circuit 20 in the next stage. Sent to -3. In this way, the jitter is amplified, and the clock signal S20 having a jitter width larger than the half cycle of the output signal S10 is output from the final stage 2-dividing circuit 20-n and sent to the clock input terminal T of the D-FF30. Be done.

【0009】

In D-FF30, the output signal S10 of OSC10 is sampled by the jitter of the clock signal S10. That is, the output signal S10 is sampled by any rising edge of the jitter at the rising point of the clock signal S20 shown in FIG. 5, and the output data DA is output from the data output terminal Q of the D-FF30. In this output data DA, for example, the data D corresponds to any rise of jitter in the clock signal S20.₁And D₂Since the boundary of is determined, the output data DA becomes random number data. That is, since there is jitter of the input clock signal S20 across the sections of "1" and "0" of the output signal S10 input to the data input terminal D of the D-FF30, the data output of the D-FF30. The output data DA output from the terminal Q becomes random data. The random number data output from the D-FF30 is read by a CPU or the like (not shown), the data to be transmitted is encrypted by the arithmetic processing of the CPU or the like, and the encrypted data is sent from the transmitter (not shown) to the outside. It is output.

【0010】

As described above, this first embodiment has the following advantages. (i) The n-stage bi-dividing circuit 20-1 to 20-n amplifies the noise that exists constantly as the jitter at the conversion point, and this amplified jitter causes the output signal S10 of the OSC10 on the D-FF30. Is sampled, and the randomized random number data of "0" or "1" is output from the data output terminal Q of the D-FF30. Therefore, even if random number data is read by a CPU or the like for encryption after a certain period of time after the power is turned on, new random number data can be obtained each time the power is turned on without causing regularity due to the reading timing. Therefore, the power supply can be turned off when the device is not in use, the battery life can be extended when the device is driven by the battery, and the power consumption can be reduced. (ii) Using a CR integrator circuit consisting of a resistor 21 and a capacitor 22, a triangular wave-shaped integrator signal S22 with jitter is generated, and the waveform is shaped by D-FF23 to generate a clock signal. A clock signal including the above can be easily and accurately generated.

【0011】

Second embodiment FIG. 6 is a configuration diagram of a random number generation circuit showing a second embodiment of the present invention, and common reference numerals are given to elements common to the elements in FIG. 1 showing the first embodiment. In this random number generation circuit, instead of one OSC10 in FIG. 1, two first oscillating means (for example, OSC) 10-1 and a second oscillating means (for example, OSC) 10-2 operating asynchronously are used. The output signal S10-1 output from the first OSC10-1 is given to the data input terminal D of the D-FF30, and the output signal S10-2 of the second OSC10-2 is given to the first stage 2-dividing circuit 20. It is configured to make the input data of D-FF30 and the input clock asynchronous, which are given to the resistor 21 in -1 and take out the random data which is the output data DA. The second OSC10-2 oscillates at a frequency that is a non-integer multiple of the first OSC10-1, and it is desirable to have a low-precision circuit configuration with low stability of this oscillation frequency and large jitter. .. The reason for using such OSC10-2 is that jitter is likely to occur due to the low stability of the oscillation frequency, and as a result, the reliability of the random number data extracted by the D-FF30 is improved.

【0012】

In the random number generation circuit of the second embodiment, when the power is turned on, the first and second OSC10-1 and 10-2 oscillate asynchronously, and the output signal S10 of the first OSC10-1 is oscillated. -1 is sent to the data input terminal D of D-FF30, and further, the output signal S10-2 of the second OSC10-2 is sent to the first stage dichotomy circuit 20-1. In the first-stage two-division circuit 20-1, the output signal S23 consisting of the clock signal is amplified by the OSC10-2's own jitter-containing output signal S10-2, and the second-stage two-division circuit 20-2 to 20 Send to -n sequentially. Therefore, the jitter contained in the output signal S10-2 gradually increases, and the clock signal S20 having a jitter width larger than the half cycle of the output signal S10-1 starts from the final stage 2-dividing circuit 20-n. It is output and sent to the clock input terminal T of D-FF30. The D-FF30 asynchronously samples the output signal S10-1 of the OSC10-1 based on the clock signal S20, and outputs the output data DA, that is, random number data.

【0013】

In addition to having the advantages of the first embodiment, this second embodiment also has the following advantages. (iii) In the first embodiment, since there is only one oscillation source called OSC10, the data input to the D-FF30 and the clock input are synchronized. Therefore, depending on the jitter distribution, a series of "0" and "1" may occur, and the reliability of the obtained random number data may be low. Therefore, in this second embodiment, the oscillation source is divided into OSC10-1 and 10-2, the data input to the D-FF30 and the clock input are made asynchronous, and the jitter included in the clock signal S20 is also included. The jitter is increased by using the low precision OSC10-2. Therefore, random number data can be obtained more reliably than in the first embodiment.

【0014】

Third embodiment FIG. 7 is a block diagram of a random number generation circuit showing a third embodiment of the present invention. In this random number generation circuit, in order to further ensure random number generation for the first or second embodiment, the random number generation circuit 40 of the first embodiment or the second embodiment is further scrambled on the output side. Circuit 50 is connected. This scramble circuit 50 has a function of further randomizing the output data DA output from the D-FF30 in the random number generation circuit 40 and outputting the random number data DAT. For example, the generated polynomial is 1 + X.^-6+ X^-7It is composed of the circuit of.

【0015】

In the scramble circuit 50, for example, the generated polynomial is 1 + X.^-6+ X^-7In the case of, it is composed of two exclusive OR gates (hereinafter referred to as "Ex-OR") 51, 53 and one shift register 52. Of the two input terminals of Ex-OR51, one input terminal is connected to the data output terminal Q of D-FF30 in the random number generation circuit 40, and the other input terminal is connected to the output terminal of the other Ex-OR53. It is connected. The output terminal of Ex-OR51 is a terminal for outputting random number data DAT, and is connected to the data input terminal D of the shift register 52. The clock signal S20 output from the random number generation circuit 40 is input to the clock input terminal T of the shift register 52, and the two data output terminals Q6 and Q7 of the shift register 52 are connected to the two input terminals of the Ex-OR 53. It is connected. In the random number generation circuit of the third embodiment, the output data DA and the clock signal S20 are output from the random number generation circuit 40 when the power is turned on, and the output data DA is sent to the scramble circuit 50. The Ex-OR51 in the scramble circuit 50 has an output signal of "1" when the two input signals do not match, and an output signal of "0" when the two input signals match, and these output signals are the shift register 52. It is sent to the data input terminal D. In the shift register 52, in response to the clock signal S20 input to the clock input terminal T, the output signal of the Ex-OR51 is sequentially taken in and shifted, and output from the two data output terminals Q6 and Q7. The output signals of these two data output terminals Q6 and Q7 are input to Ex-OR53, and the output signal of the Ex-OR53 is fed back to the input terminal of Ex-OR51. As a result, from the output terminal of Ex-OR51, the generation polynomial 1 + X^-6+ X^-7Randomized random number data DAT is output by the scramble circuit 50 represented by.

【0016】

In addition to having the advantages of the first and second embodiments, this third embodiment also has the following advantages. (iv) Even if two OSC10-1,10-2 are provided as in the second embodiment, the OSC10-1 and 10-2 have a frequency ratio that is an integral multiple of each other due to fluctuations in these oscillation frequencies. It is possible that it will become. Even in such a case, since the continuous generation of 0 or 1 is randomized by the added scramble circuit 50, the random number data DAT can be obtained more reliably than in the second embodiment. The present invention is not limited to the above embodiment, and various modifications are possible. Examples of this modification include the following.

【0017】

(a) Each of the 2-divided circuits 20-1 to 20-n in FIGS. 1 and 6 is composed of a CR integrator circuit consisting of a resistor 21 and a capacitor 22, and a 2-divided counter consisting of a D-FF23. However, this CR integrator circuit may be configured by another circuit, or the 2-divided circuit may be configured by another flip-flop circuit or the like. Further, since the clock generation means composed of n-stage 2-division circuits 20-1 to 20-n is a circuit that generates a clock signal containing jitter and amplifies this jitter, such a function is provided. It may be changed to another circuit configuration that can be executed. Further, the D-FF30 may be configured by a sampling means such as another flip-flop circuit. (b) In the scramble circuit 50 in Fig. 7, the generated polynomial is 1 + X.^-6+ X^-7However, the accuracy of scrambling can be further improved by increasing the number of these stages to make the circuit configuration of another generated polynomial. Further, these scramble circuits 50 may be configured by circuits other than those shown in the drawings. (c) In the above embodiment, the random number generation circuits for encrypting the transmission data have been described, but these random number generation circuits can be used for various purposes other than encryption.

【0018】

[Effect of the invention]

As described in detail above, according to the first, fourth and fifth inventions, the clock generation means amplifies the constantly existing noise as jitter, and the clock signal having the amplified jitter is the sampling means. Since the output signal of the oscillating means is sampled by the sampling means and the random data is taken out, for example, even if the random data is read for encryption or the like after a certain period of time after the power is turned on, this New random data can be obtained each time the power is turned on, without causing regularity due to read timing. Therefore, the power supply can be turned off when the device is not in use, and for example, the battery life can be extended when the device is driven by a battery, and power consumption can be reduced. According to the second, fourth, and fifth inventions, two first and second oscillating means having different accuracy are provided, and the data input to the sampling means and the clock input are asynchronously configured. Random data can be obtained more reliably than in the invention of. According to the third invention, since the scramble circuit is provided on the output side of the random number generation circuit of the first or second invention, the random number data obtained in the first or second invention can be further randomized. , Random number data can be obtained more reliably than in the second invention.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram of the random number generation circuit which shows the 1st Embodiment of this invention.

[Figure 2]

It is a block diagram of the conventional random number generation circuit.

[Fig. 3]

It is a figure which shows the encryption process of FIG.

[Fig. 4]

It is the operation waveform diagram of FIG.

[Fig. 5]

It is the operation waveform diagram of FIG.

[Fig. 6]

It is a block diagram of the random number generation circuit which shows the 2nd Embodiment of this invention.

[Fig. 7]

It is a random number generation circuit which shows the 3rd Embodiment of this invention.

[Explanation of symbols]

10,10-1,10-2 OSC (oscillation circuit) 20-1 ~ 20-n 2 division circuit 21 resistance 22 Capacitor 23,30 D-FF 40 Random number generation circuit 50 scramble circuit