Method and apparatus for providing of precise and perfect communication between different bus architectures in information processing system

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention generally relates to an information processing system, specifically, data communication between a component connected to two different bus architectures in the information processing system and a peripheral device is one of the bus architectures. With respect to methods and devices to be complete and accurate when going from a device or component adapted to a different bus architecture to a device or component adapted to a different bus architecture.

【0002】

[Conventional technology]

An information processing system usually has a central processing unit (CPU) as a main component. The central processing unit directs all communications in the system and harmonizes all commands executed by the information processing system. Information processing systems also usually have a network of physical connectivity devices called buses. This network connects the CPU to any number of peripherals and components so that the CPU can communicate with the peripherals and components.

【0003】

One type of bus used in information processing systems is the CPU local bus. The CPU local bus, also known as the system bus, is specially designed to connect the CPU directly to key components of an information processing system, such as system memory and memory controllers. The CPU local bus is a high-performance bus. This means that the bus can perform data transfers between the CPU connected to the bus and other components at high speed and can process multiple data transfers at the same time. Another type of bus used in information processing systems is the peripheral bus. Peripheral buses are designed to connect peripheral devices such as input / output devices (I / O) and graphics packages to information processing systems. Peripheral buses are typically connected to the CPU of the information system and the remaining key components via a host bridge that connects the bus to the CPU local bus.

【0004】

Each type of bus has a different set of standard protocols or rules that it uses to transfer data between different devices and components connected to it. These protocols are built into the bus and are called the "architecture" of the bus. The various protocols that can configure a bus architecture type include the bit length of the data string recognized by the bus, whether different signals are enabled when low or high, or on the bus. Whether the data is multiplexed on one line or transmitted in parallel on multiple lines, or whether a type of data is not accepted and causes the information processing system to malfunction or "crash".

【0005】

The bus architecture of the CPU local bus and the peripheral bus is usually different. Different architectures cause communication problems when data must be transferred between peripherals connected to the peripheral bus and the CPU or other components of the system connected to the CPU local bus. To do. Because such data transfers involve different bus architectures, the data transferred from the first bus architecture may not be available or recognizable by the second bus architecture.

【0006】

Therefore, there is a need for equipment and methods that "convert" data transferred from one bus architecture to another. The hardware and logic used to transform the data transferred between two different bus architectures is typically contained in a bridge to connect the two different buses. Therefore, the host bridge connecting the CPU local bus and the peripheral bus is a logical mechanism and hardware that translates the communication between the two buses so that the data is recognizablely transferred between the two buses. Must include clothing.

【0007】

One difference between the CPU local bus and peripheral bus bus architectures is the response of each bus to the presence of discontinuous data transferred on those buses. Non-contiguous data consists of enabled data bytes separated by non-enabled data bytes. Disabled data that is not enabled, that is, unrecognized, should be ignored and should not be transferred during a particular data transfer. Certain types of peripheral buses and devices connected to these peripheral buses can transmit discontinuous data without causing malfunction. On the other hand, sending discontinuous data on the CPU local bus can cause the information processing system to crash or cause a serious malfunction.

【0008】

Another difference between the peripheral bus architecture and the CPU local bus architecture is that the CPU local bus can recognizablely send data of different bit lengths, but the peripheral bus is limited to one standard bit length for data transfer. That is. Therefore, the CPU local bus is compatible with components designed to send and receive data of various bit lengths. For example, a component that sends and receives only 8-bit length data strings will be able to send and receive data when connected to the CPU local bus. Similarly, 16-bit or 32-bit components can also use the CPU local bus for data transmission. The ability of the CPU local bus to adapt to data transfers of various bit lengths is called dynamic bus sizing.

【0009】

[Problems to be Solved by the Invention]

On the other hand, the peripheral bus is limited to transmitting a data string having a standard bit length such as 32 bits. Therefore, components connected to the CPU local bus that transfer and accept only data with a bit length that is different from the standard bit length of the data transmitted on a particular peripheral bus will have no data conversion intervention of any kind. Cannot communicate with peripheral devices connected to the peripheral bus.

【0010】

Therefore, an object of the present invention is to determine whether the data to be transmitted on the CPU local bus is discontinuous data, and if so, to continue the discontinuous data so that the CPU local bus does not malfunction. It is to provide a method and an apparatus for replacing with data.

【0011】

Another object of the present invention, a device connected to the peripheral bus, the standard data in the said peripheral bus architecture which is connected to the CPU local bus designed data bit length and different data bit length for construction It is to provide methods and devices for transforming data transfers between elements.

【0012】

Another object of the present invention is to provide these methods and devices in hardware with a host bridge connecting the CPU local bus to the peripheral bus.

【0013】

[Means for solving problems]

According to the present invention, it is determined whether the data to be transmitted on the CPU local bus is discontinuous data, and if so, the discontinuous data is converted into continuous data so that the CPU local bus does not malfunction. Provides a hardware logic mechanism in the host bridge that connects the CPU local bus to the peripheral bus to replace. The hardware of the present invention also translates data transfers between peripheral buses, which are architecturally limited to standard length data strings, and CPU local buses, which allow dynamic bus sizing.

【0014】

The memory controller 28 responds to a memory cycle while it is directed to it. However, if the memory cycle is not directed to the memory controller 28, the information is sent over the S (system) bus 16. The PCI bus 22 has a new bus architecture called PCI. The main PCI bus 22 is a high-performance bus. That is, the main PCI bus 22 transfers a large amount of data in a relatively short time, that is, transfers a maximum of 120 megabytes of data per second. One of the reasons the PCI bus achieves such a high level of performance is that it can be linked directly to other high speed buses, such as the S bus 14, and therefore with the CPU 24 or other S bus equipment 14. This is because high-speed data transfer can be provided between the main PCI devices 18. In fact, to operate some highly integrated devices, such as some graphics packages, you need to link directly to a system bus, such as the S bus, via a high performance bus, such as the PCI bus 22.

【0015】

Also, the PCI bus architecture does not require "glue logic" to operate the connected peripherals. Glue logic for other buses usually consists of various hardware components such as decoders, buffers, and latches located between the peripheral and the bus.

【0016】

The main PCI bus 22 operates based on a 33 MHz synchronous clock signal, and the character string of the data transmitted via the PCI bus is 32 bits in length. A 32-bit data string on the PCI bus is called a double word (DWORD). Each doubleword is divided into 4 bytes, each consisting of 8 bits of data.

【0017】

The address information and data information carried by the PCI bus are multiplexed into one signal. Multiplexing eliminates the need to separate address and data lines, thus requiring fewer signals in a PCI environment than other bus architectures. The number of signals required in a PCI bus architecture is 45 to 47, but a standard non-multiplexed bus usually requires twice this. Therefore, as the number of signals is reduced, the number of pins required to support the device linked to the PCI bus is also reduced by a corresponding amount. Therefore, the PCI architecture is particularly well suited for highly integrated desktop computer systems.

【0018】

A detailed description of the structure and operation of the PCI bus architecture can be found, for example, in the "Peripheral Component Interconnect (PCI) Revision 1.0 Specification" published June 22, 1922 and the "Preliminary PCI System Design Guide" published November 1, 1992. It is described in "revision 0.6" and "Peripheral Component Interconnect (PCI) Add-in Board / Connector Addendum" (draft) issued on November 6, 1992. All of these documents are published by the PCI Special Interest Group.

【0019】

The main PCI devices 18 in the system 10 communicate with each other via the main PCI bus 22. The main PCI device communicates with the CPU, cache and memory complex 12, and other S-bus devices 14 resident on the S-bus 16 by means of the PCI host bridge 20, which is an S-bus device that resides on the S-bus itself. To do. The PCI host bridge 20 then acts as an interface between the S (system) bus 16 and the main PCI bus 22, providing an effective means of communication between these two buses and the peripherals resident on those buses. provide.

【0020】

The PCI host bridge 20 is a low latency interconnect mechanism that allows the CPU (processor) 24 or other S-bus device 14 to directly access the main PCI device 18 or devices connected to it. The PCI host bridge 20 also provides a high performance path that allows the main PCI device or its connected devices to quickly and directly access the base system memory 32. In addition, the PCI host bridge 20 provides all the hardware needed to provide an interface between the S bus 16 and the main PCI bus 22 so that data can be transferred between them.

【0021】

The main PCI bus 22 can support a variety of PCI compatible devices. As shown in Figure 3, these devices include a graphics controller 72, a serial SCSI (small computer system interface) controller 74, a PCMCIA controller 76, and a standard bus (eg, ISA or MICRO CHANNEL ("MC-A"). ")) Bridge 78, and PCI secondary bridge 80 are included. However, the device connected to the main PCI bus shown in FIG. 3 is merely an example of a system that implements the PCI bus architecture and thus the configuration disclosed herein, and does not limit the present invention in any way.

【0022】

The graphics controller 72 typically has a memory feature in the form of a VRAM 82 that allows the controller 72 to buffer video frames and controls any known graphics package supported by the PCI bus architecture. be able to. The SCSI 74 acts as an interface between the SCSI device 84 connected to the SCSI bus 86 and the main PCI bus 22, and can control any SCSI device supported by the PCI bus architecture. The PCMCIA controller 76 is connected to the card slot 88 and controls the slot 88.

【0023】

The standard bus bridge 78 acts as an interface between the I / O device 90 connected to the standard (eg MC-A or ISA) bus 92 and the main PCI bus 22. The architecture of the MC-A version of Standard Bus Bridge 78 is the subject of the following related applications assigned to IBM:

【0024】

The secondary PCI device 94 is connected to the PCI secondary bridge 80 via the secondary PCI bus 96. Any number of unidentified secondary PCI devices 94 can be connected to the secondary PCI bus 96. The PCI secondary bridge 80 acts as an interface between any number of PCI devices 94 connected to the secondary PCI bus 96 and the main PCI bus 22.

【0025】

Any number of peripherals compatible with the PCI bus architecture can be placed on the main PCI bus 22 without the presence of other PCI buses throughout the computer system 10. That is, in addition to the PCI bus 96, any number of PCI peripherals can be connected to the main PCI bus 22 via the same number of separate PCI secondary bridges 80. Can be connected to. Any number of additional PCI buses can be connected to each secondary PCI bus via a PCI secondary bridge, and yet another PCI bus can be connected to these "tertiary" PCI buses in various combinations. can do. Similarly, any number of PCI devices can be connected to each PCI bus. Each connection between the two PCI buses must be made through the same PCI secondary bridge as bridge 80.

【0026】

In addition, the same multiple bridges as the PCI host bridge 20 can be driven by the S bus 16. Any number of PCI buses, bridges and devices can then be connected to each of these host bridges in the sequence desired by the system 10 designer. Therefore, the part of the system 10 consisting of the PCI bus architecture can be composed of a plurality of buses arranged in various equal combinations and hierarchical combinations and PCI peripheral devices (hereinafter generally referred to as PCI networks). ..

【0027】

Also, in the alternative configuration of the information processing system 10, there is no S bus 16, so the host bridge 20 connects the main PCI bus 22 directly to the CPI local bus 34. In this configuration, any S-bus device 14 can be directly connected to the CPU local bus 34. Since the S bus 16 and the CPU local bus 34 operate using the same architecture, the present invention performs the same functions as the preferred embodiments shown in FIGS. 1, 2, and 3 as described below. ..

【0028】

Referring to FIG. 4, timing diagrams of various PCI bus signals during two consecutive write cycles to peripheral devices connected to the main PCI bus 22 are shown. The peripheral may be a graphics controller 72, a standard bus bridge 78, or another peripheral that can be driven from the PCI bus. Similarly, the write cycle shown in FIG. 4 is a typical PCI bus write cycle and is not unique to the main PCI bus 22. These write cycles may be write cycles on the secondary PCI bus 96 or write cycles on other PCI buses in the PCI network.

【0029】

The clock signal (CLOCK) provides the timing for all communications over the PCI network. CLOCK is an input to any PCI device and all PCI secondary bridges. CLOCK is synchronous. That is, all communication signals in the PCI architecture have a duration of at least one clock, and any command or data transfer is executed over a period of at least one clock. The signals in FIG. 4 are divided into individual "clocks" by vertical dashed lines. Each dashed line represents the beginning of one clock duration and the end of the clock duration immediately before it. The signal on each line is sampled on the rising edge of the clock signal or has a valid meaning for that clock on the rising edge of the clock signal.

【0030】

The frame signal (FRAME) is used by a PCI secondary bridge or peripheral connected to a PCI bus, and that bridge or peripheral provides a communication cycle or access to other PCI secondary bridges or peripherals connected to that bus. Indicates to start. The peripheral device or PCI secondary bridge that initiates access is called the master. The device or component to be accessed is called a slave. In the PCI bus architecture, a large number of signals are enabled or activated when driven from high voltage to low voltage, i.e. "low". FRAME is one of those signals. Therefore, when the master drives the FRAME low, as shown in the second clock, the master indicates to the slave that it is initiating access.

【0031】

The Initiator Ready Signal (IRDY) is also activated when low, indicating that the master is ready to start data transfer. Therefore, the master drives the IRDY low when it is ready to accept data during the read cycle or transfer data to the slave during the write cycle.

【0032】

The target ready signal (TRDY) is activated low to indicate that the slave is ready to start data transfer. Therefore, the slave drives TRDY low when it is ready to accept data from the master during the read cycle or transfer data to the master during the write cycle.

【0033】

The address / data signal (AD) transmits the address of the register of the target of data transfer and the data to be transferred by multiplexing them on one line. The address information is driven on the AD by the master as it asserts FRAME during the address phase. During the data phase after the address phase, the master or slave provides the data depending on whether the access is a write cycle or a read cycle, and the data is then driven on the AD line after the address phase. The address phase has a duration of 1 clock and the data phase is at least 1 clock, but more than 1 clock if the data transfer is a burst transfer or the slave TRDY assertion is delayed. There is.

【0034】

The command / byte enable signal (C / BE) provides a multiplexed PCI bus command and byte enable signal on a single line. Bus commands are asserted on AD by the master when the master asserts FRAME and during the address phase. The bus command can be a read command or a write command, depending on which type of access the master is initiating.

【0035】

The byte enable signal exists on the C / BE when transferring data over AD. The byte enable signal is contained in four bits having identification numbers 0 to 3. When all four bits are activated low (binary value 0), all four or 32 bits of data being transferred on AD are enabled and those bytes are written during transfer. Indicates that When one of the four bits is high (binary value 1), one byte of the 4-byte data being transferred on the PCI bus is disabled.

【0036】

The functions of various PCI bus signals during the simple write operation shown in Fig. 4 are as follows.

【0037】

During the second clock, the master drives FRAME low. This means that the master initiates access to the slave. IRDY and TRDY are in a turnaround cycle during the second clock.

【0038】

At this point, the master provides the address of the register in the slave that is the target of access on the AD line. At the same time, the master generates a write command on the C / BE line.

【0039】

When moving to the third clock, FRAME is deasserted. This means that you are ready to complete access. The master is now in control of the IRDY line, driving the line low to indicate that it is ready to transfer data to the slave. The slave is also under control of the TRDY line, activating the line low to indicate that the address information has already been decoded as the address of a register in the slave itself and that the register is ready to accept data. Therefore, at the third clock, the data is transferred from the master to the slave's decoded registers on the AD line.

【0040】

After the address phase, when the data phase begins, the master asserts a byte enable signal on the C / BE line indicating whether the data has been enabled. If one or more of the four bits is high, the corresponding data byte on the AD line is not enabled.

【0041】

During the fourth clock, another write clock is started, so the timing diagram is repeated. This second write cycle can be started on the same master or on different masters. Similarly, the write cycle target may be the same slave or a completely different slave.

【0042】

To eliminate the risk of contention between the various devices connected to the PCI bus, each line goes through a turnaround cycle before the second write cycle begins. A detailed description of the turnaround cycle and competition is provided in the context of "METHOD AND APPARATUS FOR PROVIDINGBACK-TO-BACK DATA TRANSFERS IN AN INFORMATION HANDLING SYSTEM HAVING A MULTIPLEXED BUS", which was filed at the same time as the present invention and assigned to IBM. Please refer to the application.

【0043】

Here, with particular reference to FIG. 5, a timing diagram at the beginning of one read cycle and another is shown. At the second clock, the master asserts FRAME low. FRAME remains low for one clock signal at the second clock. Because this is a single data phase transfer. The master also supplies the address information on the AD, and the read command is sent on the C / BE line at the second clock.

【0044】

In the third clock sequence, the AD line must enter the turnaround cycle. This is because the slave needs to gain control of the AD line during the fourth clock signal in order to provide the data that the master requested to read. This turnaround cycle is needed to eliminate conflict between master and slave for AD lines. The master asserts IRDY low on the third clock to indicate that it is ready to read the requested data. At the third clock signal, the master also asserts the byte enable signal on the C / BE line.

【0045】

At the fourth clock signal, the slave provides data on the AD line and asserts TRDY. The byte enable signal is still asserted on the C / BE line by the PCI master. Since the IRDY signal is still low at the 4th clock, the data to be read is transferred from the slave to the master.

【0046】

When a master connected to PCI needs to perform a data transfer to a CPU local bus or a component or device connected to the system bus, such as a DMA controller or system memory, a two-step procedure Must be used. In the first step, the host bridge that connects the PCI bus to the CPU bus or system bus becomes a slave for data transfer on the PCI bus. In the second step, the host bridge becomes the master of read or write cycles on the CPU local bus or system bus, and the device or component targeted for data transfer is the CPU local bus or system. Become a slave to this particular data transaction on the bus.

【0047】

For example, if the graphics controller 72 targets the DMA controller 40 for a write cycle, the PCI host bridge 20 becomes a slave for the write cycle on the main PCI bus 22. The data to be written during the write cycle is then transferred to the host bridge 20. The host bridge 20 then becomes the master of the write cycle on the S bus 16 with the DMA controller 40 as the slave or target of the write cycle. Data is then transferred again from the host bridge 20 to the DMA controller 40 during the write cycle on the S bus 16. In the read cycle, the host bridge 20 becomes a slave of the read cycle on PCI bus 22 and then becomes the master of the read cycle on S bus 16 to complete the data transfer from S bus 16 to PCI bus 22. , Operates in the same 2-step procedure.

【0048】

Further, the master on the S bus 16 must first use the host bridge 20 as a slave when initiating data transfer to the device on the PCI bus 22. The host bridge 20 then becomes the master of data transfer over the PCI bus 22.

【0049】

Data transfer between devices connected to the PCI bus below the PCI secondary bridge 80 in the PCI network and components connected to the CPU local bus 34 or S bus 16 will eventually host the data. It must be completed by performing continuous data transfers to and from the PCI secondary bridges that interconnect the network until 20 transfers are made to. If the PCI secondary bridge 80 has data to transfer and the particular transfer is a write cycle, use the two-step procedure described above to use the PCI secondary bridge 80 as a master on the PCI bus 22 and host it. -Complete data transfer using the bridge 20 as a slave on the PCI bus 22 and a master on the S bus 16.

【0050】

Data transfer between S bus 16 and PCI bus 22 must be completed in two steps because those buses have different bus architectures. The bus architecture of CPU local bus 34 and S bus 16 is the same. In the CPU local bus 34 and S bus 16 bus architectures, unlike the PCI bus architecture, data and address information is not multiplexed and is transmitted on separate lines. The data and address information strings on these lines are 32 bits in length.

【0051】

The CPU local bus architecture has a byte enable line that performs the same function as the byte enable signal of the PCI bus architecture. Therefore, the CPU local bus architecture byte enable signal is 4 bits in length and indicates whether a particular byte of data on the data line is enabled or not enabled.

【0052】

The CPU local bus 34 and the S bus 16 use the CLOCK signal from the PCI bus 22 as a timing signal. The duration of each timing signal on the CPU local bus 34 and S bus 16 is called the bus cycle.

【0053】

Unlike the PCI bus architecture, the data and address information for CPU local bus 34 and S bus 16 is transmitted on separate lines. Therefore, when the slave that is the target of the data transfer responds to the address sent on the address line, the data transfer can be completed in one bus cycle on the CPU local bus. During a burst transfer of several 32-bit data strings, if the slave acknowledges the first transfer, each subsequent data transfer can be completed in a single bus cycle. The master generates a byte enable signal on the CPU local bus during data transfer.

【0054】

Referring to FIG. 4, if the final target of the write cycle shown in the second to fourth clocks is a component connected to the S bus 16, the host bridge 20 is the slave to which the PCI write cycle is directed. Become. Therefore, the host bridge 20 receives the data transmitted in the third clock in its one internal register in response to the address transmitted in the second clock. This address will also be stored in that one internal register.

【0055】

When the host bridge 20 then gains control of the S bus 16, it acts as a master and creates a write cycle on the S bus 16. During the first bus cycle, the host bridge 20 forwards the same address information and byte enable signal received during the PCI write cycle on each line on the S bus 16. The appropriate slave responds to the address information and data is transferred over the address line during the next bus cycle following this response.

【0056】

The data on the PCI bus during the read or write cycle is non-contiguous data. Non-contiguous data is data in which two or more enabled bytes of data in a 32-bit data string are separated by bytes of non-enabled data. The four bits of the byte enable signal indicate whether the data is disabled and therefore discontinuous. Table 1 shows each possible binary combination of the four byte enable bits and whether each combination represents discontinuous data.

[table 1]

<img file="JPH06348646A_D0001.tif" />【0057】

Whenever the CPU local bus 34 and S bus 16 architectures transfer discontinuous data within a single data transfer, the information processing system malfunctions. Therefore, the host bridge 20 determines if the data is discontinuous and, if so, transmits the data from the PCI bus 22 over the S bus 16 unless the discontinuous data is converted to continuous data. I can't. Hardware that implements the present invention performs this task.

【0058】

The method for converting discontinuous data to continuous data in the present invention described below is to convert a single discontinuous data transfer on the PCI bus 22 to two or more continuous data transfers on the S bus 16. This is due to the separation. For example, if the discontinuous data from the master connected to the main PCI bus 22 has a byte enable value of 0110 and the master is writing this data to the slave connected to the S bus 16, the host bridge 20 The hardware of the invention contained within produces two write cycles on the S bus 16 containing byte enable values 1110 and 0111, respectively. The addresses and data of these two write cycles will be the same. This transfers the enabled first and fourth bytes of the data and prevents the disabled second and third bytes of the data from being transferred.

【0059】

The present invention simultaneously communicates between an 8-bit or 16-bit device connected to the CPU local bus or system bus and a device connected to a PCI bus that transfers only 32-bit length string data. Address and resolve the issue. The present invention also solves this problem by decomposing the 32-bit transfer on the PCI bus into multiple data transfers on the CPU local bus or system.

【0060】

For example, if the write cycle from the master connected to the main PCI bus 22 is directed to a slave connected to the S bus 16 that accepts only 8-bit string data, assume that all data is enabled. Therefore, the 32-bit data string from the master must be divided into four write cycles on the S bus 16. The byte enable signal for each of the four transfers changes as bytes of data are transferred to the slave. The byte enable signal for the first write on S bus 16 is 0000, which indicates that all four bytes of data are enabled. However, since the slave is an 8-bit device, only the least significant byte of data is received by the slave. Therefore, since the least significant byte of data has already been transferred to the slave, according to the present invention, a second write cycle with byte enable signal 0001 is generated in the host bridge 20. As each byte of data is transferred in a continuous write cycle, the byte enable value for the third write cycle changes to 0011 and the byte enable signal for the fourth write cycle changes to 0111.

【0061】

Table 2 below shows whether additional bus transfers on the CPU local bus or system bus are required after a single data transfer, depending on the bit size of the slave and the byte enable signal for a particular data transfer. Show me how. The table also shows the byte enable values for the following data transfers:

[Table 2]

<img file="JPH06348646A_D0002.tif" />In the present invention described below, this table is implemented in host bridge hardware, such as host bridge 20.

【0062】

With reference to FIG. 6, a diagram of the byte enable control hardware 100 of the present invention in the host bridge 20 is shown. Hardware 100 includes a first latch register 102 and a second latch register 104 connected to the C / BE line of the PCI bus 22. The latch register 104 is connected to a 5-input multiplexer 106. The latch register 104 has an output line 108 for connecting it to a two-input multiplexer 110.

【0063】

Latch registers 102 and 104 each hold 4-bit data and have the ability to latch and hold the 4-bit value of a single clock signal. The latch register 102 receives a 4-bit byte enable signal for a specific data transfer from the C / BE line of the PCI bus 22, and latches the signal on the S bus 16 until the specific data transfer is completed. I will do it.

【0064】

The latch register 104 receives a 4-bit output signal from the multiplexer 106 and holds this value until the multiplexer 106 produces another output signal. Latch register 104 outputs the current 4-bit value to the second input of the multiplexer 110 on line 108. The output from the latch register 104 is called the latched byte valid (L_BV).

【0065】

The multiplexer 106 has five inputs numbered 1 to 5 that its internal selection logic mechanism chooses to drive on its output depending on the status of the data phase on both PCI bus 22 and S bus 16. Has. Each of these inputs is a 4-bit value. The multiplexer 106 receives the status of data transfer on these buses via the hardware of the host bridge 20. The status of the data phase on PCI bus 22 and S bus 16 that causes the multiplexer 106 to select its five inputs respectively is as follows.

【0066】

First Input-The host bridge 20 first responds to a read data transfer on the PCI bus 22, and the data transfer on the S bus 16 is complete and ready to start another data transfer. Selected when you are. The first input is always the binary value "1111".

【0067】

Second Input-When write data transfer begins on PCI bus 22, the first bus cycle on S bus 16 begins, which is required to complete the corresponding write data transfer on S bus 16. Selected before. The second input is the 4-bit byte enable value from the C / BE line of PCI bus 22.

【0068】

Third Input-The data transfer to be completed on the S bus 16 is a write operation initiated from the PCI bus 22 and is selected when the transfer bus cycle on the S bus 16 has just completed. ..

【0069】

Fourth Input-The data transfer to be completed on the S bus 16 is the read operation and is selected when the bus cycle of the transfer on the S bus 16 has just completed.

【0070】

Fifth Input-Any bus cycle on S Bus 16 is selected and maintained until that bus cycle is complete. This input is fed back from the output of latch register 104.

【0071】

The multiplexer 110 has two inputs that it chooses to drive on its output, depending on whether the data transfer initiated by the PCI bus 22 is a read or write operation. Each of these inputs is 4 bits in length. The first input is selected during PCI read data transfer and the second input is selected during PCI write data transfer. The multiplexer 110 monitors the status of data transfer on both the PCI bus 22 and the S bus 16 via the hardware of the host bridge 20.

【0072】

The output of the multiplexer 110 is connected to a discontinuous data detector 114 that detects if the byte enable of the data to be transferred during the next bus cycle on the S bus 16 is discontinuous data. The detector 114 is a combination of functional blocks of the hardware logic mechanism that provides the functions in Table 1 above. Therefore, the detector 114 determines if the data to be transferred during the next bus cycle is discontinuous data and generates a binary "1" on output line 116 if the data is actually discontinuous data. To do. The output of the detector 114 is called NC.

【0073】

The four bits of the output of the multiplexer 110 are also split into three separate signals on lines 118, 120, and 122, respectively. The two lower bits, the bits with the identification numbers 0 and 1, are output on the line 118 connected to the line 124, which is further connected to the S bus 16. The output bit of the multiplexer 110 with identification number 2 is output on line 120 and becomes the input to the first 2-input OR gate 126. The output bit of the multiplexer 110 with identification number 3 is output on line 122 and becomes the input to the second 2-input OR gate 128.

【0074】

The NC output of detector 114 is also input to OR gates 126 and 128. The outputs of OR gates 126 and 128 are connected to line 124.

【0075】

Line 124 transmits a 4-bit signal PBE to S bus 16 that combines the outputs of two OR gates 126 and 128. These bits are included in the output of the multiplexer 110 and are numbered 0 and 1. This 4-bit signal is a byte enable signal for the current bus cycle on the S bus 16 and is always continuous data.

【0076】

The NC output from the detector 114 is also input to the third 2-input OR gate 130. The other input to the OR gate 130 is connected to the byte enable generator 132 via line 134. The output from the generator 132 onto the line 134 is called BSZ. The OR gate 130 has an output called BC connected to other hardware in the host bridge 20.

【0077】

The generator 132 is a functional block of known logic hardware that provides the functionality to generate Table 2 above. Therefore, the generator 132 determines if another bus cycle is required on the S bus 16 to complete the particular data transfer initiated by the PCI bus 22, and issues a byte enable signal for that transfer. provide. The output from the generator 132 depends on whether the slave to which the data transfer is output is an 8-bit device or a 16-bit device.

【0078】

The generator 132 is connected to the S bus 16 via two input lines called BS8 and BS16. The BSZ signal, BS8 signal, and BS16 signal are single-bit binary signals having a value of 0 or 1. When the slave connected to the S bus 16 to which the data transfer is directed responds to the completion of the data transfer, it sends a binary signal on BS8 or BS16, depending on whether it is an 8-bit device or a 16-bit device, respectively. To do. If it is neither an 8-bit device nor a 16-bit device, the values for BS8 and BS16 are 1. If BS8 or BS16 has a value of 0, the slaves are 8-bit or 16-bit devices, respectively, and the generator 132 produces binary 1 as the value of BSZ on line 134.

【0079】

If the NC or BSZ signal has a value of 1, the OR gate 130 produces a high value as a BC signal. The high BC signal indicates to other hardware in the host bridge 20 that at least one more bus cycle is required to complete the current data transfer.

【0080】

The generator 132 has another input from line 124, which is a byte enable signal for the current bus cycle on the S bus 16. The generator 132 generates a byte enable value for the next bus cycle based on the current byte enable value.

【0081】

The generator 132 has a second output, called the NBE, that is output on line 136. NBE is a 4-bit value. The NBE is given the value of the byte enable signal for the next bus cycle, or because the slave is an 8-bit or 16-bit device, no more S to complete the data transfer initiated by PCI bus 22. It has the value "1111" if no bus cycle on bus 16 is required.

【0082】

The NBE signal is one input to a two-input exclusive OR gate (XOR) 138 and a two-input inverting exclusive OR gate (NXOR) 140. The other input to the XOR gate 138 and NXOR gate 140 is a byte for the current bus cycle on the S bus 16 from line 124, connected to XOR gate 138 and NXOR gate 140 via line 142. The value of the enable signal.

【0083】

The output of the XOR gate 138 is connected to one input of the fourth two-input OR gate 144. The output of the NXOR gate 140 is connected to one input of the 2-input AND gate 146. The other input to the OR gate 144 and the AND gate 146 is the output of the latch register 104, which is fed back through line 148. The output of the OR gate 144 is connected to the third input of the multiplexer 106. The output of AND gate 146 is connected to the fourth input of the multiplexer 106.

【0084】

The output from the latch register 104 is also connected via wire 148 to the second 2-input NXOR gate 150, 4-input AND gate 152, and comparison mechanism 154. The four inputs of AND gate 152 are the four bits of the L_BV signal from latch register 104. The output of AND gate 152 is output to other hardware in host bridge 20 and indicates when the write cycle initiated by PCI bus 22 completed on S bus 16. This output is called W_DONE and becomes unary 1 when activated.

【0085】

The other input to the NXOR gate 150 is the output of latch register 102. Again, this output is the value of the byte enable signal from the data transfer initiated on the PCI bus 22. This value remains constant until the data transfer is complete on the S bus 16. The output of the NXOR gate is connected to the first input of the multiplexer 110.

【0086】

The output from the latch register 102 is also connected to the comparison mechanism 154. The comparison mechanism 154 compares this value with the L_BV value received via line 148. When these two values are equal, comparison mechanism 154 produces a binary 1 on the output connected to other hardware in the host bridge 20. This output, called R_DONE, indicates when the read data transfer initiated by PCI bus 22 was completed on S bus 16.

【0087】

The operation of hardware 100 differs depending on whether the data transfer initiated by the master connected to the PCI bus 22 (PCI master) is a read transfer or a write transfer. In read transfer operation, the PCI master initiates a read cycle targeting S bus 16 on PCI bus 22, and host bridge 20 responds as a slave. The byte enable signal from the PCI master is latched into latch 102 and input to comparison mechanism 154 and NXOR gate 150.

【0088】

Since the read transfer on the S bus 16 has not yet started, the multiplexer 106 outputs the first input, which is the 4-bit binary value "1111". This value is then latched into the latch register 104 and output to the NXOR150 as an L_BV signal on line 148.

【0089】

The NXOR gate 150 then produces a 4-bit output value based on the inverting exclusive OR combination of the byte enable signal from the PCI bus 22 latched in the latch register 102 and the L_BV value. Since the current transfer is a read operation, the multiplexer 110 selects the output from the NXOR gate 150 that should be driven on the output of the multiplexer 110 itself throughout the data transfer.

【0090】

The detector 114 then determines if the output from the multiplexer 110 is discontinuous, and if so activates the signal on line 116 by driving the output signal NC to the value binary 1. When NC is activated, the outputs of OR gates 126 and 128 go high, making bit numbers 2 and 3 of the PBE signal on line 124 logic 1. Therefore, PBE is always continuous data. As mentioned above, the values of bit numbers 0 and 1 in PBE are only bit numbers 0 and 1 in the output of the multiplexer 110.

【0091】

The PBE signal is then transmitted over line 124 to the S bus 16 as a byte enable signal for the current bus cycle. When the slave connected to the S bus 16 to which the read transfer is output responds affirmatively to the data transfer, it generates binary 0 on the BS8 line or BS16 line, and the slave itself is an 8-bit device or a 16-bit device, respectively. It can be shown that there is. The generator 132 generates an NBE signal on line 136 according to Table 2 above, based on the values of the BS8, BS16, and PBE signals.

【0092】

If BS8 or BS16 is enabled to binary 0 and the generator 132 determines that another bus cycle is required on the S bus 16 to complete the data transfer, the generator 132 is on line 134. Generates a binary high signal as a BSZ signal. This causes the OR gate 130 to generate a BC high signal indicating to other hardware in the host bridge 20 that another bus cycle is required to complete the data transfer. Similarly, if the detector 114 produces a high value for NC on line 116, the OR gate 130 indicates that BC needs another bus cycle to complete the data transfer. Drive to value.

【0093】

When the NBE signal is generated, it is input to the NXOR gate 140 together with the PBE signal from line 142. The 4-bit binary value output by the NXOR gate 140 is input to the AND gate 146 together with the feedback signal of the output of the latch register 104. The AND gate 146 performs a logical AND operation on these two signals and outputs the result connected to the fourth input of the multiplexer 106. Since this transfer is a read data transfer and the first bus cycle of data transfer on the S bus 16 is complete, the multiplexer 106 selects a fourth input to drive on the output.

【0094】

This new output from the multiplexer 106 is latched into the latch register 104 into the next L_BV signal. The process is repeated for this new L_BV signal.

【0095】

This process continues for each new value of L_BV until all the data indicated by the byte enable signal from the C / BE line of PCI bus 22 has been transferred. When this is done, the L_BV value is equal to the byte enable signal from PCI bus 22. Both of these signals are always input to the comparison mechanism 154, and when they are equal, the comparison mechanism 154 activates R_DONE high and informs the S bus 16 and the host bridge 20 that the data transfer is complete. Shown. When this is done, all data is read from the slave connected to S bus 16.

【0096】

The behavior of byte-enabled hardware 100 during write transfers differs from that during read transfers in some respects. The master connected to the PCI bus 22 first starts a write cycle targeting the S bus 16. The byte enable signal from the PCI bus 22 is input to the second input of the multiplexer 106. Since the first bus cycle of data transfer has not started on the S bus 16 and this operation is a read operation, the multiplexer 106 selects a signal on the second input to be driven on the output. Therefore, the latch 104 latches the values of the byte enable signals from the PCI bus 22, and these signals become the values of L_BV.

【0097】

Since this transfer is a write transfer, the multiplexer 110 selects a signal on the second input to drive on the output. This signal is L_BV. L_BV is then output to detector 114 and split on lines 118, 120, and 122. The detector 114 and the OR gates 126 and 128 provide the same functionality provided for read operation. That is, a PBE signal is generated on the S bus 16 so that the signal becomes continuous data. Similarly, generators 132, BS8, and BS16 operate in the same manner as for read transfers to generate NBE signals, and OR gate 130 provides the same function of generating BC signals.

【0098】

When the generator 132 generates an NBE signal, the signal is input to the XOR gate 138 via the line 136 together with the PBE signal. The XOR gate 138 performs an exclusive OR operation on the PBE signal and the NBE signal, and outputs the result to the input of the OR gate 144. The OR gate 144 also receives an input signal, which is an L_BV signal, via the feedback line 148. The OR gate 144 performs an OR operation on the two signals input to it and outputs the result to the third input of the multiplexer 106.

【0099】

Since the current data transfer is a write operation and the first bus cycle of data transfer on the S bus 16 has been completed, the multiplexer 106 selects a signal on the third input to be transmitted on the output. To do. The output of multiplexer number 106 is latched into latch register 104, resulting in a new value for L_BV.

【0100】

This new value of L_BV is then input to the second input of the multiplexer 110 and the entire process is repeated. The process is repeated until the value of L_BV has a binary value equal to "1111". When this happens, all the data has been transferred from the PCI bus 22 to the slave connected to the S bus 16.

【0101】

When L_BV equals "1111", AND gate 152 activates W_DONE. This indicates to the S bus 16 and the slaves connected to the bus 16 that the data transfer has been completed.

【0102】

An example of the operation of the hardware 100 during the write operation in which the byte enable signal from the PCI bus 22 equal to "0100" is output to the 8-bit slave is shown below.

【0103】

The byte enable signal "0100" is sent to the second input of the multiplexer 106. The multiplexer 106 outputs the same signal to the latch register 104, which outputs an L_BV signal equal to "0100". The multiplexer 110 inputs this signal and outputs it to the detector 114.

【0104】

The detector 114 determines that L_BV is discontinuous data, and outputs signal 1 as NC. Since NC is equal to 1, OR gates 126 and 128 equalize PBE on line 124 to "1100". This signal is transmitted on the S bus 16 as a byte enable signal for the first bus cycle.

【0105】

The slave to which the write is output responds with a low signal on the BS8, which causes the generator 132 to generate the NBE signal "1101". This is because only the data corresponding to bit number 0 of the PBE signal was transferred during the first bus cycle. The generator 132 also sets the BSZ high. With the BSZ and the high NC signal, the OR gate 130 produces a high signal on the BC indicating that at least another bus cycle needs to complete the transfer.

【0106】

The PBE and NBE are input to the XOR gate 138. The XOR gate 138 performs an exclusive OR operation and produces an output equal to "0001". The OR gate 144 then performs an OR operation with the output from the XOR gate and the feedback value from the latch 104 as inputs. The result of this operation is "0101". "0101" is sent to the third input of the multiplexer 106 and output from the multiplexer 106 to the latch register 104. This is now the value for L_BV.

【0107】

Therefore, "0101" is sent to the detector 114 via the second input of the multiplexer 110, which again determines that this value is discontinuous data and equalizes NC to 1. This causes OR gates 126 and 128 and line 118 to generate a PBE on line 124 that is equal to "1101" for the second bus cycle on S bus 16. The NC signal also indicates to the host bridge 20 that the OR gate 130 enables the BC signal and requires yet another bus cycle to complete the data transfer. During the second bus cycle, bytes of data corresponding to bit number 2 of the byte enable signal PBE are transferred to the slave.

【0108】

The slave again responds with a low signal on the BS8. Therefore, the generator 132 generates the NBE signal "1111" on line 136 without activating the BSZ signal according to Table 2.

【0109】

This value is entered into the XOR gate 138 along with the PBE value. Therefore, the XOR gate 138 produces an output "0010", which is input to the OR gate 144 via the feedback line 148 with the current value of L_BV. The OR gate 144 responds by outputting a value equal to "0111" to the third input of the multiplexer 106. This value becomes the new value for L_BV.

【0110】

Detector 114 determines that the new value for L_BV is continuous data and does not enable NC. Therefore, the value of L_BV is simply unaffected by OR gates 126 and 128 and is sent on line 124 as a new value for PBE. A third bus cycle is then generated on the S bus 16 that completes the data transfer with a byte enable signal equal to the current value of PBE, "0111".

【0111】

The slave responds by activating BS8. However, the generator 132 does not activate the BSZ signal and again generates the value "1111" for NBE on line 136. The final output of the logical operations performed by the XOR gate 138 and OR gate 144 is currently "1111", which is input to the third input of the multiplexer 106 and output to the latch register 104. Therefore, the value of L_BV becomes "1111", which causes the AND gate 152 to generate a high signal of W_DONE to end the data transfer.

【0112】

If the above example was read data transfer, the same byte enable value for PBE is used for the bus cycle on S bus 16. However, as mentioned above, these values are derived in different ways. This is because the read "logical path" is used instead of the write "logical path" in hardware 100.

【0113】

In summary, the following matters will be disclosed with respect to the constitution of the present invention.

【0114】

(1) The central arithmetic processing device, the system bus connected to the central arithmetic processing device, the peripheral bus for connecting the peripheral device to itself, and the data string to be transmitted on the system bus are not included. A logical network that detects whether it is a continuous data string and, if the data string is a non-continuous data string, converts the data string into a plurality of continuous data strings before transmitting the data on the system bus. An information processing system including a host bridge for connecting the system bus to the peripheral bus. (2) The information processing system according to (1) above, wherein the logical network is hardware in the host bridge. (3) The logical network is characterized by including a generator that generates a plurality of enable signals for the data string based on the bit size of a slave connected to a system bus that transmits and receives the data string. The information processing system described in (1) above. (4) For the logical network to convert the data string into the plurality of continuous data strings at the time of write transfer and a first logical path for converting the data string into the plurality of continuous data strings and at the time of read transfer. The information processing system according to (3) above, which includes the second logical path of the above. (5) The information processing system according to (4) above, wherein the logical network includes at least one multiplexer for selecting the first logical path or the second logical path. (6) The enable signal is processed by the first logical path at the time of write transfer and by the second logical path at the time of read transfer so as to obtain the plurality of continuous data strings. The information processing system described in (5) above. (7) The information processing system according to (1) above, wherein the peripheral bus is a PCI bus. (8) The information processing system according to (1) above, wherein the peripheral bus is a multiplexed bus. (9) The information processing system according to (1) above, wherein the peripheral device connected to the peripheral bus starts the transmission of the data string on the system bus. (10) The plurality of continuous data strings are continuously transmitted on the system so that the continuous data string and the bus cycle on the system have a one-to-one correspondence with each other. The information processing system described in (1). (11) In an information processing system, a method of transferring discontinuous data between a peripheral device connected to a peripheral bus and a component connected to the system bus, a step of providing a central arithmetic processing device, and a step of providing a central arithmetic processing device. A step of providing a system bus connected to the central arithmetic processing device, a step of providing a peripheral bus for connecting a peripheral device to itself, and a step of connecting the system bus to the peripheral bus. A step of detecting whether the data string to be transmitted on the system bus is a discontinuous data string, a step of converting the data string into a plurality of continuous data strings when the data is discontinuous data, and the system. A method comprising a step of transmitting each of the plurality of the continuous data strings on a bus. (12) It comprises an additional step of generating an enable signal for each of the continuous data strings based on the bit size of the slave connected to the system bus transmitting or receiving the continuous data string. The method described in (11) above. (13) The information processing system according to (11) above, wherein the peripheral bus is a PCI bus. (14) The information processing system according to (11) above, wherein the peripheral bus is a multiplexed bus. (15) A host bridge for connecting a system bus to a peripheral bus in an information processing system, and a data string to be transferred from the system bus to the peripheral bus or from the peripheral bus to the system bus. A detector for determining whether is a discontinuous data string, the data string is converted into a plurality of continuous data strings, and the continuous data string is transmitted on the system bus during a continuous cycle of the system bus. A logical network for the data string and a generator for obtaining an enable signal for each of the plurality of continuous data strings based on the bit size of a component of the information processing system that is a slave in the transfer of the data string. A host bridge characterized by its provision. (16) The host bridge according to (14) above, wherein the peripheral bus is a PCI bus. (17) The host bridge according to (14) above, wherein the peripheral bus is a multiplexed bus.

【0115】

[Effect of the invention]

Therefore, methods and devices are provided that provide accurate and complete communication between different bus architectures in an information processing system.

[Simple explanation of drawings]

[Figure 1]

It is a schematic diagram of an information processing system including a plurality of buses.

[Figure 2]

It is a schematic diagram of an information processing system including a plurality of buses.

[Fig. 3]

It is a schematic diagram of an information processing system including a plurality of buses.

[Fig. 4]

It is a timing diagram of two continuous write cycles on the PCI bus.

[Fig. 5]

It is a timing diagram of two continuous read cycles on the PCI bus.

[Fig. 6]

A logical diagram of the byte enable control hardware in the host bridge.

[Explanation of symbols]

16 S bus 20 PCI host bridge 22 PCI bus 34 CPU local bus 40 DMA controller 72 Graphics controller 80 PCI secondary bridge 100 hardware 102 Latch register 106 multiplexer 114 detector 116 Output line 126 OR gate 132-byte enable generator 138 2 Input exclusive OR gate 140 2 Input Inversion Exclusive OR Gate