AT188049T

Provision of accurate and complete communication between different bus architectures.

Abstract

The invention is connected with the CPU local bus and an external bus's main is connected with the logic, whether the hardware logic detecting is transmitted reverse driving the data and device on sides the CPU local bus, and replacing, the non-adjacency data with the data sides, and movable of for guaranteeing the CPU local bus without the fault. Hardware of the invention is for moving the data transmission and external bus and A local bus, an external bus limiting groove for structure is the measuring standard burst, the CPU local bus is permit the dynamic bus stage.

Term

No projected expiry on record.

  1. Priority
  2. Filed
  3. Granted
  4. Today

15 members in 10 offices

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Priority claims
DocumentOfficeKindDate
6923493United States of AmericaA

Members15

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DocumentOfficeKind
CA2124029A1CanadaA1
EP0627688A1European Patent Office (EPO)A1
BR9402108ABrazilA
JPH06348646AJapanA
CN1118478AChinaA
US5550989AUnited States of AmericaA
JP2565659B2JapanB2
KR970008191B1Republic of KoreaB1
TW321743BTaiwan Province of ChinaB
EP0627688B1European Patent Office (EPO)B1
AT188049TThis recordAustriaT
ATE188049T1AustriaT1
DE69422221D1GermanyD1
DE69422221T2GermanyT2
CN1064463CChinaC