Constitutable logical array

[Detailed Description of the Invention]

The field of an invention This invention is generally more specific, concerning a programmable logical device, It can consist of the array, and an input/output block of a logical block, and the composition program stored in the on-chip memory can constitute those each about the programmable gate array accompanied by interconnecting structure. Explanation of a pertinent art Programmable gate arrays are high performance and a user program possible device, and contain the element of three models made according to a user's system design which can be constituted. The three elements have an array of the logical block (CL B) which can be (1) constituted, and the surrounding input/output block of the circumference of (2) (IOB), and they are all linked by the programmable interconnection network with (3) flexibility. The system design considered as a request by the user is realized by constituting a programmable RAM cell in the device. These RAM cells control the logical functionality performed by CLBS IOB and interconnection. The composition is realized using a PGA design software tool. It is generally accepted that the programmable gate array was commercially introduced for the first time by Cushillinks (Xilinx) of California and Sun Joy (SAN 1ose, Ca1 i!ornia). Cushillinks introduced XC2000 series of the logic cell array first, and introduced more 2nd generation XC3000 family of the integrated circuit programmable gate array recently. It is explanation of 2000 series like the programmable logical device art of relation, [programmable gate array design handbook published by Cushillinks (found out by 1-1 of the TI (E PROGRAMMABLE GATE ARRAY DESIGHHANDBOOK) J first edition thru/or 1 - 31 pages.) The architecture for XC3000 family is shown in 1 - 31 pages of the engineering data handbook of the title rXc3000 logic cell array familiar (IC3000LOGICCEL[, ARRAY FAM[LY) J published by Cushillinks. In this application, each of the publication of these Cushillinks is used by quotation as what provides explanation of a prior art. The prior art in a programmable gate array is further illustrated by United States patent No. 4.642.487, No. 4,706.216, No. 4,713,557, and No. 4,758.985, and those each is transferred to Cushillinks parrot Holted. These United States patents are applied by quotation as what describes detailed explanation of the programmable gate array architecture and the example of realization of that. As stated above, a programmable gate array consists of a ring of the interconnection which can be constituted, and composition good Yoshihito power / output block, and an array of the logical block which can be constituted. It is the combination of these three main feature things to give the flexibility and data processing capacity for a programmable gate array. However, the programmable gate array of a prior art receives restriction in each of interconnecting structure, input/output Plock structure, and the logical block structure that can be constituted. The interconnecting structure which can be constituted must give the capability to form the network on a programmable gate array which optimizes exploitation of the resources on a chip. The interconnected system of a prior art had the tendency to force relatively the connection to the block in a logic network which can be constituted in a small field. For example, the system of precedence gives connection directly, only while [ of proximity / logical block ] can be constituted (adjacent). the input and output on [ which can be constituted ] a logical block -- the right from the left -- or in other modes, it is arranged with an asymmetric layout and it forces the flow of the signal in the direction which crosses a chip and which changes. This causes the high density on interconnecting structure to the application which needs many inputs or outputs. moreover -- the printing circuit board layout in which this contains one of these logic cell arrays designed asymmetrically is an input on the one side of a logic cell array -- and it forces preparing an output on another side. In addition, the interconnecting structure of a prior art has the number of two or more sauce networks which may be realized restricted. The input/output block in the programmable gate array of a prior art are complicated macro cells relatively, in order to give the flexibility needed for various application meant to a device. However, these complicated macro cells contain the resources which are not used within the composition of many of inputs / output blocks. A block is Late (passage through many buffers between logic cells, a multiplexer, a register, and input/output pad is needed.) relatively because of the complexity. An input/output block causes the high density on a circumference logical block in the device for the application including many inputs and outputs. The restriction which affects the flexibility of a device also in itself [ logical block ] which can be constituted is received. The logical block of the prior art operated about the input variable of a small group relatively. In this way, it needed to decode a large gate function (function), for example, 16 A bit commands, or for a large multiplexing function to make a cascade many blocks which can be constituted. In this way, the very easy function could use within the array the logical block of many numbers which can be constituted. furthermore -- originating in restriction of the number of the direct interconnection between logical blocks, when making a block into a cascade -- a signal -- many (programmable-boat fishing connection is crossed and transmitted.) This causes delay for the number of programmable Points of Interface used. quick operation -- necessity -- To do -- it becomes un-practical to make a block into a cascade for a critical course. In the logical block of a prior art which can be constituted, four input signals are typically used for a logic function. In order to obtain 5 variable (Ma amiable) gate function, the logical block which can be constituted used common use of the input mechanism. This common use of an input restricts greatly the logical flexibility for these 5 variable functions in a prior art. In order to attain a user's flexibility, for a relatively complicated structure needed to a block, the logical block of the prior art which can be constituted also covered the disadvantage of speed again. Logic will spread at a late speed relatively for a complicated structure needed for the block used for the easy function. It is more desirable to provide the programmable gate array which prepares big flexibility and logical capability than being given by the device of a prior art. The abstract of an invention This invention provides the architecture for the logic array which has interconnecting structure and which can be constituted, and it improves the flexibility of making the network which enables bigger use than that of the logical block on a device which can be constituted, and an input/output block. Therefore, this invention is the improved logic array which can be constituted, and it contains the composition memory which stores the program data which specifies a user regulation data processing function. In addition, two or more logical blocks which can be constituted are arranged at the array which consists of zero row and an R line. It is combined with a composition memory, and each logical block which can be constituted answers the input signal in each input, and answers the program data in composition memory storage, and has two or more inputs and outputs for generating an output signal in each output. two or more composition good Yoshihito power / output blocks are contained, and each is combined with input/output pad and composition memory storage -- and at least one input -- and few (it has one output.) Composition good Yoshihito power / output block answers program data, and gives the interface which can be constituted to Open of each pad, each input, and an output. the interconnection which can be constituted -- the logical block which can be constituted, and composition good Yoshihito power / output block -- and it is combined to composition memory storage, the program data in composition memory storage is answered, the input of the logical block which can be constituted, an output and composition good Yoshihito power / output block is connected, and it is made a logic network. If one aspect of affairs of this invention is followed, the interconnection which can be constituted will be symmetrically arranged about the input and output of the logical block which can be constituted. In this way, the input of CLB may be extracted from 4 sides, and an output may drive to four side of each CLB(s), and it becomes symmetrical interconnecting structure. Interconnection includes two or more perpendicular buses in alignment with two or more level buses in alignment with the line of CLB, and the sequence of CLB. It can be level, and the intersection of a perpendicular bus can be constituted so that a device may be crossed and course attachment of the network may be carried out. Another aspect of affairs of interconnection is level, and including two or more switching matrices in the intersection of a perpendicular bus, each has 1 set of level connection, and 1 set of perpendicular connection, the program data in composition memory storage is answered, and it carries out interconnection of each thing of the horizontal or vertical connection. Two or more level conductivity segments in a level bus are between level connection of a switching matrix, and are connected. Two or more programmable Points of Interface combined with each input and output of the logical block which can be constituted, and an input/output block answer program data, and it gives the connection possibility to each level segment. Similarly, two or more perpendicular conductivity segments in a perpendicular bus are between perpendicular connection of a near switching matrix, and are connected. A programmable Point of Interface answers program data, and carries out interconnection of each input and output of the logical block which can be constituted, and human power/output block to each perpendicular segment. if one aspect of affairs of this invention is followed -- a perpendicular vertical or horizontal [ a level segment ] bus "i" -- bus [ from an inner switching matrix ] 'i+2" -- it is characterized by extending to an inner switch matrix, and, so, each segment starts two sequences or line of a logical block. The bus in interconnection is further characterized by two or more horizontal and vertical conductive long lines which cross the whole chip and extend. It is connected to two or more programmable Points of Interface, and each long Line answers the program data in a composition memory, and carries out interconnection of each input or output of the logic cell which can be constituted to each long line. A long line has a programmable Point of Interface which combines the output of the logical block which is given to each long line by 3 state buffer, and which can be constituted. In another aspect of affairs, the bus within interconnecting structure is characterized by the horizontal (uncommi Red) and vertical long line which is not restrained. The each long line which is not restrained is connected to two or more 1st programmable Points of Interface, Program data is answered and interconnection of each output of the logical block which can be constituted, or an input/output block is carried out to each long line, And it is connected to two or more 2nd programmable Points of Interface, and interconnection of the long line by which it swerves and You is not restrained is carried out to the horizontal or vertical segment combined with a switching matrix. Interconnecting structure further includes directly two or more connection which carries out interconnection of the output of the logical block which can be constituted, or an input/output block to the input of another logical block which can be constituted, or an input/output block. It is the 1st subset that it is few as connection is directly connected between near input / output block, or the logical block which can be constituted, The 2nd subset connected between the logical block of the output of the logical block which can be constituted, or an input/output block, and the next proximity which can be constituted, or an input/output block is included. In one aspect of affairs of this invention, each CLB is directly connected to CLB of the eight neighborhoods. Two or more composition good Yoshihito power / output blocks are characterized by each line of the logical block which can be constituted, or the group of the input/output block of a sequence and correlation. In each group, at least one a compound (complex) input / output block are contained, and at least one a simple (limple) input / output block are contained. compound human power / output block gives functionality with the flexibility needed for many application -- on the other hand -- simple human power / appearance -- a turnip -- a lock -- the inside of an array which can be constituted -- or the quick access path from there is given. All the input/output logical blocks are characterized by 3 state possible output buffer to a pad and internal interconnection, and they answer the control signal which occurs within [ which can be constituted / program data and/or ] a logic array, and are controlled. The output of the logical block which can be constituted contains two or more 3 state buffers which receive each thing and 3 state control signals of an output signal of 1 combination logic. 3 state output buffer answers 3 state control signals, and supplies each output signal as an output from a logical block, or gives a high impedance state. Three state control signals answer the input to the program data and the logical block which can be constituted in composition memory storage, and occur. Another aspect of affairs of this invention is a re-electric power grant buffer which has the bypass course which leads via a switching matrix, and which was level and was combined with perpendicular Segment and which can be constituted (con[igutable repovering buffe+s). Supply is made via interconnection and a control signal is given from the source of a signal to all the CLB(s) in an array. If this invention is followed, it will suffer the disadvantage of speed only to the gate function to which the logical block which can be constituted is characterized by improvement of a large number exceeding a prior art and in which the logical block which can be constituted prepares mixture of a narrow gate and a large gate function specifically that it is large. The logical block which can be constituted is symmetrical, and accepts an input by 4 side Stop of each block, and supplies an output by 4 side Stop. The capability for driving directly the signal to other logical blocks which can be constituted for output structure itself to change [ and ] into three states the output connected to the interconnection which can be constituted is given. The input structure of all the 4 side Stop of the logical block which can be constituted can answer a composition program, and can constitute independently. Similarly, four output macro cells in [ each / which can be constituted ] a logical block can be constituted independently. As a feature characterized by bigger use than that of the resources on an array, inside respectively [ an output macro cell ], the register is independently accessible about the combination logic in [ which can be constituted ] a logical block. This makes it possible for these registers to combine, to be related with logic and to be used into an independent network. If one aspect of affairs is followed, the logical block which can be constituted can characterize under the condition that it has an input multiplexing tree which answers program data, and receives J input signal, and chooses a signal as a subset, and K is few or more nearly equal than J in there. Combination logic is combined with a composition memory and an input multiplexing tree, K signal and program data are answered, plurality carries out, and it generates a logic signal. Four independent output macro cells are contained, plurality carries out those each and it chooses an output signal from a logic signal. Each of an output macro cell contains 3 state possible output buffer for driving the selected output signal to the interconnection which can be constituted. Each output macro cell contains the 2nd output buffer for driving a signal directly to up to connection with other logical blocks for driving the signal selected independently of 3 state possible output buffer which can be constituted. an input multiplexing tree -- the any [ of K signal ] at least one -- although -- either of the 4 sides of the logical block which can be constituted may also be supplied Combination logic is realized by the 1st look-up table in the program data which becomes eight 8 A bit arrays from 64 A bit by which a group division is carried out. It is used in order that three signals from the subset of a signal supplied independently may carry out the address of a pair of four each of 8 A bit array for making 8 A bit array into a pair and so supplying with an input multiplexing tree. Two outputs of each set are combined with a crossing multiplexer, and it can answer program data and it can constitute it, The signal which passes directly two outputs supplied by a pair of two 8 A bit arrays or with which the 4th from a signal is supplied independently to a subset is answered, and one of two outputs is chosen as a primary output. The output of a crossing multiplexer is supplied via the 3rd multiplexing level that consists of two multiplexers, and it can control independently by each thing of the subsets of a signal respectively. the output of the 3rd level of multiplexing -- and the 4th level of multiplexing is supplied, and it is alike, is controlled by one of the subsets of a signal, it answers six inputs and supplies the output which is a perfect lookup function (IunNion) of 64 A bit array. Combination logic further contains the special 16 A bit array in the program data combined with 16 to 1 multiplexer. The control input to 16-1 multiplexer is a path through output of four crossing multiplexers referred to above. Each of these inputs is a function (a !unction) of four independent variables. The output of 16-1 multiplexer supplies a special output, and it provides the lookup function with which 16 independent variables were restricted. a special output is combined with the output of the 4th level multiplexer within the 5th level multiplexer, it is alike, and answers the input signal of the subset of a signal, or it is controlled by program data. If another aspect of affairs is followed, the logical block which can be constituted will be characterized by preload capability. Between programming of the logic array which can be constituted, each of the storage cell in the output macro cell of the logical block which can be constituted is activity-ized so that data may be received, as if it was a position in a composition memory. If this invention is followed, the architecture will prepare each line of the logical block in an array which can be constituted, and the group of the input/output block of a sequence and correlation for the specific target in which composition good Yoshihito power / output architecture is characterized by improvement of a large number exceeding a prior art. Each of a group is further characterized by having two or more compound human power / output blocks, If they bring about a flexible structure for realizing the interface between the logic array which can be constituted, and an outside device and are required by specific application, they contain at least one the simple human power / output block which provides the early course from the outside of a device to the logic array which can be constituted. It has the 2nd buffer for driving directly connection with at least one 3 state possible output buffer simple and for both compound human power / output block drive a signal on [ which can be constituted ] interconnecting structure, and the logical block in a device which can be constituted. Compound human power / output block contains an input storage cell and an output storage cell. Connection is directly given to surrounding next near compound human power / output around a device from the input storage cell of one compound human power / output cell. The output storage cell of compound human power / output cell is similar, and is connected. In this way, the storage cell in compound human power / output block may be linked to the data path which can be constituted, and they can operate as a shift register or other similar circuits in there. The storage cell in compound human power / output block is further constituted so that a synchronous function, a local reading return function, and an embedded register function may be provided. If this invention is followed, an input/output block will be further characterized by control signal generating from the long line within programmable interconnecting structure. This enables use of the network in [ which can be constituted ] a logic array for controlling operation and composition of composition good Yoshihito power / output Blodzuk by a dynamic mode. A long line is constituted so that a signal may be made to spread completely around around an array, and a common signal may be used in order to control all the inputs/output blocks so. If this invention is followed, the logic array which is provided and which can be constituted will improve the flexibility and performance of a programmable gate array greatly exceeding them which can be used in a prior art. Partially, this is attained by the symmetrical connection with the interconnecting structure which supports the network which has a long spread (reach) which crosses a device, two or more sauce network, and the logical block which can be constituted. The peculiar logical block architecture which can be constituted supports realization of the symmetrical network in efficient use of the resources in an array, a large gate function, a narrow gate function without a speed disadvantage, and an array. At the end, peculiar input/output architecture supports efficient exploitation of the resources within input/output structure, Propagation of the quick signal through simple human power / output block and the highly efficient signal propagation through the compound human power / output block into an array were enabled, and the flexibility in the source of the control signal for input/output structure was improved. The further aspect of affairs and advantage of this invention will be found out by reexamination of brief explanation of the drawings and a claim. DETAILED DESCRIPTION With reference to drawings, detailed explanation of the desirable example of this invention is given. With reference to Drawings 1 thru/or 3, the fundamental layout and programming structure of the gate array which can be constituted are explained to the 1st. Next, detailed explanation of interconnecting structure is described with reference to Drawings 4 thru/or 24. The example of realization of the logical block which is used within a programmable gate array and which can be constituted is explained with reference to Drawings 25 thru/or 44. The example of realization of the logical block which is used within a programmable gate array and which can be constituted is explained with reference to Drawings 45 thru/or 49. After explanation of the logical block which can be constituted, and input/output cell, connection between an input / output block, and the logical block that can be constituted is directly explained with reference to Drawings 50 thru/or 55. Explanation of the connection to the remainder of interconnecting structure of the logical block which can be constituted, and input/output cell follows this with reference to Drawings 56 thru/or 70. ■ A layout and Drawing 1 of programming structure show the layout of the programmable gate array according to this invention. The notation used in order to explain the programmable gate array in this application is also given in Drawing 1. If this is followed, the programmable gate array shown in Drawing 1 will consist of an array of the logical block which is shown with the sign of the quadrangle in the thick line shown in the upper part left-hand side angle of a figure and which can be constituted. Each logical block in an array which can be constituted is specified by the number of a line and a sequence, and is set on the upper part left-hand side square of them, i.e., an array, The logical blocks which can be constituted are clearly shown to be RICI and RIC2, and it continues to the lower part right-hand side angle of an array, and the logical block which can be constituted is clearly shown to be R8C8 in there. The pad of 110 for connection with an external pin is around around an array. Pads 2 thru/or 13.16 27.29 thru/or 40.43 54.57 thru/or 68.71 thru/or 82.85 thru/or 96, and 99 thru/or 110 is combined to the composition good Yoshihito power / output block expressed with the sign shown in the upper part left-hand side angle of a drawing. Pad 1.14.15.28, 41.42.55.56.69*70.83.84.79, and 98, It is used for functions composition good Yoshihito power / other than an output block, and they are electric power, grounding, a large region clock, a reset signal input, and a programming mode control signal. It is similar and connection of these miscellaneous pads is not further explained here, besides it was made in the programmable gate array of a prior art. Interconnecting structure consists of nine level buses clearly shown to be nine perpendicular bus VBUS Engineering thru/or VBUS9 crossing and HBUSl(s) thru/or HBUS9. It is characterized by the intersection with level buses 2 thru/or 8 of perpendicular bus 1 and perpendicular bus 9 having a segment box, and they provide the programmable interconnection between each level bus and perpendicular bus so that it may be explained below. Similarly, an intersection with perpendicular buses 2 thru/or 8 of level bus 1 and level bus 9 is also characterized by a segment box, and they are level and provide the programmable interconnection between perpendicular buses. The intersection of perpendicular buses 2 thru/or 8 and level buses 2 thru/or 8 is characterized by each switching matrix which is level and is provided for the interconnection between perpendicular buses. Arrangement of a segment box and a switching matrix is roughly shown in Drawing 1 using the sign shown in the lower part left-hand side angle of a drawing. A detailed structure of a switching matrix and a segment box is explained below. The programmable gate array according to this invention contains the element of three models made according to a user's system design specified in a composition memory which can be constituted. Three elements which can be constituted are an array of the logical block (CLB) which can be constituted, the surrounding surrounding composition good Yoshihito power / output block (IOB), and a programmable interconnection network. A user's system design is realized in a programmable gate array by constituting a well-known programmable RAM cell as a composition memory. These RAM cells control the logic function nature performed by CLB, IOB, and interconnection. Loading of a composition memory is realized using 1 set of design software tools which are common knowledge in the art concerned. The circumference of IOH which can be constituted gives the programmable interface between an internal logic array and a device package bottle. The array of CLB performs a user specific logic function. Interconnection consists of direct connection between specification CLB or IOB, and general connection (a general connect) programmed to form the network which is between blocks and conveys a logic signal. The logic function performed by CLB is determined by the programmed look-up table in a composition memory. A functional option is performed by the programmed control multiplexer. The interconnection network during a block consists of a metal segment combined by the programmable Point of Interface (P I F). A logic function, a functional option, and an interconnection network are activated with program data, and it is loaded in the internal distribution array of a composition memory cell. A composition pit stream is loaded in a device by upgrade, and it may be reloaded by a command. Drawing 2 is a schematic diagram of a programmable gate array seen with program data. A programmable gate array contains the distributed memory cell of the plurality called composition memory 200. The program data on line 201 answers the clock signal on line 203, and is loaded in shift register 202. When detection logic 204 reads Preamble from the data on 201, the time full of a shift register is decided. When a shift register is full, detection logic 204 sends a signal to frame pointer logic 206 via line 205, and it crosses line 207 and generates a frame pointer signal. control logic 208 answers the mode input to the device on line 209 -- between loading of composition memory 2 *O -- a frame pointer -- and line 210 is crossed and detection logic 204 is controlled. Composition memory 200 is organized by two or more frames F1 thru/or FN. If program data is loaded in a shift register, frame pointer F1 is activated and the 1st frame is loaded in a composition memory. When the 2nd frame of data is loaded to a shift register, the frame pointer to F2 is activated, the 2nd frame F2 is loaded, and it continues until the whole composition memory will be loaded. Control logic 208 generates a programmed signal (a program donesignal) on line 210. The static memory cell used within a composition memory is shown in Drawing 3. It is designed specially because of high reliability and noise immunity. Primitive cell 300 contains data input line 301 combined with path transistor 302. The gate of path transistor 302 is combined with read-out on line 303, or a write-in control signal. The output of path transistor 302 is combined with line 304. line 304 -- the input of inverter 305 -- and it is combined to the output of inverter 306. The output of inverter 305 is combined with line 307, and it returns to the input of inverter 306 and is combined with it. Lines 304 and 307 give Q for composition control, and phi output. In this way, primitive cell 300 consists of two CMOS inverters and a path transistor. A path transistor is used in order to write in and read cell data. A cell is written in only between composition and read only between the reading return in programming mode. Between the usual operations, a path transistor is in an OFF state, and does not influence the stability of a cell. Memory cell outputs Q and phi give continuous direct control, using perfect grounding and a vco level. Composition memory storage may be realized by the volatility of other models, or a fixity storage cell again. For example, EPROMXE2 PROM, a programmable resistance link, or Ferro Nonvolatile memory, such as RAM, may be used. By downloading the flow of a bit from a host system or external memory, such as EPROM, a device memory is constituted, as explained above. The composition process is the same as them which were used in the programmable gate array of a prior art, and one exception is discussed below with reference to the logical block which can be constituted. II Interconnecting structure which can be constituted Interconnecting structure is level and the interconnection of a perpendicular bus, and level and a perpendicular bus is explained with reference to Drawings 4 thru/or 24. Drawing 4 shows the notation used for a perpendicular bus. Each perpendicular bus has a line of 25. Lines 1 thru/or 4, and 15 thru/or 17 is long lines, and they cross the whole array and run. Lines 5 thru/or 14 consist of a bidirectional general interconnection segment, and they are combined via a switching matrix and a segment box so that it may be explained below. Lines 18 thru/or 25 are long lines which run the length of the whole array and which are not restrained. Drawing 5 shows the notation used for a level bus. Each level bus is a line bus of 23, line 1 thru/or 4 and 15 are long lines in there, and lines 5 thru/or 14 are bidirectional general interconnection segments, and lines 16 thru/or 32 are long lines which are not restrained. The distinction between a long line, a bidirectional general interconnection segment, and the long line that is not restrained is stated to the following in detail. Since the network through a device is constituted, level and a perpendicular bus need the means of interconnection. This happens in the intersection of a level bus and a perpendicular bus. The interconnection between the lines in an intersection is made via a programmable Point-of-Interface and switch matrix and a segment box. Drawing 6 shows arrangement of the switching matrix in interconnecting structure. Reference of Drawing 1 will understand that a switch matrix is positioned by the intersection of perpendicular buses 2 thru/or 8 and level buses 2 thru/or 8. Drawing 6 shows arrangement of the switch matrix on (adjacent) level bus 4 of proximity in logical block R3which can be constituted C5, R3C4, R4C5, and R4C4. It is understood that a switch matrix is positioned only on line 5 thru/or 14 of bidirectional general interconnecting structure. In this way, bidirectional general interconnecting structure consists of a segment which are two logical blocks which can be constituted in length, In this case, it starts to switch matrix 601 positioned from switch matrix 600 positioned on perpendicular bus 3 in line 5 thru/or 9 on perpendicular bus 5 of bidirectional general interconnection. Switch matrix 602 is combined with the segment of lines 10 thru/or 14, and it passes through them perpendicular bus 4 from perpendicular bus 2, and extends from perpendicular bus 4 to perpendicular bus 6. Perpendicular buses 2 and 6 are not shown in Drawing 6. Enabling propagation of the signal which crosses width equal to two logical blocks on an array which can be constituted is understood, without connection with bidirectional general interconnection passing via a switch matrix using arrangement of the switch matrix shown in Drawings 6 and 1. This makes the network accompanied by little delay possible rather than originating in a switch matrix. Drawings 7 and 8 show the perfect intersection between perpendicular buses 2 thru/or 8 and level buses 2 thru/or 8, and a circle shows the bidirectional programmable Point of Interface controlled by the memory cell in a composition memory in there. Drawing 7 is the structure for the intersection of the perpendicular bus of an odd number, the level level bus of an odd number and the perpendicular bus of an even number, and the level bus of an even number. Drawing 8 is perpendicular and is the structure for the even number-odd number between level buses, and an odd number-even number intersection. In Drawing 7, it is understood that horizon 1 can connect with perpendicular lines 1 and 4. Horizon 2 is connectable with perpendicular lines 2 and 3. Horizon 3 is connectable with perpendicular lines 2 and 3. Horizon 4 is connectable with perpendicular lines 1 and 4. Horizon 5 thru/or 9 is combined with left-hand side 700 of a switch matrix. Right-hand side 701 of a switch matrix can give line 5, and it can connect it to perpendicular line 14. Horizon 6 output from right-hand side 7*1 of a switch matrix is connectable with perpendicular line 13. Horizon 7 from a switch matrix is combined with perpendicular line 12 via a programmable Point of Interface (P I F). Horizon 8 from switch matrix side 701 is combined with perpendicular line 11 via PIF. Horizon 9 output from right-hand side 701 of a switch matrix is combined with perpendicular line 10 via PIF. Bidirectional general interconnection segments 10 thru/or 14 of a level bus are connectable with a bidirectional general interconnection segment via PIP within perpendicular bus lines 5 thru/or 9 in the composition shown, and 10 thru/or 14. Lines 10 thru/or 13 of a level bus bidirectional segment are connectable with long lines 19.21.23 and 25 by which an odd number is not restrained via PIF so that it may be shown. level long line 15 -- what kind of -- others -- it cannot connect with a line and passes via an intersection. - by which the odd number in a level bus is not restrained -- long lines 17.19.21 and 23 are connectable with perpendicular bidirectional interconnection segments 10 thru/or 13 so that it may be shown via PIP. Each interconnection with the level bus of odd number, the perpendicular bus of an even number and odd number, or an even number is shown in Drawing 8. Like the intersection shown in Drawing 7, the horizon in the intersection structure of Drawing 8 is connectable with a perpendicular line via PIF and a switch matrix. Level long line 1 is connectable with perpendicular lines 1 and 4. Level long line 2 is connectable with perpendicular lines 2 and 3. Perpendicular long line 3 is connectable with perpendicular long lines 2 and 3. Level long line 4 is connectable with perpendicular long lines 1 and 4. level bidirectional general interconnection 5 thru/or 9 is shown in a drawing -- as -- bidirectional general interconnection 5 thru/or 14 -- and it is connectable with long lines 18.20.22 and 24 by which an even number is not restrained. Bidirectional general interconnection 10 thru/or 14 is connectable with the segment of proximity of line 10 thru/or 14 via a switching matrix in both perpendicular bidirectional general interconnection 5 thru/or 9, and perpendicular and a level bus. Long lines 16.18.20 and 22 by which the even number on a level bus is not restrained are connectable with perpendicular bidirectional segments 6 thru/or 9 so that it may be shown. Drawing 9 shows an intersection with perpendicular buses 2 thru/or 8 of an even number of level buses 1 and 9, and perpendicular buses 1 and 9. Drawing 10 shows an intersection with perpendicular buses 3 thru/or 7 of an odd number of level buses 1 and 9. In this way, level long lines 1 thru/or 4 are connectable with perpendicular long lines 1 thru/or 4 so that it may be shown. Bidirectional-boat fishing interconnection lines 5 thru/or 9 are connectable with perpendicular interconnection 5 thru/or 9 via a segment box. Bidirectional general interconnection 1o thru/or 14 is connectable with perpendicular bidirectional general interconnection 1o thru/or 14. Bidirectional general interconnection 10 thru/or 13 is connectable with long lines 19.21.23 and 25 by which an odd number is not restrained. Long lines 17.19.21 and 23 by which the odd number on a level bus is not restrained are connectable with bidirectional general interconnection segments 1o thru/or 13 so that it may be shown. In the intersection shown in Drawing 10, long Line worker on a level bus thru/or 4 are connectable with Vertical line work thru/or 4, respectively. Bidirectional general interconnection segments 5 thru/or 9 are connectable with perpendicular segment 5 thru/or long lines 18.20.22 and 24 by which it passes nine, and an even number is not restrained so that it may be shown. In level and perpendicular both, level bidirectional general interconnection segments 1o thru/or 14 are connected to a segment box. Long lines 16.18.20 and 22 by which the even number on a level bus is not restrained are connectable with perpendicular bidirectional general interconnection segments 6 thru/or 9 so that it may be shown. The intersection of an angle is shown in Drawings 11 thru/or 14. Drawing 11 shows an intersection with perpendicular bus 1 of level bus 1. Lines 1 thru/or 14 in a level bus are connectable with lines 1 thru/or 14 in a perpendicular bus, respectively so that it may be shown. Long lines 18.20.22 and 24 by which the even number on a perpendicular bus is not restrained are connectable with level bidirectional general interconnection segments 6 thru/or 9. Long lines 16.18.20 and 22 by which the even number on a level bus is not restrained are connectable with perpendicular lines 6 thru/or 9. Drawing 12 shows an intersection with perpendicular bus 9 of level bus 1. In this example, horizon 1 is connectable with perpendicular lines 1 and 4. Horizon 2 is connectable with perpendicular lines 2 and 3. Horizon 3 thru/or 14 is connectable with perpendicular lines 3 thru/or 14, respectively. Long lines 18.20.22 and 24 by which the even number on a perpendicular bus is not restrained are connectable with horizon 6 thru/or 9. Long lines 16.18.20 and 22 by which the even number on a level bus is not restrained are connectable with perpendicular lines 6 thru/or 9. Drawing 13 shows the intersection of level bus 9 and perpendicular bus 1. Horizontal line work thru/or 14 are connectable with Vertical line work thru/or 14, respectively. Horizon 3 can be connected to perpendicular line 2, and horizon 4 can be connected to perpendicular line 1. Horizon 6 thru/or 9 is connectable with long lines 18.20.22 and 24 by which the even number on a perpendicular bus is not restrained again. Long lines 16.18.20 and 22 by which the even number on a level bus is not restrained are connectable with perpendicular lines 6 thru/or 9. Drawing 4 shows an intersection with perpendicular bus 9 of level bus 9. Horizontal line work thru/or 14 are connectable with Vertical line work thru/or 14, respectively. Horizon 6 thru/or 9 is connectable with long lines 18.20.22 and 24 by which the even number on a perpendicular bus is not restrained again. Long lines 16.18.20 and 22 by which the even number on a level bus is not restrained are connectable with perpendicular lines 6 thru/or 9. the --A [ 14 ] figure shows connection of an angle and they may be used in the intersection of level bus 1, perpendicular bus 1, level bus 1, perpendicular bus 9, level bus 9, perpendicular bus 9, level bus 9, and perpendicular bus 1. It has the advantage that it is a single layout which can be used in all the four angles, and, on the other hand, attains the capability to carry out course attachment of the signal completely from long lines 1 thru/or 4 around around a chip. Horizontal line work thru/or 14 are connectable with perpendicular lines 1 thru/or 14, respectively so that I may be understood. Horizon 1 can be connected to perpendicular line 4, horizon 2 can be connected to perpendicular line 3, and horizon 3 can be connected to perpendicular line 2, and horizon 4 can be connected to perpendicular line 1. Horizon 14 can be connected to perpendicular line 5, and horizon 13 can be connected to perpendicular line 6, Horizon 12 can be connected to perpendicular line 7, and horizon 11 can be connected to perpendicular line 8, Horizon 10 can be connected to perpendicular line 9, horizon 9 can be connected to perpendicular line 10, horizon 8 can be connected to perpendicular line 11, horizon 7 can be connected to perpendicular line 12, and horizon 6 can be connected to perpendicular line 13, and horizon 5 can be connected to perpendicular line 14. Horizon 6 thru/or 9 is connectable with long lines 18.20.22 and 24 by which the even number on a perpendicular bus is not restrained. Line 16.18.20.22 with a long even number on a level bus is connectable with perpendicular lines 6 thru/or 9. In any of the intersection with which it was level and 16 and 17 on line 15 on a perpendicular bus and a perpendicular bus were explained to be above, it is not connectable. Rather, they have the special connection structure which has been designed so that it may be used for a local clock / clock activity, a large region clock, and a large region reset signal, and is shown in Drawings 15 and 16. Drawing 15 shows connection of perpendicular line 16, the large region clock on 17, and a large region reset signal. A large region clock signal is supplied to line 1501 from input buffer 1500. Line 1501 is directly connected to line 16 in all the perpendicular buses. It is similar and a large region reset signal is supplied in large region reset buffer 1502. The output of a large region reset buffer is supplied to line 17 on all the perpendicular buses on line 1503. Lines 16 and 17 of a perpendicular bus attain to the input/output block roughly shown in Drawing 15, and are directly connected to each of the logical block which can be constituted. In order to simplify a drawing, the connection with the logical block which can be constituted is directly shown only to some blocks in the upper part left-hand side angle of an array. the --A [ 15 ] figure shows connection with the logical block of lines 16 and 17 of a perpendicular bus which can be constituted. It is combined with large region clock GK of the logical block in sequence n which can be constituted, and a large region reset GR input, and lines 16 and 17 of perpendicular bus n are n= 1 thru/or 8. In perpendicular bus 9, lines 16 and 17 are connected only to an input/output block so that it may be shown. the --B [ 15 ] figure -- IOB from input/output pad -- or the course to a large region or an alternate buffer which can be constituted is shown. It is understood that pad 1510 crosses line 1511 and is connected to line 1513 via buffer 1512. It passes through line 1513 IOB input course 1515 via path transistor 1514, or line 1517 top is passed to a buffer input circuit via path transistor 1516. Memory cell 1518 in composition memory storage controls which path transistor (1514 or 1516) is activity-ized. the --C [ 15 ] figure shows the input circuit to a large region clock buffer. l0 B-2 and input ■ of 9 are connected so that a signal may be supplied on line 1518 and 1519 as an input to 8-1 multiplexer 1521. the clock input pin in l0BIIO -- as the input to multiplexer 1521 -- the -- it is connected to line 1520 as shown inB [ 15 ] figure. Lines 14 and 15 in perpendicular bus 1 and lines 14 and 15 in level bus 1 are also combined as an input to multiplexer 1521 which can be constituted. Connection output X4 on [ which can be constituted in line 1 and sequence 1 ] a logical block is directly connected directly like the input to multiplexer 1521. The link from near CLB to multiplexer, 1521 which crosses line 1524 provides the flexibility to which it was directly added for generating of the large region clock on a chip. Composition memory storage controls multiplexer 1521 to supply the clock signal to large region clock buffer 1523 on line 1521. Drawing 16 is perpendicular and shows connection of line 15 in a level bus. It is designed as a clock activity-ized signal to function the local clock for an input / output block, or the logical block that can be constituted. Line 15 in a level bus is connectable with various sources including the output from the logical block which can be constituted, and an alternate buffer. Line 15 in a level bus can be connected to level alternate A buff 71600, and it generates a signal on line 1601. Bidirectional buffers, such as buffer 1602, are each level bus and correlation. Each bidirectional buffer contains 3 state buffer which is connected to line 15 in each level bus from line 1601 and which can be constituted. 3 state buffer which is connected from line 15 on each level bus and which can be constituted supplies an output to line 1601. 3 state buffer which can be constituted is respectively controlled by a memory cell within a composition memory. Similarly, perpendicular alternate buffer 1603 generates a signal on line 1604. Line 15 on each perpendicular buffer is connected to bidirectional buffer 1605, for example, a buffer. Each bidirectional buffer has 1st 3 state buffer connected to line 15 from line 1604 in each perpendicular bus, and 3 state buffer connected to line 1605 from line 15 in each perpendicular bus. Each of 3 state buffer is controllable from the storage cell in a composition memory. Perpendicular bus 1 and line 15 in nine are connected to the input/output block on the left-hand side of a chip, and right-hand side, respectively. Similarly, level bus 1 and line 15 in nine are connected to the input/output block on the upper part of a chip, and a bottom so that it may be shown. the --A [ 16 ] figure shows the connection with line 15 of an input/output block, and connection with line 15 of the logical block which can be constituted. Each composite ten B1606 has an input to be directly connected to line 15 on the vertical or horizontal bus of proximity of that. Via PIP, each simple l0B1607 can be level, and can supply an input signal to line 15 of a perpendicular bus. the -- each logical block which is shown inA [ 16 ] figure and which can be constituted is alike, and has 1, K2, K3, and the input that was alike and was clearly shown to be 4. 1 is connected to line 15 in a level bus in the upper part of a block at an input. 2 is directly connected to line 15 in a perpendicular bus on the right of a block at an input. 3 is directly connected to line 15 in the level bus of the lower part of a block at an input. 4 is directly connected to a perpendicular bus on the left of a block at an input. Similarly, each logical block which can be constituted has outputs Y1, Y2, Y3, and Y4. Output Y1 is connectable with line 15 in the level bus above a block via PIF. Output Y2 is connectable with line 15 in a perpendicular bus on the right of a block via PIF. Output Y3 is connectable with line 15 in the level bus of the lower part of a block via PIF. Output Y4 is connectable with line 15 in a perpendicular bus on the left of a block via PIF. Line 1601 connected to line 1604 and the level alternate buffer which are connected to a perpendicular alternate buffer can receive an input from the source of a large number containing a device pin, and carries out interconnection via PIF. Although the signal on line 1601 may be supplied to all the logical blocks which can be constituted, and an input/output blocks of proximity into a level bus, the input/output block on the left-hand side of a chip and right-hand side are exceptions. Although similarly the signal on line 1604 crosses a chip and may be supplied globally, it is accompanied by the exception that it must have been directly connected to the input/output block on the top part of a chip, and a bottom. So, a signal may be generated within [ which can be constituted ] logical block RIC1, and line 15 of perpendicular bus 2 through bidirectional buffer 1608 to line 1604 is supplied. From line 1604, it can be supplied anywhere on a chip. A similar network may be formed along a level bus. the structure of this line 15 -- any register in [ which can be constituted ] a logical block -- although -- it makes it possible to receive a clock from one of five sources. large region clock GK by whom a source is given on perpendicular bus line 16, and a local clock -- 1, K2, and K3 -- and it is alike and they are connected to line 15 on four near interconnection buses including 4. Similarly, the register in compound human power / output block can receive the clock from two sources. the 1st source being line 16 in the perpendicular bus of proximity of GK Dainyuu power of that, and being dependent on the position of an input/output block -- either of the horizontal or vertical buses -- it is via PIP from connectable input K on [ which can be constituted ] I 10 blocks in upper line 15. either of the horizontal or vertical buses -- each inner line 15 can convey the signal acquired from one of four sources. Four sources are the logical blocks which gave a signal to an alternate buffer, a near logical block which can be constituted, a near input/output block, and different line 15 of a bus and which can be constituted. It is connected to level 1601 or 1604 via a bidirectional buffer in order. If it is used in order that an alternate buffer may supply a signal to an array, It may be whether it is independent about where a bidirectional buffer is constituted so that the long line linked to the buffer may give a high impedance state to a long line, or they can use an alternate buffer as a source. the --B [ 16 ] figure shows the input structure to perpendicular alternate buffer 1603. The input to perpendicular alternate buffer 1603 is supplied on line 1610 in the output of multiplexer 1611 which can be constituted. The signal on line 1610 is connected for the supply as an output signal in l0B1612 and l0B1613. the input to multiplexer 1611 -- the -- the [D / 16 / figure and ] -- oscillator signal O8C generated by the circuit shown inE [ 16 ] figure is included. The input signal from l0B1612 is an alternative input to multiplexer 1611 which crosses line 1614. a perpendicular clock input signal -- the -- it is supplied on line 1615 as an input from l0B1616 constituted as shown inB [ 15 ] figure to multiplexer 1611. Long lines 5 and 15 of perpendicular bus 9 and long lines 5 and 15 of level bus 9 are also connected as an input to multiplexer 1611. The last input to multiplexer 1611 is a link from output X2 of the logical block in line 8 which crosses line 1617, and sequence 8 which can be constituted directly. Perpendicular alternate A buff 71603 contains memory cell 1618 for 3 state control again. the --C [ 16 ] figure shows the input structure over level alternate buffer 1600. A level alternate buffer answers the signal in memory cell 1620, and three states are possible for it. The input to level alternate buffer 1600 is supplied on line 1621 in the output of multiplexer 1622 which can be constituted. the input to multiplexer 1622 which can be constituted -- the level clock input signal on line 1623 -- and the input signal on line 1624 from input/output structures 1626 and 1627 and 1625 is included, respectively. Perpendicular bus lines 5 and 15 and level bus lines 5 and 15 are connectable as an input to multiplexer 1622 similarly. Finally, the direct link from the logical block in line 8 and sequence 1 which can be constituted, and output x4 cross line 1628 as inputs to multiplexer 1622, and are combined. the on-chip oscillator which supplies the O8C signal as one input to multiplexer 1611 which drives perpendicular alternate A buff 71603 -- the -- it is shown inD [ 16 ] figure. An O8C signal is supplied in the output of multiplexer 1630, and it is controlled by memory cell 1631. As for the input to multiplexer 1630, it is supplied to the output of reversal buffer 1633 including the signal on line 1632. The input to reversal buffer 1633 is a signal on line 1634, and it is supplied in the output of oscillator amplifier 1635. The input to oscillator amplifier 1635 is supplied in l0B1636. l0B1637 is directly combined with line 1634. Line 1634 is supplied to register 1640 as a clock input on line 1639 via reversal buffer 1638. Register 1640 is connected as a dividing circuit by 2 by the joint line combined with register 1640 as a D input via reversal buffer 1642 from Q output of that. Q output of register 1640 is supplied on line 1643 as the 2nd input to multiplexer 1630. the external connection to an oscillator -- the -- it is shown inE [ 16 ] figure. As for pad 1637, line 1 is combined with 50, and pad 1636 is combined with line 1651. Resistor R1 is connected among lines 1650 and 1651. GROUND passes through line 1651 via capacitor C1, and it is combined with line 1653 via crystal 1652. GROUND passes through line 1653 via capacitor C2, and it is combined via resistor R2 to line 1650. The option of the division by two in an oscillator circuit is provided in order to ensure the symmetry of a signal. The output of 2:1 multiplexers 1630 gives this selection, and is set between equipment configurations. when an oscillator/inverter is not used, courses 1637 and 1636 are served as standard IOB -- as -- the -- as shown inB [ 15 ] figure, it can constitute. An oscillator circuit enables it to be in an active state and to become stable, before composition is completed. The structure of a programmable Point of Interface (P I F) is shown in Drawing 17, and a substitute structure is shown in Drawing 18. The structure of Drawing 17 shows that PIF is realized using a path transistor to conductive segment 1700 and 1701 which intersects long line 1702, for example, long lines. In this way, path transistor 1703 provides the interconnection between lines 1702 and 1701. Path transistor 1704 prepares the interconnection between lines 1700 and 1702. Memory cell 1705 from composition memory storage controls path transistor 1073 to establish the bidirectional course between lines. Similarly, memory cell 1706 controls path transistor 1704 to establish a bidirectional course. These Points of Interface are shown through this document using circular sign 1707 as shown in a drawing. In this way, the sign display of the circuit on the left-hand side of Drawing 17 is shown on the right-hand side of Drawing 17. In the point of providing the bidirectional connection on the line which makes big flexibility possible, the example of realization of PIF of Drawing 17 is advantageous. However, this structure is memory concentration. So, it may be used in order that the example of realization of the substitution shown in Drawing 18 may save a memory in the given example of realization. The example of realization of Drawing 18 shows that PIP may be realized as multi-sauce multiplexer 1800. Multiplexer 1800 may have three sources, source 1, source 2, and source 3, and answers memory cell 1802 in composition memory storage, and chooses destination line 1801. Two memory cells can provide selection from between three or four sources using the example of multiplexer realization. The equivalent sign to the circuit using multiplexer 1800 is shown by 1803. The example of multiplexer realization is undirectional interconnection, and although it enables connection with one destination line of the original lines from one, it should be understood that a contrary is not the same. Only one original line may be activated to given operation. Drawing 19 shows the example of realization of the switch matrix according to this invention. Each switch matrix has five connection on the bottom clearly shown to be five connection on the upper part clearly shown to be 1 thru/or 5, five connection on the right-hand side clearly shown to be 6 thru/or 10, 1 Engineering, or 15, and five connection on the left-hand side clearly shown to be 16 thru/or 20. It is [ as opposed to / line top 1 ] connectable [ line 1 / to line 20 / via P I P 1-6 ] via PIPI-20 to line 15 to line 6 via PIPI-15 via PIPI-11. Via PIF2-19, to line 19, it can pass by PIF2-7, and line 2 can pass through it line 14 by PIF2-14 to line 7, and it can connect it to line 15 by P I F2-15. Via PIF3-18, to line 18, it can pass by PIF3-8, and line 3 can pass through it line 13 by PIF3-13 to line 8, and it can connect it to line 14 by PIPI-14. Via PIF4-17, to line 17, it can pass by PIF4-9, and line 4 can pass through it line 12 by PIF4-12 to line 9, and it can connect it to line 13 by PIF4-13. Via 5-16, to line 16, it can pass by PIF5-10, and line 5 can pass through it line 11 by PIF5-11 to line 10, and it can connect it to line 12 by PIF5-12. In addition to the bidirectional connection with already described lines 1 thru/or 5, connection of lines 6 thru/or 10 contains the following. To line 15, it can pass through line 6 line 16 via PIF6-16 via PIF6-15, and can connect it to line 20 via P I F6-20. It can pass through line 7 line 14 via PIF7-14, can pass through it line 19 via PIF7-19, and can connect it to line 20 via PIF7-20. Via PIF8-13, it can pass through line 8 to line 13 line 18 by PIF8-18, and can connect it to it by PIF8-19 to line (varnish T-4 board white) 19. It can pass through line 9 line 12 via PIF9-12, can pass through it line 17 by PIF9-17, and can connect it to line 18 by PIF9-18. Via PIFIO-11, it can pass through line 10 to line 11 line 16 by PIPlo-16, and can connect it to it by PIFIO-17 to line 17. Connection of line 20 to line 15 by which other bidirectional connection which has not been described yet passes PIF20-15, Connection of line 19 to line 14 through PIF19-14, connection of line 18 to line 13 through PIPI8-13, connection of line 17 to line 12 through PIF17-12, and connection of line 16 to line 11 through PIF16-11 are included. Drawing 20 shows a re-electric power grant buffer (the repovering butler), and it is used with the level segment and perpendicular segment to each switching matrix. A re-electric power grant buffer is used in order to re-form a signal after it passes via much PIF. Each re-electric power grant buffer adds delay to the network by which course attachment is carried out. In this way, probably, the designer is going to avoid using a re-electric power grant buffer for the short network. the re-electric power grant buffer shown in Drawing 20 is connected on [ of the bidirectional-boat fishing interconnection segments shown by line X in a drawing ] one, in there, lines 5 thru/or 14 in a horizontal or vertical bus obtain X, and it is one of the - Chi. Line X goes into the left-hand side of a re-electric power grant buffer in point 2000. Point 2000 is supplied as an input to 1st 3 state buffer 2001. The output of 3 state buffer 2001 is connected to point 2002, and it returns to line X and is supplied with the output of a re-electric power grant buffer. Point 2002 is supplied to the input of 3 state buffer 2003 again. The output of 3 state buffer 2003 is connected in point 200.0 for supply of the signal in the direction of [ from the right ] the left. The 3rd course through path transistor 2004 is supplied among points 2000 and 2002. The 1st memory cell M1 and 2nd memory cell M2 control operation of a re-electric power grant buffer. The true output of memory cell M1 is given to AND gate 2005. The output of Tasuku of memory cell M2 is given as the 2nd input to AND gate 2005. The output of AND gate 2005 is 3 state activity-ized input to buffer 2003. the output by which similarly memory cell M1 was reversed -- the 1st input Hey to AND gate 2006 -- it is supplied. The 2nd input to AND Gaea 2006 is an output by which memory cell 2002 was reversed. The outputs of AND gate 2006 are 3 state control signals over buffer 2001. It is supplied in order that the true output of memory cell M2 may control path transistor 2004. In this way, supplying for re-electric power grant of the signal which the re-electric power grant buffer shown in Drawing 20 spreads in the direction of either which meets line X is understood. When similarly line X is used for two or more sauce network which a signal can spread in any direction, path transistor 2004 is enabled to bypass a re-electric power grant buffer. It should be decided that the position of the line of the re-electric power grant buffer for a given switching matrix or a segment box suits the necessity for specific application. The re-electric power grant buffer should be used for the CMO3 present art for what kind of network path which passes via the circumference of PIF beyond four or it, and does not progress via CLB or IOB. Drawing 21 shows the interconnection option for the switch matrix using the PIP array shown in Drawing 19. The drawing is graph expression which shows Connection worker through a switch matrix thru/or the possible interconnection of 20. In this way, the possible interconnection of connection 1 is shown in an upper part left-hand side angle. Similarly, the possible interconnection of connection 20 is shown in a lower part right-hand side angle. Drawing 22 shows the interconnection array for perpendicular bus 1 and the segment box on nine. A segment box is a substitute switch matrix design, and conforming for a circumference bus is understood. Each segment box has input connection of 20, and as shown in a drawing, each side Stop has five. Input connection 20 and 6 is connected directly, input connection 19 and 7 is connected, inputs 18 and 8 are connected, and inputs 17 and 9 are connected, and inputs 16 and 10 are connected. Inputs 1 and 15 are connectable with the line which connects inputs 20 and 6 via PIP. Inputs 2 and 14 are connectable with the line which connects inputs 9 and 7 via each PIF. Inputs 3 and 13 are connectable with the line which connects inputs 18 and 8 via PIP. Inputs 4 and 12 are connectable with the line which connects inputs 17 and 9 via PIP. Finally, inputs 5 and 11 are connectable with the line which connects inputs 16 and 10 via PIP. Level bus 1 and the segment box on nine are shown in Drawing 23. In this example of realization, inputs 1 and 15 are connected directly, inputs 2 and 14 are connected directly, inputs 3 and 13 are connected directly, and inputs 4 and 12 are connected directly, and inputs 5 and 11 are connected directly. Inputs 20 and 6 can be connected to the line which connects inputs 1 and 15 via PIP, and inputs 19 and 7 can be connected to the line which connects inputs 2 and 14 via PIF. Inputs 18 and 8 are connectable with the line which connects inputs 3 and 13 via PIP. Inputs 17 and 9 are connectable with the line which connects inputs 4 and 12 via PIP. Finally inputs 16 and 10 are connectable with the line which connects inputs 5 and 11 via PIP. Drawing 24 is a style of Drawing 21 and shows the possible interconnection to the segment box for each input in graph. Such possible interconnection suits equally to the segment box on a level bus as opposed to the segment box on a perpendicular bus. The fundamental interconnecting structure of the programmable gate array was explained, without emphasizing until now connection with the logical block which can be constituted, and an input/output block. Therefore, in order to explain those connection, detailed explanation of the logical block which can be constituted, and an input/output block continues. Connection with the interconnecting structure of an input / output block, and the logical block that can be constituted is then described. I I The detailed example of realization of the logical block which it can be 1. constituted and which can be logical block constituted is described with reference to Drawings 25 thru/or 44. An outline block diagram is shown in Drawing 25. Logical block 2500 which is shown in Drawing 25 and which can be constituted combines, and it receives an input from four side roughly shown by bus 2502-1.2502-2.2502-3 and 2502-4 including a function and control generator 2501. a combination function and control generator 2501 -- four -- it communicates independently with output port 2503-1.2503-2.2503-3 which can be constituted, and 2503-4. an output port combines via each bus 2504-1.2504-2.2504-3 and 2504-4 -- a function and control generator 2501 -- and a signal is received from there and a feedback signal is supplied. Each output port supplies two or more output signals, as shown in diagram in each output bus 2505-1.2505-2.2505-3 and 2505-4. The block diagram of Drawing 25 shows the symmetry of high-level logical block 2500 which can be constituted. An input signal may be received from all the four side of blocks, and an output signal may be similarly supplied to all by the side of four of a block. Since the input signal from input bus 2502 generates an output signal via bus 2505-1.2505-2.2505-3 or 2505-4 as shown below, it may be used. Similar flexibility is provided from all other input buses in [ which can be constituted ] a logical block. The input and output to the logical block which can be constituted are shown in Drawing 26. The notation for an input and an output is given. As for the input signal which meets above a bus, it is understood A.I. Artificial Intelligence thru/or Dl, EMl, ENI, FMl, FNI, G1, and that 1 is specified by that Hl reaches. Outputs are clearly shown to be Xl and Yl. It is similar, subscript 2 is given to the right-hand side of a chip, and subscript 3 is given to the bottom of a chip, and subscript 4 is given to the left-hand side of a chip. On the left-hand side of a chip, additional inputs GR and GK for large region reset and a large region clock signal are provided. As the introductory notes of Drawing 26 are shown, they are inputs A1 thru/or A4 and an input of a line with B1 thru/or B4 [ long ]. They are inputs C1 thru/or C4 and the input by which Dl thru/or B4 were combined with the bidirectional general interconnection segment for a logic signal. Inputs EMI thru/or EM4, FMI or FM4, ENI or EN4, and FNI thru/or FN4 are connection inputs directly. Inputs G1 thru/or G4, and Hl thru/or H4 are the inputs to the bidirectional-General interconnection segment for a control signal. it is an input of the long line from 1 thru/or bus line 15 by which it is alike and 4 is used for a clock and clock activity-ized function at an input. An output is supplied in terminals X1 thru/or X4, and Yl thru/or Y4. Connection structure is directly connected to Xl thru/or X4. - Boat fishing interconnecting structure is combined with outputs Y1 thru/or Y4. 64-bit RAM by which an address is carried out via the multiplexing tree in which a combination logical block is shown in Drawing 27, RAM of the additional bit of 16 by which an address is carried out via a special output multiplexer as shown in Drawing 28, It consists of multiplexing structure where it is used for a control signal since it is generating of a logic input to the multiplexing tree shown in four independent output macro cells shown in Drawings 29 thru/or 32, and Drawings 35 thru/or 44. A fundamental combination logic function is given with the multiplexing tree shown in Drawing 27. As stated above, program data is stored in composition memory 2700 of 64 A bit. The Lebel multiplexing structure divides 64-bit RAM into eight 8 A bit sections. An eight A bit each section is combined with 8:1 multiplexers, 2701-1 to 2701-8. Three common address signal vA1, VBI, [ as opposed to / 8 A bit multiplexer is combined with a pair and / multiplexer 2701-1 and 2701-2 in them ] At vCl, multiplexer 2701-3, signal VA2 to 2701-4, VB2, VO2, multiplexer 2701-5, signal VA3 to 2071-6, VB3, VO3, and the last, Multiplexer 2701-7, signal VA4 to 2701-8, VB4, and VO2 are shared. Eight independent outputs are generated by eight multiplexers [ 8:1 ]. Outputs FAI thru/or FA4 are given from multiplexer 2701-1.2701-3.2701-5 and 2701-7, respectively. Outputs FBI thru/or FB4 are supplied from multiplexer 2701-2.2701-4.2701-6 and 2701-8, respectively. A pair of output FAI/FBI is supplied to crossing multiplexer 2702-1. FA2/FB2 are supplied to crossing multiplexer 2702-2. FA3/FB3 are supplied to crossing multiplexer 2702-3. FA4-FB4 is supplied to crossing multiplexer 2702-4. Respectively, it is combined with each memory cell 2703-1 thru/or 2703-4 within a composition memory, and crossing multiplexer 2702-1 thru/or 2702-4 receive each control variable VDI thru/or VB4. Crossing multiplexer 2702-1 generates outputs FC1 and FDI. Crossing multiplexer 2702-1 generates outputs FC2 and FD2. Crossing multiplexer 2702-3 generates outputs FC3 and FD3. Crossing multiplexer 2702-4 generates outputs FC4 and FD4. If memory cell 2703-1 of crossing multiplexer 2701-1 and correlation is equal to zero, input FAI will be then connected to output PCI, and input FBI will be connected to output FDI. Any effect doesn't control variable ■D1 combined with crossing multiplexer 2702-1 have, when memory cell 2703-1 is 0? In this way, it is only that a crossing multiplexer establishes the path through course for signals FAI and FBI, and, so, outputs FC1 and FDI are two independent variables of three control signals VAI thru/or vCl. When memory cell 2703-1 is set equally to 1, control input vD1 is then activity-ized. If vDl becomes zero, input FAI will be then connected to both outputs PCI and FDI. If logic signal vD1 is [ one ] equal, input FBI will be then connected to both outputs PCI and FDI. In this way, when memory cell 2703-1 is truth, logic signal vD1 works as the 4th variable, and, so, its signal on output PCI/FDI is equal to the peculiar combination function of four variables vA1 thru/or VDI. Crossing multiplexer 2702-2 thru/or the function of 2702-4 are the same as that of it of 2702-1, if it removes that control signals VD2 thru/or VD4 are supplied independently of input multiplexing structure. Each memory cell 2703-2 thru/or 2703-4 are separately constituted between programming. Output signals PCI and Fe2 are supplied as an input to the 3rd level multiplexer 2704-1. Similarly, signals FC3 and Fe2 are supplied to the 3rd level multiplexer 2704-2. Logic signals VEI and VF6 control multiplexer 2704-1 and 2704-2, respectively. Output FE1 of multiplexer 2704-1 and FEof 2704-22 express the AND function of five variables. Signals FEI and FE2 are supplied as an input to the 4th level multiplexer 2705. Multiplexer 2705 is controlled by signal VF, and answers six variables, and generates output F. Finally, signal F is supplied to special output multiplexer 2706. The 2nd input to multiplexer 2706 is special output signal G. Multiplexer 2706 answers independent variable VG, and is controlled, and generates output signal H. Special output signal G is generated by the special output stage shown in Drawing 28. The special output stage consists of RAM2800 of 16 A bit within a composition memory. 16 A bit are combined with 16:1 multiplexers 2801. The control input to 16:1 multiplexers includes signals FDI thru/or FD4 generated by crossing multiplexer 2702-1 of Drawing 7 thru/or 2702-4. Since control signal VAI of 16 thru/or ■D1, VA2 to VD2, VA3 to VD3, and VA4 thru/or VD4 may be independently supplied by input multiplexing structure from from outside CLB, special output G expresses the large gate function of 16 variables. In this way, the function with which 16 variables were restricted can be used in G output. The logical block of this invention which can be constituted gives the capability to decode 64 states of 16 human-power variable using 64 A bit made into a cascade by 16 A bit. The output macro cell for the logical block which can be constituted is shown in Drawing 29 thru/or 32 figure. The macro cell of Drawing 29 is combined with outputs x1 and Yl of the logical block which can be constituted. The input to a macro cell contains FCl, FEl, H, and FDI. Input FC1, FEl, and H are combined with multiplexer 2900. Output DQ1 of multiplexer 2900 is supplied as a D input to register 2901. Output Q1 of register 2901 is combined with multiplexer 2902 as an input. Two additional inputs to multiplexer 2902 contain PCI and FBI. The output of multiplexer 2902 is combined with line 2903. Line 2903 supplies signal QFI as feedback on a combination function. Similarly, it is directly combined with output buffer 2904 for driving output signal X1 for direct connection. Signal 2903 is combined with multiplexer 2905 again. The 2nd input to multiplexer 2905 is signal FDI. Output TYI of multiplexer 2905 is combined to 3 state output buffer 2906. The output of buffer 2906 is Y1 signal for connection with interconnecting structure. Control signal OE 11 which occurs within [ which can be constituted ] a logical block so that 3 state buffer 2906 may be explained below; therefore, it is controlled. Register 2901 in a macro cell further has the capability by which preload is carried out between programming. this functionality -- the --A [ 29 ] figure is shown and signal DQ1 is given to multiplexer 2908 in there. The 2nd input to multiplexer 2908 is program data. Multiplexer 2908 is control signal P ROG RA M. D ON E+,: Watt control. PROGRAM When DONE is an imitation, program data is chosen to D input of register 2901, and it passes. Signal DQI is supplied in other modes. Similarly, clock operation of the register 2901 is carried out with the output of gate 2909. Gate 2909 gives OR function with the output of a frame pointer and AND gate 2910. Clock signal CK with which the input to AND gate 2910 occurred within [ which can be constituted ] the logical block, and PROGRAM The contrary of DONE is included. In this way, between programming stages, in order that a clock signal may be made impossible and a frame pointer may carry out clock operation of the register 2901 by program data, it is used. After programming is completed, a clock signal passes to register 2901 directly, and is supplied to it. In order to make a figure plain, it is not shown clearly, but the same structure is used in each of a macro cell. Drawing 30 shows the macro cell which supplies outputs X2 and Y2. - The input to macro cell 2 of Drawing 30 contains Fe2, FE2, H, and FD2. Fe2, FE2, and H are supplied via multiplexer 3000, and generate signal DQ2. DQ2 is given to register 3001. Output Q2 of register 3001 is supplied as an input to multiplexer 3002. Other inputs to multiplexer 3002 contain Fe2 and FE2. output QF2 of multiplexer 3002 -- as feedback -- line 3003 top -- and it is given directly to output buffer 3004 which supplies signal X2 to connection directly. The signal on line 3003 is supplied to multiplexer 3005 again. The 2nd input to multiplexer 3005 is signal FD2. Output TY2 of multiplexer 3005 is supplied to 3 state output buffer 3006 as an input, and it drives signal Y2. 3 state buffer 3006 is controlled by control signal OE2. The output macro cell of Drawing 31 drives signals x3 and Y3. The input of that contains signal FC3, FEI, Dl, Hl, and FD3. It is combined via multiplexer 3100 and input FC3, FEl, and Dl supply signal DQ3. Signal DQ3 is supplied to register 3101. Output Q3 of register 3101 is considered as the input to multiplexer 3102, and is supplied. Other two inputs to multiplexer 3102 contain Fe2 and H. Output QF3 of multiplexer 3102 is directly supplied as feedback on line 3103 at buffer 3104, and it drives signal X3. The signal on line 3103 is supplied to multiplexer 3105. The 2nd input to multiplexer 3105 is signal FD3. Output TY3 of multiplexer 3105 is supplied to 3 state buffer 3106 which drives signal Y3. 3 state buffer 3106 is controlled by signal OE3. The output macro cell for drive signals X4 and Y4 is shown in Drawing 32. It is similar to the macro cell of Drawing 31. An input signal contains Fe2, FE2, D2, H, and FD4. Signal FC4, FE2, and D2 are supplied via multiplexer 3200, and supply signal DQ4. Signal DQ4 is supplied via register 3101 and it generates output signal Q4. Output signal Q4 is supplied to multiplexer 3202. Other inputs to multiplexer 3202 contain Fe2 and H. The output of multiplexer 3202 is signal QF4 on line 3203, and since it is supplied as feedback and signal X4 is driven, it is combined with buffer 3204. The signal on line 3203 is supplied to multiplexer 3205 again. The 2nd input to multiplexer 3205 is signal FD4. Multiplexer 3205 generates signal TY4 and it is combined with 3 state buffer 3206. 3 state buffer 3206 is controlled by signal OE4, and drives output Y4 of the cell which can be constituted. The target of a design of a macro cell is providing each symmetrical function of a macro cell. Therefore, in order to provide bigger symmetry, macro cell 1 and macro cell 2 may be changed so that addition of input signals D3 and D4 may be enabled in input multiplexers 2900 and 3000, respectively. Capability for it to have been registered or to give signal H in one function of the combination may be made possible in each of a macro cell. The same thing is truth to signals FEI and FE2. In order to optimize Di's use in an example desirable with a deer, the macro cell shown in Drawings 29 thru/or 32 was adopted. Perfect symmetry will be acquired by transposing 3:1 multiplexers to 4:2 multiplexers in Drawing 29 thru/or 32 figure. It should note preparing to use of registers 3101 and 3201 even noting that it is not used, since they combine and the macro cell of Drawings 31 and 32 drives the output of logic. This is given by making it possible to combine input D1 and B-2 with the register in an output macro cell directly. Although not shown in Drawings 29 thru/or 32, each register includes a clock, the formation of clock activity, and reset control. Each of the multiplexer shown in a drawing is controlled by the memory cell in a composition program, unless a dynamic control signal is shown clearly. In this way, the composition of a macro cell is set up between programming of a device. Please note that each of a macro cell receives the signal and output signal H from the 2nd level of multiplexing, and the 3rd level of multiplexing. Please also note enabling a macro cell to drive from the source where output x1 differs from output Y1 simultaneously. This gives the capability to generate the output which the logical block which can be constituted goes up to 8 at a stretch. Supplied so that Yl thru/or Y4 signal may drive eight bus lines in the interconnection through PIP, those one is a long line which is not restrained. Outputs x1 thru/or x4 give a high speed signal course to the logic cell of (adjacent) and the next contiguity of contiguity in an array which can be constituted, or input/output cell. Input multiplexing for the logical block for generating of signals vA1 thru/or VA4 which can be constituted is shown in Drawing 33. The structure contains 1st 4:1 multiplexer 3300 that receives signals A1 and A2, FD2, and QF2 as an input. The output of multiplexer 3300 is supplied to 3:1 multiplexers 3301 as an input. Two additional inputs to multiplexer 3301 contain FM2 and FN2. The output of multiplexer 3301 is signal DA3 on line 3302. Other inputs to a multiplexing tree include signals C1 and QFI supplied to 2:1 multiplexers 3303. The output of 2:1 multiplexers 3303 is signal DA1 on line 3304. Inputs C1 and QFI are supplied to 2nd input multiplexer 3310 again, and it supplies output DA2 on line 3311. Input signals EMI and ENI are supplied to 2:1 multiplexers 3305. Output E1 is supplied on line 3306. Input D1 is combined with line 3307. Signal VAI is supplied in the output of 4:1 multiplexers 3308. Four inputs to multiplexer 3308 contain signal D1, El, DAI, and DA3. Signal VA2 is supplied to the output of multiplexer 3309. The input to multiplexer 3309 contains signal D1, El, DAI, and DA3. Signal VA3 is supplied to the output of multiplexer 3312. The input to multiplexer 3312 contains Dl, B3, DA2, and DA3. Finally, signal VA4 is supplied to the output of 4:1 multiplexers 3313. The input to multiplexer 3313 contains Dl, El, DA2, and DA3. All the multiplexers shown in Drawing 33 are controlled by the memory cell in a composition memory. Control signals VBI thru/or VB4 are generated in a multiplexing tree, and it is the same to the MUX tree of Drawing 33 except for the point that inputs differ. In this way, connection of a multiplexing tree is not repeated here. Rather, only an input is described. The input to a multiplexing tree contains FN3, FM3, A3, A4, FD3, QF3, C2, QF2, EM2, EN2, and B-2. therefore -- any [ of the control signal generated by the multiplexing tree of Drawing 34 ] at least one -- although -- it is chosen from one of 11 human power. It is similar and Drawings 35 and 36 show the multiplexing tree which generates control signals MCI thru/or VO2, and vDl thru/or VD4, respectively. The input to the multiplexing tree of Drawing 35 contains FN4, FM4, B1, B-2, FD4, OF4, C3, OF3, EM3, EN3, and B3. The input to the multiplexing tree of Drawing 36 contains FNl, FMl, B3, B4, FDI, QFI, C4, OF4, EM4, EN4, and B4. It is understood from reexamination of Drawings 33 thru/or 36 that control signal VAI thru/or VA4, VBI or VB4, VCI or VG4, VDI, or VD4 is generated using the input multiplexing tree which does not need common use of an input variable. Each of an output may be extracted from the independent input variable which makes possible the function of one to 16 independent variable. An input is extracted from all the four side of the logical blocks which can be constituted, and it enables symmetrical realization of the network on an array. Drawings 37, 38, and 39 show generating of control signal VEI, VF2, VF, and VG. In Drawing 37, a MUX tree reaches control signal CT1, attains to CT2, answers to input signals C1 and C3, and generates signals vE1 and VF2. VEI occurs in the output of multiplexer 3700 and it receives all the four input variable CT1, CT2, C1, and C3 as an input. Signal VE2 considers it as an input. - (generated in the output of 4:1 multiplexers 3701 which receive CT2, CT1, C1, and C3.) the [ control signals CT1 and CT2, CT3, CT4, and CT5 of Drawing 37 are explained to be below ] -- the [A / 40 / figure thru/or ] -- it is generated inE [ 40 ] figure. Signal VF occurs with the output of multiplexer 3800 shown in Drawing 38. Multiplexers 3800 are 4:1 multiplexers which receive input CT3, CT4, C2, and C4. Signal VG occurs with the output of 3:1 multiplexers 3900 shown in Drawing 39, and it receives input signal CT5, VCC, and GROUND. the -- the [A / 40 / figure thru/or ] -- 40H figure shows generating of internal control signals CT1 thru/or CT8, respectively. the --A [ 40 ] figure shows generating of signal CTI which answers inputs G1 and G2 through multiplexer 4001. the --B [ 40 ] figure shows generating of signal CT2 through multiplexer 4002 which answers input G3 and G4. the --C [ 40 ] figure shows generating of signal CT3 through multiplexer 4003 which answers inputs H1 and H2. the --D [ 40 ] figure shows generating of signal CT4 through multiplexer 4004 which answers inputs H3 and H4. the --E [ 40 ] figure shows generating of signal GT5 by multiplexer 4005 which answers inputs G1 and G2. The 40th F figure shows generating of signal CT6 by multiplexer 4006 which answers input G3 and G4. The 40thG figure shows generating of signal CT7 by multiplexer 4007 which answers inputs H1 and H2. The 40thH figure shows generating of signal CT8 by multiplexer 4008 which answers inputs H3 and H4. Drawing 41 shows generating of output activity-ized signals OE1 thru/or OF2 used in the output macro cell of Drawings 29 thru/or 32. Each of signals OE1 thru/or OF2 is independently supplied by each multiplexer 4100.4101.4102 and 4103. The input of multiplexer 4100.4101.4102 and 4103 is ■. . And the common OE control signal on line 4104 is included. The signal on line 4104 occurs in the output of 4:1 multiplexers 4105. 4:1 multiplexers 41-05 are combined with four memory cells in composition memory 4106. Multiplexer 4105 is controlled by signals CT5 and CT6. In this way, when each output activity-ized signal chooses this VCC as an output signal, it may be constituted so that it may be activity-ized statically. instead -- being alike -- it answers the common OE control signal on line 4104 -- dynamic -- activity-izing -- or it may become impossible. The further independence of a A program mink may be attained by giving the independent dynamic signal for using as formation of output activity. Drawing 42 shows generating of clock signal CK, and it is used in order to carry out clock operation of the register in an output macro cell. This signal occurs in the output of 2:1 multiplexers 4200. The input to 2:1 multiplexers 4200 contains the thing of the truth and Tasuku of a signal supplied on line 4201 in the output of 6:1 multiplexers 4202. multiplexer 4202 -- the signal from bus line 15 of 4 side Stop of a macro cell -- 1 -- or it is alike and receives input GK and control signal CT7 from 4 and a large region clock line as an input. The multiplexer of Drawing 42 is constituted by the memory cell in a composition memory. Drawing 43 shows generating of the clock activity-ized signal combined with the register in an output macro cell. A clock activity-ized signal occurs in the output of multiplexer 4300. As for it, the input to multiplexer 4300 is supplied in the output of 3:1 multiplexers 4302 including the signal on line 4301. The 2nd input to multiplexer 4300 is vo. It is a signal. In this way, a clock activity-ized signal may be permanently activity-ized by connection with VCC. the input to multiplexer 4302 is boiled and contains one signal, K2 signal, and control signal CT7. Drawing 44 shows generating of reset signal R3T supplied to the register in the output macro cell in [ which can be constituted ] a logic cell. A reset signal is generated in the output of OR gate 4400. As for the input to OR gate 4400, it occurs in the output of multiplexer 4402 including the signal on line 4401. Other inputs to OR gate 4400 are large region reset signals GR. Two inputs to multiplexer 4402 contain CT8 and GROUND. In this way, reset signal CT8 may be eternally controlled by connection with GROUND. Large region reset is always permitted. In this way, the logical block which was explained above and which can be constituted prepares the symmetrical interface of all the 4 side Stop of the block to interconnecting structure. Large gating and a narrow gating function are enabled, without suffering the speed disadvantage to a narrow gate function. A large gate function does not need common use of the input signal which complicates the logic design which uses the logical block which can be constituted. ■ An input/output block The composition good Yoshihito power / output block in the programmable gate array of this invention consist of a compound block shown in the simple block shown in Drawing 45, and Drawing 46. Everybody power / output block (IOB) is combined with the memory cell in a composition memory, and the state of that controls the composition of IOB. - IOB makes [ data ] it possible to pass from (i i) programmable general connection and specific CLB to a pad from two directions, i.e., (i) input / output pad, to programmable general connection and specific CLB at boat fishing. The composition of IOB sets up the model of conditioning of a signal received by passage through IOB. A pad does not have to be carried out even if a bond is carried out to a physical package pin. IOB of two models is in a device. Simple IOB shown in Drawing 45 combines, and has only an input and an output. In addition to the combination feature, Composite work alumnus by whom it is shown in Drawing 46 has an input register / latch, and an output register. in order that composite IOB may give user input register reading return in a package pin again -- an internal link -- and it has directly a link of the proximity which makes it possible to transmit data to the register of proximity IOB compound [ IOB ]. there is more Silicon die than the IOB pad on Gui -- also depending -- note that it may be put in in the package which has few or same number of package pins. If there are package pins fewer than an IOB pad, IOB of some then does not need to be linked to a device package pin, and, so, it will be set to embedded ■alumnus for internal apparatus use. Simple IOB on given realization proportionality and a number compound [ IOB ] may originate and change to restraint of Di's size and speed so that it may be suitable for the necessity for a specific user. furthermore -- supposing it is a request -- PGA -- all -- simple IOB -- or composite IOB may also be included altogether. Drawing 45 shows the desirable example of realization of simple IOB. IOB provides the interconnection which can be constituted between input/output pad 4500 and interconnecting structure. Interconnecting structure supplies an output signal as an input to multiplexer 4501. IOB supplies input signal I to an interconnection bus in the output on line 4503 of buffer 4502. Input signal DI is combined with the near logical block which can be constituted in the output on line 4505 of buffer 4504. The specific input to multiplexer 4501 is described below. Each IOB has at least one input supplied from the long line on a bus, and it is perpendicular to the chip side with which IOB is placed on That '. It attains to the bidirectional-boat fishing interconnection line on the bus which runs in parallel to a flank, and is connected to the long line on a bus parallel to a flank which is not restrained. IOB has two connection inputs directly again. The output of multiplexer 4501 is supplied to 3 state buffer 4506. 3 state buffer 4506 has slew-rate control circuit 4507 which is common knowledge in the art concerned. Buffer 4506 is controlled by 3 state output signal TO on line 4508. 3 state output signal TO is supplied to the output of multiplexer 4509. The inputs to multiplexer 4509 are a thing of the truth and Tasuku of signal OEM supplied as power supply V0 * and a control input from the interconnecting structure to IOB, and GROUND. When activity-ized, pin output signal PO crosses line 4510, and is supplied to output pad 4500. Passive pull-up circuit 4511 constituted by answering program data via transistor 4512 is similarly combined with line 4510. Pull-up resistor 4513 is combined with vcc from the output of transistor 4512. The input from IO pad 4500 is supplied via buffer 4514. Output PI of buffer 4514 is in output buffer 4504, and is supplied on line 4515 as an input to output buffer 4502. Output buffer 4502 is 3 state buffer controlled by 3 state input signal TI on line 4516. 3 state input signal TI on line 4516 occurs in the output of multiplexer 4517. The inputs to multiplexer 4517 are a thing of the truth and Tasuku of Vcc and control signal IEN supplied as an input to IO block, and GROUND. Multiplexer 4501.4509 and 4517 are respectively controlled by the memory cell in a composition memory. The signal supplied as an input to buffer 4514 is extracted from three sources, and they are high level made by output PO1 of the output buffer on the package pin combined with IO pad, and line 4510, or the passive pull-up circuit. Multiplexer 4517 generates the TI signal from four sources. ■ . . When Is selected(ing), buffer 4502 is activity-ized permanently. When GROUND is chosen, buffer 4502 is permanently made impossible, it does not switch between operations of a programmable gate array, but it can cause useless current Dorain. When it is constituted so that multiplexer 4517 may choose an IEN signal in either of the forms of the truth or Supplement of that, buffer 4502 is controlled dynamically. In a desirable system, multiplexer 4501 has six inputs. Two of inputs come as direct connection from the nearby logical block which can be constituted, and a residual thing comes from programmable-boat fishing interconnecting structure. Output activity-ization TO on line 4508 is V. . It comes from OEN or GROUND. vo. When Is selected(ing), buffer 4506 is activity-ized permanently. When GROUND is chosen, buffer 4506 is permanently made impossible. In either of the forms of the truth or Supplement of that, when OEN is chosen, buffer 4506 is controlled dynamically. Passive pull-up 4511 to output link 4510 is controlled by memory cell 4511. When activity-ized, it ensures that a pad or a package pin does not float when it is not used in application. Drawing 46 shows composite IOB. Composite IOB crosses lines 4601 and 4602 from IO pad 4600 to interconnection, and establishes the data path from the interconnection combined with input multiplexer 4603 to IO pad 4600 which can be constituted. In addition, it is combined with a front clock and composite IOB of proximity of the circumference of the contrary, and IOB receives input signals QPI and QP2 in lines 4604 and 4605. IOB is supplied to composite IOB of the proximity of the following clockwise rotation by signals Q1 and Q2 on line 4606 and 4607 as an output. As for an input course, it is connected from IO pad 4600 as an input to input buffer 4609 including line 4608. An input buffer drives signal PI on line 4610. Signal PI is combined as an input to multiplexer 4611. The 2nd input to multiplexer 4611 is output 4612 of multiplexer 4613. The input to multiplexer 4613 includes signals QPI and QP2. Multiplexer 4611 answers signal SL1, is controlled and supplies signal D1 on line 4614. Signal D1 is supplied to the data input of an input register / latch 4615. Clock operation of a register / the latch 4615 is carried out by output 4616 of multiplexer 4617. As for the input to multiplexer 4617, they are supplied to control signal GK as an input to IOB including CEN. In a register/latch, it receives GR signal including large region reset human power 4618 further, and it is an input to JOB. Clock activity-ized input signal LHI is supplied to a register / latch 4615 on line 4619. This signal LHI is supplied to the output of multiplexer 4620. The inputs to multiplexer 4620 are a CEN signal and vo. including. Output Q1 of a register / latch 4615 is supplied on line 4621 as an input to multiplexer 4622, and is supplied as Q1 output signal and an input to multiplexer 4640 on line 4606 as an input to multiplexer 4623. The 2nd input to multiplexer 4622 is PI time signal is there on line 4610. The 3rd input to multiplexer 4622 is an output of the output register on line 4624 explained below. The output of multiplexer 4622 is supplied to line 4625. Line 4625 is combined as an input to buffer 4627 which is 3 state buffer which drives connection with a long line on line 4601 as an input to buffer 4626 which drives line 4602 to connection directly. Buffer 4627 is controlled by 3 state input signal on line 4628. The signal on line 4628 is supplied in the output of 4:1 multiplexers 4629. The input to 4:1 multiplexers 4629 contains truth, and Tasuku's formal IENl and GROUND of a vcc signal and that. It is connected so that the output course through composite IOB may receive signal O on line 4630 in the output of multiplexer 4603. Signal O on line 4630 is supplied as the 2nd input to multiplexer 4623. The output of multiplexer 4623 is supplied as an input to multiplexer 4631. The 2nd input to multiplexer 4631 is supplied in the output of multiplexer 4632. The input to multiplexer 4632 is QPI and QP2 signal. The output of multiplexer 4631 is D2 signal on line 4633. D2 signal is combined as data input to output register 4634. Output register 4634 is combined on line 4635 to large region reset signal GR. Clock operation of it is carried out by 2 at the signal on line 4636, and it occurs in the output of multiplexer 4637. The input to multiplexer 4637 includes a signal and a CEN signal in large region clock GK. Clock activity-ized signal LH2 is supplied to register 4634 on line 4638. The source of signal LH2 on line 4638 is multiplexer 4639, and it receives a CEN signal and VCC as an input. The output of register 4634 is supplied to line 4607, and it drives output Q2, and line 4624 is supplied, and it is combined as an input to multiplexer 4622 as the 1st input to multiplexer 4640. The 2nd input to multiplexer 4640 is output Q1 of the register / latch 4615 on line 4621. The 3rd input to multiplexer 4640 is signal O on line 4630. The output of multiplexer 4640 is pin output signal PO on line 4641. It is supplied to IO pad 4600 via 3 state output buffer 4642. 3 state buffer includes slew-rate control circuit 4643 which is common knowledge with the art concerned. Path transistor 4644 and resistor 4645 establish the pull-up course to VCC in the output of buffer 4642. This pull-up course answers passive pull-up circuit 4646, and is activity-ized, and it is realized by the composition memory cell. 3 state buffer 4642 is controlled by 3 state output signal TO on line 4647. A signal is generated in the output of multiplexer 4648 and it receives four inputs. The input is ■. The thing of the truth and Tasuku of CXGROUND and signal OEN is included. GK and GR are supplied to a control signal directly from interconnecting structure. Control signals IEN, CEN, and OEN are supplied in each multiplexer 4650.4651 and the output of 4652, and those each receives two inputs from general interconnection. The signal on IEN gives the capability for the dynamic control of the input course through buffer 4627. The signal on OEN gives the capability for the dynamic control of the output course through output buffer 4642. Signal CEN may be used as a clock activity-ized signal as a clock. Signals SLI and SL2 are extracted in the output of 3; 1 multiplexers 4653 and 4654. Two of the inputs to multiplexers 4653 and 4654 are extracted from interconnecting structure so that it may be stated below, and the 3rd thing is combined with grounding. Signal SLI makes it possible to be loaded by data from either the clock of a pad or proximity of the input register of IOB or composite IOB of the circumference of the contrary via QPl or QP2. Signal SL2 makes it possible to load the data through QPl or QP2 from the clock of the output of MUX4623, or the next proximity, and either of the circumference IOB(s) of the contrary to the output register of IOB. An input register / latch 4615 may be constituted so that the memory cell in a composition memory may be answered and it may operate by either as a latch or a register. When the element operates as a register, the data in Input is transmitted to the clock signal on line 4616 on the standup edge of 1 at output Q. When the element operates as a latch, any data change by D is looked at by the signal by Q between highs [ 1 ]. When K1 returns to a low state, output Q is frozen by the present state of that, and doesn't any change on D influence the state of Q? Slew-rate control circuit 4643 enables an output to have either of the early or late standup time according to the state of the memory cell which controls the function. Each of the multiplexer shown in Drawing 46 is controlled by the memory cell (one or more) in a composition memory except for multiplexers 4631 and 4611. These two multiplexers are controlled by signals SLI and SL2. In operation, an input course receives the signal from pad 4600 on line 4608, and passes it via buffer 4609, and generates signal PI on line 4610. Signal PI is supplied as an input to register load multiplexer 4611, and it is controlled by control signal SLI. The 2nd input to multiplexer 4611 is extracted from the output of multiplexer 4613, and it enables supply of the signal from either the input register of proximity of the circumference of the contrary a front clock and compound [ IOB ], or an output register. When signal SLI is connected to neither of the lines in a circuit, it enables signal PI to default in the low state and to pass. Output D1 of multiplexer 4611 is data input to input memory element 4615. In this way, the sauce of the data in an input storage cell is either an input of IO pad and output buffer °4642, the high state generated by passive pull-up circuit 4646, or proximity compound [ IOB ], or an output register. The contents of an input register/the latch may be frozen by (assthetart) what signal LHI is asserted for. As for an input course, it drives output buffers 4627 and 4626 again including multiplexer 4622. The input to multiplexer 4622 includes signal PI from line 4610, signal Q1 in the output of storage cell 4615, and signal Q2 in the output of output register 4634. In this way, the input signal to interconnecting structure may be extracted from the combination signal on an input register and line PI, or an output register. This was extracted from IO pad, and the register was carried out, or it makes the option for the signal of combination possible. It makes possible the output signal which synchronized again, and it may be extracted by driving the signal which crosses line 4624 via output register 4634 from input register output Q1, and returns to input drive multiplexer 4622. Input register 4615Q1 output can be used as an input to 3:1 multiplexers 4640 again, and it drives signal PO. This makes read return of an input signal easy as a part of user application. In order to make a synchronous course, it passes through signal Q1 in the output of an input register 2:1 multiplexer 4623, and it is combined as an input to output pin Q1 for the combination to composite IOB of the clockwise rotation of the next proximity. Operation of an output course is similar to it of an input course. Signal 0 on line 4630 extracted from multiplexer 4603 comes from the programmable-boat fishing interconnecting structure for carrying out course attachment from near CLB to pad 4600. The input to an output register may be extracted from the output or signal O of input register Q1 on [ signals QPI and QP2 from a near clock and composite IOB of the circumference of the contrary to ] line 4621 via the multiplexing tree which consists of 4623 and 4631. It may be extracted from either from line 4630 which signal PO supplied to output buffer 4642 combines an output signal from output Q2 of output register 4634, output Q1 of input register 4615, or the output of multiplexer 4603, and supplies signal 0. The contents of the output register may be frozen by asserting signal LH2 on line 4638. Output buffer 4642 crosses line 4608 and drives both pad 4600 and an input circuit. In this way, IOB may be used as an embedded structure, when the bond of the pad is not carried out to a physical package pin. Drawings 47 and 48 show the input and output of composite and simple IOB, respectively. These drawings may be referred to when re-investigating the interconnecting structure explained in the following sections. In Drawing 47, signal DI corresponds to the signal on line 4602 in Drawing 46. Signal I is equivalent to the signal on line 4601 of Drawing 46. Signal O corresponds to the output of multiplexer 4603. Other specified signals may be clearly connected with the signal given in Drawing 46 mutually. Similarly, in Drawing 48, signal DI is a signal supplied on line 4505. Signal l is a signal supplied on line 4503. Signal 0 corresponds to the output of multiplexer 4501. IEN and an OEN signal are input control signals clearly shown in Drawing 45. Drawing 49 shows notionally link QPI during composite IOB, Q2, Ql, and operation of Q2. In a programmable gate array, IOB is arranged at the surroundings around a device. They are combined so that the direction of clockwise data flow may be made possible, and so, inputs QPI and QP2 are combined with outputs Q1 and Q2 of the circumference of the contrary the clock of the next proximity, and compound [ IOH ]. Outputs Q1 and Q2 are combined as inputs QPI and QP2 of the following proximity clockwise rotation compound [ IOB ]. In this mode, it may be connected to a string and both composites IOB enable realization of a structure similar to a shift register or it. This may increase use of the logic provided in composite IOB, and it may not be used in given application in other modes. V Connection of the interconnecting structure to CLB and IOB Both the interconnecting structure that can be constituted establishes a means to connect CLB and IOB. It is divided into two main categories and they are called connection and directly programmable general-connection. Programmable general connection contains a long line, bidirectional-boat fishing interconnection, and the long line that is not restrained. The programmed connection which is between blocks and is needed for a user's application is called a network. A network may have a single or multiple source and single or multiple destination. The model of the interconnection resources used in order to make a network is decided from the availability over the propagation delay by which software course material is permitted to an algorithm and a network. The propagation delay permitted is prescribed by a user's application. Connection structure is directly shown in the 1st in Drawings 50 thru/or 55. Drawings 50 and 51 are combined and all the connection supplied as inputs EMI thru/or EM4, ENl or EN4 supplied from outputs X1 thru/or X4 of CLB of the eight neighborhoods, FMI or FM4, and FNl thru/or FN4 is shown directly. In Drawing 50, the following inputs FMI thru/or FM4 of near CLB and connection of FNI thru/or FN4 are shown. In this way, connection x4 from CLB of i-2 rows of lines j is combined with input FNI of CLB of line i in sequence j. Output X2 of CLH of line i-2 in sequence j is combined with input FM3. Output X1 of CLB of line i and sequence j+2 is combined with input FN2. Output x3 of CLB of line i sequence j+2 is combined with input FM4. Output X4 of CLB of line i+2 in sequence j is combined with input FMI of center CLB. Output X2 of line i+2 and sequence j is combined with input FN3 of center CLB. Output X3 of CLB of line i and sequence j-2 is combined with input FN4. Output X1 of CLB of line i in sequence j-2 is combined with input FM2. As shown in Drawing 51, output X4 of CLB in line i-1 and sequence j is combined with input ENI of center CLB in line i and sequence j. Output X2 of CLB in line i-1 and sequence j is combined with input EM3 in center CLB. Output X1 of CLB in line i and sequence j+1 is combined input EN2 of center CLB. Output X3 of CLB in line i sequence j+1 is combined with input EM4. Output x2 of CLB in line i+1 and sequence j is combined with input EN3. Output X4 of CLB in line i+1 in sequence J is combined with input EMI. Output X3 of CLB in line i and sequence j-1 is combined with input EN4. Output X1 in CLB in j-11 rows of line 1 is combined with input EM2. The structure shown in Drawings 50 and 51 should note that it is shown that CLB in the center of an array is directly combined with eight neighborhoods CLB. The interconnection permits the direction of the data flow in what kind of direction which passes the connection structure between CLB(s) directly. As for line i-1. sequence j+1; line i+1, sequence j+1; line i-1, sequence j-1;, and i+1 row of lines, in the system of the substitution which has CLB of the eight neighborhoods, CLB of j-1 may be connected instead of CLB besides four shown in Drawings 50 and 51. This gives the interconnection course of the diagonal which passes a device to the thing of the eight neighborhoods. However, bringing about the speed that whose the capability to cross the line or sequence accompanied by direct connection structure crosses a device, and it transmits a signal it improved was found out. Drawing 52 shows connection of outputs x1 thru/or X4 on center CLB in line i sequence j to CLB of the eight neighborhoods. Output X4 of central CLB is connected to CL of input ENI; of CLB in input FMI of CLB in line i-2 and sequence j, input EMI of CLB in line i-1; sequence j, line i+1, and sequence j, line i+2, and sequence j, and input FNI in B. output X1 -- the input of CLB in j-11 rows of line 2 -- input EM2 in CLB in j+11 rows of input EN2; line of CLB in FN2 and j-11 rows of line 1 1 ; And it is combined with input FM2 in CLB in j+11 rows of line 2. Output X2 is combined with inputs FN3 and EN3 in each CLB in line i-2, i-1, and sequence j and line i+1, i+2, input EM3 in CLB of sequence j, and F1a, respectively. Finally, output x3 is combined [ at inputs FM4 and EM4 of CLB in line i sequence j-2 and j-1 ] to inputs EN4 and FN4 in CLB in each, line i sequence j+1, and j+2, respectively. The connection on circumference CLB which includes connection with IOB directly is directly shown in Drawings 53 thru/or 55. The sequences of circumference CLH which it has IOB along the left-hand side of a drawing, and a drawing is shown, and is so shown are sequences 1 and 2. however, the connection -- not sequences 1 and 2 but lines 1 and 2, and not sequences 1 and 2 but sequences 7 and 8, and sequences 1 and 2 -- Then. (it suits similarly to structure with circumference CLB on line 7 and 8.) Connection merely rotates in a suitable place. Connection of CLB in an angle is not shown. These CLB(s) originate in the network concentrated in those angles, and may be connected to various composition. The specific connection with CLB of an angle and IOB on the array of circumference CLB of everything but all is directly shown in the 1st table. (Bottom of varnish all white) 1st Table Pad CLB From a number To a position From IOB (DI) To CLB From CLB To IOB IC2 2C2 FNI F1a IC2 2C2 ICI M3 2CI M3 IC3 2C3 IC1 FNI F1a 2CI IC3 2C3 FNI F1a ICI NI 2CI N1 IC3 2C3 IC2 M3 2C2 M3 IC4 2C4 RIC4 NI M3 2C4 IC4 2C4 IC5 2C5 IC5 NI M3 2C5 IC5 2C5 IC6 2C6 IC8 NI M3 2C8 IC8 2C8 IC8 IC7 IC8 IC7 N2 M4 IC8 IC7 2C8 2C7 IC6 2C6 NI M3 IC6 2C6 IC7 2C7 IC7 2C7 NI M3 IC7 2C7 IC8 2C8 2C8 2C7 N2 M4 2C8 2C7 3C8 3C7 3C8 3C7 N2 M4 3C8 3C7 4C8 4C7 R4C8 4C7 N2 M4 4C8 4C7 SC8 5C7 5C8 N2 M4 5C7 5C8 5C7 6C8 6C7 8C8 8C7 N2 M4 8C8 8C7 8C8 7C8 8C8 MI N3 7C8 8C8 7C8 8C7 7C7 6C8 6C7 N2 M4 6C8 6C7 7C8 7C7 7C8 7C7 N2 M4 7C8 7C7 8C8 8C7 8C7 7C7 MI N3 8C7 7C7 8C6 7C6 8C6 7C6 MI N3 8C6 7C6 8C5 7C5 R8C5 MI N3 7C5 6g 8C5 7C5 8C4 7C4 8C4 MI N3 7C4 8C4 7C4 8C3 7C3 8CI 7C1 MI N3 8CI 7C1 llCl 8C2 8C1 M2 N4 8C2 8C1 8C2 7C1 7C2 8C3 7C3 MI N3 8C3 7C3 8C2 7C2 8C2 7C2 MI N3 8C2 7C2 8CI 7C1 7CI 7C2 M2 N4 7CI 7C2 6CI 6C2 z 6CI 6C2 M2 N4 l1CI 6C2 5CI 5C2 R5C1 FM2 FM4 5C2 3CI 3C2 FM2 FM4 5C1 N4 5C2 N4 3CI 3C2 4C1 FM2 4C2 FM2 2CI 2C2 4C1 FM2 FM4 4C2 2CI 2C2 FM2 FM4 4C1 4C2 2CI 2C2 Q2 3C1 3C2 FM2 FM2 RICI IC2 G9 RICI FM2 FM4 IC2 11Q RICI R84X1RIC2FM4 Drawing 53 of Xi shows connection of sequence i CLB of one line, and i"is between 6 as 3. Connection of CLB of sequence i of two lines is also shown. In this way, output x1 of CLB in sequence i of one line is directly combined with composite IOB of the proximity clearly shown to be R11. Please note that the group division of the IOB in [ which can be constituted ] a gate array of this invention is carried out for every line of an array, or sequence at three blocks. In this way, they are three IOB(s) as shown in Drawing 53 to line i. There are Ril, Ri2, and Ri3. R11 and Ri3 are composites IOB, and, on the other hand, Ri2 is simple IOB. Each has a multiplexer which receives two or more signals for the supply as an output signal to a mutually related pin. These inputs are shown by reference O. CLB Output x1 in ClR1 is IOB. To the output in R11, it is CLB. It passes in C2R1 input EM2, and is CLB. It is combined directly input FM2 in C3Ri. CLB Output X2 of ClR1 is combined directly to inputs FN3 and FM3 of CLB in sequence [ of one line ] R1-2, and i-1, respectively. Output X2 is combined directly to inputs EM3 and FM3 in sequence Ri+l of one line and, and CLB in Ri+2, respectively. CLB Output X3 of ClR1 is composite IOB. It passes in IC3 terminal 0, and is CLB. It is directly connected to C2R1, FM4 of C3Ri, and FN4 human power, respectively. CLB CIRi (7) output x4 is simple IOB. They are direct and CLB to a Ri 2(7) O terminal. It is combined directly to FMI and EMI of ClR1-2 and ClR1-1, respectively. CLB As for the sequence of one line, output X4 of ClR1 is combined directly to ENI and the FNI input of CLB in i+1 and i+2, respectively. CLB output X1 in C2R1 -- O terminal of compound l0BRil -- and CLB It is combined directly to EN2 terminal of CIRt. Output X1 is combined to EM2 of CLBC3Ri and C4R1, and FM2 human power again, respectively. CLB Output X2 of C2R1 is CLB. It is directly combined with inputs FN3 and EN3 of C2Ri-2 and C2Ri-1. Output X2 of C2R1 is CLB again. It is combined with 2M3 of C2R1+1 and C2R1+2, and FM3 human power. CLB output X3 of C2R1 -- composite IOB O terminal of R13 -- CLB EM4 human power of ClR1 -- CLB EN4 human power of C3Rf -- and it is combined directly input FN4 of CLBC4Ri. CLB Output terminal X4 of C2R1 is CLB. It is directly connected to inputs FMI and EMl of C2Ri-2 and C2Ri-1. Output X4 is CLB again. It is combined to inputs EN1 and FNI of C2R1+1 and C2R1+2, respectively. In addition, CLB Output X4 of C2R1 is simple IOB. It is directly connected to zero terminal of Ri2. CLB Inputs EMI thru/or EM4 of ClR1, and ENI thru/or EN4 are shown in Drawing 54. Terminal EMI is CLB. It is combined so that output X4 of ClR1+1 may be received. It is combined so that input ENI may receive output x4 of CLBCIRi-1. Input EM2 is composite IOB. It is combined so that an input may be received from Ri3. Input EN2 is combined so that output X1 of CLBC2Ri may be received. Input EM3 is CLB. It is combined so that output X2 of ClR1-1 may be received. Input EN3 is combined so that output X2 of CLBCIRi+1 may be received. Input EM4 is CLB. It is combined so that output X3 of C2R1 may be received. Input EN4 is composite IOB. It is combined so that the input from Ril may be received. In Drawing 55, it is CLB. FMI [ of ClR1 and C2R1 ] FM4 and FNI thru/or FN4 human power is shown. CLB Output X4 of ClR1-2 and C2Ri-2 is CLB. It is connected to FN1 human power of ClR1 and C2R1, respectively. CLB ClR1-2 and C2Ri-2(7) output x2 is CLB. It is directly connected to input FM3 of ClR1 and C2R1. CLB Output X1 of C3Ri and C4R1 is CLB. It is directly connected to FN2 human power of ClR1 and C2R1, respectively. CLB Output X3 of C3Ri and C4R1 is directly connected to four FM mosquito of ClR1 and C2Ri. CLB Output X2 of ClR1+2 and C2R1+2 is CLB. It is directly connected to FN3 human power of ClR1 and C2R1, respectively. CLB Output X4 of ClR1+2 and C2R1+2 is directly connected to CLBCIRt and FM1 input of C2R1, respectively. Composite 10B Terminal DI of Rtl is CLB. It is combined directly to four FN(s) mosquito of C2R1. Input DI received from simple IO and BRi2 is CLB. It is directly combined with FN4 human power of ClR1, and FM2 human power. To the last, it is composite IOB. Input signal DI extracted from Ri3 is CLB. It is directly combined with FM2 human power of C2R1. Programmable general connection is shown in Drawings 56 thru/or 70. It provides the means for carrying out course attachment of the network around a device. CLB and IOB are linked by programmable Point-of-Interface PIF via this network. Programmable general connection is subdivided by a long line and bidirectional-boat fishing interconnection BGI, They are lines which incorporate the metal segment concerning one or two CLB(s), and as usually explained above with reference to Drawings 4 thru/or 24, they serve as a termination in a switching matrix or a segment box. Selection of those connections with the input and output of the position of PIF and the logical block which can be constituted is a problem of design selection. The desirable example of realization is shown as follows. Drawing 56 shows programmable connection of outputs Y1 thru/or Y4 to a long line and BGI. It is connected to the long line which is not restrained as outputs Y1 thru/or Y4 are shown in Drawing 58 again. Outputs differ into perpendicular bus 1, level bus 1, perpendicular bus 9, and level bus 9, and are combined with them, it is shown in Drawing 59, and it is related to long lines 1 thru/or 4 in each bus. PIF of lines 3.4 and 15 with long Drawing 56, and correlation -- and HBUS It is shown that output Y1 is combined BGI5.9.13 in i and 14. CLB (output Y2 of tRi -- VBUS i+1 -- combined long line 1, 2 and 15, BGI5.7.11, and 14.) output Y3 of C1R1 -- HBUS'i+1 -- long lines 1.2 and 15 and BGI lines 5.8.12 and 14 -- joint Sarel. output Y4 of C1R1 -- VBUS i -- long lines 3.4 and 15 -- and it is combined BGI5.6.10 and 14. The input of C1 thru/or C4, and Dl thru/or D4 is also shown in Drawing 56. In a desirable system, these inputs are combined as undirectional PIF using 4-1 multiplexer, in order to save a memory. Bidirection PIP may be used if it is a request. Input C1 is HBUS. It is combined with BGI7.9.11 on i, and 13. Input D1 is combined BGI6.8.10 on HBUSi, and 12. Input C2 is VBUS. It is combined to BGI of i+1 lines 6.8.10 and 12, and, on the other hand, input D2 is VBUS. i+I It is combined BGI7.9.11 and 13. Input C3 is HBUS. It is combined with i+IBGI6.8.10 and 12. Input D3 is on [ I ] HBUSi. It is combined with BGI7.9.11 and 13. Input C4G;! VBUS i It is combined with BGI7.9.11 and 13. Input D4 is VBUSi. It is combined with BGI6.8.10 and 12. Drawing 57 is CLB from a near bus. The input fixed from the long line of C1R1 and BGI is shown. HBUS To i, long line 4 is combined with input A1, long line 3 is combined with input B1, BGI5 is combined with input G1, BGI14 is combined with input H1, and long line 15 is combined with an input by 1. VBUS To i+1, long line 1 is combined with input A2, long line 2 is combined with input B-2, BGI5 is combined with input G2, BGI14 is combined with input H2, and long line 15 is combined with an input by 2. HBUS To i+1, long line 1 is combined with input A3, long line 2 is combined with input B3, BGI5 is combined with input G3, BGI14 is combined with input H3, and long line 15 is combined with an input by 3. VBUS To i, long line 4 is combined with input A4, long line 3 is combined with input B4, BGI5 is combined with input G4, BGI14 is combined with input H4, long line 15 is combined with an input by 4, long line 16 is combined with input GK, and long line 17 is combined with input GH. Connection of the logical block to the long line which is not restrained which can be constituted is shown in Drawing 58. (Each CLB, for example, CLB, R3C4 has outputs Y1 thru/or Y4 respectively combined with one long line which is not restrained.) It is because the connection is not described, because they are shown in Drawing 58. In Drawing 58, it is because only lines 18 thru/or 25 of a perpendicular bus and lines 16 thru/or 23 of a level bus are shown, because these are the only long lines which are not restrained. It is CLB in order to show the example for reading Drawing 58. R3C4 output Y1 is combined with long line 21 by which HBUS3 is not restrained. Output Y2 of R3C4 is combined with long line 23 by which "v'BUs5 are not restrained. Output Y3 is combined with long line 21 by which HBUS4 is not restrained. Output Y4 is combined with long line 23 by which VBUS4 is not restrained. Please note that the long line which is not restrained does not have the programmable connection with the input of CLB. Selection of connection of the output of the long line which is not restrained was performed in order to attain the distributed uniform pattern which makes programming of the network through an array easy. Drawing 59 shows connection of long lines 1 thru/or 4 in HBUSl, VBUSl, VBUS9, and HBUS9. Drawings are HBUSl of VBUS9, and HBUS9.l! Use of the intersection of the angle of : (7) and VBUSl(7) HBUS 1, and HBUS9 is shown, and they enable the propagation which turns around the chip of the signal supplied to any at least one of the long lines of the four outsides all the time. This makes easy use of the single signal as a control input to all the IOB(s) Desire. output Y1 of CLB in line 1 -- all -- HBUSl -- being connected to long lines 1.3 and 4 -- as an exception -- RIC8Y1 output -- HBUSl -- it is combined with long lines 2.3 and 4. output Y2 of CLB in line 1 -- RIC8 -- as an exception -- all -- HBUSl -- it is connected to long line 2. RIC8Y4 output -- HBUSl -- it is combined with long line 1. removing R8C8 -- Y2 output of all the CLB(s) in sequence 8 -- VBUS9 -- it is combined with long lines 1.2 and 4. making C8R8 into an exception -- Y3 output of all the CLB(s) in sequence 8 -- VBUS9 -- it is combined with long line 3. Ceight R8Y1 output -- VBUS9 -- it is combined with long line 4. CLB Ceight R8Y2 output -- VBUS9 -- it is combined with long lines 1.2 and 3. making ClR8 into an exception -- Y3 output of all the CLB(s) in line 8 -- HBUS9 -- it is combined with long lines 1.2 and 4. making ClR8 into an exception -- Y4 output of CLB in line 8 -- HBUS9 -- it is combined with long line 3. ClR8Y2 output is combined with long line 4 of HBUS9. ClR8Y3 output is combined with long lines 1.2 and 3 of HBUS9. making CIRI into an exception -- the inside of sequence 1 -- (7) CL B and Y4 -- VBUSl -- it is connected to long lines 1.3 and 4 -- as -- and Yl -- V:BUS1 -- it is connected so that it may be connected to long line 2. CLB CIRI output Y4 -- VBUSl -- being connected to long lines 2 thru/or 4 -- and output Y3 -- VBUSl -- it is connected to long line 1. passage of the signal on what kind of long line of the circumference around a chip -- although -- interconnecting structure 5900 in the intersection of VBUS9 and HBUSl -- and it is activity-ized by interconnecting structure 5901 in the intersection of VBUSl and HBUS9. Such structures 5900 and 5901 make it possible to connect a thing signal to one of the long lines of the two outsides on each bus on one [ which / of four surrounding surrounding long lines ], and are the same. [ of a contrary ] Drawing 60 shows a spread of the long line between IOB and CLB. The signal input from IOB may actually be directly supplied as an input to CLB only by one PIP delay. The signal output from CLB may be supplied as an output signal to IOB only by one PIF delay. For example, CLB Signal Y1 which occurs in R6C5 is simple IOB. It may be supplied along long line 4 of HBUS6 via PIP6000 as an input which crosses line 6001 of R6-2. The signal which occurred in CLB inside an array in this mode may spread quickly on the outside of a chip. Please note that sign 6003 on long line 4 to PIF corresponds to the input of multiplexer 4501 of Drawing 45. Similarly, it is IOB. R6-2 and IOB The input signal from R6-1 may be combined with long line 3 via PIF, and it is in R6C5 and is supplied as direct human power B1 of R6C4. In this way, in point 6002, the input signal from R6-1 may be directly supplied to CLB in the inside of a device via single PIF delay. In the top part or the bottom of a chip, it is IOB. A similar course is seen from C4-1, C4-2, C4-3, C5-1, C5-2, and C5-3. In each sequence in a chip, or the end of a line, to IOB, these connection is similar and is made. Four long lines 1 thru/or 4 of each bus have a programmable pull-up resistor in those ends (not shown). It is thought that these four long lines are used for a long spread between the connectivity between IOB and CLB in the center of a device or CLB. If a pull-up resistor may be activity-ized with the program data in a composition memory and a signal so does not reach a line, as for the line, one state of logic can be taken. This stops a line crossing the whole device and conveying a spurious signal. The 2nd feature of a pull-up is the capability to make wired AND, by driving the line from CLB or the IOB output buffer of a large number in which three states are possible. When passing O of logic, each output buffer may be constituted so that a buffer may assert a low to a long line. When passing 1 of logic, a buffer asserts three states (high impedance) to a line. If other buffers do not drive a line (in namely, the case of 1 of logic [ as opposed to 3 state - of each in all the buffers connected ]), then, a pull-up resistor forces the high of logic on a line, and gives the result of the AND function needed. Drawings 61 thru/or 70 show connection with ■alumnus structure of having interconnection. In Drawing 61, connection with level bus 1 of input terminal I of eight groups of an input/output block and output terminal O in alignment with the upper part side of an array is shown. In a figure, the circular sign in the intersection of a line shows bidirectional PIF connection. The quadrangle in an intersection shows connection with the multiplexer within IOB, and it generates zero signal explained above with reference to Drawings 45 and 46. If Drawing 61 is referred to again, it will be understood that each IOB input terminal I is combined with one BGI and one long line which is not restrained via PIF. Each output terminal O in IOB is combined with one the long line and one BGI which are not restrained in an input multiplexer. In addition, input terminal I of simple IOB in each center of a triplet is altogether combined with long line 15 via PIP. Distribution of connection was chosen so that the mechanism which makes programming of the network on a device easy and which can be predicted might be established. Various interconnection mechanisms may be realized so that the necessity for specific application may be satisfied. Drawing 62 shows connection with IOB in alignment with the bottom side to level bus 9. The pattern of connection of Drawing 62 is similar to it of Drawing 61. The same explanation suits. Drawing 63 shows the IOB connection along the left-hand side of the array to perpendicular bus 1. Again, besides this connection mechanism was explained with reference to Drawing 61, it is similar and explanation is not put in another way. Drawing 64 shows the IOB connection along the right-hand side of the array to perpendicular bus 9. This interconnection mechanism is similar to what was explained with reference to Drawing 61, and is not explained again. Drawings 65 thru/or 68 are perpendicular buses VBUSi and VBUS. Connection of IOB in alignment with the upper part side of the array of i+1 is shown, and the input for control signals GK, GR, and K is shown. It adds to the connection shown in Drawing 61, and is IOB. Please note that input I of Cil is combined via P[' to long line 3 of VBUS i. Terminal 0 of IOBCil is combined via the multiplexer in IOB to long line 4 of VBUSi. GK and GR ON conversion signal VBUS It is combined with long lines 16 and 17 of i. Input K is HBUS. It is directly combined with long line 15 of 1. Simple IOB Terminal I of that passes PIF and Ci2 is VBUS. To long lines 3 and 15 of i, it is Pencream VBUS. It is connected to long line 1 of i+1. Simple IOB Terminal O on Ci2 is VBUS as an input to the multiplexer of that. Long line 2 and VBUS of i+1 Connection with long line 4 of i is received. Composite IOB Input terminal ■ of that of Ci3 is VBUS. It is combined with long line 1 of f+l, and the multiplexer of that is VBUS. Signal 0 combined so that the signal on long line 2 of i+1 might be received is generated. Control signals GK and GR in IOBCiS are VBUS(s). It is combined with long lines 16 and 17 of i. It is combined with control human power by long line 15 of HBUSl. Drawing 66 is perpendicular bus VBUS like control human power KSGR and GK. Connection of IOB in alignment with the bottom i and VBUSi+1 side is shown. Besides connection with these IOB(s) was explained with reference to Drawing 65, he would like to be observed by the similar thing, but it is simple IOB as an exception. Terminal ■ in CtZ is VBUS. Long line 4 and VBUS of i It is connected to long lines 2 and 15 of i+1. In this mode, it is VBUS. It is connected so that the signal from simple IOBCi2 with which long line 15 of i+1 meets the bottom side of an array may be received, and on the other hand, it is VBUS. i line 15 is combined so that the signal from IOB by the side of the upper part of the array for IOB covering one sequence of CLB may be received. Drawing 67 is level bus HBUS. i and HBUS Are with i+i and it is VBUS. Connection of IOB along the left-hand side of an array with the control signal supplied along with 1 is shown. Composite IOB Ril is HBUS in terminal O of that. An input is received from long line 3 of i. I terminal of Ril passes PIF and it is HBUS. It is combined with long line 4 of i. Control signals KSGR and GK are combined with lines 15.17 and 16 of VBUS 1, respectively. Simple IOB Output O of Ri2 is HBUS. Long line 3 and HBUS of i It is combined so that an input may be received from long line 1 of i+1. Simple IOB Terminal I of Rt2 passes F'IF' and it is HBUS. Long line 4 of i, HBUS Long line 2 and HBUS of i+1 It is combined with long line 15 of i+1. Composite IOB R13 (7) terminal 0 is HBUS. It is combined so that the input from long line 1 of i+1 may be received. GR and GK are combined with a control signal by lines 15.17 and 16 of VBUSI, respectively. Composite IOB Terminal worker in Ri3 passes PIF and it is HBUS. It is combined with long line 2 of i+1. Drawing 68 is level bus HBUS. i and HBUS It is for showing connection of IOH along the right-hand side of the array of i+1, and it receiving a control signal from perpendicular bus VBUS9. These connection is similar to them which were referred to and were explained in Drawing 67, and does not have Is mentioned again. Long line 15 of HBUSi is combined with terminal I of Ri2 along right-hand side (Drawing 68), and, on the other hand, the only exception is HBUS. Long line 15 of i+1 is combined with terminal I of simple IOB along left-hand side (Drawing 67). Drawing 69 shows connection of other control inputs IENSOEN and SLI compound [ along an array top and left-hand side / IOB ], SL2, and CEN. Each of these signals occurs in the output of the multiplexer explained with reference to Drawing 46. In this way, in the intersection of two lines, the agreement using a quadrangle shows an input into not bidirectional PIF but a multiplexer. In this way, as shown in Drawing 69, to IOB in alignment with the upper part, the input to the multiplexer which generates signal ■EN is level bus HBUS1 of proximity, and is supplied from long line 1 and BGI9 of perpendicular bus VBUS 1 of proximity to IOB along left-hand side. Similarly, signal OEM is supplied from long line 1 or either from BGI8. Signal SL1 is supplied from either of long line 2 or BGI7. Signal SL2 is supplied from either of long lines 3 of BGI6. Signal CEN is supplied from either of long line 4 or BGI5. Drawing 70 shows the input to the multiplexer for the control signal compound [ IOB ] in alignment with the right [ of an array ], and bottom side. In this way, signal IEN is supplied from long line 4 of VBUS9 or HBUS9, or either of the BGllo(es). Signal OEN is supplied from either long line 4 or BGIII. Signal SL1 is supplied from either of long line 3 or BG112. Signal SL2 is supplied from long line 2 or either from BG113. Signal CEN is supplied from either of long line 1 or BG114. VI Conclusion This invention can be characterized as the new architecture for a programmable gate array device including the input/output block, the logical block that can be constituted, and interconnecting structure which were improved. as a whole -- the architecture -- a prior art -- many (a problem is conquered.) Propagation of a signal is not controlled any longer by the input and for Output arrangement from the left on the right. [ of interconnecting structure or CLB ] The interconnecting structure of this invention makes easy propagation of the signal which crosses the device in the state where there is no PIF delay not much. This is attained using BGI which is CLB whose length is two by providing connection directly between use of the long line which is not restrained, and the thing of the eight neighborhoods. The architecture removes the necessity for distributed 3 state buffer through the device which must be incorporated into a network. This is attained by moving 3 state buffer within IOB and CLB. In this way, interconnection resources are not used up to the application which needs a multiplex sauce network. The architecture further provides two or more sources for the clock which was not able to be used in the system of a prior art. Specifically, a clock may be driven from any CLB(s) in an array. This invention brings about still bigger use than that of the resources in composition good Yoshihito power / output block. IOB needs big functionality, in order to satisfy flexibility required for devices, such as a programmable gate array. However, in the prior art, these resources were used only for input/output function, and when not used, they made a space and logic useless. This invention establishes various courses, in order to use the resources of an input/output block for the objects other than an input and an output. IO block of a prior art is comparatively slow because of the complicated character of structure. In this way, this invention is simple and provides mixture of compound human power / output block. For the availability of simple human power / output block, it may be avoided to the application which the disadvantage of the speed of a compound block and correlation comprises. furthermore -- setting the input/output block of this invention to a prior art -- also depending -- it is directly connected to the logical block of a large number of proximity which can be constituted. Many application becomes an input/output, and this prevents restricting use of the logic which can be used on a chip. The logical block according to this invention which can be constituted removes common use of the input variable in a large gate function, It enables much more big use of the combination logic which can give the capability to perform a gate function large without the disadvantage of the speed for a narrow gate function, and can be used within CLB for input multiplexing structure. CLB is [ / that the input and output from all the four side of their block are enabled, and a control signal and a clock signal can be received from all the four side ] symmetrical. CLB under use does not suffer the disadvantage of speed for the flexibility in the input and output structure of CLB. As a whole, this invention enables realization of a programmable gate array, Without suffering the disadvantage of capability and speed which provides the symmetry of interconnection, and a multiplex sauce network in there, an array is crossed and the capability to spread a signal, and a bigger combination logic possibility are combined in a long distance. This invention enables realization of the programmable gate array which can suit various application larger than a prior art in this way. These examples of realization enable manufacture of the programmable gate array which may be efficiently used by the capability of bigger percentage and which has bigger functional density rather than were able to use in the architecture of the prior art for PGA. Explanation of the above-mentioned of the desirable example of this invention was provided for the object of illustration and explanation. Restricting to an exact form that there being no place to leave or this invention was indicated is not meant. Clearly, probably, many corrections and change will be clear to a person skilled in the art. An example is chosen and described in order to explain the principle of this invention, and practical application of that to best, and it makes it possible to understand that this invention is suitable for the specific use considered by it with various corrections since persons skilled in the art are various examples. It is meant that the scope of this invention is specified by claims shown above and those equivalents.

[Brief Description of the Drawings]

Drawing 1 is a schematic diagram showing the layout of the programmable gate array according to this invention. Drawing 2 is a schematic diagram of the composition memory in the programmable gate array according to this invention. Drawing 3 is a figure of a composition memory storage cell. Drawing 4 is a figure showing the notation mechanism for the perpendicular bus in a programmable gate array. Drawing 5 is a figure showing the notation mechanism for the level bus in a programmable gate array. Drawing 6 is a figure showing that level and there is the arrangement of the switch matrix in lines 5 thru/or 14 of a perpendicular bus in a programmable gate array. Drawing 7 is a figure showing the intersection of a perpendicular bus and a level bus. Drawing 8 is a figure showing the intersection of substitution with a thing level into a perpendicular bus. Drawing 9 is a figure showing the intersection of the level bus of the even number of perpendicular buses 1 and 9, and the perpendicular bus of the even number of level buses 1 and 9. Drawing 10 is a figure in which being with perpendicular buses 1 and 9 and the level bus of an odd number, and showing the intersection of level buses 1 and 9 and the perpendicular bus of an odd number. Drawing 11 is a figure showing the intersection of level bus 1 and perpendicular bus 1 in an angle. Drawing 12 is a figure showing the intersection of perpendicular bus 9 and level bus 1 in an angle. Drawing 13 is a figure showing the intersection of level bus 9 and perpendicular bus 1 in an angle. Drawing 14 is a figure showing the intersection of level bus 9 and perpendicular bus 9 in an angle. the --A [ 14 ] figure is a figure showing the connection mechanism of a substitute angle in which it may be used in the intersection of all the four angles, instead of the mechanism of Drawings 11 thru/or 14. Drawing 15 is a figure showing connection with lines 16 and 17 of a perpendicular bus, large region reset, and a large region clock buffer. the --A [ 15 ] figure is a figure showing connection between perpendicular buses 16 and 17 and the logical block which can be constituted. the --B [ 15 ] figure is a figure showing the signal path from input/output pad which bypasses the internal IOB logic for connection with a large region clock buffer, a level alternate buffer, or a perpendicular alternate buffer. the --C [ 15 ] figure is a figure showing the input to a large region clock buffer. Drawing 16 is a figure in which being with a level alternate buffer and line 15 on a level bus, and showing connection between a perpendicular alternate buffer and line 15 on a perpendicular bus. the --A [ 16 ] figure is a figure showing connection with line 15 of an input / output block, and the logical block that can be constituted. the --B [ 16 ] figure is a figure showing the input course to a perpendicular alternate buffer. the --C [ 16 ] figure is a figure showing the input course to a level alternate buffer. the --D [ 16 ] figure is a figure in which oscillator signal O8C shows the crystal oscillator circuit which occurs on a chip by it. the --E [ 16 ] figure -- the -- it is a figure showing the external connection to the oscillator ofD [ 16 ] figure. Drawing 17 is a figure showing one example of the programmable Point of Interface which uses a bidirectional path transistor. Drawing 18 is a figure showing the substitute composition of the programmable Point of Interface which uses undirectional multiplexer art. Drawing 19 is a figure showing the interconnecting structure of a switch matrix. Drawing 20 is a figure showing the re-electric power grant buffer used in programmable interconnection. Drawing 21 is a figure showing the switch matrix interconnection option to each connection with a switch matrix. Drawing 22 is a figure showing the interconnection in perpendicular bus 1 and the segment box on nine. Drawing 23 is a figure showing the interconnection in level bus 1 and the segment box on nine. Drawing 24 is a figure showing the segment box interconnection option for each connection with a segment box. Drawing 25 is an outline block diagram of the logical block which can be constituted. Drawing 26 is a figure which shows an input and an output roughly and gives the notation for the logical block which can be constituted. Drawing 27 is a schematic diagram of the combination logic in [ which can be constituted ] a logical block. Drawing 28 is a schematic diagram of the special output stage combined to the combination logic of Drawing 27. Drawing 29 is a schematic diagram of the macro cell to outputs X1 and Yl on [ which can be constituted ] a logical block. the --A [ 29 ] figure is a figure showing connection of the register in the macro cell which prepares preload between programming of the logic array which can be constituted. Drawing 30 is a schematic diagram of the macro cell to outputs X2 and Y2 on [ which can be constituted ] a logical block. Drawing 31 is a schematic diagram of the macro cell to outputs X3 and Y3 on [ which can be constituted ] a logical block. Drawing 32 is a schematic diagram of the macro cell to outputs X4 and Y4 on [ which can be constituted ] a logical block. Drawing 33 is a figure of the input multiplexing structure over signals vAL thru/or VA4 used in The Lebel multiplexing in the combination logic section of the logical block which can be constituted. Drawing 34 is a schematic diagram of the input multiplexing structure for signals VBI thru/or VB4 used in The Lebel multiplexing in the combination logic section of the logical block which can be constituted. Drawing 35 is a schematic diagram of the input multiplexer structure for signal ■C Engineering [ which is used in The Lebel multiplexing in the combination logic section of the logical block which can be constituted ] thru/or VO2. Drawing 36 is a schematic diagram of the input multiplexing structure for signal vD Engineering [ which is used in the 2nd level multiplexing within the combination logic section of the logical block which can be constituted ] thru/or VB4. Drawing 37 is a figure of the input multiplexing structure for VEI and VB2 which are used in the 3rd level multiplexing of combination logic. Drawing 38 is a figure of the input multiplexing structure for the 4th level multiplexed signals VF in combination logic. Drawing 39 is a schematic diagram of the input multiplexing structure for control signal VG used in providing a special output. the -- the [A / 40 / figure thru/or ] -- 40H figure is a figure showing input multiplexing to general object control lines CTI thru/or C70, respectively. Drawing 41 is a schematic diagram of a circuit which generates output activity-ized control signals OEI thru/or OF2 in the logical block which can be constituted. Drawing 42 is a figure showing selection of the clock signal within [ which can be constituted ] a logical block. Drawing 43 is a schematic diagram showing generating of the clock activity-ized signal in [ which can be constituted ] a logical block. Drawing 44 is a schematic diagram showing selection of the reset signal in [ which can be constituted ] a logical block. Drawing 45 is a schematic diagram of the simple human power / output cell according to this invention. Drawing 46 is a schematic diagram of the compound human power / output cell according to this invention. Drawing 47 is a figure showing the input and output of compound human power / output block. Drawing 48 is a figure showing the input and output of simple human power / output block. Drawing 49 is a figure showing connection of the compound human power / output block in shift register composition in diagram. Drawing 50 is a figure showing directly connection with the input of a given logical block from the following output of the near (next) logical block which can be constituted. Drawing 51 is a figure showing directly connection with the input of a logical block to the logical block which can be proximity constituted, and which can be central constituted. Drawing 52 is a figure showing directly connection with proximity and the logical block of the next proximity which can be constituted. [ output / of the logical block which can be central constituted ] Drawing 53 is a figure showing directly connection of outputs x1 thru/or X4 on [ which can be circumference constituted ] a logical block. Drawing 54 is a figure showing directly connection with the input of the logical block which can be circumference constituted. Drawing 55 is a figure showing directly the connection to inputs F1 thru/or F4 on [ which can be circumference constituted ] a logical block. Drawing 56 is a figure showing the programmable connection between interconnecting structure and the logical block which can be constituted. Drawing 57 is a figure showing the fixed connection between interconnecting structure and the logical block which can be constituted. Drawing 58 is a figure showing the programmable connection with the long line which is not restrained from the logical block in an array which can be constituted. Drawing 59 is a figure showing the programmable connection with an outside long line from CLB. Drawing 60 is a figure showing a spread between the input / output block on a long line, and the logical block which can be constituted. Drawing 61 is a figure showing the programmable connection between the input / output block on the upper part the array which can be constituted side, and level bus 1. Drawing 62 is a figure showing the programmable connection between level bus 9 on the bottom the array which can be constituted side, and an input/output block. Drawing 63 is a figure showing the programmable connection between perpendicular bus 1 on the left-hand side of an array, and an input/output block. Drawing 64 is a figure showing perpendicular bus 9 on the right-hand side of an array, and the programmable interconnection between an input/output block. Drawing 65 is a figure showing connection of a clock, and a reset signal and a compound logical block like the programmable connection with the perpendicular bus of the input of the input/output block on the upper part array side, and an output. Drawing 66 is a figure showing the connection with the clock on the bottom array side, and the input/output block of a reset signal, and connection with the perpendicular bus of these bottom side human power / output blocks. Drawing 67 is a figure showing the connection with a clock, and the input/output block on the left-hand side of a reset signal, and connection with the level bus of these left-hand side human power / output blocks. Drawing 68 is a figure showing the connection with the clock on the right-hand side of an array, and the input/output block of a reset signal, and connection with the level bus of these right-hand side human power / output blocks. Drawing 69 is a figure showing connection with the interconnection bus of proximity of the control signal input on the input/output block on an array and left-hand side. Drawing 70 is a figure showing connection with the interconnection bus of proximity of the control signal input to the right of an array, and the input/output block on the bottom side. in a figure, CLB is a logical block which can be constituted, and IOB(s) are an input/output block -- 2 -- *O is a composition memory and 300 is a primitive cell. applicant for a patent an advanced micro and a diva -- a Isis parrot -- Held representative patent attorney Fukami Kubu (two Hocas) each End Fuji 3 A non-Nanamathoso 57 Kudzu, a Mutually No. j, and h It was. tau Off * Si 1 A FIG, -21 Roku 1 A (Make sure 45 S, Funt / 'Dy) Another person O Scoundrel G Di FIG, -24alphaJ" Fellowship 2 FIG, -27 "11 Yu upsilon It was - UX Hand Continuing Tasuku Positive Writing alpha Te 0 6 * The object of amendment 4 * of a request Applicant's for a patent representative's column, a drawing complete diagram, August 29, Heisei 2 A power of attorney and a translation 7 * The contents of amendment The passage of an attached sheet. A drawing has no change by the contents. 2, the title of an invention Logic Kerei which can be constituted Above Those who do 3 and amendment A relation with an incident