Transponder capable of coding

[Detailed Description of the Invention]

[Industrial Application] It is related with a transponder element, if the present invention is specified from °, it is programmable, and when a question is asked, it relates to the transponder element or tag which answers according to a program. Programming of the tag will change the operational mode of the tag including data insertion in a memory.

[Description of the Prior Art] There is art which inserts data from remoteness into two tags currently used well now. The 1st uses a career signal as a reference clock for controlling the internal circuit of a tag. And the 2nd signal of different frequency is used in order to write in and insert data. Such a method is CB. It is indicated by 2077556B and 2102250B. Another method is piling up data on a career by a phase thru/or amplitude modulation. It is carry 6 when a phase modulation is adapted. A frequency is a means to operate the internal reference oscillator in a tag.

[Problem(s) to be Solved by the Invention] Law both has a limit. According to two separated input signals, two analog input circuits and two input antennas are needed. This brings about the price of tags, and the increase in internal current capacity. A heavy burden called the complexity of a control device is also included. Before a system writes in a certain data into a tag as applying the phase modulation technique to a single signal career, it is necessary to identify what the antenna detected. It is required that this should write in the direction of the antenna of a tag again and should maintain it uniformly to the quantity control machinery of a phase. This gives a certain restriction to the use including the increase in a certain amount of price about an additional circuit. It is influenced by restriction of a dynamic range although amplitude modulation conquers the problem of a direction. In the number system of low frequency waves which the strength of an electric field decreases according to the 3rd power solution of a zone, suitable automatic gain control must be included in the input amplifier of the tag. This means a difficult technical challenge and restricts the Dina Ivy which can always be attained in practice. An object of the present invention is to provide the read-out write-in art which covers large Dynamic range and has neither the price compensation by the double antenna input device which can be employed, nor the systematic complexity by a phase or amplitude modulation.

[Means for solving problem] EP-A-0289136 is indicating the data transmission system pulse-ized, in order that the output of a control device resonant circuit may change the logic level of the data signal read into the memory of a tag. However, since a clock is determined by the data-communications protocol, the tag must have an internal timing circuit. Desirably, a new data bit occurs, without changing the output of a control device resonant circuit.

[Function] According to the 1st field of the present invention, including an input circuit and a data accumulation means, an input circuit is constituted so that the pulse of a career signal may be received, It is dependent on the length of the input career pulse to which the logic value of a logic signal corresponds including a means to answer a pulse and to supply a logic signal, In order to prevent the logic value supplied to a data accumulation means until a pulse is completed, the electronic device provided with a means which can be coded is provided. The advantage of the above-mentioned element is that a tag does not need an internal timing means. The clock of data can be made and accomplished only by the end of a career pulse. This will save a space, material, and a price. In a desirable element, a data accumulation means constitutes the main memory of an element, the means which carries out a logic signal there supply 6 is a separator sequence, a prevention means is a reset output of an input circuit, and a reset output is connected to the memory input which sends data into a memory. A prevention means is constituting the output of the input circuit which already exists in an element, and the advantage of this composition is not needing the additional parts of 9 or more those so. A data accumulation means constitutes the functional alteration means of an element additionally as an alternative plan. The contents of the functional alteration means are compared with a key, and when in agreement, they operate a means to permit the data which should be sent in into the main memory. In desirable composition, when coincidence occurs, a key considers as enabling latch circuitry which makes Open an and gate for a signal to transmit to the clock input of the main memory from a reset output, An element includes a means to generate the delayed reset signal, when the time between the continuing career pulses exceeds the maximum which resets a functional alteration means and latch circuitry and which was set up beforehand, They are To 2 Including this about the means for resetting a functional alteration means, when the interval of a career pulse exceeds the maximum defined beforehand. The advantage of this composition is decreasing the possibility of all the random noises or an unidentified source which affects normal operation of an element. One problem of the existing tag is interfering by the method which is not expected to be a control device of other tag systems 0. For example, although widely used as a shoplifter prevention system in the electronic article investigation (BAS) system, the porter of the coded tag to other systems makes it careless enough to start a store alarm system, and a rule feels bad. The present invention also makes it the object to conquer this problem again. Therefore, when the contents of the functional alteration means are compared with a key and it is in agreement in other desirable composition, in order to answer the corresponding Intergo ration pulse transmitted there, a means to start an element is operated. This has the coded usable element which has a plurality of setup of the one structure, and the element of each setup has the advantage of answering only the Intergo ration pulse led by the signal corresponding to each key. According to the 2nd field of the present invention, data is transmitted to the accumulation means of the electronic device which can be coded, It is the way supply the pulse of a career signal to the input of the element, and each pulse has the controlled length, defining the value of a corresponding data bit with the single length of a pulse -- and -- or -- or the way the end of each pulse causes a data bit which should be sent in into an accumulation means is provided. An electronic element is a transponder element like an electronic tag, and, as for data, it is desirable for a tag to constitute the startup instructions which permit to carry out transmission Perilla frutescens (L.) Britton var. crispa (Thunb.) Decne. of the more detailed information, or to receive it. In a desirable method, the width of a pulse defines value *1degree" or "0 The, and sets it as the specific point of an electronic element, and the end of a pulse brings about the value which should be sent in into the shift register of an element, or a memory.

[An example and the effect of an invention] Although a desirable example is only one mere example, it is explained, referring to an attachment figure. The circuit shown in Drawing 1 is CB. It has what was indicated by 2102250B, and identity of a certain kind. 6 which the circuit was amplified with input amplifier 400 of 132KH2, and was modulated It comprises output drive stage 401 of 6 K Hz. Counter sequence 134 divided into 128 is used in order to extract a wood quality internal timing function. The data in a tag is accessed by data selector 402 from shift register SRI of N bit. The 2nd shift register that consists of one or a plurality of stages is provided with the means which a transponder writes in by that cause and will be changed to a state or the mode. The state of shift register SR2 is compared with key 403 set up beforehand. It will write in, if shift register SR2 and key 403 are in agreement, and latch 404 is considered as enabling. The output of a write-in latch turns into the 1st input to and gate 405. The 2nd input to an and gate is reset signal R drawn from the output of input circuit 400, and has the recovery time for 250 microseconds typically. The output from and gate 405 forms the clock input to the main shift register SRI. One 2nd paste all A circuit 407 which has the recovery time for about 2 ms is also drawn from the 1st reset signal R. Output R9 of the 2nd reset circuit 407 is written in, and is a To 3-set input of latch 404. this -- again -- or it becomes a reset signal of shift register SR2 via gate 408. When R is reset, it should memorize R1 or not being reset automatically. R9 is reset only when the following pulse reaches after 2-ms or more progress from reset of R. The 2nd input of Oike- 40B is drawn from output delta 1 of a counter sequence. Output A of a counter sequence. It is the data input of Is shift register SRI and SR2 both. About one to five microsecond delay of the Ri cent line to separator sequence 134 is carried out by delay circuit 411. operation of the circuit between typical programming or a write-in sequence is explained below -- it comes out. In order to change an input into the state where the Acceptance can put in a circuit, it is required to transmit the key signal defined beforehand first. the protection of an internal memory to programming this necessary condition is not recognized to be -- or let protection of data to the noise of a high level of sporadicness be a positive thing. A key is ON 4 To be in a tag by transmitting the train of impulses defined beforehand. Shortly after a circuit detects the 1st pulse in a sequence, let both reset circuits 400 and 407 be high levels. Next, separator sequence 134 drives at the rate determined on the frequency of an input. Input A to both shift registers. The state is a function of the number of the cycles in an input signal in any cases. Therefore, input A of as opposed to a shift register to the 132-kHz input signal for 1*5 ms. It will become Is data 1. If the input signal was completed 1.5 ms afterward, change of the state of reset circuit 400 sends in data 1 into shift register SR2. R and A. It is desirable that it is the clock and data input of Respectively shift register SR2. Transmission of the pulse for 0.5 ms sends in data 0 into shift register SR2 similarly. Glitch with a possibility of breaking the data inputted into shift register SR2 is defended by delay circuit 411. This makes it a clear thing not to reset it, if separator sequence 134 is not after data has been sent in into shift register SR2. By sending the sequence of the pulse of a suitable interval, it becomes possible to send in the right key into shift register SR2. All the data written in into shift register SR2 is held for two conditions. The 1st [ the ] is that data is reset when the interval of the continuing pulse exceeds 2 ms. Generating To shake and RD write in with shift register SR2, and this state resets latch 404. The 2nd condition is that the state where there is no pulse continues 2 ms or more. Generating To shake and A1 change to value 1, or this state resets shift register SR2 via gate 408. This demand decreases the possibility of all the random noises sent into shift register SR2. When the data written in shift register SR2 is in agreement with key 403, write-in latch 404 is considered as enabling in input C. This permits that reset signal R supplied to and gate 405 sends data into the memory in the main shift register SRI. And data is written in into the main shift register SRI by having been used in order to write in into shift register SR2, and the nothing technique. It will write in, if data sending is completed to the main shift register SRI, and latch 404 is reset by change of the state of RD by the end of a train of impulses. Limited standup falling time exists to signal transmission from a control device in fact. So, it will become a response of itself, and a function of the distance of the tag from a transmission antenna at the exact moment when a tag rises. A generation acceptable value is between tags to the recovery time of a reset circuit similarly. These factors give practical restriction to the rate in which data is written. This is shown in the waveform of Drawing 2. Locus A (the typical waveform of the train of impulses transmitted at 132 kHz by the control device is shown.) The standup falling time of a transmission envelope is Udah for 250 microseconds. Locus B shows the output from the counter sequence which forms the data input to shift registers SRI and SR72. A solid line shows output A0 in the case of being in the range which the tag approached. It is response A when a tag is in the maximum operation distance. It is given by Is the broken line. An ultimate state is generating To shake when separator sequence 134 starts sending after 250 microseconds of starts of a transmission pulse in the maximum distance. This corresponds, when a transmission envelope reaches the peak value. Locus C shows the response of reset line R. A reset line serves as a high level between 1 [ mere ] of 132KH2 input signal, or 2 cycles. However, the time for the reset line which sets up the end of a pulse has A different and big allowable width more. This is not a problem, if there is time between pulses to such an extent that it permits that a reset line returns to a reset state. The worst case where it is called the reset recovery time for 500 microseconds is drawn on the locus. Shortly after a 132-kHz input signal stops, it does not drive any longer but input A0 to both shift registers is fixed there. It only maintains this state until reset line R sets this as the point that data is sent in for any of shift 8 register being. A small delay of 1-5microsecond brought about by time delay circuit 411 is output A in a shift register, before resetting a counter sequence. Let Is sent rare To be a clear thing. As for a transponder, Acceptance puts in data at the rate for 1.5 ms per data bit typically. Said [ of it ] is essentially carried out to the read-out range from character of operation, and it has a write-in range. As for this, compared with the read-out range, the write-in range is contrastive with other art of often very little many. this -- only -- one input amplifier -- further -- : (i) Decrease stillness current capacity, \ and (if) losing Necessity which equips the necessity of dealing with the 2nd input signal of different frequency, or an internal oscillator -- further (iii) Simplify the internal structure of a special order chip and a control device very much. The complicated AGC circuit in a special order chip which is required from an amplitude amplification career by the writing to the transponder by a train of impulses becomes unnecessary. Pulse modulation is not influenced by the problem of the direction between a tag and a control device which are experienced in a phase modulation system. And the state of the data bit from which the interval of all the input pulses smaller than the interval by which the maximum definition was carried out should be taken in is established, and the cheap and easy method related with the data in the transponder whose end of a pulse is a means to send a data bit into the internal memory of a transponder is provided. Programming is recognized and moved from a single career by the train of impulses. reset input [ as opposed to latch 404 as a proposed change ] -- or it takes out from the output of gate 408 and transmission extended in this case ends the data input to the inside of shift register SR1 again. Otherwise in a proposed change, key 403 comprises software, and the data input of the beginning to a transponder sets up a key. This is an example of how the parameter of a tag is incorporated into software. If an one or less shift register [ SR ] circuit is wanted to be omitted, SRI will drive directly by reset from output 440 in this case. Although the circuit mentioned above shows the data stored in single shift register SRI, probably, the tag has a more nearly mass memory in practice. In such a situation, shift register SRI will operate as a middle accumulation means. It is divided into three fields which usually consist of addresses, commands, and data. From shift register SRI, data decodes the write-in command from a control device to the right address in the main memory, and is transmitted to it. Drawing 3 shows the 2nd example of what was indicated by CB2102250B, and the present invention which has identity. However, it is used in order that transmission of the data based on coding of a train of impulses may control the operating characteristic of a tag in this example. this -- for example, probably, it is a value when it is desirable to have a kind of two tags in the same structure. One kind will be attached to each expensive goods for the object of =21 property pursuit. Those who are carrying property with an access card without distinction between kinds are not read, and the article will not be distinguished. By assigning a different key signal to several kinds of a tag, they can be operated alternatively. One method for attaining this is shown in Drawing 3. Additional Ann Thorn- 510 is inserted in the line to the output from the input of a tag in Drawing 3. The 2nd input of an and gate receives a signal from output Q of latch 500. This latch is controlled by the circuit which comprises Oike- 1-508 and shift register SR3 and key circuit 503 like above-mentioned latch 404. Or gate 508 receives RD as an input from a dividing network as a reset signal delayed from circuit 407 in aluminum. Or the output of gate 508 receives reset signal R from output 440 of input circuit 400 as a clock pulse, and constitutes the reset input of shift register SR3 which Trust separator output AO Acceptance 2 as data input. In the usual state, since a tag is in a prohibited state by control latch 500, it cannot output all the data. However, when the train of impulses which constitutes the right key detected by circuit 503 is received, control latch 500 is removed. If a Intergo ration pulse continues after this train of impulses, namely, before reset signal R9 occurs, a tag will output the data currently held by the usual method shift register SR1. The application of the above-mentioned composition which has an advantage specially is generating To shake when operating the tag in which the easy detection system used in electronic article investigation (RAS) was coded. As for a RAS control device, a false alarm is given when the coded tag answers a signal on the same frequency as the tag of EAS. This effect that is not very desirable is removable by the demand referred to as that a signal is transmitted to the coded tag which answers an ink volley In signal by the key signal beforehand defined as shown in Drawing 3. It can also have a very easy prohibition circuit for this object so that it may be explained with reference to Drawings 4 and 5. In this example, it is reset signal R from output 440 of input circuit 400, Set input S and diode 515 of clock input [ of the data accumulation means constituted by A flip-flop 520 ] C (A) and B flip-flop 530 are passed, and it is reset input [ of flip-flop 520 ] R (connected to aluminum.). Outputs Q and A of flip-flop 520 and the 2nd input of Is and gate 51O are supplied. Low Than is also shown by quantity as the reset state of reset output R is shown in Drawings 1 and 3 in this example. Clock input C (B) of flip-flop 530 is output X from counter sequence 134 which has a cycle of 5 5.82 m. Data input [ of flip-flop 530 ] D (Ill is held at zero and output Q (B) is data input [ of flip-flop 520 ] D (supplied as Ill .)) At the time of low Became, for diode 515, as for R (A), in RC circuit 560, R goes up gradually so that it may become settled by RC damping time constant of voltage The circuit 560 of R1 *, when R becomes quantity again immediately in low Become. Although explained, the function of the circuit of Drawing 4 referring to Drawing 5, Locus A shows here the main Intergo ration pulse I transmitted by short career pulse P, Locus B shows the action as a result of reset signal R from output 440, locus C shows the action to which the voltage of reset input [ of flip-flop 520 ] R (A) corresponds, and Trajectory shows output Q (A) of flip-flop 520 supplied to and gate 520. In the state of reset, reset signal R is quantity, and it is output Q of flip-flop 520 (aluminum is low Is in order to forbid operation of and gate 520.). If 132-kHz career signal P exists succeedingly in input 400, R will be a low next door (refer to 5th [ The ] figure locus B), and it will be input R (A). Reset 5 signal will be removed from S. Output Q (D as aluminum (the value which aluminum follows is driven.)) which reset R serves as quantity and is supplied to and gate 510 after a career signal pulse is completed There are two methods in this. In the case of the 1st, a career pulse is when shorter 2.91 m than the half of the cycle of 5, i.e., X. In this case, clock input C (B) It is maintained as [ low of ], therefore is still QcB and Is quantity, and makes it possible to answer the main Intergo ration pulse ■ which the Takanobu item is supplied to Ann Thorn- 510, and a transponder follows. In the case of the 2nd, a career pulse signal is when longer 2.91 m than 5. in this case, Q (Ill -- low -- When -- in order for X to become quantity like, therefore to forbid a response of l and Reims Vonda at the time of the end of career pulse P, a low signal continues being supplied to and gate 510.) Thus, it will be understood that logic value Q (B) is dependent on the length of the career pulse inputted. 6 If the circuit of Drawing 4 inspects the validity of an ink volley In signal further, namely, main Inko ration Bals ■ does not follow the period which becomes settled by the reset time of RC circuit 560 after initial pulse P, R<4> It becomes quantity in order to reset flip-flop 520. The tag system of Drawing 1 can be combined with the tag system of Drawings 3 or 4, and all the tag systems will be provided with one or a plurality of features which were indicated by CB JP,2102250,B B. The invention will be used also about the simple data accumulation element and a one-way element like a beacon, although the transponder was described.

[Brief Description of the Drawings]

The block diagram of a transponder circuit based on the 1st example of the present invention in Drawing 1, The signal diagram concerning [ Drawing 2 ] Drawing 1 and Drawings 3 and 4 are the block diagrams of a transponder circuit based on the 2nd and 3rd examples of the present invention, Since the lower part of the example of Drawing 4 is equivalent to the lower part of Drawing 3, it has omitted, and Drawing 5 is a signal diagram about Drawing 4. Set to a figure. 400 ... Input circuit 401 ... Output stage 402 ... Data selector 403 ... 404 ... Latch 405 --- And gate 408 -- - or gate Hand Continuing Tasuku Positive Writing (Method) July, Heisei 2 A second Day