Codable electronic devices, e.g. transponders

265 641 T3

DESCRIPTION

Codeable electronic devices, eg transponders.

The present invention relates to transponder devices, and more particularly to transponder devices or tags which can be programmed and which, when interrogated, provide a response according to the program. Programming the tag may involve data entry into a memory or it may modify the mode of operation of the tag.

There are currently two commonly used techniques to remotely enter data on labels. The first is to use a carrier signal as a reference clock to control the internal circuitry within the tag. A second signal at a different frequency is then used to write or enter the data. Such provisions are disclosed in GB 2077556B and 2102250B. The alternative procedure is to superimpose the data on the carrier by means of phase or amplitude modulation. Where phase modulation is used, the carrier is often the means by which an internal reference oscillator is activated within the tag.

Both procedures have their limitations. With two separate input signals, it is necessary to incorporate two analog input circuits and two input antennas. This increases the cost of the tag and also the internal power requirements. Furthermore, this places an additional burden of complexity on the control unit.

Using a single carrier phase modulated procedure requires the system to determine the direction of the antennas on the tag before writing any data. This also requires that the antenna orientation of the tag remains constant with respect to the antennas in the control equipment during the write phase. This implies a certain level of cost in additional circuitry and can impose some limitations of the system in its use.

Amplitude modulation overcomes the orientation problem but suffers from limitations in dynamic range. In low frequency systems where the field strength decreases according to the inverse of the cubed range, adequate automatic gain control must be included within the tag input amplifier. This represents a difficult technical challenge and invariably limits the dynamic range that can be practically achieved.

The present invention seeks to provide read and write techniques capable of operating over a wide dynamic range that have neither the cost drawbacks of the dual antenna input procedure nor the system complexities associated with amplitude or phase modulation.

EP-A-0289136 discloses a data transmission system in which the output of a resonant control circuit is pulsed to change the logic level of a data signal read from the memory of a tag. However, the timing is determined according to a data transmission protocol, so the tag has to have an internal timing circuit. Where appropriate, a new data bit is generated without a change in the output of the control resonant circuit.

EP-A-0112043 discloses a self-timed binary receiver in which a data output is controlled by the pulse lengths arriving at an input. US-A3679874 also discloses an arrangement in which incoming pulses are integrated and used to produce different logic outputs depending on their length.

According to a first aspect of the present invention there is provided an encodable electronic device as defined in claim 1.

An advantage of the above-mentioned device is that the tag does not require internal timing means. The timing of the data is effected only by termination of the carrier pulses. This saves space, material and expenses.

In a preferred device the data storage means comprise means for changing the operation of the device. The content of the operation change means can be compared to a key which, upon matching, acts as means to allow data to be clocked into main memory.

In a preferred embodiment, upon matching, the key activates a latch circuit that opens an AND gate to pass signals from the reset output to the clock input of main memory, the device further comprising means for producing a lock signal. delayed zeroing if the time between successive carrier pulses exceeds a predetermined maximum value that zeroes the operation change means and the latch circuit, and means for zeroing the operation change means if the duration of a carrier pulse exceeds a predetermined maximum value. An advantage of this arrangement is that the possibility of any random noise or unauthorized source interfering with the correct operation of the device is reduced.

One problem with existing labels is that they can interact in unwanted ways with the control units of other label systems. For example, Electronic Article Surveillance (EAS) systems are widely used as anti-shoplifting systems, and the bearer of a tag coded by another system can inadvertently set off a store alarm with disturbing results. The present invention also seeks to overcome this problem.

Consequently, in another preferred arrangement the content of the operation change means is compared with a key which, upon matching, activates means to allow the device to respond to a respective interrogation pulse transmitted thereto. This has the advantage that a number of different sets of coded devices can be used in a single building; the devices in each game will respond only to interrogation pulses that are preceded by a signal corresponding to their respective key.

According to a second aspect of the present invention there is provided a method of communicating data to data storage means of an encodable electronic device, as defined in claim 10.

The electronic device is preferably a transponder device such as an electronic tag and the data may constitute an instruction

ES 2 265 641 T3 of actuation, which allows the label to transmit and / or receive additional information.

In a preferred method the duration of the pulse determines the value, "1" or "0", set at a particular point within the electronic device, and the termination of the pulse causes that value to be entered into a shift register or a memory inside the device.

Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

Figure 1 shows a block diagram of a transponder circuit according to a first embodiment of the present invention;

Figure 2 is a signal diagram referring to Figure 1;

Figures 3 and 4 show block diagrams of transponder circuits according to a second and third embodiment of the present invention, the bottom portion of the embodiment of Figure 4 having been omitted since it corresponds to that of Figure 3; Y

Figure 5 is a signal diagram referring to Figure 4.

The circuit shown in Figure 1 has certain similarities to that disclosed in GB 2102250B.

The circuit comprises an input amplifier 400 to 132 kHz and an output driver 401 to 66 kHz modulated in amplitude. A 134 divide-by-128 count string is used to derive the internal timing functions. The data within the tag is accessed via data selector 402 from the N-bit shift register SR1. A second shift register SR2 comprising one or more stages provides a means by which the transponder can be switched to a write mode or condition. The state of shift register SR2 is compared to a preset key 403. If there is a match between shift register SR2 and key 403 then a write latch flip-flop 404 is triggered. The output of the write latch flip-flop provides a first input. to an AND gate 405. The second input to the AND gate is the first reset signal R derived from the output 440 of input circuits 400 and having a typical recovery time of 250 jus. The output of AND gate 405 forms the clock input to main shift register SR1. A second zeroing circuit 407 with a recovery time of approximately 2 ms is also derived from the first zeroing signal R. The output R_D from the second reset signal 407 is the reset input to the write latch flip-flop 404. It is also, through the OR gate 408, a reset signal for shift register SR2. It should be noted that RD does not automatically reset when R is reset. RD will only cause a reset if the next pulse arrives in an interval that exceeds 2 ms from the reset signal from R. The second input to the OR gate 408 is derived from the output Ai of the counting chain. Output A₀ in the count string is data input to both shift registers SR1 and SR2. The zero line to divider string 134 is delayed by approximately 1-5 microseconds by a delay circuit 411.

The operation of the circuit during a typical programming or writing sequence will now be described. In order to put the circuit in a condition where it will accept data, it is first necessary to transmit a predefined "key" signal. This prerequisite ensures protection of the internal memory against unauthorized programming or data corruption by any sporadic high level noise sources. The key is entered by transmitting a predetermined pulse train to the tag.

As soon as the circuit detects the first pulse in the train both reset circuits 440 and 407 are activated. The divider chain 134 is then timed at a rate determined by the frequency of the input signal. The state of the A0 input to both shift registers at any time is a function of the number of cycles within the input pulse. Thus, for an input signal at 132 kHz for a duration of 1.5 ms the input of A0 to the shift register will be data 1. If the input signal is terminated after 1.5 ms the change in the state of the resetting 400 will clock data 1 into shift register SR2. It will be appreciated that R and A₀ are respectively the clock and data inputs in shift register SR2. Similarly, a transmission pulse duration of 0.5 ms will clockwise pass data 0 to shift register SR2. Any possible interferences that could disturb the input of data to the shift register SR2 are canceled out by means of the delay circuit 411. This ensures that divider string 134 is not reset until data has been clocked into shift register SR2. By sending a sequence of pulses of the appropriate duration it is therefore possible to enter the correct key in shift register SR2.

Any data written to shift register SR2 remains subject to two conditions. The first of these is that the data is reset if the period between successive pulses exceeds 2 ms. If this happens, RD clears shift register SR2 and write latch flip-flop 404. The second condition is that no pulses should exceed a duration of 2 ms. If this happens, Ai switches to the value "1" which, through the OR gate 408, sets the shift register SR2 to zero. These requirements significantly reduce the possibility of any random noise being clocked into shift register SR2.

If the data written in shift register SR2 matches key 403 the write latch flip-flop 404 is activated at input C. This allows the reset signal R, which is supplied to AND gate 405, to pass through clock pulse the data to memory in main shift register SR1.

The data can now be written to the main shift register SR1 by means of the same technique that has been used to write to the shift register SR2. Once data entry in the main shift register SR1 is complete, the write latch latch 404 is reset by the change of state of R_D at the termination of the pulse train.

In practice there is a finite rise and fall time for the transmit signal from the control unit.

ES 2 265 641 T3 control. The exact time a tag will go live will therefore be a function of your own response and the tag's range from the transmitting antenna. Similarly, there is a production tolerance between labels for the recovery time of the zeroing circuits. These factors put a practical limit on the speed at which data can be written. This is illustrated by the waveforms in Figure 2.

Trace A shows a typical waveform for a pulse train transmitted at 132 kHz by a controller. The rise and fall times of the transmit envelope are of the order of 250 jus. Trace B shows output A₀ from the count string that forms the data input to shift registers SR1 and SR2. The solid line shows the response of A0 when the tag is in close range. When the label is at its maximum operational range, the response of A0 is given by the dashed line. It can be clearly seen that the limiting condition occurs at the maximum range when the divider chain 134 begins timing 250 ps after the start of the transmit pulse. This corresponds to the instant the transmit envelope has reached its peak value.

Trace C shows the response of the zeroing line R. The zeroing line will rise within just one or two cycles of the 132 kHz input signal. However, the time for the zero line to come to the end of a pulse is much longer and is subject to wide tolerances. Providing that there is enough time between pulses to allow the zero line to recover to its resting condition this is not a problem. A worst case zero recovery time of 500 ps is shown in the trace. As soon as the 132 kHz input signal ceases, the input of A0 to both shift registers can no longer be timed and is therefore fixed. It will simply remain in this state until the zeroing line R establishes at which point the data is timed in one of the shift registers. The small delay of, say, 1-5 ps provided by the time delay circuit 411 ensures that the data from the output of A0 is timed in the shift registers before the count string is reset.

The transponder can accept data typically at a rate of 1.5 ms per data bit. By the nature of its operation it has a write range that is essentially the same as its read range. This is in contrast to many other techniques where the write range is often significantly less than the read range. It is based only on a single input amplifier and therefore:

(i) Reduces the quiescent current requirement;

(ii) eliminates the need to deal with a second input signal at a different frequency or to provide an internal oscillator; and (iii) greatly simplifies the internal complexity of the custom chip and control unit.

Also writing to the transponder by means of a series of pulses there is no need for complex AGC (Automatic Gain Control) circuits none on the chip custom made as would be required for an amplitude modulated carrier. Nor does a pulse modulated attempt suffer from any tag-to-controller orientation problems as experienced with a phase modulated system.

This provides an inexpensive and simple way of programming data into a transponder whereby the duration of any input pulse of less than a defined maximum period establishes the state of the data bit to be entered and the termination of the pulse is the means by which that the data bit is timed in an internal memory within the transponder. Programming is authorized and carried out by means of a single carrier pulse train.

In a modification the reset input to latch 404 is taken from the output of OR gate 408 in which case the long transmission will also terminate data input in shift register SR1.

In another modification the key 403 is configured in software and an initial data entry to the transponder establishes the key. This is an example of how the parameters of a tag can be set in software.

Although the circuit described above shows data that is stored in a single shift register SR1, in practice the label can have a much larger memory. In these circumstances the shift register SR1 would act with the capacity of a buffer store. It would most usually be subdivided into three fields comprising address, instruction, and data. Data would be transferred from shift register SR1 to the correct address within main memory by decoding a written instruction from the controller.

Figure 3 shows a second embodiment of the present invention which also has similarities to that disclosed in GB 2102250B. In this embodiment however, pulse train encoding data transfer is used to control the operating characteristics of a tag. This can be of value for example where within the same building it may be desirable to have two families of tags. A family can be attached to individual high value merchandise for asset tracking purposes. The second family of tags can be used for access control. Without some form of discrimination between families, a person with an access card carrying a tagged asset could not be read, and the item would not be identified.

By assigning a different key signal to each family of tags, they can be selectively activated. One way this can be accomplished is with the circuit shown in Figure 3.

In Figure 3, an extra AND gate 510 is inserted in the line from the input to the output of the tag. A second input of the AND gate receives a signal from the Q output of a latch flip-flop 500. The latch flip-flop is controlled in a similar manner to the above-mentioned latch flip-flop 404 by a circuit comprising an OR gate 508, a shift register SR3 and a 503 key circuit. The OR gate 508 receives an input Ai from the divider circuits and the delayed reset signal R_d of the circuit 407. The output of the OR gate 508 constitutes the zero input of the data register.

ES 2 265 641 T3 offset SR3 that receives the reset signal R from the output 440 of the input circuit 400 as its clock pulse, and the divider output A₀ as your data entry.

Under normal circumstances the tag cannot output any data since it is inhibited by the control latch flip-flop 500. However, upon receiving a pulse train comprising the correct key as detected by circuit 503, the control latch flip-flop 500 is unlocked. If the pulse train is immediately followed by an interrogation pulse, that is, before a zeroing signal occurs R_D, the label will output the data held in its shift register SR1 in the normal way.

A particularly advantageous application of the above-mentioned arrangement is presented where a simple detection system used in electronic article surveillance (VEA) can activate a coded tag. If the coded tag responds with a signal at the same frequency as the VEA tag, the VEA control unit will give a false alarm. This very undesirable effect can be eliminated by requiring that for an encoded tag to respond to an interrogation signal, the signal must be preceded by a predetermined key signal, as in Figure 3.

An even simpler inhibitor circuit may be provided for this purpose as will now be described with reference to Figures 4 and 5. In this embodiment the reset signal R from the output 440 of the input circuits 400 is connected to the input. clock C_(TO) of data storage means comprising a flip-flop flip-flop A 520, at the setting input to one S of a flip-flop flip-flop B 530 and through a diode 515 at the reset input R_(TO) of flip-flop 520. One Q output_(TO)of the flip-flop latch 520 is fed to the second input of the AND gate 510. In this embodiment, the idle state of the reset output R is shown as high instead of low as in the embodiments of Figures 1 and 3.

Clock input C_(B) of flip-flop 530 is an output X of count string 134 that has a period of 5.82 ms. Data input D (B) of flip-flop 530 is held at zero and output Q (B) is fed as data input D (A) of flip-flop flip-flop 520. An RC 560 circuit is connected to the zeroing input R (A) so that when R goes low, R (A) goes low simultaneously by diode 515, but when R goes high again, the Voltage across R (A) grows only gradually as determined by the RC time constant of the 560 circuit.

The operation of the circuit of Figure 4 will now be described with reference to Figure 5 in which:

Trace A shows a main interrogation pulse I preceded by a short carrier pulse P;

trace B shows the resulting course of the reset signal R from output 440;

Trace C shows the corresponding course of the voltage at the zeroing input R (A) of flip-flop 520; Y

Trace D shows the Q (A) output of flipflop 520 supplied to AND gate 510.

In the rest condition the reset signal R is high and the output Q (A) of the flip-flop 520 is low, which inhibits the operation of the AND gate 510. S, Q (B) and D ( A) are all tall. The subsequent presence of a 132 kHz carrier signal P at input 400 causes R to go low (see trace B in Figure 5), which eliminates zeroing signals from inputs R (A) and S . At the termination of the carrier signal pulse, the reset signal R goes high, which passes the current value of D (A) as the output Q (A) supplied to the AND gate 510 by a clock pulse. There are two alternatives.

The first case is when the carrier pulse is shorter than 2.91 ms, that is, half the period of X. In this case the clock input C (B) remains low and therefore Q (B) remains high and thereby a high signal is supplied to AND gate 510 to activate the transponder to respond to a subsequent main interrogation signal I.

The second case is when the P signal of the carrier pulse is longer than 2.91 ms. Here X goes high after 2.91 ms so that Q (B) is turned low, and thus upon termination of the carrier pulse P a low signal continues to be fed to AND gate 510, inhibiting the response by the transponder. Thus it can be seen that the logical value Q (B) is dependent on the length of an input carrier pulse.

The circuit of Figure 4 performs a further check of the validity of the interrogation signal in which, unless the main interrogation pulse I follows the initial pulse P within a period defined by the reset time of the circuit RC 560, R (A) grows to zero flipflop 520.

The label system of Figure 1 can be combined as appropriate with the label system of Figure 3 or Figure 4.

Although the invention has been described in relation to transponder devices, it can also be used in connection with unidirectional devices such as simple data storage devices and beacons.