Method for manufacturing semiconductor device

The present invention relates to a semiconductor device having a circuit including at least one semiconductor element such as a transistor, and a manufacturing method thereof, for example, to an electronic device equipped with a power device mounted in a power supply circuit, a semiconductor integrated circuit including a memory, a thyristor, a converter, an image sensor, or the like, an electro-optical device such as a liquid crystal display device, or a light-emitting display device having a light-emitting element as a component.

In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all classified as semiconductor devices.

As typified by liquid crystal display devices, transistors formed on glass substrates and the like are made of amorphous silicon, polycrystalline silicon, and the like. Amorphous silicon-based transistors have low field-effect mobility but are compatible with large-area glass substrates. Polycrystalline silicon-based transistors have high field-effect mobility but are not suitable for large-area glass substrates.

In contrast to transistors using silicon, techniques for manufacturing transistors using oxide semiconductors and applying them to electronic devices and optical devices have been attracting attention. For example, Patent Documents 1 and 2 disclose techniques for manufacturing transistors using zinc oxide or In-Ga-Zn-O-based oxides as oxide semiconductors and using them as switching elements for pixels of display devices.

Regarding the oxide semiconductor used in such a transistor, it has been stated that "the oxide semiconductor is insensitive to impurities, and there is no problem even if a considerable amount of metal impurities are contained in the film, and inexpensive soda-lime glass containing a large amount of alkali metal such as sodium can also be used" (see Non-Patent Document 1).

<p><patcit num="1"><text>JP 2007-123861 A</text></patcit><patcit num="2"><text>JP 2007-96055 A</text></patcit></p>

<p><nplcit><text>Kamiya, Nomura, and Hosono, "Physical properties of amorphous oxide semiconductors and the current status of device development," Solid State Physics, September 2009, Vol. 44, pp. 621-633</text></nplcit></p>

<p>In a device manufacturing process, the electrical conductivity of an oxide semiconductor may change if hydrogen or water, which serves as a carrier supply source, is mixed in. Such a phenomenon can cause fluctuations in the electrical characteristics of a transistor using an oxide semiconductor.</p><p>In addition, there is a possibility that electrical characteristics of a semiconductor device including an oxide semiconductor may change when irradiated with visible light or ultraviolet light.</p><p>In view of the above problems, an object of the present invention is to provide a semiconductor device including an oxide semiconductor film with stable electrical characteristics and to manufacture a highly reliable semiconductor device.</p><p>Another object of the present invention is to provide a manufacturing process for a semiconductor device that enables mass production of highly reliable semiconductor devices by using a large substrate such as a mother glass.</p>

<p>One embodiment of the present invention is to form a crystalline oxide semiconductor film without going through multiple steps by using differences in atomic weights of multiple types of atoms contained in an oxide semiconductor target in the same sputtering step, preferentially depositing zinc with a small atomic weight on an oxide insulating film, forming a seed crystal having a hexagonal crystal structure containing zinc on at least the surface of the deposited film during the film formation, and depositing tin, indium, or the like having a large atomic weight on the seed crystal while causing crystal growth. Note that the seed crystal containing zinc is not limited to being formed on the surface of the deposited film during the film formation, and the seed crystal may be formed from the interface of the oxide insulating film. Furthermore, the present invention is to form a crystalline oxide semiconductor film that is single crystal or substantially single crystal by forming a crystalline oxide semiconductor film by performing crystal growth using a seed crystal having a hexagonal crystal structure containing zinc as a nucleus.</p><p>Another embodiment of the present invention is to form a seed crystal having a hexagonal crystal structure containing zinc over an oxide insulating film formed over a substrate by a sputtering method, and grow a crystal using the seed crystal as a nucleus to form a crystalline oxide semiconductor film having the crystals having a hexagonal crystal structure, and to manufacture a transistor using the crystalline oxide semiconductor film.</p><p>The crystalline oxide semiconductor film is formed by a sputtering method while performing a first heat treatment at 250° C. to 350° C. in an atmosphere containing oxygen. Therefore, the first heat treatment is performed in a treatment chamber. In addition, in a sputtering apparatus used for the above film formation, the distance between the target and the substrate is set to a distance that allows an element with a small atomic weight to arrive preferentially on the substrate. As a result, zinc is preferentially deposited on the oxide insulating film, and the deposited zinc is oxidized to form a seed crystal having a hexagonal crystal structure containing zinc, typically a seed crystal having zinc oxide having a hexagonal crystal structure. For this reason, a seed crystal grown from a surface of the oxide insulating film can be formed. Furthermore, by subsequently performing sputtering, a crystal is grown using the seed crystal having a hexagonal crystal structure containing zinc as a nucleus, and a crystalline oxide semiconductor film having a hexagonal crystal structure, a bond having a hexagonal lattice in an ab plane parallel to the substrate surface that is the film formation surface, and a c axis approximately perpendicular to the substrate plane approximately parallel to the ab plane can be formed.</p><p>A crystalline oxide semiconductor film having hexagonal crystals with bonds forming a hexagonal lattice in the ab plane and a c-axis perpendicular to the substrate plane has a highly regular crystal structure. A planar TEM photograph of the crystalline oxide semiconductor film is shown in FIG. 17, and a partially enlarged view of the photograph, in which atoms are surrounded by white lines to make the hexagonal lattice easier to see, is shown in FIG. 18. A transistor having such a crystalline oxide semiconductor film has stable electrical characteristics and is highly reliable.</p><p>One of the reasons why a transistor including a crystalline oxide semiconductor film has high reliability will be described below.</p><p>Compared to amorphous oxide semiconductors, crystalline oxide semiconductors have regular metal-oxygen bonds (-MOM-, where O is an oxygen atom and M is a metal atom). In other words, when an oxide semiconductor has an amorphous structure, the coordination number may vary depending on the individual metal atoms, but in crystalline oxide semiconductors, it is almost constant. This reduces microscopic oxygen vacancies, and has the effect of reducing the movement and instability of charges due to the desorption of hydrogen atoms (including hydrogen ions) and alkali metal atoms in the "space" as described below.</p><p>On the other hand, in the case of an amorphous structure, the coordination number differs for each metal atom, so the concentration of metal atoms and oxygen atoms becomes microscopically non-uniform, and there may be some places where no atoms exist ("voids"). In such "voids", for example, hydrogen atoms (including hydrogen ions) and alkali metal atoms are captured, and in some cases they are thought to bond with oxygen. It is also possible for these atoms to move through such "voids".</p><p>Such atomic movement leads to fluctuations in the characteristics of the oxide semiconductor, and the presence of these atoms is a major problem in terms of reliability. In particular, such atomic movement occurs when a high electric field or light energy is applied, and therefore, when the oxide semiconductor is used under such conditions, the characteristics become unstable. In other words, the reliability of the amorphous oxide semiconductor is inferior to that of the crystalline oxide semiconductor.</p><p>Below, the results of different reliability of actually obtained transistors (samples 1 and 2) are described. However, in the actually obtained sample 2 described below, a first material film was formed at a film formation temperature of 200°C, and then heated at 450°C in a nitrogen atmosphere, and a second material film was formed at a film formation temperature of 200°C, and then heated at 450°C in a dry air atmosphere to obtain a crystalline oxide semiconductor film. Sample 2 is a crystalline semiconductor film in which the first material film and the second material film are the same, but it goes without saying that the same can be said even if they are different.</p><p>Sample 1 used for comparison was obtained by heating a single-layer material film at 650° C. by RTA and then heating it at 450° C. in a dry air atmosphere to obtain a crystalline oxide semiconductor film.</p><p>As a test method for checking reliability, the Id-Vg curve of a transistor is measured by measuring the current (Id) flowing between the drain and source electrodes of the transistor when the voltage (Vg) between the gate and source electrodes of the transistor is changed while irradiating light. Note that in transistors using an oxide semiconductor film, there is degradation in which the threshold voltage of the transistor changes when a -BT test is performed while irradiating light, that is, when a negative gate bias is applied. This degradation is also called negative bias light degradation.</p><p>FIG. 19 shows the negative bias stress stress photodegradation of Samples 1 and 2.</p><p>In FIG. 19, sample 2 has a smaller change in Vth than sample 1.</p><p>Next, the transistor of sample 1 (L/W=3 μm/50 μm) was exposed to light (wavelength 400 nm, irradiation intensity 3.5 mW/cm) for 600 seconds.²The photoresponse was measured before and after irradiation with light. A photoresponse graph (photocurrent time dependency graph) created from the results is shown in Figure 20(A).</p><p>Note that Vd is 0.1V.</p><p>In addition, the transistor of sample 2 (L/W = 3 μm/50 μm) was exposed to light (wavelength 400 nm, irradiation intensity 3.5 mW/cm) for 600 seconds.²The photoresponse was measured before and after irradiation with light. A photoresponse graph (photocurrent time dependency graph) created from the results is shown in Figure 20(B).</p><p>In addition, measurements were also performed under the same fabrication conditions as Sample 2, but with a larger W width (L/W = 30 μm/10,000 μm), and under the same fabrication conditions as Sample 2, but with a larger W width and an even larger Vd (Vd = 15 V). Fitting was performed to determine the relaxation times (τ₁and τ₂The calculated results and maximum current value (Imax) are shown in Table 1.</p><p><tables><img file="JP7584586B2_D0001.tif" /></tables></p><p>In addition, there are two types of relaxation times (τ₁and τ₂) is a value that depends on the trap density. τ₁and τ₂The method for calculating this is called the light response defect evaluation method.</p><p>From Table 1, it can be seen that Sample 2, which has smaller negative bias light photodegradation, has faster photoresponse than Sample 1. From these, it can be found that the smaller the negative bias light photodegradation, the faster the photoresponse.</p><p>One of the reasons will be explained below. If a deep donor level exists and holes are trapped in the donor level, then in the case of negative bias light photodegradation, the negative bias applied to the gate will turn them into fixed charges, and as a result, in the case of photoresponse, the relaxation time of the current value may become long. It is expected that the reason why transistors using crystalline oxide semiconductor films have small negative bias light photodegradation and fast photoresponse is that the density of the donor levels that trap the above-mentioned holes is small. Figure 21 shows a schematic diagram of the expected donor levels.</p><p>In addition, to investigate the change in the donor level depth and density, low-temperature PL measurements were performed. Figure 22 shows the results when the substrate temperature during the deposition of the oxide semiconductor film was 400°C and when the substrate temperature during the deposition of the oxide semiconductor film was 200°C.</p><p>22, when the substrate temperature during deposition of the oxide semiconductor film is 400° C., the peak intensity at approximately 1.8 eV is significantly reduced compared to that at a substrate temperature of 200° C. This measurement result suggests that the donor level depth remains unchanged but the density is significantly reduced.</p><p>In addition, the conditions of the substrate temperature during the formation of the oxide semiconductor film were changed, and the respective conditions were compared and evaluated for a single film.</p><p>Sample A is a quartz substrate (thickness 0.5 mm) on which an oxide semiconductor film is formed to a thickness of 50 nm. The oxide semiconductor film is formed under the following conditions: an oxide semiconductor target (In-Ga-Zn-O-based oxide semiconductor target (In₂O₃:Ga₂O₃The conditions were as follows: a ZnO gas phase with a molar ratio of 1:1:2 (ZnO:ZnO = 1:1:2 [molar ratio]), a distance between the substrate and the target of 60 mm, a substrate temperature of 200°C, a pressure of 0.4 Pa, a direct current (DC) power of 0.5 kW, and a mixed atmosphere of argon (30 sccm) and oxygen (15 sccm).</p><p>ESR (electron spin resonance) was measured at room temperature (300K) and the magnetic field value (H₀) from the equation g=hv/βH₀Using this we can obtain a parameter called g, where h is the Planck constant and β is the Bohr magneton, both of which are constants.</p><p>A graph showing the g value of sample A is shown in FIG.</p><p>Moreover, after forming a film under the same conditions as Sample A, heating was performed in a nitrogen atmosphere at 450° C. for 1 hour to obtain Sample B. A graph showing the g value of Sample B is shown in FIG.</p><p>In addition, after forming a film under the same conditions as Sample A, it is heated at 450° C. for 1 hour in a mixed atmosphere of nitrogen and oxygen to obtain Sample C. A graph showing the g value of Sample C is shown in FIG.</p><p>In the graph of the g value of sample B, a signal of g = 1.93 was confirmed, and the spin density was 1.8 × 10¹⁸[spins/cm³On the other hand, in the ESR result of sample C, a signal at g=1.93 cannot be confirmed, and therefore the signal at g=1.93 is attributed to a metal dangling bond in the oxide semiconductor film.</p><p>Samples D, E, F, and G are obtained by forming an oxide semiconductor film having a thickness of 100 nm on a quartz substrate (thickness 0.5 mm). The oxide semiconductor film was formed under the following conditions: using an oxide semiconductor target (In-Ga-Zn-O-based oxide semiconductor target (In₂O₃:Ga₂O₃The conditions were as follows: ZnO = 1:1:2 [molar ratio], the distance between the substrate and the target was 60 mm, the pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and the atmosphere was a mixture of argon (30 sccm) and oxygen (15 sccm). Samples D, E, F, and G had different substrate temperatures during film formation: room temperature for sample D, 200°C for sample E, 300°C for sample F, and 400°C for sample G.</p><p>The ESR spectra of samples D, E, F, and G are shown in Figure 24.</p><p>In sample G, where the substrate temperature during deposition (denoted as Tsub) was 400°C, a signal of g=1.93 was confirmed, and the spin density was 1.3×10¹⁸[spins/cm³The spin density is comparable to that of the signal with g=1.93 obtained from sample B.</p><p>Figure 25, which shows the results of ESR measurement of sample B, shows the difference in g value (anisotropy) between when a magnetic field is applied perpendicular to the substrate surface (spectrum shown by solid line) and when it is applied parallel to the substrate surface (spectrum shown by dotted line).</p><p>Moreover, the results of ESR measurements on Sample H, which was formed under the same conditions as Sample G and then heated in a nitrogen atmosphere at 450°C for 1 hour, are shown in Figure 26. Figure 26 shows the difference in g value (anisotropy) between when a magnetic field is applied perpendicular to the substrate surface (spectrum shown by a solid line) and when it is applied parallel to the substrate surface (spectrum shown by a dotted line).</p><p>Comparing Figures 25 and 26, we can see that at a substrate temperature of 200°C, the change in g value due to anisotropy, Δg, was less than 0.001, whereas at a substrate temperature of 400°C, it became larger, Δg~0.003. It is generally known that the better the crystallinity (the more aligned the orbitals are), the greater the anisotropy, and we can conclude that the film with a substrate temperature of 400°C has more aligned metal dangling bonds formed by heating at 450°C for 1 hour in a nitrogen atmosphere than the film with a substrate temperature of 200°C, i.e., it has better crystallinity.</p><p>In addition, ESR measurements were performed by changing the thickness of the oxide semiconductor film. In the obtained ESR spectrum, the change in the intensity of the g=1.93 signal is shown in Fig. 27, and the total number of spins is shown in Fig. 28. From the results in Figs. 27 and 28, it was confirmed that the intensity of the g=1.93 signal increases as the thickness of the oxide semiconductor film increases. This suggests that the dangling bonds causing the g=1.93 signal are not present at the interface between the quartz substrate and the oxide semiconductor film or on the surface of the oxide semiconductor film, but are present in the bulk.</p><p>These results show that the metal dangling bonds have anisotropy, and that the anisotropy increases as the film formation temperature increases due to better crystallinity. In addition, it is clear that the metal dangling bonds exist in the bulk, not at the interface or surface.</p><p>These results confirmed that the anisotropy of the g value increases when the substrate temperature during film formation is increased, which is believed to be due to improved crystallinity. In addition, the dangling bonds causing the g=1.93 signal are film thickness dependent, suggesting that they are due to dangling bonds present in the IGZO bulk.</p><p>Note that the oxide insulating film in contact with the crystalline oxide semiconductor film is preferably formed using an oxide insulating film from which part of oxygen is released by heating. As the oxide insulating film from which part of oxygen is released by heating, an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric ratio is preferably used. By performing second heat treatment after the formation of the crystalline oxide semiconductor film, oxygen contained in the oxide insulating film can be diffused into the crystalline oxide semiconductor film or to the interface between the oxide insulating film and the crystalline oxide semiconductor film, and oxygen vacancies in the crystalline oxide semiconductor film can be reduced. The second heat treatment is performed at a temperature of 150° C. or higher and lower than the distortion point of the substrate, preferably 250° C. or higher and 450° C. or lower.</p><p>Furthermore, by setting the pressure in the processing chamber of the sputtering apparatus to 0.4 Pa or less, it is possible to reduce the inclusion of impurities such as alkali metals and hydrogen in the film-forming surface and film-forming object. Note that hydrogen contained in the film-forming object may be contained as hydrogen atoms, hydrogen molecules, water, hydroxyl groups, or hydrides.</p><p>In addition, the distance between the targets (TS distance) is set to 40 mm or more and 300 mm or less (preferably 60 mm or more). The larger the TS distance, the more zinc, which has the smallest atomic weight among the metal elements contained in the sputtering target for oxide semiconductor, deposits preferentially on the substrate side over other elements with large atomic weights, forming bonds with a hexagonal lattice. Therefore, the larger the TS distance, the more preferable it is.</p><p>In addition, when forming a film by sputtering, the temperature of the surface to be formed is set to 250°C or higher, preferably below the upper limit of the heat treatment temperature of the substrate. 250°C is the temperature at which impurities such as water and hydrogen are prevented from being mixed into the object to be formed and the impurities are released into the gas phase in the chamber. In addition, the upper limit of the temperature of the surface to be formed when forming a film by sputtering is set to the upper limit of the heat treatment temperature of the substrate or the upper limit of the temperature of the object to be formed (the temperature at which the components during film formation change significantly when the temperature is exceeded).</p><p>In addition, the leak rate of the sputtering equipment processing chamber was set to 1×10^-10Pam³By setting the rate at or below 1/sec, it is possible to reduce the inclusion of impurities such as alkali metals and hydrides into the crystalline oxide semiconductor film during film formation by a sputtering method. In addition, by using an adsorption vacuum pump as an exhaust system, it is possible to reduce the backflow of impurities such as alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, and hydrides from the exhaust system.</p><p>By setting the purity of the target to 99.99% or more, it is possible to reduce alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, hydrides, and the like contaminated in the crystalline oxide semiconductor film. Furthermore, by using the target, the concentration of alkali metals such as lithium, sodium, and potassium in the crystalline oxide semiconductor film can be reduced.</p><p>By forming a crystalline oxide semiconductor film under the above film formation conditions, the material is refined during film formation, and the concentration of the alkali metal is reduced to 5×10¹⁶atoms/cm³Below, the concentration of hydrogen is 1×10¹⁹atoms/cm³A crystalline oxide semiconductor film with extremely reduced impurities can be formed as follows: By reducing the impurities in the crystalline oxide semiconductor film, crystal growth of the seed crystal and the crystalline oxide semiconductor film is further promoted, and a single-crystal or substantially single-crystal crystalline oxide semiconductor film can be formed.</p><p>In addition, a top-gate transistor or a bottom-gate transistor can be appropriately used as the structure of the transistor. In manufacturing a top-gate transistor, one of the features is that a seed crystal having a hexagonal crystal structure containing zinc is formed by a sputtering method on an oxide insulating film formed on an insulating surface, a crystal is grown using the seed crystal as a nucleus to form a crystalline oxide semiconductor film having a hexagonal crystal structure, the crystalline oxide semiconductor film is subjected to heat treatment, and then the heat-treated crystalline oxide semiconductor film is selectively etched, a pair of electrodes is formed on the selectively etched crystalline oxide semiconductor film, a gate insulating film is formed over the selectively etched crystalline oxide semiconductor film and the pair of electrodes, and a gate electrode is formed on the gate insulating film. Another feature of manufacturing a bottom-gate transistor is that a gate electrode is formed over an insulating surface, a gate insulating film including an oxide insulating film is formed over the gate electrode, a seed crystal having a hexagonal crystal structure containing zinc is formed over the gate insulating film by a sputtering method, and a crystalline oxide semiconductor film having the crystals with a hexagonal crystal structure is formed by growing a crystal using the seed crystal as a nucleus, the crystalline oxide semiconductor film is subjected to heat treatment, and the heat-treated crystalline oxide semiconductor film is selectively etched, and a pair of electrodes is formed over the selectively etched crystalline oxide semiconductor film.</p>

<p>By manufacturing a transistor having a channel region made of a crystalline oxide semiconductor film having crystals with a hexagonal structure, which has bonds with a hexagonal lattice in the ab plane and has a c-axis approximately perpendicular to a substrate plane approximately parallel to the ab plane, the amount of change in threshold voltage of the transistor can be reduced even before and after light irradiation or bias-thermal stress (BT) testing, and a transistor with stable electrical characteristics can be manufactured. Furthermore, by setting the first heat treatment and the second heat treatment to 450° C. or lower, it is possible to mass-produce highly reliable semiconductor devices using a large substrate such as mother glass.</p>

<figref num="1">1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.</figref><figref num="2">1A to 1C are top views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention.</figref><figref num="3">FIG. 2 is a schematic diagram illustrating a sputtering apparatus.</figref><figref num="4">FIG. 2 is a schematic diagram illustrating the crystal structure of a seed crystal.</figref><figref num="5">1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention.</figref><figref num="6">1A to 1C are top views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention.</figref><figref num="7">1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention.</figref><figref num="8">1A to 1C are top views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention.</figref><figref num="9">1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention.</figref><figref num="10">1A to 1C are top views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention.</figref><figref num="11">1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention.</figref><figref num="12">1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention.</figref><figref num="13">FIG. 2 is an example of a top view of a manufacturing apparatus for manufacturing one embodiment of the present invention.</figref><figref num="14">1A to 1C are a cross-sectional view, a top view, and a circuit diagram illustrating one embodiment of the present invention.</figref><figref num="15">1A and 1B are a block diagram and a circuit diagram illustrating one embodiment of the present invention.</figref><figref num="16">1A to 1C are external views of an electronic device illustrating one embodiment of the present invention.</figref><figref num="17">This is a planar TEM photograph.</figref><figref num="18">This is an enlarged view of a portion of Figure 17, with one of the hexagons indicated by a white line.</figref><figref num="19">1A and 1B are diagrams illustrating negative bias stress stress photodeterioration.</figref><figref num="20">FIG. 13 is a graph illustrating the time dependence of photocurrent.</figref><figref num="21">FIG. 2 is a schematic diagram illustrating a donor level.</figref><figref num="22">FIG. 1 is a diagram illustrating the results of low-temperature PL measurements.</figref><figref num="23">FIG. 1 is a diagram illustrating the measurement results of ESR.</figref><figref num="24">FIG. 1 is a diagram illustrating the measurement results of ESR.</figref><figref num="25">FIG. 1 is a diagram illustrating the measurement results of ESR.</figref><figref num="26">FIG. 1 is a diagram illustrating the measurement results of ESR.</figref><figref num="27">FIG. 1 is a diagram illustrating the measurement results of ESR.</figref><figref num="28">FIG. 1 is a diagram illustrating the measurement results of ESR.</figref>

The embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the present invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted.

In addition, in each figure described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

In addition, the terms "first," "second," "third," etc., used in this specification are used to avoid confusion of components and are not intended to limit the number. Therefore, for example, "first" can be appropriately replaced with "second" or "third" to explain.

(Embodiment 1) In this embodiment, a method for manufacturing a crystalline oxide semiconductor and a method for manufacturing a transistor using the oxide semiconductor will be described with reference to Figures 1 and 2. Figure 1 is a cross-sectional view illustrating a manufacturing process of a transistor, which is one mode of a semiconductor device, and the cross-sectional view taken along dashed dotted line AB in Figure 2 corresponds to Figure 1(E). In this embodiment, a transistor with a top-gate structure will be described.

As shown in FIG. 1(A), an oxide insulating film 53 is formed on a substrate 51 .

The substrate 51 must have at least a heat resistance sufficient to withstand the subsequent heat treatment. When a glass substrate is used as the substrate 51, it is preferable to use a substrate having a distortion point of 730° C. or higher. For the glass substrate, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used.₂O₃It is preferable to use a glass substrate containing more BaO. When the substrate 51 is a mother glass, the size of the substrate may be the first generation (320 mm×400 mm), the second generation (400 mm×500 mm), the third generation (550 mm×650 mm), the fourth generation (680 mm×880 mm, or 730 mm×920 mm), the fifth generation (1000 mm×1200 mm, or 1100 mm×1250 mm), the sixth generation (1500 mm×1800 mm), the seventh generation (1900 mm×2200 mm), the eighth generation (2160 mm×2460 mm), the ninth generation (2400 mm×2800 mm, or 2450 mm×3050 mm), the tenth generation (2950 mm×3400 mm), or the like. Mother glass shrinks significantly when the processing temperature is high and the processing time is long, so when using mother glass for mass production, it is desirable to carry out the heat treatment in the manufacturing process at 600°C or less, preferably 450°C or less.

Instead of the above glass substrate, a substrate made of an insulating material such as a ceramic substrate, a quartz substrate, or a sapphire substrate can be used. In addition, crystallized glass can be used. Furthermore, a semiconductor substrate such as a silicon wafer or a conductive substrate made of a metal material on which an insulating film is formed can also be used.

The oxide insulating film 53 is formed using an oxide insulating film from which part of oxygen is released by heating.

As the oxide insulating film from which part of oxygen is released by heating, an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric ratio is preferably used. The oxide insulating film from which part of oxygen is released by heating can diffuse oxygen into the crystalline oxide semiconductor film by heating.

The oxide insulating film 53 can be typically formed using silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, hafnium oxide, yttrium oxide, or the like.

An oxide insulating film that contains more oxygen than the stoichiometric ratio releases some of the oxygen when heated. The amount of oxygen released at this time was calculated as 1.0×10¹⁸atoms/cm³More than 1.0×10²⁰atoms/cm³More preferably, 3.0×10²⁰atoms/cm³That's all.

Here, a method for measuring the amount of released oxygen converted into oxygen atoms by TDS analysis will be described below.

The amount of gas released during TDS analysis is proportional to the integral value of the spectrum. Therefore, the amount of gas released can be calculated from the ratio of the integral value of the spectrum of the oxide insulating film to the reference value of the standard sample. The reference value of the standard sample is the ratio of the density of a given atom to the integral value of the spectrum of a sample containing that atom.

For example, the amount of oxygen molecules released from the oxide insulating film (N(O₂)) can be calculated using Equation 1. Here, it is assumed that all the spectra detected at mass number 32 obtained by TDS analysis are derived from oxygen molecules.₃Although there is OH, it is unlikely to exist and will not be considered here. In addition, oxygen molecules containing oxygen atoms with mass numbers 17 and 18, which are isotopes of oxygen atoms, will not be considered because their abundance in nature is extremely small.

N(O₂)=N(H₂)/S(H₂)×S(O₂) × α (Number 1)

N(H₂) is the density of hydrogen molecules desorbed from the standard sample.₂) is the integral value of the spectrum when the standard sample is analyzed by TDS. Here, the reference value of the standard sample is N(H₂)/S(H₂) S(O₂) is the integral value of the spectrum obtained by TDS analysis of the oxide insulating film. α is a coefficient that affects the spectrum intensity in the TDS analysis. For details of Formula 1, refer to Japanese Patent No. 3298974. Note that the amount of oxygen released from the oxide insulating film was measured using a thermal desorption analyzer EMD-WA1000S/W manufactured by Electro-Science Corporation, and a standard sample of 1×10¹⁶atoms/cm³The measurement is performed using a silicon wafer containing hydrogen atoms.

In addition, in TDS analysis, some of the oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above α includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can also be estimated by evaluating the amount of released oxygen molecules.

In addition, N(O₂) is the amount of released oxygen molecules. In the oxide insulating film, the amount of released oxygen converted into oxygen atoms is twice the amount of released oxygen molecules.

The oxide insulating film 53 has a thickness of 50 nm or more, preferably, 200 nm or more and 500 nm or less.

By making the oxide insulating film 53 thicker, the amount of oxygen released from the oxide insulating film 53 can be increased, and the increase in the amount of oxygen released can reduce defects at the interface between the oxide insulating film 53 and an oxide semiconductor film that will be formed later.

The oxide insulating film 53 is formed by a sputtering method, a CVD method, or the like. Note that an oxide insulating film from which part of oxygen is released by heating is preferably formed by a sputtering method because it can be easily formed.

In the case where an oxide insulating film that releases part of oxygen by heating is formed by a sputtering method, it is preferable that the oxygen content in the deposition gas is high, and oxygen, a mixed gas of oxygen and a rare gas, or the like can be used. Typically, the oxygen concentration in the deposition gas is preferably 6% or more and 100% or less.

In the case of forming a silicon oxide film as a representative example of an oxide insulating film that releases a portion of oxygen by heating, quartz (preferably synthetic quartz) is used as a target, the substrate temperature is 30°C to 450°C (preferably 70°C to 200°C), the distance between the substrate and the target (TS distance) is 20 mm to 400 mm (preferably 40 mm to 200 mm), the pressure is 0.1 Pa to 4 Pa (preferably 0.2 Pa to 1.2 Pa), the high-frequency power source is 0.5 kW to 12 kW (preferably 1 kW to 5 kW), and O in the film-forming gas is 0.01 Pa to 0.05 Pa.₂/(O₂It is preferable to form a silicon oxide film by RF sputtering with a ratio of 1% to 100% (preferably 6% to 100%). Note that a silicon target can be used instead of the quartz (preferably synthetic quartz) target. Note that only oxygen can be used as the film formation gas.

When a glass substrate containing impurities such as alkali metals is used, a silicon nitride film, an aluminum nitride film, or the like may be formed as a nitride insulating film between the substrate 51 and the oxide insulating film 53 in order to prevent the intrusion of the alkali metals. The nitride insulating film can be formed by a CVD method, a sputtering method, or the like. Since alkali metals such as lithium, sodium, and potassium are impurities, it is preferable to reduce the content of these metals.

Next, an oxide semiconductor film with a thickness of 30 nm to 50 μm is formed over the oxide insulating film 53 by sputtering using a sputtering apparatus.

Here, the processing chamber of the sputtering apparatus will be described with reference to Fig. 3(A). An exhaust means 33 and a gas supply means 35 are connected to the processing chamber 31. A substrate support 40 and a target 41 are provided in the processing chamber 31. The target 41 is connected to a power supply unit 37.

The processing chamber 31 is grounded. The leak rate of the processing chamber 31 is set to 1×10^-10Pam³By setting the sputtering time to 100 s or less, it is possible to reduce the inclusion of impurities in a film formed by sputtering.

To reduce the leak rate, it is necessary to reduce not only external leaks but also internal leaks.

An external leak is when gas flows in from outside the vacuum system due to a tiny hole or poor seal. An internal leak is caused by leakage from partitions such as valves in the vacuum system or gas released from internal components. The leak rate is 1×10^-10Pam³In order to keep the figure at or below 1/sec, measures must be taken to prevent both external and internal leaks.

To reduce external leakage, it is advisable to seal the opening and closing parts of the processing chamber with a metal gasket. It is preferable to use a metal material coated with iron fluoride, aluminum oxide, or chromium oxide for the metal gasket. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. In addition, by using a metal material coated with a passivation material such as iron fluoride, aluminum oxide, or chromium oxide, the release of gases including hydrogen from the metal gasket is suppressed, and internal leakage can also be reduced.

The inner wall of the processing chamber 31 is made of aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emits less gas, including hydrogen. The above-mentioned materials may be coated on alloy materials containing iron, chromium, nickel, etc. The alloy materials containing iron, chromium, nickel, etc. are rigid, heat-resistant, and suitable for processing. Here, if the surface irregularities of the members are reduced by polishing or the like to reduce the surface area, the amount of emitted gas can be reduced. Alternatively, the members of the above-mentioned film forming apparatus may be coated with a passivating material such as iron fluoride, aluminum oxide, or chromium oxide.

It is preferable that the components installed inside the processing chamber 31 are constructed solely from metal materials, and even if an observation window made of quartz or the like is installed, it is advisable to thinly coat the surface with a passivating material such as iron fluoride, aluminum oxide, or chromium oxide in order to suppress the release of gas.

Furthermore, it is preferable to provide a sputtering gas refiner immediately before introducing the sputtering gas into the processing chamber 31. In this case, the length of the piping from the refiner to the processing chamber is set to 5 m or less, preferably 1 m or less. By setting the length of the piping to 5 m or less or 1 m or less, the influence of gas released from the piping can be reduced depending on the length.

For the piping for flowing the sputtering gas from the cylinder to the processing chamber 31, it is preferable to use metal piping whose inside is coated with a passivating material such as iron fluoride, aluminum oxide, or chromium oxide. The above-mentioned piping has a smaller amount of emissions including hydrogen compared to, for example, SUS316L-EP piping, and can reduce the mixing of impurities into the deposition gas. In addition, it is preferable to use high-performance ultra-compact metal gasket joints (UPG joints) for the joints of the piping. In addition, it is preferable to use only metal materials for the piping, since this reduces the effects of released gas and external leaks compared to when resin or the like is used.

The adsorbed matter present inside the processing chamber 31 does not affect the pressure of the processing chamber because it is adsorbed on the inner wall, but it causes gas emission when the processing chamber is evacuated. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbed matter present in the processing chamber as possible and evacuate the chamber in advance. In addition, the processing chamber may be baked to promote the desorption of the adsorbed matter. By baking, the desorption speed of the adsorbed matter can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, if the adsorbed matter is removed while introducing an inert gas, the desorption speed of water and the like, which is difficult to desorb by only exhausting, can be further increased.

The exhaust unit 33 can exhaust impurities in the process chamber 31 and control the pressure in the process chamber 31. The exhaust unit 33 is preferably an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. By using the adsorption type vacuum pump, the amount of hydrogen contained in the oxide semiconductor film can be reduced.

The processing chamber 31 may be evacuated by appropriately combining a roughing pump such as a dry pump with a high vacuum pump such as a sputter ion pump, a turbo molecular pump, or a cryopump.

While turbomolecular pumps are excellent at pumping large molecules, they have low pumping capabilities for hydrogen and water. Therefore, it is effective to combine a cryopump, which has high pumping capabilities for water, with a sputter ion pump, which has high pumping capabilities for hydrogen.

Note that hydrogen contained in the oxide semiconductor film may be contained in the form of hydrogen molecules, water, a hydroxyl group, or a hydride in addition to hydrogen atoms.

The gas supply means 35 is a means for supplying a gas for sputtering the target into the processing chamber 31. The gas supply means 35 is composed of a cylinder filled with gas, a pressure regulating valve, a stop valve, a mass flow controller, and the like. Incidentally, impurities contained in the gas introduced into the processing chamber 31 can be reduced by providing a refiner in the gas supply means 35. As the gas for sputtering the target, a rare gas such as helium, neon, argon, xenon, or krypton is used. Alternatively, a mixed gas of one of the above rare gases and oxygen can be used.

The power supply 37 may be an RF power supply, an AC power supply, a DC power supply, or the like. Although not shown, if a magnet is provided inside or outside the target support that supports the target, high-density plasma can be confined around the target, improving the deposition rate and reducing plasma damage to the substrate. This method is called magnetron sputtering. Furthermore, in magnetron sputtering, if the magnet is made rotatable, the bias of the magnetic field can be reduced, thereby increasing the utilization efficiency of the target and reducing the variation in film quality within the surface of the substrate.

The substrate support 40 is grounded. The substrate support 40 is provided with a heater. The heater may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element, and may be, for example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

A metal oxide target containing zinc can be used as the target 41. Representative examples of the target 41 include In-Sn-Ga-Zn-O-based metal oxides, which are quaternary metal oxides, In-Ga-Zn-O-based metal oxides, In-Sn-Zn-O-based metal oxides, In-Al-Zn-O-based metal oxides, Sn-Ga-Zn-O-based metal oxides, Al-Ga-Zn-O-based metal oxides, and Sn-Al-Zn-O-based metal oxides, and In-Zn-O-based metal oxides and Sn-Zn-O-based metal oxides, which are binary metal oxides, can be used.

As an example of the target 41, a metal oxide target containing In, Ga, and Zn is used.₂O₃:Ga₂O₃The composition ratio is ZnO=1:1:1 [molar ratio].₂O₃:Ga₂O₃A target having a composition ratio of ZnO=1:1:2 [molar ratio], or In₂O₃:Ga₂O₃A target with a composition ratio of ZnO=1:1:4 [molar ratio], In₂O₃:Ga₂O₃A target having a composition ratio of ZnO=2:1:8 [molar ratio] can also be used.

The distance between the target 41 and the substrate 51 (TS distance) is set so that elements with small atomic weights can arrive preferentially at the oxide insulating film 53 on the substrate 51.

Next, a method for forming a crystalline oxide semiconductor film over an oxide insulating film will be described.

As shown in FIG. 3A, a substrate 51 on which an oxide insulating film 53 is formed on a substrate support 40 is placed in a process chamber 31 of a sputtering device. Next, a gas for sputtering a target 41 is introduced from a gas supply means 35 into the process chamber 31. The purity of the target 41 is 99.9% or more, preferably 99.99% or more. Next, power is supplied to a power supply device 37 connected to the target 41. As a result, ions 43 and electrons of the sputtering gas introduced from the gas supply means 35 into the process chamber 31 sputter the target 41. In this embodiment, the distance between the target 41 and the substrate 51 is such that elements with a small atomic weight can preferentially arrive and be deposited on the oxide insulating film 53 on the substrate 51. For this reason, as shown in FIG. 3B, among the elements contained in the target 41, elements 45 with a small atomic weight move preferentially toward the substrate side over elements 47 with a large atomic weight.

In the target 41 described in this embodiment, zinc has a smaller atomic weight than tin and indium. Therefore, zinc is preferentially deposited on the oxide insulating film 53. Furthermore, the atmosphere during film formation contains oxygen, and the substrate support 40 is provided with a heater for heating the substrate and the deposited film during film formation, so that the zinc deposited on the oxide insulating film 53 is oxidized to form seed crystals 55a having crystals with a hexagonal structure containing zinc, typically seed crystals having zinc oxide with a hexagonal structure.

When the target 41 contains atoms having an atomic weight smaller than that of zinc, such as aluminum, the aluminum is preferentially deposited on the oxide insulating film 53 together with the zinc.

The seed crystal 55a has a hexagonal crystal structure containing zinc, which has a bond with a hexagonal lattice in the ab plane and a c-axis approximately perpendicular to the substrate plane approximately parallel to the ab plane. Here, a hexagonal crystal structure containing zinc, which has a bond with a hexagonal lattice in the ab plane and a c-axis approximately perpendicular to the substrate plane approximately parallel to the ab plane, will be described with reference to FIG. 4. Here, zinc oxide will be used as a representative example of a hexagonal crystal structure containing zinc, and black circles indicate zinc and white circles indicate oxygen. FIG. 4(A) is a schematic diagram of zinc oxide with a hexagonal crystal structure in the ab plane, and FIG. 4(B) is a schematic diagram of zinc oxide with a hexagonal crystal structure in which the c-axis direction is the vertical direction. As shown in FIG. 4(A), zinc and oxygen are bonded to form a hexagon on the upper plane of the ab plane. Also, as shown in FIG. 4(B), layers having bonds with a hexagonal lattice formed by zinc and oxygen are stacked, and the c-axis direction is perpendicular to the ab plane.

The seed crystal 55a has one or more atomic layers having bonds with a hexagonal lattice on the ab plane in the c-axis direction.

As the sputtering gas, a rare gas (typically argon), oxygen gas, or a mixed gas of a rare gas and oxygen is appropriately used. As the sputtering gas, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydrides have been removed.

Subsequently, the target 41 is sputtered with a sputtering gas, so that atoms contained in the target are deposited on the seed crystal 55a, and at this time, the seed crystal 55a serves as a nucleus for crystal growth, so that a crystalline oxide semiconductor film 55b having a crystal with a hexagonal structure can be formed on the seed crystal 55a. Note that since the substrate 51 is heated by a heater provided on the substrate support 40, the seed crystal 55a serves as a nucleus for crystal growth of atoms deposited on the target surface while being oxidized, so that a crystalline oxide semiconductor film can be manufactured.

The heating temperature of the substrate by the heater at this time is 200° C. to 400° C., preferably 250° C. to 350° C. The first heat treatment is performed by depositing a film while heating the substrate to 200° C. to 400° C., preferably 250° C. to 350° C. The temperature of the film-depositing surface during sputtering is 250° C. to the upper limit of the heat treatment temperature of the substrate.

The crystalline oxide semiconductor film 55b grows as a crystal by oxidizing atoms with a heavy atomic weight on the surface of the target 41 and atoms with a light atomic weight sputtered after the formation of the seed crystal 55a, using the seed crystal 55a as a nucleus. As a result, like the seed crystal 55a, the crystalline oxide semiconductor film 55b has a hexagonal crystal structure containing zinc, which has bonds having a hexagonal lattice in the ab plane and has a c-axis approximately perpendicular to the substrate plane approximately parallel to the ab plane. That is, the crystalline oxide semiconductor film 55 formed by the seed crystal 55a and the crystalline oxide semiconductor film 55b has a hexagonal crystal structure containing zinc, which has bonds having a hexagonal lattice in the ab plane parallel to the surface of the oxide insulating film 53 and has a c-axis approximately perpendicular to the substrate plane approximately parallel to the ab plane. The crystalline oxide semiconductor film 55 described in this embodiment has a crystalline structure, not an amorphous structure, ideally a single crystal structure, and is a crystalline oxide semiconductor (also referred to as C Axis Aligned Crystal; CAAC OS) having a c-axis approximately perpendicular to the substrate plane.

Note that by setting the pressure of the treatment chamber containing the substrate support 40 and the target 41 to 0.4 Pa or less, inclusion of impurities such as alkali metals and hydrogen into the surface and inside of the crystalline oxide semiconductor film can be reduced.

In addition, the leak rate of the sputtering equipment processing chamber was set to 1×10^-10Pam³By setting the discharge time to 100 s or less, it is possible to reduce the inclusion of impurities such as alkali metals, hydrogen, water, a hydroxyl group, or hydrides into the crystalline oxide semiconductor film during film formation by a sputtering method. In addition, by using an adsorption-type vacuum pump as an exhaust system, it is possible to reduce the backflow of impurities such as alkali metals, hydrogen, water, a hydroxyl group, or hydrides from the exhaust system.

In addition, when the purity of the target 41 is 99.99% or higher, alkali metal, hydrogen, water, a hydroxyl group, hydride, or the like that is mixed into the crystalline oxide semiconductor film can be reduced.

In addition, by using the target, the lithium concentration in the crystalline oxide semiconductor film 55 can be increased to 5×10¹⁵cm^-3Less than or equal to 1×10¹⁵cm^-3The concentration of sodium is 5×10¹⁶cm^-3Less than or equal to 1×10¹⁶cm^-3Less than 1×10, more preferably¹⁵cm^-3The potassium concentration is 5×10¹⁵cm^-3Less than or equal to 1×10¹⁵cm^-3It can be as follows:

Alkali metals and alkaline earth metals are harmful impurities for crystalline oxide semiconductors, and it is preferable to have less of them. In particular, among alkali metals, sodium diffuses into the oxide insulating film in contact with the crystalline oxide semiconductor and becomes sodium ions (Na⁺) In addition, in the crystalline oxide semiconductor, hydrogen breaks the bonds between metal and oxygen or enters into the bonds. As a result, the transistor characteristics are deteriorated (for example, normally on (negative shift of threshold voltage), reduced mobility, etc.). In addition, hydrogen also causes variations in characteristics. Such problems become prominent when the concentration of hydrogen in the crystalline oxide semiconductor is sufficiently low. Therefore, when the concentration of hydrogen in the crystalline oxide semiconductor is 5×10¹⁹cm^-3Below, especially 5×10¹⁸cm^-3If it is below this value, it is highly desirable to have the alkali metal concentration be set to the above value.

By forming a crystalline oxide semiconductor film under the above conditions, the concentration of the alkali metal is 5×10¹⁶atoms/cm³Below, the concentration of hydrogen is 1×10¹⁹atoms/cm³A crystalline oxide semiconductor film with extremely reduced impurities can be formed as follows: By reducing the impurities in the crystalline oxide semiconductor film, crystal growth of the seed crystal and the crystalline oxide semiconductor film is promoted, and further, a crystalline oxide semiconductor film that is single crystal or substantially single crystal can be formed.

In a crystalline oxide semiconductor, oxygen that is bonded to a metal element has a lower reactivity with hydrogen than in an amorphous oxide semiconductor, and thus the generation of defects is reduced. Therefore, a transistor that uses a crystalline oxide semiconductor film as a channel region has a small change in threshold voltage before and after light irradiation or a BT test and has stable electrical characteristics.

Furthermore, in the process of forming a crystalline oxide semiconductor film, by setting one or more, preferably all, of the pressure in the process chamber, the temperature of the surface to be formed, the leak rate in the process chamber, and the purity of the target to the above conditions, it is possible to reduce the inclusion of hydrogen and alkali metals in the oxide insulating film and the crystalline oxide semiconductor film. In addition, it is possible to reduce the diffusion of hydrogen and alkali metals from the oxide insulating film to the crystalline oxide semiconductor film. Hydrogen in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, and defects are formed in the lattice from which oxygen is released (or in the portion from which oxygen is released).

For this reason, by significantly reducing the amount of impurities in the process of forming the crystalline oxide semiconductor film, it is possible to reduce defects in the crystalline oxide semiconductor film. For these reasons, a transistor that uses a crystalline oxide semiconductor film as a channel region has a small change in threshold voltage before and after light irradiation or a BT test and has stable electrical characteristics.

In this embodiment, by utilizing the difference in atomic weight contained in the target in the same sputtering process, zinc having a small atomic weight is preferentially deposited on the oxide insulating film to form a seed crystal, and tin, indium, or the like having a large atomic weight is deposited on the seed crystal while growing as a crystal, so that a crystalline oxide semiconductor film can be formed without going through multiple processes. Furthermore, since a seed crystal having a hexagonal crystal structure containing zinc is used and an oxide semiconductor having a hexagonal crystal structure is deposited, a crystalline oxide semiconductor film that is single crystal or substantially single crystal can be formed.

Note that a metal oxide that can be used for the crystalline oxide semiconductor film 55 has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. By using a metal oxide with a wide band gap in this manner, the off-state current of the transistor can be reduced.

In this embodiment, the crystalline oxide semiconductor film 55 is formed by sputtering using an In-Ga-Zn-O-based metal oxide target and a mixed gas of argon and oxygen as a sputtering gas.

Next, the substrate 51 is subjected to heat treatment to release hydrogen from the crystalline oxide semiconductor film 55 and to diffuse part of the oxygen contained in the oxide insulating film 53 into the crystalline oxide semiconductor film 55 and the vicinity of the interface of the oxide insulating film 53 with the crystalline oxide semiconductor film 55.

The heat treatment temperature is preferably a temperature at which hydrogen is released from the crystalline oxide semiconductor film 55 and part of oxygen contained in the oxide insulating film 53 is released and diffused into the crystalline oxide semiconductor film 55, and is typically set to a temperature higher than or equal to 150° C. and lower than the strain point of the substrate 51, preferably higher than or equal to 250° C. and lower than or equal to 450° C. Note that by setting the heat treatment temperature higher than the deposition temperature of the crystalline oxide semiconductor film, more part of oxygen contained in the oxide insulating film 53 can be released.

The heat treatment is preferably performed in an inert gas atmosphere, typically, in a rare gas atmosphere such as helium, neon, argon, xenon, or krypton, or in a nitrogen atmosphere.

It may also be performed in a reduced pressure atmosphere.

Through this heat treatment, hydrogen can be released from the crystalline oxide semiconductor film 55, and part of oxygen contained in the oxide insulating film 53 can be diffused to the crystalline oxide semiconductor film 55 and the oxide insulating film 53 in the vicinity of the interface between the crystalline oxide semiconductor film 55. Through this process, oxygen vacancies in the crystalline oxide semiconductor film 55 can be reduced, and oxygen can be diffused into the oxide insulating film in the vicinity of the crystalline oxide semiconductor film 55, thereby reducing defects at the interface between the oxide semiconductor film and the oxide insulating film. As a result, a crystalline oxide semiconductor film in which the hydrogen concentration and oxygen vacancies are reduced can be formed.

Next, a mask is formed over the crystalline oxide semiconductor film that has been subjected to the heat treatment, and then the crystalline oxide semiconductor film that has been subjected to the heat treatment is selectively etched using the mask to form a crystalline oxide semiconductor film 59. After that, the mask is removed (see FIG. 1C).

A photolithography process, an ink-jet method, a printing method, or the like can be appropriately used as a mask for etching the crystalline oxide semiconductor film 55. The crystalline oxide semiconductor film 55 can be etched by wet etching or dry etching as appropriate.

Next, as shown in FIG. 1D, a pair of electrodes 61 in contact with the crystalline oxide semiconductor film 59 are formed.

The pair of electrodes 61 function as a source electrode and a drain electrode.

The pair of electrodes 61 can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. A metal element selected from any one or more of manganese and zirconium may also be used. The pair of electrodes 61 may have a single-layer structure or a laminated structure of two or more layers. For example, there are a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film, and a three-layer structure in which a titanium film is laminated on the titanium film, an aluminum film is laminated on the titanium film, and a titanium film is further formed on the aluminum film.

The pair of electrodes 61 may be formed of a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide has been added. A stacked structure of the light-transmitting conductive material and the metal element may also be used.

The pair of electrodes 61 are formed by a printing method or an inkjet method. Alternatively, a conductive film is formed by a sputtering method, a CVD method, a vapor deposition method, or the like, and then a mask is formed on the conductive film and the conductive film is etched to form the pair of electrodes 61. The mask formed on the conductive film can be appropriately formed by a printing method, an inkjet method, or a photolithography method.

Here, a conductive film is formed over the crystalline oxide semiconductor film 59 and the oxide insulating film 53, and then the conductive film is etched into a predetermined shape to form the pair of electrodes 61.

Note that after forming a conductive film over the crystalline oxide semiconductor film that has been subjected to heat treatment, a mask having a projection and recess is formed using a multi-tone photomask, the crystalline oxide semiconductor film that has been subjected to heat treatment and the conductive film are etched using the mask, and then the projection and recess mask is separated by ashing, and the conductive film is selectively etched using the separated mask, so that the crystalline oxide semiconductor film and the pair of electrodes can be formed. This process can reduce the number of photomasks and the number of photolithography processes.

Next, a gate insulating film 63 is formed over the crystalline oxide semiconductor film 59 and the pair of electrodes 61 .

Next, a gate electrode 65 is formed over the gate insulating film 63 so as to overlap with the crystalline oxide semiconductor film 59 .

After that, an insulating film 69 may be formed as a protective film (see FIG. 1(E)). In addition, after contact holes are formed in the gate insulating film 63 and the insulating film 69, wirings connected to the pair of electrodes 61 may be formed.

The gate insulating film 63 can be formed as a single layer or a stack of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, or gallium oxide. Note that the gate insulating film 63 preferably contains oxygen in a portion in contact with the crystalline oxide semiconductor film 59, and is particularly preferably formed using an oxide insulating film that releases oxygen by heating like the oxide insulating film 53. By using a silicon oxide film, oxygen can be diffused into the crystalline oxide semiconductor film 59, leading to improved characteristics.

The gate insulating film 63 is made of hafnium silicate (HfSiO_x), nitrogen-doped hafnium silicate (HfSi_xO_yN_z), nitrogen-doped hafnium aluminate (HfAl_xO_yN_zGate leakage can be reduced by using a high-k material such as SiO 2 , hafnium oxide, or yttrium oxide. Furthermore, a stacked structure of a high-k material and at least one of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, and gallium oxide can be used. The thickness of the gate insulating film 63 is preferably 1 nm or more and 300 nm or less, more preferably 5 nm or more and 50 nm or less.

Note that before the gate insulating film 63 is formed, the surface of the crystalline oxide semiconductor film 59 may be exposed to plasma of an oxidizing gas such as oxygen, ozone, or nitrous oxide to oxidize the surface of the crystalline oxide semiconductor film 59 and reduce oxygen vacancies.

The gate electrode 65 can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. A metal element selected from one or more of manganese and zirconium may also be used. The gate electrode 65 may have a single-layer structure or a laminated structure of two or more layers. For example, there are a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film, and a three-layer structure in which a titanium film is laminated on the titanium film, an aluminum film is laminated on the titanium film, and a titanium film is further formed on the aluminum film.

The gate electrode 65 may be formed of a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide has been added. A stacked structure of the light-transmitting conductive material and the metal element may also be used.

The insulating film 69 can be formed using any of the insulating films listed for the gate insulating film 63 as appropriate.

Furthermore, when a silicon nitride film is formed as the insulating film 69 by a sputtering method or a CVD method, it is possible to prevent the intrusion of moisture or alkali metals from the outside, and the impurity content of the crystalline oxide semiconductor film can be reduced.

Note that heat treatment may be performed after the formation of the gate insulating film 63 or the insulating film 69. The heat treatment causes oxygen to diffuse from the gate insulating film 63 to the crystalline oxide semiconductor film. As a result, the amount of change in the threshold voltage due to the -BT test while irradiating light is suppressed as the temperature of the heat treatment is higher.

Through the above steps, the transistor 120 having a crystalline oxide semiconductor film in a channel region can be manufactured. The transistor 120 having a crystalline oxide semiconductor film in a channel region, which has crystals with a hexagonal structure having bonds with a hexagonal lattice in the ab plane and a c-axis approximately perpendicular to a substrate plane approximately parallel to the ab plane, has a small change in threshold voltage before and after light irradiation or a BT test, and therefore can have stable electrical characteristics.

(Embodiment 2) In this embodiment, a manufacturing method of a transistor having a structure different from that of Embodiment 1 will be described with reference to FIGS. 5 and 6. This embodiment differs from Embodiment 1 in that a pair of electrodes is provided between an oxide insulating film and a crystalline oxide semiconductor film. Note that the cross-sectional view of the dashed-dotted line CD in FIG. 6 corresponds to FIG. 5(D).

5A, in a manner similar to that of Embodiment 1, an oxide insulating film 53 is formed over a substrate 51. Next, a pair of electrodes 71 is formed over the oxide insulating film 53. Next, a crystalline oxide semiconductor film 73 is formed over the pair of electrodes 71 and the oxide insulating film 53.

The pair of electrodes 71 can be formed using a material and a manufacturing method similar to those of the pair of electrodes 61 described in Embodiment 1 as appropriate.

The crystalline oxide semiconductor film 73 can be formed using a material and a formation method similar to those of the crystalline oxide semiconductor film 55 described in Embodiment 1 as appropriate.

Next, the substrate 51 is heated as in Embodiment 1 to form a crystalline oxide semiconductor film in which the hydrogen concentration and oxygen vacancies are reduced, and then a mask is formed over the crystalline oxide semiconductor film in which the hydrogen concentration and oxygen vacancies are reduced, and the crystalline oxide semiconductor film in which the hydrogen concentration and oxygen vacancies are reduced is selectively etched to form the crystalline oxide semiconductor film 75. After that, the mask is removed (see FIG. 5B).

5C, a gate insulating film 77 is formed over the pair of electrodes 71 and the crystalline oxide semiconductor film 75. Next, a gate electrode 79 is formed over the gate insulating film 77 so as to overlap with the crystalline oxide semiconductor film 75. Next, an insulating film 81 may be formed over the gate insulating film 77 and the gate electrode 79 as a protective film.

The gate insulating film 77 can be formed using a material and a formation method similar to those of the gate insulating film 63 described in Embodiment 1 as appropriate.

The gate electrode 79 can be formed using a material and a manufacturing method similar to those of the gate electrode 65 described in Embodiment 1 as appropriate.

The insulating film 81 can be formed using a material and a formation method similar to those of the insulating film 69 described in Embodiment 1 as appropriate.

Next, a mask is formed on the insulating film 81, and then contact holes are formed by etching parts of the gate insulating film 77 and the insulating film 81. Next, wiring 83 is formed to connect to the pair of electrodes 71 through the contact holes.

The wirings 83 can be formed using a material and a manufacturing method similar to those of the pair of electrodes 71 as appropriate.

Through the above steps, a transistor having a crystalline oxide semiconductor film in a channel region can be manufactured. A transistor having a crystalline oxide semiconductor film in a channel region, which has crystals with a hexagonal structure having bonds with a hexagonal lattice in the ab plane and a c-axis approximately perpendicular to a substrate plane approximately parallel to the ab plane, has a small change in threshold voltage before and after light irradiation or a BT test, and therefore can have stable electrical characteristics.

Note that this embodiment mode can be appropriately combined with other embodiment modes.

(Embodiment 3) In this embodiment, a transistor different from those in Embodiments 1 and 2 will be described with reference to Fig. 7 and Fig. 8. In this embodiment, a transistor having a bottom gate structure in which a gate electrode is provided on the substrate side is different from those in Embodiments 1 and 2. Note that the cross-sectional view of the dashed and dotted line EF in Fig. 8 corresponds to Fig. 7(C).

7A, an oxide insulating film 53 is formed over a substrate 51. Next, a gate electrode 91 is formed over the oxide insulating film 53. Next, a gate insulating film 93 is formed over the oxide insulating film 53 and the gate electrode 91. Next, a crystalline oxide semiconductor film 95 is formed over the gate insulating film 93 in a manner similar to that of Embodiment 1.

The gate electrode 91 can be formed in a manner similar to that of the gate electrode 65 shown in the first embodiment.

The gate insulating film 93 can be formed in a manner similar to that of the gate insulating film 63 described in the first embodiment.

The crystalline oxide semiconductor film 95 can be formed in a manner similar to that of the crystalline oxide semiconductor film 55 described in Embodiment 1.

Next, in a manner similar to that of Embodiment 1, the crystalline oxide semiconductor film 95 is heated to form a crystalline oxide semiconductor film in which the hydrogen concentration and oxygen vacancies are reduced.

Next, a mask is formed over the crystalline oxide semiconductor film in which the hydrogen concentration and oxygen vacancies are reduced, and the crystalline oxide semiconductor film in which the hydrogen concentration and oxygen vacancies are reduced is selectively etched to form a crystalline oxide semiconductor film 99. After that, the mask is removed (see FIG. 7B).

7C, a pair of electrodes 101 are formed over the crystalline oxide semiconductor film 99. Next, an insulating film 103 is formed over the crystalline oxide semiconductor film 99 and the pair of electrodes 101.

The pair of electrodes 101 can be formed using a material and a manufacturing method similar to those of the pair of electrodes 61 described in Embodiment 1 as appropriate.

The insulating film 103 can be formed in a manner similar to that of the gate insulating film 63 described in Embodiment 1.

After this, a heat treatment may be carried out.

Through the above steps, a transistor having a crystalline oxide semiconductor film in a channel region can be manufactured. A transistor having a crystalline oxide semiconductor film in a channel region, which has crystals with a hexagonal structure having bonds with a hexagonal lattice in the ab plane and a c-axis approximately perpendicular to a substrate plane approximately parallel to the ab plane, has a small change in threshold voltage before and after light irradiation or a BT test, and therefore can have stable electrical characteristics.

Note that this embodiment mode can be appropriately combined with other embodiment modes.

(Embodiment 4) In this embodiment, a bottom-gate transistor different from that in Embodiment 3 will be described with reference to FIGS. 9 and 10. This embodiment differs from Embodiment 3 in that a pair of electrodes is provided between a gate insulating film and an oxide semiconductor film. Note that the cross-sectional view along dashed line GH in FIG. 10 corresponds to FIG. 9(D).

9(A), an oxide insulating film 53 is formed over a substrate 51. Next, a gate electrode 91 is formed over the oxide insulating film 53. Next, a gate insulating film 93 is formed over the oxide insulating film 53 and the gate electrode 91. Next, a pair of electrodes 105 is formed over the gate insulating film 93.

The pair of electrodes 105 can be formed using a material and a manufacturing method similar to those of the pair of electrodes 61 described in Embodiment 1 as appropriate.

Next, as shown in FIG. 9B, the crystalline oxide semiconductor film 107 is formed over the gate insulating film 93 in a manner similar to that of Embodiment 1.

The crystalline oxide semiconductor film 107 can be formed in a manner similar to that of the crystalline oxide semiconductor film 55 described in Embodiment 1.

Next, in a manner similar to that of Embodiment 1, the crystalline oxide semiconductor film 107 is heated to form a crystalline oxide semiconductor film in which the hydrogen concentration and oxygen vacancies are reduced.

Next, a mask is formed over the crystalline oxide semiconductor film in which the hydrogen concentration and the oxygen vacancies are reduced, and the crystalline oxide semiconductor film in which the hydrogen concentration and the oxygen vacancies are reduced is selectively etched to form the crystalline oxide semiconductor film 109. After that, the mask is removed (see FIG. 9C).

Next, as shown in FIG. 9D, a protective film 111 is formed over the crystalline oxide semiconductor film 109 and the pair of electrodes 105.

The protective film 111 can be formed in a manner similar to that of the gate insulating film 63 described in the first embodiment.

After this, a heat treatment may be carried out.

Through the above steps, a transistor having a crystalline oxide semiconductor film in a channel region can be manufactured. A transistor having a crystalline oxide semiconductor film in a channel region, which has crystals with a hexagonal structure having bonds with a hexagonal lattice in the ab plane and a c-axis approximately perpendicular to a substrate plane approximately parallel to the ab plane, has a small change in threshold voltage before and after light irradiation or a BT test, and therefore can have stable electrical characteristics.

Note that this embodiment mode can be appropriately combined with other embodiment modes.

(Embodiment 5) In this embodiment, a transistor having a plurality of gate electrodes will be described in Embodiments 1 to 4. Here, the transistor described in Embodiment 3 will be used for description; however, the transistor can be appropriately applied to Embodiments 1, 2, and 4.

As in embodiment 3, as shown in FIG. 11 , an oxide insulating film 53 is formed over a substrate 51, a gate electrode 91 and a gate insulating film 93 are formed over the oxide insulating film 53, and a crystalline oxide semiconductor film 99, a pair of electrodes 101, and an insulating film 103 are formed over the gate insulating film 93.

Next, the backgate electrode 113 is formed over the insulating film 103 so as to overlap with the crystalline oxide semiconductor film 99. Next, an insulating film 115 may be formed over the insulating film 103 and the backgate electrode 113 as a protective film.

The backgate electrode 113 can be formed in a manner similar to that of the gate electrode 65 shown in the first embodiment.

The insulating film 103 functions as a gate insulating film on the back gate electrode 113 side. The insulating film 115 can be formed in a manner similar to that of the insulating film 69 described in Embodiment 1.

The gate electrode 91 and the back gate electrode 113 may be connected to each other. In this case, the gate electrode 91 and the back gate electrode 113 have the same potential, and thus channel regions are formed on the gate insulating film 93 side and the insulating film 103 side of the crystalline oxide semiconductor film 99, thereby increasing the on-state current and the field-effect mobility of the transistor.

Alternatively, different potentials may be applied to the gate electrode 91 and the backgate electrode 113 without being connected to each other. In this case, the threshold voltage of the transistor can be controlled.

Note that in this embodiment, the pair of electrodes 101 are formed between the crystalline oxide semiconductor film 99 and the insulating film 103 ; however, they may be formed between the gate insulating film 93 and the crystalline oxide semiconductor film 99 .

Through the above steps, a transistor having a plurality of gate electrodes can be manufactured.

(Embodiment 6) In this embodiment, a method for manufacturing a transistor in which the contact resistance between a crystalline oxide semiconductor film and a pair of electrodes can be reduced compared to Embodiments 1 to 5 will be described.

1A and 1B, a crystalline oxide semiconductor film 55 is formed over an oxide insulating film 53. Next, the crystalline oxide semiconductor film 55 is heated to form a crystalline oxide semiconductor film in which the hydrogen concentration and oxygen vacancies are reduced. Next, as shown in FIG. 12A, a buffer 84 having n-type conductivity is formed over a crystalline oxide semiconductor film 57 in which the hydrogen concentration and oxygen vacancies are reduced.

The buffer 84 having n-type conductivity may be a metal oxide selected from indium oxide, indium tin oxide, indium zinc oxide, tin oxide, zinc oxide, and tin zinc oxide, or may be a material containing one or more elements selected from aluminum, gallium, and silicon in the metal oxide. With this structure, the contact resistance between the pair of electrodes functioning as a source electrode and a drain electrode to be formed later and the crystalline oxide semiconductor film can be reduced.

Here, the crystalline oxide semiconductor film is heated to release hydrogen from the crystalline oxide semiconductor film and oxygen is diffused from the oxide insulating film to the crystalline oxide semiconductor film, and then the buffer 84 having n-type conductivity is formed on the crystalline oxide semiconductor film, so that hydrogen can be sufficiently released from the crystalline oxide semiconductor film. As a result, the hydrogen concentration and oxygen vacancies in the crystalline oxide semiconductor film can be reduced, and a negative shift in the threshold voltage of the transistor can be reduced.

Next, a mask is formed over the buffer 84 having n-type conductivity, and then the crystalline oxide semiconductor film in which the hydrogen concentration and oxygen vacancies are reduced and the buffer 84 having n-type conductivity are etched to form the crystalline oxide semiconductor film 59 and the buffer 85 having n-type conductivity.

After that, the mask is removed (see FIG. 12(B)).

12C, a pair of electrodes 61 are formed over the crystalline oxide semiconductor film 59 and the buffer 85 having n-type conductivity. In order to maintain the quality of the gate insulating film, a material that does not extract oxygen from the gate insulating film is preferably used for the pair of electrodes 61. Examples of materials for the pair of electrodes 61 include tungsten, molybdenum, and the like.

However, tungsten and molybdenum form a metal oxide having high resistance in a region in contact with the crystalline oxide semiconductor film and the gate insulating film. By providing a buffer having n-type conductivity between the crystalline oxide semiconductor film 59 and the pair of electrodes 61, the contact resistance between the crystalline oxide semiconductor film 59 and the pair of electrodes 61 can be reduced.

Next, using a mask (not shown) formed on the pair of electrodes 61, the exposed portion of the buffer 85 having n-type conductivity is etched to form a pair of buffers 87 having n-type conductivity (see FIG. 12(D)).

After removing the mask formed on the pair of electrodes 61, the exposed portion of the buffer 85 having the n-type conductivity may be etched using the pair of electrodes 61 as a mask to form a pair of buffers 87 having the n-type conductivity.

When etching the buffer 85 having n-type conductivity, it is preferable to use conditions (conditions with a high etching selectivity) under which the crystalline oxide semiconductor film 59 is not etched and the buffer 85 having n-type conductivity is selectively etched. Note that when the etching selectivity of the crystalline oxide semiconductor film 59 and the buffer 85 having n-type conductivity is low, part of the crystalline oxide semiconductor film 59 is also etched during the etching of the buffer 85 having n-type conductivity, and a shape having a groove (depression portion) may be formed.

According to this embodiment, since the buffer 87 having n-type conductivity is provided between the crystalline oxide semiconductor film 59 and the pair of electrodes 61, the contact resistance between the crystalline oxide semiconductor film 59 and the pair of electrodes 61 can be reduced. As a result, a decrease in the on-current of the transistor can be suppressed. In addition, a change in the on-current (Ion deterioration) before and after application of a negative gate bias stress in a BT test can be suppressed.

Next, in the same manner as in the first embodiment, a gate insulating film 63, a gate electrode 65, and an insulating film 69 are formed (see FIG. 12(E)). After forming contact holes in the gate insulating film 63 and the insulating film 69, wirings connected to the pair of electrodes 61 may be formed.

Through the above steps, a transistor including a crystalline oxide semiconductor film in a channel formation region can be manufactured.

According to this embodiment, a buffer having n-type conductivity that reduces contact resistance between the oxide semiconductor film and the pair of wirings is formed, so that a reduction in the on-state current of a transistor can be suppressed and a change in the on-state current (Ion degradation) before and after application of a negative gate bias stress in a BT test can be suppressed.

This embodiment mode can be freely combined with other embodiment modes.

(Embodiment 7) In this embodiment, FIG. 13 shows an example of a manufacturing apparatus that performs the steps from the formation of the oxide insulating film 53 shown in Embodiment 1 to the formation of a conductive film to be a source electrode or a drain electrode in succession without exposure to air.

The manufacturing apparatus shown in Figure 13 is a single-wafer multi-chamber apparatus and includes three sputtering apparatuses 10a, 10b, and 10c, a substrate supply chamber 11 having three cassette ports 14 for accommodating substrates to be processed, load lock chambers 12a and 12b, a transport chamber 13, a substrate heating chamber 15, and the like.

A transport robot for transporting the substrate to be processed is disposed in each of the substrate supply chamber 11 and the transport chamber 13. The sputtering devices 10a, 10b, 10c, the transport chamber 13, and the substrate heating chamber 15 are preferably controlled to an atmosphere containing almost no hydrogen or moisture (an inert atmosphere, a reduced pressure atmosphere, a dry air atmosphere, etc.), and for example, a dry nitrogen atmosphere with a dew point of -40°C or less, preferably -50°C or less, with respect to moisture.

13, first, a substrate to be processed is transferred from a substrate supply chamber 11, and then moved to a substrate heating chamber 15 via a load lock chamber 12a and a transfer chamber 13. In the substrate heating chamber 15, moisture attached to the substrate to be processed is removed by a heat treatment in a vacuum atmosphere or the like. Then, the substrate to be processed is moved to a sputtering apparatus 10c via the transfer chamber 13, and an oxide insulating film 53 is formed in the sputtering apparatus 10c. The substrate to be processed is then moved to a sputtering apparatus 10a via the transfer chamber 13 without being exposed to the air. Zinc is preferentially deposited on the oxide insulating film 53 in the sputtering apparatus 10a, and then oxidized to form a seed crystal 55a having a hexagonal crystal structure containing zinc. Then, sputtering is performed in the same sputtering apparatus to form a crystalline oxide semiconductor film 55b having a hexagonal crystal structure on the seed crystal 55a, which is grown using the seed crystal 55a as a nucleus. Then, the substrate to be processed is moved to the substrate heating chamber 15 via the transfer chamber 13 without being exposed to the air, and a heat treatment is performed thereon. Then, the substrate to be processed is moved to the sputtering apparatus 10b via the transfer chamber 13 without being exposed to the air, and a conductive film for forming a source electrode and a drain electrode is formed on the crystalline oxide semiconductor film 55b using a metal target in the sputtering apparatus 10b.

In this manner, by using the manufacturing apparatus of FIG. 13, part of the transistor manufacturing process can be carried out without exposure to the air.

This embodiment mode can be freely combined with other embodiment modes.

(Embodiment 8) In this embodiment, an example of a semiconductor device with a new structure in which stored data can be retained even in a state in which power is not supplied and the number of times writing is not limited is described, using a transistor including an oxide semiconductor described in any of Embodiments 1 to 7.

The transistors including an oxide semiconductor described in any of the embodiments 1 to 7 have an extremely small off-state current, and thus can retain stored data for an extremely long period of time. That is, a refresh operation is unnecessary or the frequency of the refresh operation can be reduced extremely, so that power consumption can be sufficiently reduced. Furthermore, even when power is not supplied, stored data can be retained for a long period of time.

14 shows an example of the configuration of a semiconductor device. FIG. 14(A) shows a cross section of the semiconductor device, and FIG. 14(B) shows a plan view of the semiconductor device. Here, FIG. 14(A) corresponds to the cross sections along E1-E2 and F1-F2 in FIG. 14(B). The semiconductor device shown in FIG. 14(A) and FIG. 14(B) has a transistor 260 using a material other than an oxide semiconductor in a lower portion, and a transistor 120 using an oxide semiconductor in an upper portion. Since the transistor 120 is the same as that in the first embodiment, the same reference numerals are used in FIG. 14(A), (B), and (C) to describe the same parts as those in FIG. 1(E).

The transistor 260 has a channel formation region 216 provided in a substrate 200 containing a semiconductor material (e.g., silicon), an impurity region 214 and a high-concentration impurity region 220 (collectively referred to as simply impurity regions) provided to sandwich the channel formation region 216, a gate insulating film 208 provided on the channel formation region 216, a gate electrode 210 provided on the gate insulating film 208, and a source or drain electrode 230a and a source or drain electrode 230b electrically connected to the impurity region.

Here, a sidewall insulating film 218 is provided on the side of the gate electrode 210. In addition, a region of the substrate 200 that does not overlap with the sidewall insulating film 218 when viewed from a direction perpendicular to the surface has a high-concentration impurity region 220, and a metal compound region 224 that contacts the high-concentration impurity region 220 is present. In addition, an element isolation insulating film 206 is provided on the substrate 200 so as to surround the transistor 260, and an interlayer insulating film 226 and an interlayer insulating film 128 are provided so as to cover the transistor 260. The source or drain electrode 230a and the source or drain electrode 230b are electrically connected to the metal compound region 224 through openings formed in the interlayer insulating film 226 and the interlayer insulating film 128. In other words, the source or drain electrode 230a and the source or drain electrode 230b are electrically connected to the high-concentration impurity region 220 and the impurity region 214 through the metal compound region 224. Note that the sidewall insulating film 218 may not be formed due to integration of the transistor 260, etc.

14 includes a crystalline oxide semiconductor film 59, a pair of electrodes 61 functioning as source and drain electrodes, a gate insulating film 63, and a gate electrode 65. The transistor 120 can be obtained through the process described in Embodiment 1.

14, by improving the planarity of the interlayer insulating film 128, which is a surface on which the crystalline oxide semiconductor film 59 is formed, the thickness distribution of the crystalline oxide semiconductor film 59 can be made uniform, thereby improving the characteristics of the transistor 120. However, the channel length is short, for example, 0.8 μm or 3 μm. The interlayer insulating film 128 corresponds to the oxide insulating film 53 and is formed of the same material.

14, a capacitance is formed by one of the pair of electrodes 61, the gate insulating film 63 functioning as a dielectric, and the electrode 248. In the capacitor 265 shown in FIG.

In addition, an insulating film 69 is provided over the transistor 120 and the capacitor 265 , and a protective insulating film 110 is provided over the insulating film 69 .

In addition, wirings 242a and 242b are provided which are formed in the same process as the pair of electrodes 61. The wiring 242a is electrically connected to the source/drain electrode 230a, and the wiring 242b is electrically connected to the source/drain electrode 230b.

14C shows a circuit configuration. Note that in the circuit diagram, a reference symbol OS may also be used to indicate that the transistor includes an oxide semiconductor.

14(C), a first wiring (1st Line) and a source electrode of the transistor 260 are electrically connected, and a second wiring (2nd Line) and a drain electrode of the transistor 260 are electrically connected. A third wiring (3rd Line) and one of the source electrode or the drain electrode of the transistor 120 are electrically connected, and a fourth wiring (4th Line) and a gate electrode of the transistor 120 are electrically connected. The gate electrode of the transistor 260 and the other of the source electrode or the drain electrode of the transistor 120 are electrically connected to one of the electrodes of the capacitance element 265, and a fifth wiring (5th Line) and the other of the electrodes of the capacitance element 265 are electrically connected.

In the semiconductor device illustrated in FIG. 14C, by utilizing the feature that the potential of the gate electrode of the transistor 260 can be held, data can be written, held, and read as follows.

First, writing and holding of data will be described. First, the potential of the fourth wiring is set to a potential that turns on the transistor 120, so that the transistor 120 is turned on.

As a result, the potential of the third wiring is applied to the gate electrode of the transistor 260 and the capacitor 265. That is, a predetermined charge is applied to the gate electrode of the transistor 260 (written). Here, one of charges that apply two different potential levels (hereinafter referred to as low-level charge and high-level charge) is applied. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 120 to turn off the transistor 120, whereby the charge applied to the gate electrode of the transistor 260 is held (retained).

The off-state current of the transistor 120 is extremely small. Specifically, the off-state current at room temperature (here, the value per unit channel width (1 μm)) is 100 zA/μm (1 zA (zeptoampere) is 1×10^-21A) or less, and preferably 10 zA/μm or less, the charge in the gate electrode of the transistor 260 is held for a long time. Also, as shown in the fifth embodiment, a backgate electrode may be provided, and it is preferable to ensure that the transistor 120 is normally off by applying a voltage to the backgate electrode.

The substrate 200 may be a semiconductor substrate called silicon-on-insulator (SOI substrate). Alternatively, the substrate 200 may be an insulating substrate such as glass on which an SOI layer is formed. As an example of an SOI substrate having an SOI layer formed on a glass substrate, there is a method of forming a thin single crystal silicon layer on a glass substrate by using a hydrogen ion implantation delamination method. Specifically, an ion doping apparatus is used to implant H₃⁺A separation layer is formed at a predetermined depth from the surface of the silicon substrate by irradiating the silicon substrate with radiation, a glass substrate having an insulating film on its surface is pressed against the surface of the silicon substrate to bond them, and a heat treatment is performed at a temperature that is lower than the temperature at which separation occurs within the separation layer or at the interface, and at which the separation layer becomes weak. As a result, a part of the semiconductor substrate is separated from the silicon substrate within the separation layer or at the interface, forming an SOI layer on the glass substrate.

This embodiment can be combined with any one of the first to seventh embodiments.

(Embodiment Mode 9) In this embodiment mode, an example in which at least a part of a driver circuit and a transistor disposed in a pixel portion are manufactured over the same substrate will be described below.

The transistor disposed in the pixel portion is formed according to any one of the first to seventh embodiments.

Further, since the transistors described in any of the embodiments 1 to 7 are n-channel TFTs, part of the driver circuit that can be formed using an n-channel TFT is formed over the same substrate as the transistors in the pixel portion.

An example of a block diagram of an active matrix display device is shown in Fig. 15(A). A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a signal line driver circuit 5304 are provided on a substrate 5300 of the display device. A plurality of signal lines are arranged extending from the signal line driver circuit 5304 in the pixel portion 5301, and a plurality of scanning lines are arranged extending from the first scanning line driver circuit 5302 and the scanning line driver circuit 5303. Note that pixels having display elements are provided in a matrix shape in the intersecting regions between the scanning lines and the signal lines. The substrate 5300 of the display device is connected to a timing control circuit (also called a controller or a control IC) through a connection portion such as an FPC (Flexible Printed Circuit).

In FIG. 15A, a first scan line driver circuit 5302, a second scan line driver circuit 5303, and a signal line driver circuit 5304 are formed over the same substrate 5300 as the pixel portion 5301. Therefore, the number of components such as driver circuits provided outside is reduced, and costs can be reduced. In addition, when a driver circuit is provided outside the substrate 5300, it is necessary to extend wirings, and the number of connections between wirings increases. When a driver circuit is provided over the same substrate 5300, the number of connections between wirings can be reduced, and reliability or yield can be improved.

An example of the circuit configuration of the pixel section is shown in Figure 15(B), which shows the pixel structure of a VA type liquid crystal display panel.

In this pixel structure, one pixel has multiple pixel electrodes, and a transistor is connected to each pixel electrode. Each transistor is configured to be driven by a different gate signal. In other words, in a pixel with a multi-domain design, the signal applied to each pixel electrode is controlled independently.

A gate wiring 602 of the transistor 628 and a gate wiring 603 of the transistor 629 are separated so that different gate signals can be applied to them. On the other hand, a source or drain electrode 616 functioning as a data line is shared by the transistors 628 and 629. The transistors 628 and 629 can be any of the transistors described in Embodiments 1 to 7 as appropriate.

The first pixel electrode electrically connected to the transistor 628 and the second pixel electrode electrically connected to the transistor 629 have different shapes and are separated by a slit. The second pixel electrode is formed so as to surround the outside of the first pixel electrode spreading in a V-shape. The timing of the voltage applied to the first pixel electrode and the second pixel electrode is made different by the transistor 628 and the transistor 629, thereby controlling the alignment of the liquid crystal. The transistor 628 is connected to the gate wiring 602, and the transistor 629 is connected to the gate wiring 603. By applying different gate signals to the gate wiring 602 and the gate wiring 603, the operation timing of the transistor 628 and the transistor 629 can be made different.

Moreover, a storage capacitor is formed by the capacitance wiring 690, the gate insulating film functioning as a dielectric, and a capacitance electrode electrically connected to the first pixel electrode or the second pixel electrode.

The first pixel electrode, the liquid crystal layer, and the counter electrode overlap to form a first liquid crystal element 651. The second pixel electrode, the liquid crystal layer, and the counter electrode overlap to form a second liquid crystal element 652. A multi-domain structure is formed in which the first liquid crystal element 651 and the second liquid crystal element 652 are provided in one pixel.

Note that the pixel configuration shown in Fig. 15B is not limited to this. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel shown in Fig. 15B.

An example of the circuit configuration of the pixel portion is shown in Fig. 15(C), which shows the pixel structure of a display panel using organic EL elements.

In an organic EL element, when a voltage is applied to a light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, causing a current to flow. Then, the carriers (electrons and holes) recombine, causing the light-emitting organic compound to form an excited state, and light is emitted when the excited state returns to the ground state. Due to this mechanism, such light-emitting elements are called current-excited light-emitting elements.

FIG. 15C is a diagram showing an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device.

The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. Here, an example will be shown in which one pixel includes two n-channel transistors each having an oxide semiconductor layer in its channel formation region.

The pixel 6400 has a switching transistor 6401, a driving transistor 6402, a light emitting element 6404, and a capacitor 6403. The switching transistor 6401 has a gate electrode connected to a scanning line 6406, a first electrode (one of a source electrode and a drain electrode) connected to a signal line 6405, and a second electrode (the other of a source electrode and a drain electrode) connected to a gate electrode of the driving transistor 6402. The driving transistor 6402 has a gate electrode connected to a power line 6407 via the capacitor 6403, a first electrode connected to the power line 6407, and a second electrode connected to a first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a potential that satisfies low power supply potential&lt;high power supply potential with reference to the high power supply potential set to the power supply line 6407, and the low power supply potential may be set to, for example, GND or 0 V. To apply the potential difference between the high power supply potential and the low power supply potential to the light emitting element 6404 to cause a current to flow through the light emitting element 6404 and cause the light emitting element 6404 to emit light, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is equal to or greater than the forward threshold voltage of the light emitting element 6404.

It is to be noted that the capacitor 6403 can be omitted by substituting the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the driving transistor 6402, a capacitance may be formed between a channel formation region and a gate electrode.

Here, in the case of a voltage input voltage driving method, a video signal is input to the gate electrode of the driving transistor 6402 so that the driving transistor 6402 is in two states, fully on or off. That is, the driving transistor 6402 is operated in a linear region. To operate the driving transistor 6402 in a linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate electrode of the driving transistor 6402. Note that a voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied to the signal line 6405.

Moreover, when analog gray scale driving is performed instead of digital time gray scale driving, the same pixel configuration as that in FIG. 15C can be used by changing the signal input.

When analog grayscale driving is performed, a voltage equal to or greater than the forward voltage of the light-emitting element 6404 plus the Vth of the driving transistor 6402 is applied to the gate electrode of the driving transistor 6402. The forward voltage of the light-emitting element 6404 refers to a voltage for achieving a desired luminance, and includes at least a forward threshold voltage. It is to be noted that a current can be made to flow through the light-emitting element 6404 by inputting a video signal that causes the driving transistor 6402 to operate in a saturation region. In order to operate the driving transistor 6402 in a saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the driving transistor 6402. By making the video signal analog, a current corresponding to the video signal can be made to flow through the light-emitting element 6404, and analog grayscale driving can be performed.

Note that the pixel configuration shown in Fig. 15C is not limited to this. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be newly added to the pixel shown in Fig. 15C.

(Embodiment 10) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). Examples of electronic devices include television devices (also called televisions or television receivers), monitors for computers, cameras such as digital cameras and digital video cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game machines, personal digital assistants, sound reproduction devices, and large game machines such as pachinko machines. Examples of electronic devices equipped with the semiconductor device described in the above embodiments will be described.

16A shows a portable information terminal, which includes a main body 3001, a housing 3002, and display units 3003a and 3003b. The display unit 3003b is a touch panel, and a keyboard button 3004 displayed on the display unit 3003b can be touched to operate the screen or input characters. Of course, the display unit 3003a may be configured as a touch panel. A liquid crystal panel or an organic light-emitting panel is manufactured using the transistor described in Embodiment 1 as a switching element and is applied to the display units 3003a and 3003b, thereby providing a highly reliable portable information terminal.

16(A) can have a function of displaying various information (still images, videos, text images, etc.), a function of displaying a calendar, date, time, etc. on the display unit, a function of operating or editing the information displayed on the display unit, a function of controlling processing by various software (programs), etc. Also, the back or side of the housing may be provided with an external connection terminal (earphone terminal, USB terminal, etc.), a recording medium insertion portion, etc.

The portable information terminal shown in Fig. 16(A) may be configured to transmit and receive information wirelessly. It is also possible to configure the terminal to purchase and download desired book data from an electronic book server wirelessly.

16B shows a portable music player, which includes a display unit 3023, a fixing unit 3022 for wearing on an ear, a speaker, operation buttons 3024, an external memory slot 3025, and the like in a main body 3021. By manufacturing a liquid crystal panel or an organic light-emitting panel using the transistor described in Embodiment 1 as a switching element and applying it to the display unit 3023, a more reliable portable music player can be provided.

Furthermore, if the portable music player shown in FIG. 16(B) is equipped with an antenna, microphone function, and wireless function and is linked to a mobile phone, it will be possible to have wireless hands-free conversations while driving a passenger car.

16C shows a mobile phone which includes two housings, a housing 2800 and a housing 2801. The housing 2801 includes a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, and the like. The housing 2800 also includes a solar cell 2810 for charging the portable information terminal, an external memory slot 2811, and the like. An antenna is built inside the housing 2801. By applying the transistor described in Embodiment 1 to the display panel 2802, a highly reliable mobile phone can be obtained.

The display panel 2802 is equipped with a touch panel, and a plurality of operation keys 2805 on which images are displayed are indicated by dotted lines in Fig. 16(C). Note that a boost circuit for boosting the voltage output from the solar cell 2810 to a voltage required for each circuit is also mounted.

For example, a power transistor used in a power supply circuit such as a booster circuit can also be formed by setting the thickness of the crystalline oxide semiconductor film 59 of the transistor 120 described in Embodiment 1 to 2 μm or more and 50 μm or less.

The display direction of the display panel 2802 changes appropriately depending on the usage mode. In addition, a camera lens 2807 is provided on the same surface as the display panel 2802, so video calling is possible. The speaker 2803 and the microphone 2804 are capable of video calling, recording, playback, and the like, in addition to voice calling. Furthermore, the housing 2800 and the housing 2801 can be slid from an unfolded state as shown in FIG. 16(C) to an overlapping state, so that the device can be made compact and suitable for portability.

The external connection terminal 2808 can be connected to various cables such as an AC adapter and a USB cable, and allows charging and data communication with a personal computer, etc. Also, a recording medium can be inserted into the external memory slot 2811 to accommodate the storage and movement of larger amounts of data.

In addition to the above functions, the device may also be equipped with an infrared communication function, a television receiving function, and the like.

16D illustrates an example of a television set. In the television set 9600, a display portion 9603 is incorporated in a housing 9601. Images can be displayed by the display portion 9603. Here, the housing 9601 is supported by a stand 9605 having a built-in CPU. By using the transistor described in Embodiment 1 in the display portion 9603, the television set 9600 can have high reliability.

The television set 9600 can be operated using an operation switch provided in the housing 9601 or a separate remote control. The remote control may be provided with a display unit that displays information output from the remote control.

The television device 9600 includes a receiver, a modem, etc. The receiver can receive general television broadcasts, and by connecting to a wired or wireless communication network via the modem, it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

The television device 9600 also includes an external connection terminal 9604, a storage medium playback/recording unit 9602, and an external memory slot. The external connection terminal 9604 can be connected to various cables such as a USB cable, and is capable of data communication with a personal computer or the like. The storage medium playback/recording unit 9602 allows a disk-shaped recording medium to be inserted, and allows data stored in the recording medium to be read and written to the recording medium. It is also possible to display on the display unit 9603 images and videos stored as data in an external memory 9606 inserted in the external memory slot.

In addition, by applying the semiconductor device described in Embodiment 8 to the external memory 9606 or the CPU, the television set 9600 can have sufficiently reduced power consumption and high reliability.

11 Substrate Supply Room

13 Transport room

14 Cassette Port

15 Substrate Heating Chamber

31 Processing Room

33 Exhaust means

35 Gas Supply Means

37 Power Supplies

40 Substrate Support

41 target

43 ion

51 substrate

53 Oxide insulating film

55 Crystalline oxide semiconductor film

57 Crystalline oxide semiconductor film

59 Crystalline oxide semiconductor film

61 electrode

63 Gate insulating film

65 Gate electrode

69 Insulating film

71 electrode

73 Crystalline oxide semiconductor film

75 Crystalline oxide semiconductor film

77 Gate insulating film

79 Gate electrode

81 Insulating film

83 wiring

84 buffer

85 buffer

87 buffer

91 Gate electrode

93 Gate insulating film

95 Crystalline oxide semiconductor film

99 Crystalline oxide semiconductor film

101 electrode

103 Insulating film

105 electrode

107 Crystalline oxide semiconductor film

109 Crystalline oxide semiconductor film

10a Sputtering equipment

10b Sputtering equipment

10c Sputtering equipment

110 Protective insulating film

111 Protective Film

113 Backgate electrode

115 Insulating film

120 Transistor

128 Interlayer insulating film

12a Load lock chamber

200 substrate

206 Element isolation insulating film

208 Gate insulating film

210 Gate electrode

214 Impurity Region

216 Channel formation region

218 Sidewall insulating film

220 High concentration impurity region

224 Metal Compounds

226 Interlayer insulating film

248 electrode

260 Transistor

265 Capacitive element

55a Seed crystal

55b Crystalline oxide semiconductor film

602 Gate wiring

603 Gate wiring

616 Source or drain electrode

628 Transistor

629 Transistor

651 Liquid crystal element

652 Liquid crystal element

690 Capacitive wiring

230a source electrode or drain electrode

230b Source electrode or drain electrode

242a Wiring

242b Wiring

2800 Chassis

2801 Chassis

2802 Display Panel

2803 speaker

2804 microphone

2805 Operation Keys

2806 Pointing Device

2807 Camera Lenses

2808 External connection terminal

2810 Solar Cell

2811 External memory slot

3001 Main unit

3002 Chassis

3004 Keyboard buttons

3021 Main unit

3022 Fixed part

3023 Display

3024 Operation buttons

3025 External memory slot

5300 substrate

5301 Pixel section

5302 Scanning Line Driving Circuit

5303 Scanning Line Driving Circuit

5304 Signal Line Driver Circuit

6400 Pixels

6401 Switching Transistors

6402 Driving Transistor

6403 Capacitive element

6404 Light emitting element

6405 Signal Line

6406 Scan Line

6407 Power line

6408 Common Electrode

9600 Television equipment

9601 Chassis

9602 Storage media playback and recording section

9603 Display

9604 External connection terminal

9605 stand

9606 External memory

3003a Display unit

3003b Display unit