Logic circuitry

Background I Squared Sea (I²At least one "master" integrated circuit (IC ) can communicate with at least one "slave" IC, eg, via bus I2C, and other communication protocols, to communicate data according to the clock cycle. For example, a voltage signal can be generated, where the voltage value is associated with the data. For example, a voltage value greater than or equal to x may indicate a logic "1", while a voltage value less than x voltage may indicate a logic "0", where x is a predetermined numerical value. By generating the appropriate voltages on each of a series of clock cycles, data can be communicated over a bus or another communication link.

Some 2D and 3D printing systems include print material containers (e.g., inkjet cartridges, toner cartridges, ink supplies, build material supplies, etc.), inkjet printhead assemblies, and the like. Contains one or more replaceable printing device components. In some examples, the logic associated with the replaceable printing device component(s) communicates with the logic of the printing device to which the replaceable printing device component is attached, e.g. Conveys information such as identity (identity, identity), capacity, status, and the like.

In some examples, these communications utilize I2C communications. In such examples, a master IC can generally be provided as part of a printing device (may be referred to as a "host"), and replaceable printing device components include a "slave" IC, which Not necessarily the case in every instance. There can be multiple slave ICs (eg containers of different colored printing agents) connected to the I2C communication link. The slave IC(s) may contain logic circuitry to perform data manipulations prior to responding to requests from the printing system logic circuitry.

In some examples, it may be intended to detect the physical location of slave devices attached along a serial bus. For example, a device such as a replaceable printing device component may be intended to occupy a particular designated physical location within the printing device. For example, in a printing device with an ink supply device attached to a serial bus, there may be expected locations for, for example, a black cartridge, a yellow cartridge, a cyan cartridge and a magenta cartridge, which Each can have a specific address under the communication protocol. By detecting whether a cartridge of a particular ink color has been incorrectly installed or replaced, printing with the wrong or unintended color can be prevented. The conventional patent information disclosure is Patent Document 1.

<p><patcit num="1"><text>U.S. Patent Application Publication No. 2011/0029705</text></patcit><patcit num="2"><text>International Patent Application Publication No. 2016/028272</text></patcit><patcit num="3"><text>International Patent Application Publication No. 2018/009235</text></patcit><patcit num="4"><text>International Patent Application Publication No. 2015/016860</text></patcit><patcit num="5"><text>EP-A-0941856</text></patcit><patcit num="6"><text>U.S. Patent No. 9619663</text></patcit><patcit num="7"><text>U.S. Patent No. 9561662</text></patcit></p><p>A non-limiting example will now be described with reference to the accompanying drawings.</p>

<figref num="1">1 is an example of a printing system.</figref><figref num="2">1 is an example of a replaceable printing device component;</figref><figref num="3">1 illustrates an example of a printing device; FIG.</figref><figref num="4">FIG. 4 illustrates an example method of operation of logic circuitry associated with replaceable printing device components.</figref><figref num="5">FIG. 2 shows a schematic example of printing device logic and logic associated with replaceable printing device components connected to a serial bus;</figref><figref num="6">FIG. 5 illustrates another example method of operation of logic circuitry associated with replaceable printing device components.</figref><figref num="7">It is a figure which shows an example of a logic circuit package.</figref><figref num="8">FIG. 1 illustrates an example of a replaceable printing device component that includes a logic circuit package;</figref>

DETAILED DESCRIPTION Several examples of I2C communication applications are described herein in the context of printing devices. However, all examples are not limited to such applications, and at least some of the principles presented herein can be used in other contexts.

In some examples, logic circuitry within the printing device can receive information from logic circuitry associated with replaceable printing device components via a communication interface and/or You can send commands to components. Exemplary printing devices include two-dimensional imaging devices and three-dimensional additive manufacturing devices, such as inkjet printers, dry toner printers, liquid toner printers, 3D powder bed inkjet printers, and the like. Exemplary printing device components include ink tanks; ink bottles; printheads; inkjet printhead cartridges; dry toner reservoirs; dry toner cartridges; three-dimensional printing agents including inks, stimulants, adhesives, inhibitors, etc.; three-dimensional printing building materials; printing device service components; including any other component that may or may not contain In this disclosure, printing materials or agents can include inks, dry or liquid toners, three-dimensional printing agents, three-dimensional building materials (plastics, metals, etc.), fibers, and the like. The reservoirs described above may contain pigmented printing material.

Communication between a printing device and replaceable printing device components attached to the device can provide a variety of functions. For example, the identity, function and/or status of a replaceable printing device component, and/or logic circuitry associated therewith, may be communicated to the logic circuitry of the printing device via a communication interface. . For example, a logic circuit associated with (or provided on or within) a printing agent container may identify a serial number and/or identity, such as a brand, and/or color, Identification characteristics, such as color maps, color map reconstruction recipes, maximum printing agent capacity or functions, can be communicated to the printing device to which the container is attached, e.g. See Document 4 or Patent Document 5. Status, such as fill level, can be provided via a communication interface, for example, so that the printing device can generate an indication of fill level to the user. In some examples, the verification process may be performed by the printing device. For example, a printing device can verify that replaceable printing device components come from an authorized source to ensure their quality. For example, logic circuitry associated with a replaceable printing device component can store a private key, generate a session key, a session key identifier and/or a message verification code for generating an authenticated cryptographic response to the printer. See, for example, US Pat. The logic may also include an authentication mechanism such as dedicated hardware for computing responses within a predetermined relatively short time window, see for example US Pat. In some examples, the verification process can include consistency checks to ensure that the replaceable printing device components and/or logic circuits associated therewith are functioning as expected.

Instructions to perform the task can then be sent from the logic associated with the printing device to the logic of the printing device component via the communications interface. For example, these may include instructions for performing authentication or encryption functions, printing material level detection functions, printing tasks, or other tasks.

In at least some of the examples described below, logic circuit packages are described. A logic circuit package may, for example, be associated with a replaceable printing device component attached to it, or may be configured at least partially within its housing, and may include a bus provided as part of the printing device. adapted to communicate data to and from the printing device controller via the

A "logic circuit package," as that term is used herein, means one or more logic circuits that can be interconnected or communicatively linked together. Where more than one logic circuit is provided, these may be encapsulated as a single unit, or may be separately encapsulated or non-encapsulated, or some combination thereof. Each package may be configured to communicate via a serial bus interface.

In some examples, each logic circuit package is provided with at least one processor and memory. In one example, the logic circuit package can be a microcontroller or a secure microcontroller, or can function as a microcontroller or a secure microcontroller. In use, the logic circuit package can be attached to a replaceable printing device component or integrated with a replaceable printing device component.

In some examples, a logic circuit package can respond to various types of requests (or commands) from a host (eg, a printing device). Requests can include requests for data, such as identification and/or authentication information (eg, read requests). In another example, the request can include a "write" request. Another request from the host can be a request to perform an action, such as performing at least one measurement, or performing a print task or the like. Another type of request can be a request for a data processing operation.

In an interaction example, the host can send a command to a logic circuit package associated with a replaceable printing device component, which executes the command and produces a resulting Data can be loaded into memory (in some examples, buffers and/or specific registers in memory). The host can send further commands to read the response, which is then transmitted as serial data over the attached bus. Such a process may be used, for example, to retrieve data held in memory of a logic circuit package. For example, the first request may be a request for the package's identifier, and may result in the package loading the identifier into a memory buffer. Subsequent "read" requests can result in data being read from the buffer and transmitted as a serial data signal.

In at least some examples, multiple such logic packages (each of which may be associated with a different replaceable printing device component) may be connected to the I2C bus.

FIG. 1 is an example of a printing system 100. As shown in FIG. Printing system 100 includes printing device 102 that communicates with replaceable printing device components 104 via communication link 106 . For clarity, the replaceable printing device component 104 is shown as being external to the printing device 102, but in some examples the replaceable printing device component 104 may be housed within the printing device. Printing device 102 can be any type of 2D or 3D printing device.

Replaceable printing device components 104 may include, for example, consumable resources of printing device 102 or components that may have a lifespan that is shorter than (and in some examples significantly shorter than) the lifespan of printing device 102. can be done. For example, the printing device component 104 can physically store ink, toner, 3D printing agent, or 3D printing build powder and can be intended to be replaced after substantial depletion. Replaceable printing device components 104 can include, for example, a printing material container or cartridge (which can be a build material container for 3D printing or a liquid printing material container for 2D or 3D printing). In some examples, replaceable printing device components 104 may include printheads or other ejection components. In this example, a single replaceable printing device component 104 is shown, but other examples may include, for example, different color printing agent containers, printheads (which may be integrated into the container), or the like. There can be multiple interchangeable printing device components, including:

In some examples, communication link 106 may include a serial bus, such as an I2C-compatible bus or an I2C-compatible bus (hereinafter I2C-bus).

FIG. 2 shows an example of a replaceable printing device component 200 that can provide the replaceable printing device component 104 of FIG. Interchangeable printing device component 200 includes data interface 202 integrated into logic circuit package 204 . During use of replaceable printing device component 200 , logic package 204 decodes data received via data interface 202 . Data interface 202 may include an I2C interface.

In some examples, logic circuit package 204 may be further configured to encode data for transmission over data interface 202 . In some examples, there may be more than one data interface 202 provided for a single component 200. FIG.

In some examples, logic package 204 may be configured to act as a "slave" in I2C communications.

The replaceable printing device component 200 in this example includes a printing material reservoir 206 that can contain any of the printing material examples described above.

FIG. 3 shows an example of a printing device 300. As shown in FIG. Printing device 300 may provide printing device 102 of FIG. The printing device 300 includes a controller 304 that includes an interface 302 and a communication bus 306 for communicating with interchangeable printing device components. Controller 304 includes logic circuitry. In some examples, interface 302 is an I2C interface and communication bus 306 is an I2C compatible communication bus.

In some examples, controller 304 may be configured to act as a host or master in I2C communications. The controller 304 can generate and send commands to the at least one replaceable printing device component 200, receive responses from it, and decode the received responses.

Such printing devices 102, 300 and replaceable printing device component(s) 104, 200 and/or their logic circuit packages may be manufactured and/or sold separately. In one example, a user can obtain a printing device 102, 300 and keep the device 102, 300 for many years, while having multiple replaceable printing device components 104, 200 that can replace them. Over the years, for example, printing agents can be purchased when used in producing printed output. Accordingly, there may be at least some degree of forward compatibility and/or backward compatibility between the printing device 102,300 and the interchangeable printing device components 104,200.

FIG. 4 is an example of a method that may be performed by a logic circuit package associated with a replaceable printing device component. In some examples, the method may be performed such that a printing device to which the replaceable printing device component is attached can determine the physical location of the replaceable printing device component. It should be noted that although the methods described herein can be used with communication protocols other than I2C, such as the Serial Peripheral Interface (SPI) protocol, in the I2C protocol, multiple devices are are serially connected on a single bus without any means of immediately determining or specifying their physical location or order. However, when considering SPI for example, there are two wiring configurations, parallel and daisy chain. In a parallel wiring configuration there is a separate line dedicated to each "slave" logic circuit, and in a daisy chain configuration the devices are wired serially in a particular order so that their relative positions are , may be enabled in some other way. Thus, the methods described herein can have particular utility with protocols such as I2C where it is difficult to verify the physical location of a device. However, it is not so limited.

Block 402 includes receiving a first command sent via a serial data bus (eg, an I2C bus) to an address of a logic circuit associated with a replaceable printing device component. In some examples, the first command can be an operational mode indication. In some examples, the first command can be an indication of a time period. The address can be an I2C bus interface address stored and/or hardwired into the logic circuit/logic circuit package. A first command may be sent to the address by the controller of the printing device. The first command can be a predetermined command.

Block 404 involves generating a low voltage state on the serial data bus by logic circuitry. As will be explained in more detail below, this essentially provides a connection between the serial data bus (more specifically, the data lines of the serial data bus) and ground. can contain. In one example, the low voltage is nominal ground or a reference voltage such as about 0V. A low voltage is a lower than high or default voltage state or voltage condition, also described below.

Block 406 includes monitoring the duration of the low voltage condition using a logic circuit timer. The timer can consist of an integrated timer inside a logic circuit, e.g., a resistive-capacitance (RC) circuit configured to act as a timer, a logic gate configured with a counter, a crystal or ring oscillator, phase-locked. A loop (also known as a phase-locked loop) or the like, or any timer that logically constitutes part of a logic circuit provided in connection with a replaceable printing device component. A timer can provide an internal clock signal that is provided without a clock signal on the serial data bus. The timer can count, thus allowing determination of the duration of the timer period specified in the first command.

A timer may be dedicated to measuring the time duration of the command. In a particular example, the timer measures time independent of other general cycles in the active I2C logic circuit package, such as I2C clock cycles and/or processing cycles of the host device or the central processing unit of the logic circuit. Dedicated to doing. For example, the timer can be configured to count faster than the clock frequency and can start and stop counting regardless of the timing of the clock signal. The timer can be configured to count regardless of the processor speed of the central processing unit of the logic circuit/host device, eg, having nominal specifications regardless of the central processing unit.

In other examples, the logic circuit/logic circuit package may be suitable for determining the duration of a time period based on monitoring an external timer, such as an external clock, or in certain instances an external clock. Alternatively, the time period can be monitored by monitoring an internal waveform signal, oscillation (vibration) signal, or the like. In one example, the timer of the logic circuit package can be a timer wirelessly linked with the logic circuit (so one timer can be shared by more logic circuits).

The method is different for different serial data buses.<u style="Single">and</u>and/or the default<u style="Single">high</u>It can include releasing the bus or removing the low voltage state at the end of the period of time that the voltage state or the voltage state is reached. This includes, for example, breaking the connection to ground. Outside the time period, eg, before and after the duration of the time period as initiated in response to the first command, the logic circuit/logic circuit package can generate the high voltage state. Alternatively, such a high voltage state can be a default state caused by including a "pull-up" resistor on the bus, as described below.

For example, consider an I2C data bus, which includes two communication lines, a serial data line (SDA) and a serial clock line (SCL). SDA and SCL can be bidirectional lines connected to a positive voltage source through current sources or pull-up resistors.

If there is no signal on the line (ie, no clock signal on SCL and/or no data signal on the data line), both lines may default to a HIGH voltage state. The exact value of the high voltage state voltage depends on many operating factors, but in some instances can be a few volts, for example between about 3 and 6 volts. So, in general, the "high" voltage can be relatively low, which is higher than the "low" voltage state of the bus, which can be, for example, less than 1 volt.

The master/host device (e.g., in this context, the processing circuitry or controller of the printing device to which the replaceable printing device component is attached) pulls the voltage on the SCL line to a LOW state (e.g., , using an open-drain configuration to effectively provide a short circuit to ground) to generate the clock signal. For example, a switch (such as a field effect transistor) can be energized (closed) to provide a low voltage state, and then a pull-up resistor on the line pulls the voltage to a HIGH state. is reopened to allow In another example, an open-collector configuration can be used, in which case a bipolar junction transistor (BJT) can be used to similar effect. The pull-down and release timings provide clock signals that are controlled by the processing circuitry of the master device.

To transmit data, a master device or slave (in this example, logic circuitry associated with a replaceable printing device component) pulls a voltage LOW (e.g., provides a connection to ground). Similarly, the voltage on SDA can be selectively controlled by setting the voltage to "float high" (eg, breaking the connection to ground). This is timed with a clock signal, ie according to the I2C protocol, the state of the SDA line when the SCL line is HIGH provides at least one data bit. Normally, when the SDA line is LOW (and stable) while SCL is HIGH, this indicates a binary 0, and SDA is LOW when SCL is HIGH (and stable). When the line is HIGH, it indicates a binary 1, but this is a convention and so can be changed in a given system.

In one example of the method of FIG. 4, instead of providing a data signal timed to coincide with the SCL line being high, the state of the SCL line is not considered. In practice, the voltage is pulled low (again, e.g., by providing a connection to ground) for a duration monitored by a timer in the logic circuit, and then "released" or default high (HIGH ) state (eg, by breaking its connection). In fact, in some embodiments, the clock signal provided by the master device may be absent for at least a portion, and in some instances throughout, the duration of the low voltage state.

As noted above, this method may be utilized in the context of detecting the physical location of replaceable printing device components, as described herein with respect to FIG. For example, the method can be utilized in detecting whether a replaceable printing apparatus component, such as a supply of printing material, has been installed in its intended location. In some instances, this can eliminate or reduce the use of "mechanical keying," in which interchangeable printing device components have complementary shapes. It is specially shaped to match the "slot" it has. As a result, this reduces manufacturing complexity as interchangeable printing device components for different print material types, such as different colors, can have a common physical design. In some examples, a combination of mechanical key engagement and the techniques described herein may be used. For example, in some applications, black (K) colorant tends to jet more frequently than other colors (e.g., in contexts where text is often printed), so black printing materials A supply cartridge may be physically larger than a cyan, magenta or yellow print material supply cartridge, for example in a CMYK cartridge set. Thus, in some instances, mechanical keying (e.g., by sheer size of black cartridges versus other colors) can be used with black cartridges, which are intended for black cartridges. can be sufficient to ensure that the cartridge is placed in the correct "slot", and the techniques described herein are used to ensure that other color cartridges are placed as intended. can be used for

In some examples, a time period monitoring function, such as by a timer, can be used for other purposes. For example, a logic circuit package may be connected across the same I2C bus interface of the logic circuit package (e.g., same single data interconnect pad, same single power pad, same single ground pad and/or same signal clock pad). - via pads), can be configured to have more than one I2C address to facilitate communication with different logic circuits or different functions contained in the package. For example, default data read/write communications and low voltage generation and/or detection may be associated with the primary address of the logic circuit package, which is the package address described above. The logic package is adapted to be able to temporarily "switch" (i.e., in response to a command directed to it) to a secondary (e.g., temporarily I2C address upon receipt of the corresponding command) can be This command can include a second time period. This second period of time can be monitored by the logic circuit package, for example using a timer, to determine when the logic circuit package can respond to commands received via the second address. For example, a logic circuit may be associated with a primary address for a first time period and a secondary address for a second time period, where the second time period can be monitored using In this context, the first time period can be any time period outside the second time period. In certain embodiments, this second time period can be longer than the time period for generating the low voltage state to facilitate sufficient time for data communication via the second address. The time period can be longer than, for example, location detection of replaceable printing device components of the present disclosure. Activating at least one different address may, for example, write a different address to a portion of memory indicating the address of the logic circuit package.

The logic circuit is configured to provide a first set of responses or to operate in a first mode in response to commands sent to a first address and sent to a second address. may be configured to provide a second set of responses or to operate in a second mode in response to a given command. In other words, the address can trigger different functions provided by the circuit. In some examples, the first set of responses is accessible in response to commands sent to the first address and not accessible in response to commands sent to the second address; A second set of responses is available in response to commands sent to the second address and not available in response to commands sent to the first address. In some examples, the first set of responses can be cryptographically authenticated (e.g., accompanied by message authentication, or cryptographically "signed" and/or encrypted). ), the second set of responses is cryptographically unauthenticated. In some examples, for example, the second address may be utilized to access other cells or sensors or the like that may be provided in or associated with the logic circuit.

By making the time period monitoring function versatile, the time to perform these multiple tasks (e.g., location detection and secondary address communication) can be scaled by, e.g., speed, capability, logic package specifications, single It can be specified depending on the platform characteristics of each printing device, including the number of replaceable components that are potentially connectable to the bus, bus speed, and the like.

FIG. 5 shows an example of a serial bus 500 that includes a total of four lines, two active lines, SDA and SCL, a voltage source connection Vdd and a ground connection GND as described above. Active lines are bidirectional. A voltage source connection Vdd is connected to a first voltage source 502 and the SDA line is connected through a pull-up resistor 506 to a second voltage source 504 .

Attached to bus 500 is master device 508 , which includes, for example, a printing device controller associated with analog-to-digital converter 510 . Bus 500, master device 508 and analog-to-digital converter 510 may be provided by the printing device. The master device 508 includes processing circuitry associated with (in some examples, provided within) the printing device. The four "slave devices" 512a-512d associated with the replaceable printing device components 514a-514d, which in this example include logic circuits attached to the replaceable printing device components 514a-514d, are also connected to the bus. Mounted on 500. In this example, each of the replaceable printing device components 514a-514d includes an ink cartridge of a given color.

In this example, each slave device 512a-512d attached to bus 500 has its own unique address and can be a receiver and/or transmitter. In typical operation, a serial clock signal and a serial data signal are provided from the master device 508 via clock signal line SCL and data line SDA, while the slave device's operating voltage is determined by the voltage supply line. Provided between Vdd and the ground line GND. Data signals may also be transmitted from slave device 512 to master device 508 .

In one example, a communication that begins in a START state and ends in a STOP state can be referred to as an I2C "packet." In one example of an I2C packet sent by master device 508, this is the address of the slave device, an indication of whether the command is a read or write command (in some examples, these together form a byte ), the command code (which can be the second byte of data), and in some examples any additional command data (e.g., one or more subsequent data bytes additional command parameters, message authentication code (MAC), cyclic redundancy check (CRC) and the like).

In one example of operation in performing the method of FIG. 4, the master device 508 can first issue a START condition, which acts as an "attention" signal to all of the connected slave devices 512. . This can be characterized, for example, by a drop in voltage on the SDA line while the SCL voltage is HIGH. Master device 508 then sends a byte containing the address of slave device 512 that master device 508 wishes to access and a bit that provides an indication of whether the access is a read or write operation. can be sent.

After receiving the address byte, all slave devices 512a-512d compare it with their own addresses. If not, slave device 512 generally waits for the next START condition initiated by master device 508 .

However, if the addresses match, the circuitry of that slave device 512a-512d receives subsequent command information and then generates an acknowledgment signal (ACK signal) (by activating the SDA line for a particular clock period). (can include pulling LOW).

In some examples described herein, the command may be a command for slave device 512 to generate a low voltage state for a period of time. A low voltage condition may be provided after generation of the ACK response signal. Master device 508 can then generate a STOP condition.

Once master device 508 receives the acknowledgment signal (and in some instances, after generating a STOP condition), master device 508 signals slave device 512 to a low voltage on SDA. We can try to see if we have generated the state (and in some instances we can stop sending clock signals on SCL while this LOW voltage state is expected). .

In this example, the SDA line of serial bus 500 is provided with a resistive voltage divider network to allow electronic determination of the individual physical locations of slave devices 512 . In particular, series voltage divider resistors 516a-516d are provided on data line SDA, and there is a connection 518 from data line SDA to analog-to-digital converter (ADC) 510 . This configuration forms a ladder divider network (or ladder resistor network) by which when device 512 is connected to the ladder divider network at different locations, , the voltage of the signal from each device 512 varies depending on the physical location of the device 512 . For example, the signal from slave device 512d passes through four of divider resistors 516, while the signal from slave device 512a passes through only one of divider resistors 516a. By detecting the voltage value, the location of the slave device 512 producing the low voltage condition can be determined. In other words, each slave device 512 produces a different low voltage state. The voltage can be detected using ADC510. ADC 510 includes circuitry that converts analog voltages to digital signals that indicate voltage levels. This digital signal is used by master device 508 to electronically distinguish the physical location of slave device 512 on the bus based on the voltage level of the signal from slave device 512 . The voltage can be compared to the expected voltage of the device 512 whose address was used for the command.

ADC 510 can receive control signals and provide data to master device 508 via a communication link (which can be another communication bus). Although ADC 510 is shown separate from master device 508, ADC 510 can be physically part of master device 508 or can reside at a separate location.

The ADC510 and ladder divider network distinguishes location by detecting the voltage order of the devices on bus 500 without interfering with the identification of high (HIGH) and low (LOW) states used for data transmission. may be configured to operate to allow In other words, all of the characteristic low voltages generated on the bus by each slave device 512 are relatively far from the threshold for characterizing each data bit as being high (HIGH) or low (LOW). can be done.

Considering an example, when receiving data, master device 508 may be configured to detect any signal below a threshold to be in a low (LOW) voltage state. For example, any voltage less than 2V or less than 1V when the SCL voltage is HIGH can be identified as a LOW data bit (0 in some examples), while this Values above the threshold may be identified as HIGH data bits (1 in some examples). In some examples, the threshold for detecting a LOW data bit is a voltage below 1.3V.

However, the master device 508, using the converted voltage from the ADC 510, may use certain signals below this threshold and zero (or nominally 0V) (e.g., on the order of several hundred millivolts) to enable position identification. mV)) or higher. Each divider resistor 516 can have sufficient resistance such that the voltage generated between the sum of the divider resistors 516 and the pull-up resistor 504 is below the LOW voltage threshold. However, the resistance of divider resistor 516 is such that discrimination of high (HIGH) voltage signals from master device 508 is not overly compromised during normal operation, i.e., the high (HIGH) voltage provided by second voltage source 504 is can be chosen to be small enough to remain relatively close to the maximum voltage applied.

In one embodiment, the divider resistors 516 each have a resistance of approximately 51 ohms, but this is only one of many resistance levels that may be used, and the resistance levels vary between different resistors 516. Sometimes. In such an example, the first and second voltage sources 502, 504 can each provide approximately 3.3 volts and the pull-up resistor 506 is a resistor of approximately 1000 ohms (1 kilohm), i.e. a divider It can be of a resistance value significantly greater than resistor 516 .

In other words, divider resistor 516 can act as a separate "extra" pull-up resistor on the SDA line, preventing it from dropping to nominal 0V. For example, given the values specified above, this can provide a voltage difference of about 100-200 mV. This can be measured in terms of counts by the ADC 510 . For example, in a 3.3V system, if a 9-bit ADC is provided, then this means that each count represents approximately 6mV (determined by dividing 3.3V by 512). Thus, the ADC 510 can be expected to record about 20 counts for the lowest voltage cartridges to about 80 counts for the highest voltage cartridges.

As noted above, if at least some of the replaceable printing device components can have their positions verified using mechanical keying instead of the methods described herein. There is Thus, the number of voltage levels detected may be less than the number of print supply cartridges used, for example.

It should be noted that since there are specific addresses associated with the replaceable printing device components 514a-514d, specific commands can be sent to 514a, for example, to sample the voltage and then perform the process. is repeated for each of the replaceable printing device components 514b, 514c, and 514d in turn. When replaceable printing device components 514a-514d are in their expected locations, a gradual change from lower voltage values to higher voltage values can be expected if measured in that order. However, if the replaceable printing device components 514a-514d are not in the expected locations, this pattern (more specifically the expected relative voltages) may not be seen and an alert may be generated.

In practice, the time period the SDA line is held low may be greater than the sampling time period. For example, slave device 512 may be commanded by master device 508 to hold the SDA line low for 50 ms. During this time, the data line SDA may be sampled a certain number of times (eg, 3-10 times) by the host device's ADC 510 . In some examples, if at least one of these readings is not within a specified threshold range, the command can be executed again and new samples can be taken. In another example, samples may be taken until there is a threshold number of "good" samples. In some such examples, there may be a maximum number of samples allowed before an error condition is declared, e.g. , or a maximum of 10 samples are acquired. An error can be indicated if a "good" set of samples is not obtained. The samples can be averaged to produce a representative value for that replaceable printing device component 514a-514d.

The sampling period can be relatively short. For example, after slave device 512 has been commanded to hold the SDA line low, master device 508 may wait before sampling the bus to allow it to stabilize ( for about 10ms). Acquisition of a sample can occur within about 1 ms. However, the SDA line can be held low for a longer period (eg, 50ms) to allow retesting, etc. This period of time may be specified or, in some examples, associated with the first command (eg, by reference to a lookup table or register maintained in slave device 512).

Therefore, the SDA line may not need to be held low by the first command or for the entire time period specified in the first command, if applicable. However, slave device 512, at least statistically, holds the SDA line low so that the sampling period is likely to occur during the time the SDA line is held low for at least one of the allowable sets of trials. sometimes you can.

It should be understood that the SDA line is held low by sending a data signal that is actually made up of a series of data bits (eg, a series of 0 bits) associated with the low voltage state. obtain. This results in the SDA line being held low for a period of time. However, when transmitting data signals, the slave device 512 must release the SDA line when to allow it to return to a HIGH state (i.e., when the serial data bus is at a different high and/or Instead of its own internal timer, the signal on SCL can be referenced to determine when to leave the low voltage state (to be the default voltage state or voltage condition). However, in the method described herein, the low voltage state applied after the first command is applied independently of any clock signal on the SCL bus (in some cases, the without any such clock signal).

FIG. 6 illustrates another example of a method for operation of logic circuitry (eg, logic circuitry packages as described above) associated with replaceable printing device components. In this example, at block 602, the logic circuit receives a first command specifying a first time period over the I2C data bus. In this example, the first command also includes an indication of a START condition, an address of the logic package, an identification field indicating a write command, and an indication of a STOP condition (e.g., a clock pulse high ( rising voltage on the data line during the HIGH) portion).

In some examples, the time period may be selected based on attributes of the host device or its circuitry. In general, the time period can be long enough to allow good samples to be captured, but not so long as to unduly lengthen the time spent verifying the position of replaceable printing device components. is.

Block 604 causes logic circuitry to transmit a signal on the serial data line of the I2C bus after receipt of an indication of a STOP condition (which itself follows transmission of a command) and for the substantial duration of a first time period. generating a low voltage state to As noted above, in some examples, the low voltage state may be generated for the entire time period, but in some examples, the method includes generating serial data during a portion of the first time period. It can include letting the line "float high" (ie, the line can be held low in an interrupted manner). In some examples, the serial data line is at least 60% of the first time period, or at least 70% of the first time period, or at least 80% of the first time period, or It may be held low for at least 90% of the time period, or at least 95% of the first time period. In some examples, the voltage is held low for a sufficient portion of the time to ensure that it coincides with the sampling period. The duration of the low voltage state includes at least one sampling period, where the sampling is performed by processing circuitry of the printing device as described above. Furthermore, if the data line is held low for an excessively long period of time, this can block communication, thereby allowing, for example, the host device to generate timeout errors or the like.

Generating a low voltage state after receipt of an indication of a STOP condition means that the bus is not blocked during ongoing transmission of data packets.

In this example, generating a low voltage state coincides with the absence of a clock signal on the serial data bus, and block 606 uses an internal timer in the logic circuit to time the duration of the low voltage state. Including monitoring.

The method further includes, at block 608, performing a read operation with logic circuitry in response to a read request having an identification field indicating a read mode. In other words, in addition to the special functions described herein, the logic circuit can function as an I2C slave device. The logic circuit may also perform other features of the I2C slave device, such as participating in authentication and/or verification exchanges, receiving read and/or write commands or acting on read and/or write commands, processing. It can be presented as taking on a task or the like.

FIG. 7 is an example of logic circuit package 700 associated with replaceable printing device components, logic circuit package 700 includes logic 702, serial data bus interface 704, timer 706, and this Includes memory 708 in the example. During use of logic circuit package 700, logic 702 responds to a first command sent to logic circuit package 700 via a serial data bus connected to serial data bus interface 704 to cause logic circuit Package 700 is configured in this example to generate a low voltage condition on the serial data bus and timer 706 is used to monitor the duration of the time period. In some examples, timer 706 can communicate with logic 702, eg, via a wired or wireless link. In some examples, timer 706 may be provided on a common substrate with logic 702 .

In some examples, logic 702 may be configured to monitor the duration of the time period independently of the clock signal of the serial data bus. Serial data bus interface 704 may include an I2C data bus interface.

The first command may specify a time period, and logic 702 may be configured to generate a low voltage state on the serial data bus for a substantial duration of the first time period. Logic 702 may perform any aspect of the methods described in connection with FIGS. 4-6 above.

In response to the second command, logic 702 may be configured to write data received via serial data bus interface 704 to memory 708 . In response to read requests, logic 702 may be configured to read data from memory 708 and transmit data signals over serial data bus interface 704 .

FIG. 8 shows an example of a replaceable printing device component that includes a logic circuit package such as that shown in FIG. In this example, the replaceable printing device component is a print cartridge 800 with a housing 802 having a width less than a height. A printing liquid output 804 (in this example the outlet is provided on the underside of the cartridge 800), an air input 806 and a recess 808 are provided on the front of the cartridge 800. FIG. A recess 808 extends across the top of the cartridge 800 so that the I2C bus contacts 810 of a logic circuit package 812 (eg, the logic circuit package 700 described above) are positioned adjacent the top and front sides of the housing 802 in the side walls of the housing 802 . provided on the side of the recess 808 opposite the inner wall of the recess 808 . In this example, a logic circuit package 812 is provided against the inside of the sidewall.

Examples of the present disclosure may be provided as a method, system or machine readable instructions, such as any combination of software, hardware, firmware or the like. Such machine-readable instructions may be contained on a machine-readable storage medium (including, but not limited to, disk storage devices, CD-ROMs, optical storage devices, etc.), in which or have machine-readable program code thereon.

The present disclosure is described with reference to flowchart illustrations and block diagrams of methods, devices and systems according to examples of the disclosure. Although the flow diagrams described above show a particular order of execution, the order of execution can differ from that shown. Blocks described in connection with one flowchart may be combined with blocks in another flowchart. It should be understood that at least some of the blocks in the flow diagrams and block diagrams, and combinations thereof, can be implemented by machine readable instructions.

Machine-readable instructions can be executed, for example, by an embedded processor or processor of a general purpose computer, special purpose computer, or other programmable data processing device to perform the functions described in the description and drawings. In particular, a processor or processing circuit is capable of executing machine-readable instructions. Thus, functional modules (e.g., logic circuits and/or controllers) of apparatus and devices are embodied by processors executing machine-readable instructions stored in memory or by processors operating according to instructions embedded in logic circuits. can be The term "processor" should be interpreted broadly to include CPUs, processing units, ASICs, logic units or programmable gate arrays, and the like. All methods and functional modules may be executed by a single processor or may be shared among several processors.

Such machine-readable instructions may also be stored on a machine-readable storage device (e.g., a tangible machine-readable medium) to guide a computer or other programmable data processing device to operate in a particular mode. can be done.

Also, such machine-readable instructions can be loaded onto a computer or other programmable data processing apparatus such that the computer or other programmable data processing apparatus can be used to generate computer-implemented processes. The instructions executed on the computer or other programmable data processing apparatus perform the sequences of operations and thus perform the functions specified by the block(s) in the flow diagrams and/or block diagrams.

Furthermore, the teachings herein can be embodied in the form of a computer software product stored on a storage medium and used to implement the methods described in the examples of this disclosure on a computer device. contains a number of instructions for implementing the

Although the methods, apparatus, and related aspects have been described with reference to particular examples, various modifications, alterations, omissions, and substitutions may be made without departing from the spirit of the disclosure. It is therefore intended that the methods, apparatus and related aspects be limited only by the scope of the following claims and their equivalents. It should be noted that the examples described above are not meant to limit what has been described herein, but that those skilled in the art will be able to make many alternative implementations without departing from the scope of the appended claims. You can design the form. Features described in relation to one example may be combined with features of another example.

The word "comprising" does not exclude the presence of elements other than those listed in a claim, nor does "a" or "an" exclude a plurality; The functions of several units recited in the claims may be implemented.

Features of any dependent claim may be combined with features of any independent or other dependent claim.

Statements In some examples, a method can be described by any of the following statements.

Statement 1. In response to a first command sent over the serial data bus to a logic circuit address associated with a replaceable printing device component, said logic circuit transmits said serial data A method comprising generating a low voltage condition on a bus and using a timer of said logic circuit to monitor the duration of said low voltage condition.

Statement 2. The first command specifies a first period of time, and generating a low voltage state on the serial data bus is performed on the serial data bus based on the first period of time. The method of statement 1 including generating a low voltage state on.

Statement 3. The method of Statement 2 including generating a low voltage state on said serial data bus for a substantial duration of said first time period.

Statement 4. The method of any one of Statements 1-3 including producing a low voltage state on a serial data line of the serial data bus.

Statement 5. Any one of Statements 1-4, wherein the duration of the low voltage state includes at least one sampling period, and sampling is performed by processing circuitry of the printing device during the sampling period. Method.

Statement 6. The method of any one of Statements 1-5, wherein generating the low voltage condition corresponds to no clock signal on the serial data bus.

Statement 7. The first command includes an identification field indicating a write command and an indication of a halt condition, and the method causes the logic circuit to output a low signal on the serial data bus after receiving the indication of a halt condition. 7. The method of any one of statements 1-6, further comprising generating a voltage state.

Statement 8. The method of Statement 7 further comprising performing a read operation with the logic circuit in response to a read request having an identification field indicating a read mode.

Statement 9. The method of any one of Statements 1-8, wherein the voltage value of the low voltage state indicates a position of the replaceable printing device component in the printing device.

Statement 10. Any one of Statements 1-9 further comprising releasing said low voltage state such that said serial data bus is at a different high and/or default voltage state or voltage condition. the method of.

Statement 11. A logic circuit package associated with a replaceable printing device component, including logic and a serial data bus interface, said serial data bus interface being connected to the serial data bus of the printing device. and the logic is responsive to a first command sent to the logic circuit package via the serial data bus connected to the serial data bus interface. a logic circuit package capable of generating a low voltage state on said serial data bus to monitor the duration of a time period.

Statement 12. The logic circuit package of Statement 11, further comprising a timer, wherein the logic can monitor the duration of the time period using the timer.

Statement 13. The logic circuit package of statements 11 or 12, wherein said logic is capable of releasing said low voltage condition on said serial data bus at the end of said time period.

Statement 14. Any one of statements 11-13, wherein said logic is configured to force said serial data bus to different high and/or default voltage states or conditions outside of said time period logic circuit package as described in .

Statement 15. The logic circuit of any one of Statements 11-14, wherein the logic is capable of outputting an acknowledgment prior to generating the low voltage state upon receiving the first command. package.

Statement 16. The logic circuit package of any one of Statements 11-15, wherein the logic is capable of monitoring the duration of the time period independently of a clock signal on the serial data bus.

Statement 17. The first command specifies a time period, and the logic is capable of generating a low voltage state on the serial data bus within the duration of the time period of statements 11-16. A logic circuit package according to any one of claims 1 to 3.

Statement 18. The logic circuit package of any one of Statements 11-17, wherein the logic is configured to produce the low voltage state for the period of time specified in the first command.

Statement 19. The first command specifies a time period, and the logic may generate a low voltage state on the serial data bus for a substantial duration of the time period, Statement 11. 19. The logic circuit package according to any one of -18.

Statement 20. Any of statements 11-19, further including memory, wherein in response to a second command, the logic can write data received via the serial data bus interface to the memory. or the logic circuit package according to item 1.

Statement 21. Further comprising a memory, and in response to a read request, the logic is capable of reading data from the memory and transmitting data signals over the serial data bus interface, statements 11- 21. The logic circuit package according to any one of 20.

Statement 22. The logic circuit package of any one of Statements 11-21, wherein said serial data bus interface is an I2C data bus interface.

Statement 23. Communicate over the same I2C bus interface via two or more I2C addresses and temporarily use different secondary I2C addresses to receive commands associated with commands containing a second time period, said 23. The logic of any one of statements 11-22, configured to monitor a second time period and respond to commands directed to the secondary I2C address during the second time period. circuit package.

Statement 24. The logic circuit package of statement 22, dependent on statement 12, wherein the logic circuit package includes a timer, and wherein the second time period is monitored using the timer.

Statement 25. A replaceable printing device component comprising the logic circuit package of any one of Statements 11-24.

Statement 26. A replaceable printer cartridge for connection to a printer, comprising a reservoir containing pigmented printing material and a logic circuit package, said logic circuit package having logic and a serial data bus. an interface, wherein said serial data bus interface is connectable to a serial data bus of a printing device, said logic adapted to enable said interchangeable printing device when connected to said printing device; responsive to a first command sent to the logic circuit package over a serial data bus connected to the serial data bus interface to determine the location of the serial data bus; A replaceable printer cartridge capable of producing a low voltage condition on the bus and monitoring the duration of a period of time.

Statement 27. The replaceable printer cartridge of Statement 26, further including any of the features set forth in any one of Statements 11-25.

Statement 28. A printing apparatus including a communication bus having a resistive ladder network therein and adapted to receive at least two of the logic circuit packages described in any one of Statements 11-25; , the logic packages have different I2C addresses, and each logic package is connected to the communication bus at a different point of the ladder resistor network to provide a different I2C address on the communication bus in response to a predetermined command. A printing device that produces a low voltage state.