Correction of errors in a memory array

The present invention relates to an error correction code (ECC) that corrects an error in memory.

Non-volatile memory devices, especially solid-state memory devices, tend to deteriorate over time. An error occurs in the stored data as the main result of such deterioration. The reliability of equipment that is generally accepted in the industry depends on the type of equipment, for example, the technology used and the manufacturing process tolerances that can be achieved. The flash controller is designed to be able to correct errors up to the first (week) bit error rate (for example, up to 6 bits per 512 bytes) in a correctable memory cell group of standard size (eg 256 bytes). Some require a second bit error rate (eg, up to 8 bits per 512 bytes) that is higher than the first bit error rate for stronger protection.

In the art, several error handling methods have been devised to provide strong bit error rate protection using weak error handling methods. One solution is to divide the group of memory cells into subgroups (correctable groups) and apply the existing weak error correction method to each subgroup separately. In this case, each subgroup is individually protected by the weak bit error rate. However, in such an error correction method, an error correction operation is required for each subgroup, so that the overall performance deteriorates. Apart from this, efforts are being made to newly design a robust error correction method that can correct errors up to the desired bit error rate. Newly designed systems have the drawbacks of being cost effective and time consuming to design. Prior art error handling methods provide some protection against defective memory locations, but none are perfect. Some error handling methods require excessive resources and development time, while others reduce the read performance of the entire system. In addition, some are inadequately protected.

The present invention is embodied as a computer system and a method thereof having an error correction algorithm for correcting errors in a memory array. Memory cells are stored in the memory array in relation to the corresponding ECC bits. ECC bits are generated as follows. One set of ECC bits contains information corresponding to the first memory cell group (the first group has a first size of, for example, 256 bytes or more), and the second ECC bit set is the second. Contains information corresponding to the memory cell group of (the second group is contained within the first group), and the third ECC bitset contains information corresponding to the third memory cell group (third group). Is included in the second group), and so on. By generating ECC bits in this way, the best overall performance is achieved while performing error correction on the memory array.

In one embodiment of the approach described above, the method of correcting an error in a memory array comprises providing an error correction algorithm capable of correcting the error up to the first bit error rate in a correctable memory cell group. be able to. Correctable groups have standard sizes. The method also generates a first ECC bit set with information corresponding to the first memory cell group and a second ECC bit set with information corresponding to the second memory cell group. And the step of applying an error correction algorithm to correct the error in the first group based on the first ECC bit set. The first group has a first size larger than the standard size. The second group has a second size smaller than the first size and is part of the first group. The method also includes applying an error correction algorithm to correct the error in the second group based on the second ECC bit set if the error correction algorithm fails based on the first ECC bit set. The method also involves correcting the first group based on the first ECC bitset. The method also involves correcting the second group based on the second ECC bit set.

The method also comprises generating additional ECC bit sets with information corresponding to additional memory cell groups. Additional ECC bit sets can be generated prior to the application of the error correction algorithm. Further groups have a third size smaller than the second size and are part of the second group. The method also includes applying an error correction algorithm to correct an error in a further group based on a further ECC bit set if the error correction algorithm fails based on a second ECC bit set. The method involves correcting additional groups based on additional ECC bit sets. An error correction algorithm is applied in the first group to correct the error up to the second bit error rate, where the second bit error rate is greater than the first bit error rate.

In another embodiment of the approach described above, a computer system that corrects errors in a memory array includes an error correction algorithm that can correct errors up to the first bit error rate in a correctable memory cell group. Correctable groups have standard sizes. The memory functions to store a first ECC bit set having information corresponding to the first memory cell group and a second ECC bit set having information corresponding to the second memory cell group. .. The first group has a first size larger than the standard size, the second group has a second size smaller than the first size, and is part of the first group. If the error correction algorithm applied to the first group based on the first ECC bitset fails, the error correction algorithm functions to correct the error in the second group based on the second ECC bitset.

The memory may be a flash memory. The error correction algorithm may also function to correct the first group based on the first ECC bit set. The error correction algorithm can also function to correct the second group based on the second ECC bit set. The memory may function to store additional ECC bit sets with information corresponding to additional memory cell groups. Further groups have a third size smaller than the second size and are part of the second group. The error correction algorithm may further function to be applied to a second group based on a second ECC bit group and, in the event of failure, to be applied to a further group based on an additional ECC bit set. The error correction algorithm may function to correct additional groups based on additional ECC bit sets. An error correction algorithm can be applied in the first group to correct the error up to the second bit error rate, where the second bit error rate is greater than the first bit error rate.

Further features, advantages, and modifications of the above-described embodiments will be clarified from the drawings and description below. For a better understanding of the present invention with respect to these embodiments, reference is made to the accompanying drawings. Similar numbers in the attached drawings refer to matching parts or elements.

<figref num="1A">It is a block diagram of one Embodiment of the computer system which corrects an error with a memory array.</figref><figref num="1B">FIG. 1A is a block diagram of the memory array, in which the error correction algorithm is implemented to generate 3 sets of ECC bits for each data unit.</figref><figref num="2">It is a flowchart which writes data to a memory array according to a typical embodiment.</figref><figref num="3">It is a flowchart which reads data from a memory array according to a typical embodiment.</figref>

The invention, defined by the appended claims, is better understood by reference to a detailed description of typical and preferred embodiments. This description is not intended to limit the scope of claims and provides examples of such embodiments. Therefore, typical embodiments presented in the following discussion include computer systems and methods thereof for correcting errors in memory arrays.

In one embodiment of a computer system, an error correction algorithm is used to correct errors in the memory array. This memory array contains two or more memory cell groups, the smaller memory cell group contains the smallest memory cell group, the larger group contains the smaller memory cell group, and so on. Each memory cell group is stored in the memory array in relation to a set of ECC bits corresponding to the width and length of the group. One set of ECC bits contains information corresponding to the first memory cell group, another set of ECC bits contains information corresponding to the second memory cell group, and so on. By generating ECC bits in this way, the best overall performance is achieved while performing error correction on the memory array.

This error correction algorithm can correct errors up to the first bit error rate (eg up to 6 bits per 512 bytes) in a correctable memory cell group of standard size (eg 256 bytes). An error correction algorithm is first applied to correct a large memory cell group using the corresponding ECC bits of this group, and if this corrective action fails, an error correction algorithm is applied to correct a small memory cell group. .. If this small group fails, further error correction algorithms can be applied to correct the smaller memory cell groups contained within this group. This corrective action can be repeatedly applied to smaller memory cell groups based on the corresponding ECC bits until the correction is successful. If successful, the data in all interrelated memory cell groups will be corrected in this process.

FIG. 1A is a typical embodiment of a computer system 10 having an error correction algorithm 12 that corrects errors in the memory array 14. The memory array 14 may be a flash memory. The error correction algorithm 12 can correct errors up to the first bit error rate (eg up to 6 bits per 512 bytes) in a correctable memory cell group (eg MC1) of standard size (eg 256 bytes). A controller 18 is provided to write data to the memory array 14 and read data from the memory array 14.

The memory array 14 includes a plurality of data units 16. The number of bytes in the data unit may be any number, including, but not limited to, 256 bytes, 512 bytes, and the like. In this example, the error correction algorithm 12 is implemented so as to generate two sets of ECC bits for each data unit 16. The first ECC bit set ECC1-2 has the information corresponding to the first memory cell groups MC1 and MC2, and the second ECC bit set ECC1 has the information corresponding to the second memory cell group MC1. (Alternatively, the second ECC bitset may have information corresponding to memory cell group MC2). The first memory cell groups MC1 and MC2 have a first size (eg, 512 bytes) that is larger than the standard size. The second memory cell group MC1 has a second size (eg, 256 bytes) that is smaller than the first size. The second memory cell group MC1 forms part of the first groups MC1 and MC2. The first ECC bit set ECC1-2 and the second ECC bit set ECC1 are stored in the memory array 14 in relation to the respective data unit 16.

The error correction algorithm 12 functions to correct errors in the first groups MC1 and MC2 based on the first ECC bitset ECC1-2. If this process fails (for example, if there are 7 or more errors in the first group MC1 and MC2), error correction algorithm 12 will try to correct the errors in the second group MC1 based on the second ECC bitset ECC1. Function. In other words, if the error correction algorithm 12 applied to the first groups MC1 and MC2 based on the first ECC bitset ECC1-2 fails, the error correction algorithm 12 will be based on the second ECC bitset ECC1. Works to correct errors in group MC1 of 2. Therefore, in order to correct errors in the first groups MC1 and MC2 up to a second bit error rate greater than the first bit error rate, for example 8 bits per 512 bytes, error correction algorithm 12 (initially up to 6 bit error rate). (Implemented to correct) is used.

It should be understood that different memory configurations can be used for different embodiments and that the particular embodiment shown in the figure should not be construed as limiting to this embodiment. For example, ECC bit sets may be adjacent to memory cells, their placement may be non-data units, and / or various types of error correction algorithms can be provided. The error correction algorithm can be applied to generate two more sets of ECC bits, three sets of ECC bits (see Figure 1B), or four or more sets of ECC bits, and the memory array has two sets of ECC bits, three sets of ECC bits. It can be implemented to store ECC bits or 4 or more sets of ECC bits.

The error correction algorithm 12 may also function to correct the first groups MC1 and MC2 based on the first ECC bitset ECC1-2. Instead of those mentioned above, otherwise in addition to those mentioned above, error correction algorithm 12 may function to correct the second group MC1 based on the second ECC bitset ECC1. The memory array 14 can function to store an additional ECC bit set with information corresponding to an additional memory cell group, which has a third size smaller than the second size and a second group. It forms a part of MC1. In this case, if the error correction algorithm 12 applied to the second group MC1 based on the second ECC bit group ECC1 fails, the error correction algorithm 12 is applied to additional memory cell groups based on the additional ECC bitset. (See Figure 1B). Error correction algorithm 12 also functions to correct additional memory cell groups based on additional ECC bit sets.

FIG. 1B is a typical embodiment of the memory array 14 of FIG. 1A, in which the error correction algorithm 12 is implemented to generate 3 sets of ECC bits for each data unit 16. In this example, the error correction algorithm 12 is implemented to generate 3 sets of ECC bits for each data unit 16. The first ECC bitset ECC'1-3 has information corresponding to the first memory cell groups MC'1, MC'2, and MC'3, and the second ECC bitset ECC'1-2 It has information corresponding to the second memory cell groups MC'1 and MC'2, and the third ECC bit set ECC'1 has information corresponding to the third memory cell group MC'1. The first memory cell groups MC'1, MC'2, and MC'3 have a first size (eg, 640 bytes) that is larger than the standard size. The second memory cell groups MC'1 and MC'2 have a second size smaller than the first size. The second memory cell groups MC'1 and MC'2 form part of the first groups MC'1, MC'2, and MC'3. The third memory cell group MC'1 has a third size smaller than the second size. The third memory cell group MC'1 forms part of the second groups MC'1 and MC'2. The first ECC bitset ECC'1-3, the second ECC bitset ECC'1-2, and the third ECC bitset ECC'1 are in the memory array 14 in relation to their respective data units 16. Stored.

The error correction algorithm 12 functions to correct errors in the first groups MC'1, MC'2, and MC'3 based on the first ECC bitset ECC'1-3. If this process fails (for example, if there are 7 or more errors in the first group MC'1, MC'2, and MC'3), the error correction algorithm 12 will use the second ECC bitset ECC'1-2. It works to correct the error in the second groups MC'1 and MC'2 based on. Only if this second process fails (for example, if there are 7 or more errors in the second groups MC'1 and MC'2), the error correction algorithm 12 goes to the third ECC bitset ECC'1. Based on this, it works to correct the error in the third group MC'1.

FIG. 2 is a flowchart 30 of a method of writing data to the memory array of the computer system 10 having the error correction algorithm 12 according to a typical embodiment. 32 writes data to the memory array. The error correction algorithm can correct errors up to the first bit error rate in a correctable memory cell group of standard size (eg 256 bytes). In this example, the error correction algorithm 12 is implemented to generate 3 sets of ECC bits for each data unit 16.

In 34, the first ECC bit set ECC'1-3 is generated because of the written data. The first ECC bit set has information corresponding to the first memory cell groups MC'1, MC'2, and MC'3. The first group has a first size (eg, 512 bytes) that is larger than the standard size. At 36, a second ECC bit set ECC'1-2 is generated for the written data. The second ECC bit set has information corresponding to the second memory cell groups MC'1 and MC'2. The second group has a second size smaller than the first size and forms part of the first memory cell group. At 38, for the written data, an additional ECC bit set (in this example, the third set ECC'1) is generated. An additional ECC bit set has information corresponding to an additional memory cell group (in this example, a third group MC'1). The third memory cell group has a third size smaller than the second size and forms a part of the second memory cell group. At 39, all ECC bit sets are written to the memory array.

In some embodiments and / or some codes, the generation of the first, second, and third ECC bit sets is applied as a single step. In another embodiment, there may be at least two separate steps to generate a first ECC bit set, a second ECC bit set, and a third ECC bit set.

FIG. 3 is a flowchart 50 of a method of reading data from a memory array according to a typical embodiment. In 52, the data and the corresponding ECC bits are read from the memory array, and an error correction algorithm (the one in Fig. 2) is applied to correct the error in the first memory cell group based on the first ECC bit set.

If the error correction algorithm succeeds based on the first ECC bitset (54), then the first memory cell groups MC'1, MC'2, and MC' based on the first ECC bitset ECC'1-3. 3 is corrected and the success signal is asserted (step 56). If the error correction algorithm fails based on the first ECC bitset (54), the second memory cell groups MC'1 and MC'2 are corrected based on the second ECC bitset ECC'1-2. .. If the error correction algorithm succeeds based on the second ECC bitset (60), the second memory cell groups MC'1 and MC'2 are corrected based on the second ECC bitset ECC'1-2. The first memory cell groups MC'1, MC'2, and MC'3 are then corrected based on the first ECC bitset ECC'1-3. Then, the success signal is asserted (step 56). If the error correction algorithm fails based on the second ECC bitset (60), the additional memory cell group MC'1 is corrected based on the additional ECC bitset ECC'1 (62). In this step (62), the additional memory cell group MC'1 is corrected based on the additional ECC bitset ECC'1 and then the second memory cell group MC'1 based on the second ECC bitset ECC'1-2. 1 and MC'2 are corrected, and then the first memory cell groups MC'1, MC'2, and MC'3 are corrected based on the first ECC bitset ECC'1-3. Then, the success signal is asserted (step 56).

Here, the computer system consists of an error correction algorithm applied to generate two or three ECC bit sets and a memory array implemented to store these ECC bit sets. It should be understood that computer systems and methods can also be applied to generate four or more sets of ECC bits and store four or more sets of ECC bits. Also, the hub that serves as the connection port to the large-capacity storage device may be of any type.

Although various embodiments of the system and method have been described so far, those skilled in the art will come up with further amendments, and such amendments will be treated as being within the appended claims, so this description limits them. It should be understood that it is not intended.