Correction of errors in a memory array

A is used for a school according the computer system in memory array, comprising error correction algorithm and memory. The error correction algorithm is a middle of with standard of High Connection of a set of storage device adjustable first bit rate error interpolation. The memory and operation of storage with device of storage device communication information first device for ECC Bits, and storage with the second group of storage device information openings and device for ECC Bits, wherein the set of storage device with is larger than of the standard of the first size, and second group of storage device with smaller than of the first of the second size and is the device for part. The error correction algorithm to be operation, and based on ECC Bits of the first device is a set of when the adjusting unsuccessfully, based on ECC Bits of the second device to synchronize to the middle is provided with a clamping the second group.