A stacked non-volatile memory device

This application claims priority under US Provisional Application No. 60 / 748,807, entitled "Process of Multi Layer NAND NROM," filed December 9, 2005, under United States Code Vol. 35, 119 (e). And incorporate the whole here as a reference.

The embodiments described herein relate to a non-volatile memory device and its manufacturing method, and more particularly to a stacked non-volatile memory device and its manufacturing method.

Non-volatile memory devices are being used in more products. For example, flash-type memory devices are used in MP3 players, digital cameras, and as storage devices for computer files and the like. As these uses increase, there is a demand for large memory that fits in a small package. This requires the production of higher density memory. Therefore, research and development has been directed to increasing the density of conventional non-volatile memory devices.

One way to increase the density of non-volatile memory devices is to create stacked memory devices (ie, devices with memory cell layers stacked on top of each other). Unfortunately, to date, few attempts have been made to create some sort of stacked memory device. For example, there are few laminated nitride read-only memory designs. This is partly because stacked memory devices are not always compatible with the latest manufacturing processes, which can make manufacturing stacked memory devices inefficient and costly. is there.

There are other ways to increase the density of traditional non-volatile memory devices, but these methods do not raise the need for all applications. Therefore, additional or other methods are still needed to increase the density of conventional non-volatile memory devices.

A particular type of non-volatile memory device is a nitride read-only memory device. FIG. 1 illustrates a conventional nitride read-only memory structure 150. As can be seen, the nitride read-only memory 150 is built on a silicon substrate 152. The silicon substrate may be a P-type silicon substrate or an N-type silicon substrate, but for various design reasons, a P-type silicon substrate is often preferred. Then, the source / drain regions 154 and 156 are injected into the substrate 152. Then, the trap structure 158 is formed between the source / drain regions 154 and 156 on the substrate 152. A control gate 160 is formed on top of the trap structure 158.

Source / drain regions 154, 156 are silicon regions doped in the opposite mold to that of substrate 152. For example, when a P-type silicon substrate 152 is used, N-type source / drain regions 154 and 156 can be injected into it.

The charge trap structure 158 has a nitride trap layer and an isolation oxide layer between the trap layer and the channel 166 in the substrate 152. In other embodiments, the trap structure 158 can also include a nitride trap layer, such as an oxide or, more specifically, a silicon dioxide layer, sandwiched between two isolation or dielectric layers. Such a configuration is often referred to as an oxide-nitride-oxide (ONO) trap structure.

The charges are accumulated and confined in the trap structure 158 next to the source / drain regions 154, 156 and effectively store two separate independent charges 162, 164. Each charge 162, 164 can be maintained in one of two states, programmed or erased, represented by the presence or absence of trap electron pockets. This allows two bits of information to be stored without the complexity of multi-level cell technology.

Each storage area in the nitride read-only memory cell 150 can be programmed independently of the other storage areas. Nitride read-only memory cells are programmed by applying a voltage that injects negatively charged electrons into the nitride layer of trap structure 158 near one end of the cell. Elimination is previously accomplished by applying a voltage that injects vacancies into the location of the nitride layer that can supplement the electrons stored in the nitride layer during the program.

The nitride read-only memory device is constructed by manufacturing a memory cell array such as the cell illustrated in FIG. Arrays are constructed by connecting cells together with words and bitlines.

Nitride read-only memory devices, such as the device illustrated in FIG. 1, can be configured to store a large number of bits per cell, but the increased density of nitride read-only memory devices is instead stacked. This is possible by using the type configuration. Unfortunately, stacking nitride read-only memory devices is rare, making the process inefficient and costly.

A method for manufacturing a stacked non-volatile memory device is disclosed. The disclosed method utilizes efficient processing techniques to manufacture laminated devices. Thus, the embodiments described herein can be freely resized to achieve varying levels of lamination.

According to one aspect, the laminated nitride read-only memory can be manufactured using the method described herein.

According to another aspect, laminated nitride read-only memory devices can be manufactured using silicon on insulator (SOI) processing techniques, such as thin film transistor (TFT) processing techniques.

According to another aspect, stacked memory devices manufactured using the methods described herein can be configured for NAND operations.

These and other features, aspects, and embodiments of the invention are described in the section entitled "Detailed Descriptions" below.

The dimensions, measured values, ranges, test results, numerical data, etc. presented below are approximate values by nature and are not intended to be accurate data except as stated otherwise. The nature of the relevant estimates depends on the nature of the data, the context, and the nature of the particular embodiment or implementation described.

FIG. 2 illustrates an example of the laminated nitride read-only memory 100 according to one embodiment. In the example of FIG. 2, the laminated nitride read-only memory 100 is manufactured on the insulating layer 102. Therefore, the device 100 is manufactured using SOI processing technology. For example, device 100 can be manufactured using thin film transistor (TFT) processing technology. Then, the subsequent bit line layer and word line layer can be manufactured on the insulating layer 102. For example, in FIG. 2, the first bitline layer 110 is manufactured on top of the insulating layer 102. Then, the first word line layer 120 is manufactured on the first bit layer 110. The second bitline layer 130 is then manufactured on top of the first wordline layer 120. Finally, the second wordline layer 140 is manufactured on the second bitline layer 130.

Following this, additional bitline and wordline layers can be manufactured on top of the layers illustrated in FIG. Therefore, the two bitline layers and the two wordline layers are only shown for convenience, and the method described here should be considered as limiting the bitline layer and / or the wordline layer to a certain number. Absent. Each bitline layer 110, 130 has a plurality of bitlines 104 separated by an insulating region 106. Each of the wordline layers 120 and 140 has a wordline conductor 105 sandwiched between the trap layers 103 and 107.

Larger memory densities can be achieved by utilizing the stacked configuration shown in FIG. Further, as described below, the structure 100 can be manufactured using efficient processing techniques.

FIG. 3-21 illustrates a sequence example of the structure 100 manufacturing steps according to one embodiment. As illustrated in FIG. 3, the semiconductor layer 204 can be formed on the insulating layer 202. In certain embodiments, for example, the insulating layer 202 may include an oxide material. The semiconductor layer 204 can include a P-type semiconductor material such as silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, it would be preferable for layer 204 to contain thin film polysilicon deposited on insulating layer 202. It will be appreciated that in other embodiments, the semiconductor layer 204 may include an N-type semiconductor material. Then, the cap layer 206 can be formed on the semiconductor layer 204. In certain embodiments, for example, the cap layer 206 can include a silicon nitride (SiN) material.

As illustrated in FIG. 4, layers 204, 206 can be patterned and etched using conventional photolithography techniques. FIG. 5 shows a top view of the layer containing the devices manufactured up to this point. FIG. 4 is a cross-sectional view taken along the line AA'of FIG. As can be seen in FIG. 5, the layers 206, 204 are patterned and etched to form a region 205 that completely traverses the insulating layer 202. As described below, the region 205 forms the bitline of the first bitline layer 110 shown in FIG.

With reference to FIG. 6, the dielectric layer 209 can be formed on the insulating layer 202, as illustrated. The dielectric layer 209 is, for example, silicon dioxide (SiO).₂) Layer, which can be formed using dense plasma (HDP) -chemical vapor deposition (CVD). Referring to FIG. 7, a portion of the dielectric layer 209 has been removed to expose the rest of the cap layer 206 and the rest of the semiconductor layer 204. For example, a portion of the dielectric layer 209 can be removed using conventional wet etching (ie, isotropic step). Removal of an appropriate amount of the dielectric layer 209 can be achieved by having a high etching selectivity between the dielectric layer 209 and the cap layer 206. By the etching process, a dielectric region 210 is formed on top of the cap layer 206 and a dielectric region 212 is formed between the rest of the semiconductor layer 204.

FIG. 8 shows a top view of the layers manufactured up to this point. FIG. 7 is a cross-sectional view taken along the line AA'of the layer. Therefore, as can be seen from FIG. 8, the dielectric region 212 now exists between the regions 205. According to the figure, the dielectric region 210 covers a part of the cap layer 206.

With reference to FIG. 9, when removing the region 210 of the dielectric layer 209, the remaining portion of the cap layer 206 can also be removed. For example, hot phosphoric acid can be utilized to remove the rest of the cap layer 206. Since the portion 210 is separated from the dielectric region 212, the region 210 of the dielectric layer 209 is automatically removed during the removal of the rest of the cap layer 206.

The process illustrated in Figure 6-9 is described in US Pat. No. 6,380,068, entitled "Methods for Flattening Flash Memory Devices," issued April 30, 2002, which has been assigned to the assignee of the present application. , As a whole, incorporate here as a reference. The process described in Figure 6-9 results in efficient flattening of the remaining surface shown in Figure 9. Therefore, the manufacturing process described here is compatible with a newer and more efficient processing technique. This makes the manufacture of stacked non-volatile memory devices efficient and cost effective.

FIG. 10 is a top view of the layers formed so far. FIG. 9 is a cross-sectional view taken along the line AA'of the layer shown in FIG. Thus, the insulating layer 202 is now alternately coated with an oxide region 212 and a bitline 205 formed from the rest of the semiconductor material 204.

The wordline 220 can then be formed on top of the bitline 205, as illustrated in Figure 11-13. As illustrated in FIG. 12, in the formation of the wordline 220, the trap structure 222 is first formed over the rest of the semiconductor layer 204 and the insulating region 212. Then, the wordline conductor 224 may be formed on the trap structure 222, and the second trap structure 218 may be formed on the wordline conductor 224. Then, a SiN layer (not shown) may be formed on the second trap structure 218. These layers can then be patterned and etched using conventional photolithography techniques to produce the wordline 220 as shown in FIG. Etching can be configured such that the HDP oxide region 212 acts as a stop in the etching process. Another HDP oxide layer (not shown) can also be formed on the etched wordline 220 (including SiN not shown). Then, the HDP layer may be partially etched to remove a part of the HDP oxide layer together with the rest of the SiN layer (not shown) in the same manner as shown in FIGS. 6-9. .. This leaves the HDP oxide region 242 between the word lines 220, as described below in the context of FIGS. 14 and 15.

In the examples of FIGS. 11 and 12, the trap structures 218 and 222 are ONO structures. Therefore, the trap structures 218 and 212 are formed by forming the oxide layer, the nitride layer, and the oxide layer in this order. For example, the oxide layer is SiO₂The nitride layer can have a SiN layer. As will be appreciated, the nitride layer acts as a trap layer that traps charges during programming. The trapped charge changes the threshold voltage of the memory cell, and when this is detected, the program state of the cell can be determined.

FIG. 23A-23H illustrates exemplary embodiments of various trap structures available within device 100. For example, with reference to FIG. 12, the structure illustrated in FIGS. 23A-23H can be used as the trap structure 222. The first exemplary embodiment illustrated in FIG. 23A has a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In this structure, the oxide layer 272, the nitride layer 274, and the oxide layer 276 are sequentially formed on the polysilicon layer 214. The oxide region 272 functions as a tunnel dielectric layer, and the nitride layer 274 accesses a trap layer that traps charges. Utilizing the SONOS structure of FIG. 23A, the charge is stored in the trap layer 274 of a particular cell by vacancy injection into the trap layer 274. By tunneling the vacancies directly to the trap layer 274, the cells can be erased, thereby supplementing the electrons previously stored in the trap layer 274. Tunneling to the trap layer 274 of the vacancies is achieved by tunneling by Fowler Nordheim. The oxide layer 272 may be a thin oxide layer (thickness less than 3 nanometers). The cells formed using the SONOS trap structure illustrated in FIG. 23A can be used, for example, in NAND memory applications.

NAND devices constructed using the SONOS trap structure illustrated in Figure 23A may be somewhat inferior in terms of charge conservation due to leakage current resulting from direct tunneling to the vacant trap layer 274 during charge conservation. is there.

FIG. 23B illustrates a nitride read-only memory trap structure. Again, the nitride read-only memory trap structure has an ONO structure formed by forming an oxide layer 278, a nitride layer 280, and a second oxide layer 282 in this order on the polysilicon region 214. However, here the oxide layer 278 has a thickness in the range of about 5-7 nanometers. The cells formed using the nitride read-only memory structure of FIG. 23B are programmed by injecting electrons into layer 280. The cells formed using the nitride read-only memory structure of FIG. 23B can then be erased by hot hole erase techniques. The nitride read-only memory structure of Figure 23B can also be used for NOR applications, but devices built using the nitride read-only memory structure of Figure 23B suffer some degradation due to hot vacancy elimination technology. Present.

Figure 23C illustrates the Band-gap Engineered (BE) -SONOS structure. The BE-SONOS structure shown in FIG. 23C is manufactured by forming the ONO structure 294, then the nitride layer 290, and the dielectric layer 292 in that order. Therefore, the ONO structure 294 is formed by forming the oxide layer 284, the nitride layer 286, and the oxide layer 288 on the polysilicon layer 214 in this order. Similar to the SONOS structure in Figure 23A, the BE-SONOS structure in Figure 23C also uses Fowler Nordheim's vacant tunneling to erase memory cells, but the BE-SONOS structure in Figure 23C is directly subject to tunneling leaks. No device deterioration due to storage inconvenience due to or hot vacancies erasure damage is observed. Furthermore, the BE-SONOS structure in Figure 23C can be used for both NOR and NAND applications.

23I and 23J are band diagrams illustrating the band of the ONO structure 294 of the BE-SONOS structure illustrated in FIG. 23C. FIG. 23I is a band diagram during data storage, and FIG. 23J is a band diagram during erasure. As can be seen from FIG. 23I, during storage, the vacancies do not have sufficient energy to overcome the potential wall of the layer with ONO structure 294. Data storage occurs in the presence of low electric fields across the trap structure 294. Since the structure 294 blocks the tunneling of the holes, there is not much tunneling leakage during the application of low electric fields. However, as illustrated in FIG. 23J, when a high electric field is present over the trap structure 294, the band shifts to tunnel the vacancies into the structure 294. This is because the walls exhibited by layers 286 and 288 are almost eliminated in terms of vacancies due to the band shift in the presence of high electric fields.

FIG. 23D-23H illustrates other exemplary structures available for the trap layer included in device 100. For example, FIG. 23D illustrates the SONS structure available for the trap layer included in device 100. The structure illustrated in FIG. 23D includes a thin oxide layer 302 formed on top of the polysilicon layer 214. Then, the nitride layer 304 is formed on the thin oxide layer 302. Then, the gate conductor layer 224 can be formed on the nitride layer 304. The thin oxide layer 302 functions as a tunnel dielectric and can store charges in the nitride layer 304.

FIG. 23E is an example of the upper BE-SONOS structure that can be used for the trap structure included in the device 100. Thus, the structure illustrated in FIG. 23E includes an oxide layer 306 formed on the polysilicon layer 214. Then, the nitride layer 308 is formed on the oxide layer 306, and the ONO structure 315 including the oxide layer 310, the nitride layer 312, and the oxide layer 314 is formed on the nitride layer 308. In the example of FIG. 23E, the oxide layer 306 can function as a tunnel dielectric layer and trap charges in the nitride layer 308.

FIG. 23F illustrates the lower SONOSOS structure available for the trap layer contained in device 100. The structure illustrated in FIG. 23F includes an oxide layer 316 formed on the polysilicon layer 214 and a nitride layer 318 formed on the oxide layer 316. A thin oxide layer 320 is then formed on the nitride layer 318, followed by a thin polysilicon layer 322. Another thin oxide layer 324 is then formed on top of the polysilicon layer 322. Therefore, layers 320, 322, and 324 were formed, and an OSO structure was formed near the gate conductor 224. In the example of FIG. 23F, the oxide layer 316 can function as a tunnel dielectric and can store charges in the nitride layer 318.

FIG. 23G illustrates the lower SOSONOS structure. Here, a thin OSO structure 325 is formed on the polysilicon layer 214. The OSO structure 325 has a thin oxide layer 326, a thin polysilicon layer 328, and a thin oxide layer 330. Then, the nitride layer 332 can be formed on the OSO structure 325, and the oxide layer 334 can be formed on the nitride layer 332. In the example of FIG. 23G, the OSO structure 325 can act as a tunnel dielectric and store charges in the nitride layer 332.

FIG. 23H illustrates an example of a SONONS structure that can be used for the trap structure included in device 100. Here, the oxide layer 336 is formed on the polysilicon layer 214, and the nitride layer 338 is formed on the oxide layer 336. The ON structure 341 is formed on the nitride layer 338. The ON structure 341 has a thin oxide layer 340 formed on the nitride layer 338 and a thin nitride layer 342 formed on the thin oxide layer 340. In the example of FIG. 23H, the oxide layer 336 has access to the tunnel dielectric and the charge can be trapped in the nitride layer 338.

In other embodiments, the trap structure is SiN or SiON, or HfO.₂, Al₂O₃, AlN and other Hi-K materials can be included. In general, any trap structure or material can be utilized as long as it meets the requirements of a particular application.

Wardline conductor 224 can be formed from polysilicon materials, N + or P + conductor materials such as polysilicon / VDD / polysilicon materials, or metals such as aluminum (Al), copper (Cu), or tungsten (W). ..

Once the wordline 220 is formed, the source and drain regions 216 can be formed in the region of the semiconductor layer 204 having the bitline 205 uncovered by the wordline 220. Therefore, these source and drain regions 216 can be injected and thermally driven into the region 216 of the semiconductor layer 204. As will be understood, this process is a self-aligning process. In the example of FIG. 11, the source and drain regions should be N + regions formed by utilizing arsenic (As), phosphorus (P), etc., because the semiconductor layer 204 is a P-type semiconductor material. Because it consists of. It will be understood that the P + region should be formed in embodiments that utilize N-type semiconductor materials.

After the formation of the source and drain regions 216, the semiconductor layer 204 has a source / drain region 216 doped as an N + region and a P-type region 214 remaining beneath the wordline 220. As described below, these P-type regions 214 form channel regions for specific memory cells.

FIG. 12 is a cross-sectional view taken along the line AA'of the layer illustrated in FIG. As can be seen, the P-type region 214 remains below the wordline 220 and is separated by the dielectric region 212. FIG. 13 is a cross-sectional view taken along the line BB'. As can be seen from FIG. 13, the N + doped region 216 is formed between the word lines 220 and separated by the dielectric region 212. HDP oxide regions 242 can also be formed between word lines 220, as illustrated in FIGS. 14 and 15.

As illustrated in FIG. 16-18, a second bitline layer (bitline layer 130) is formed on the wordline 220. Therefore, as shown in FIG. 16, the bit line 228 can be formed on the word line 220. These bitlines can be formed in the same process that was used to form the bitline 205 illustrated in Figure 6-9. The bit line 228 is therefore separated by the dielectric region 236. FIG. 17 is a cross-sectional view taken along the line BB'. As can be seen, the first bitline layer 110 is separated from the second bitline layer 130 by the HDP oxide 242 in the region between the wordlines 220. FIG. 18 is a cross-sectional view taken along the line AA'. As can be seen, the bitline 228 is formed on the wordline 220 formed on the bitline 205.

As illustrated in FIG. 19-21, a wordline 230 can be formed on the bitline 228 to form a second wordline layer (wordline layer 140). Like the wordline 220, the wordline 230 can include a wordline conductor 246 sandwiched between trap structures 240, 244. This is illustrated in FIG. 21, which is a cross-sectional view taken along line AA'of the layer illustrated in FIG. FIG. 20 is a cross-sectional view taken along the line BB'.

Therefore, in the example of FIG. 21, the trap structures 240 and 244 are formed by forming the oxide layer, the nitride layer, and the oxide layer in this order. For example, the oxide layer is SiO₂The nitride layer can have a SiN layer. As will be appreciated, the nitride layer acts as a trap layer that traps charges during device programming processing. The trapped charge changes the threshold voltage of the memory cell, and when this is detected, the program state of the cell can be determined.

In other embodiments, the trap structures 240, 244 can have any of the structures illustrated in FIGS. 23A-23H.

In other embodiments, the trap structure is SiN or SiON, or HfO.₂, Al₂O₃, AlN and other Hi-K materials can be included. In general, any trap structure or material can be utilized as long as it meets the requirements of a particular application.

Wardline conductor 246 can be formed from polysilicon materials, N + or P + conductor materials such as polysilicon / VDD / polysilicon materials, or metals such as aluminum (Al), copper (Cu), or tungsten (W). ..

Once the wordline 230 is formed, the source and drain regions 234 can be formed in the region of the bitline 228 that is not covered by the wordline 230. Thus, these source and drain regions 234 can be injected and heat driven into the bitline 228. As will be understood, this process is a self-aligning process. In the example of FIG. 19, the source and drain regions should be N + regions formed using arsenic (As), phosphorus (P), etc., because the bitline 228 is a P-type semiconductor material. Because it consists of. It will be understood that the P + region should be formed in embodiments that utilize N-type semiconductor materials.

After the formation of the source and drain regions 234, the bitline 228 has a source / drain region 234 doped as an N + region and a P-region 232 that remains beneath the wordline 230. As described below, these P-type regions 232 form channel regions for specific memory cells.

As illustrated in FIG. 22, the process shown in FIG. 3-21 produces a stacked memory array containing a plurality of memory cells. These three cells 250, 252, and 254 are illustrated in FIG. Region 234 forms the source and drain regions of each cell, and current flows through the cells in the direction of the arrow. The cell can be configured for NAND processing. Cells 250, 252, 254 are in the upper layer of the array, but the array contains multiple cell layers stacked on top of each. This can be illustrated in the cross-sectional view of FIG.

As can be seen from FIG. 21, the trap structure 240 forms the gate of the structure of cells 250, 252, 254, the area 236 below the trap structure 240 forms the channel area of cells 250, 252, 254, and the wordline 230. The source / drain region 234 on either side of the cell forms the source and drain regions of cells 250, 252, and 254 (see Figure 22). In addition, the trap structure 218 can form a layered gate structure of memory cells (cells 256, 258, 260 under cells 250, 252, 254). The area 236 above the trap structure 218 forms the channel area of cells 256, 258, 260, and the source / drain area 234 on either side of the wordline 230 covers the source and drain areas of cells 256, 258, 260. Form. Here, the conductive conductor 224 forms an actual wordline that supplies voltage to the gate structures of cells 256, 258, 260.

A third layer of memory cells (eg, cells 262, 264, 266) resides below cells 256, 258, 260, as illustrated in FIG. The trap structure 222 forms the gate structure of these cells. The conductor layer 224 forms the actual wordline that supplies voltage to the gate structures of the various cells. The area 214 below the wordline 220 forms the channel area of these cells, and the area 216 on either side of the wordline 220 forms the source and drain areas of these cells.

FIG. 24 illustrates a stacking example. The non-volatile memory device is configured according to one embodiment. 25-35 illustrates the progress of the manufacturing step of the device of FIG. 24 according to another embodiment. The embodiments described with respect to FIGS. 24-35 present a simpler design in which the wordline cannot be shared between memory cells. As can be seen from FIG. 24, the process illustrated in FIGS. 24-35 has an insulator or dielectric layer 2402 with a wordline / bitline layer laminated on top of the insulator 2402, interlayer or intermodule dielectric. Manufacture a stacked memory structure separated by layer 2404. The wordline and bitline layers have a bitline 2410 separated from the wordline 2406 by a trap structure 2408. As described below, the bitline layer can also be deposited and patterned and etched to form the bitline 2410. The trap structure layer can also be deposited to deposit the wordline layer on top of the trap structure layer. The wordline and trap structural layers can also be patterned and etched to form a wordline above the bitline 2410. The trap structure 2408 above the bit line 2410 and below the word line 2406 can then function as a trap layer for storing charges in memory cells.

25-35 illustrates an example of the manufacturing process of the device illustrated in FIG. 24. As illustrated in FIG. 25, the polysilicon layer 2504 can be deposited on top of the insulating layer 2502. The insulating layer 2502 can include an oxide layer (eg, silicon dioxide material (SiO)). The polysilicon layer 2504 can have a thickness in the range of about 200-1,000 A. For example, the thickness of the polysilicon layer 2504 is preferably about 400A, according to some embodiments.

Referring to FIG. 26, the polysilicon layer 2504 is patterned and etched by a conventional photolithography process to produce the bitline region 2506. For example, the insulating layer 2502 is used as an etching stop in the etching process to produce region 2506. The total thickness of the layer illustrated in FIG. 26 may be about 200-1000A, preferably about 400A.

Figures 27A-27C illustrate an alternative process of etching the polysilicon layer 2504 to produce the bitline region 2506. With reference to FIG. 27A, the cap layer 2508 can be formed on top of the polysilicon layer 2504. For example, the cap layer 2508 can have a silicon nitride (SiN) layer. The polysilicon layer 2504 and cap layer 2508 can then be patterned and etched using conventional photolithography techniques, as illustrated in FIG. 27B. Again, the insulating layer 2502 can function as an etching stop in the etching process.

With reference to FIG. 27C, after etching layers 2504 and 2508 to form regions 2506, 2510, and cap layer 2508, the previous steps can be used to remove region 2510.

With reference to FIG. 28, the trap structure layer 2508 can be formed on the insulating layer 2502 and the bitline region 2506. As mentioned above, the trap structure layer 2508 can include any of a plurality of trap structures, such as SONOS, BE-SONOS, upper BE-SONOS, SONONS, SONOSLS, SLSLNLS, and the like. In other embodiments, the trap structure layer 2508 is a SiN material, a SiON material, or an HfO.₂, Al₂O₃, High-K materials such as AlN, etc. can be included.

With reference to FIG. 29, the wordline layer 2510 can be formed on top of the trap structure layer 2508. For example, the wordline layer 2510 can include a polysilicon material deposited on top of the trap structure layer 2508. Layers 2510 and 2508 can then be patterned and etched using conventional photolithography techniques. As illustrated in FIG. 31, this creates a wordline 2510 on top of the bitline 2506.

As can be seen from FIG. 30, the etching process is configured to etch the trap structure layer 2508 in the region between the word lines 2510. As a result, the region 2506 is generated so that the region 2512 of the trap structure layer 2508 remains on both sides of the region 2506.

FIG. 31 is a top view of the layers formed so far. FIG. 29 is a cross-sectional view taken along the line AA'of the layer illustrated in FIG. FIG. 30 is a cross-sectional view taken along the line BB'of the layer illustrated in FIG. 31.

With reference to FIG. 34, the source and drain regions 2514 can be deposited within the region of bitline 2506, not below the wordline 2510. For example, if the wordline 2506 is made of P-type polysilicon material, the N-type source / drain region 2514 can be injected and thermally driven into the region of bitline 2506 that is not below the wordline 2510. Instead, given that the wordline 2506 consists of an N-type polysilicon material, the P-type source / drain region can be injected and thermally driven into the bitline 2506.

FIG. 32 is a cross-sectional view taken along the line AA'of the layer illustrated in FIG. 34. FIG. 33 is a cross-sectional view taken along the line BB'of the layer illustrated in FIG. 34. Therefore, it can be seen that the bitline 2506 now contains the channel region 2516 below the wordline layer 2510. The source and drain regions 2514 are then formed on either side of the wordline 2510. It will be understood that the formation of the source / drain region 2514 is a self-aligning process.

With reference to FIG. 35, an interlayer or intermodule dielectric layer 2518 can be formed on top of the wordline layer 2510. Another bitline and wordline layer can then be formed on top of the interlayer or intermodule dielectric 2518 using the same machining steps as described above. In this way, any number of wordline and bitline layers separated by the interlayer or intermodule dielectric 2518 can be formed on the insulating layer 2502.

With reference to FIG. 34, memory cells 2520-2526 can be formed in the structure shown. Memory cells 2520, 2522 are also illustrated in FIG. The source and drain areas of the memory cell are formed from the source / drain area 2514 on either side of the associated wordline 2510. The channel region is formed from region 2516 of bitline 2506 below wordline 2510. The cell is a tri-gate device, which suffers from excessive cornering effects, but as the device width increases, so does the cell current.

As mentioned above, the methods described here can be used to form stacked NAND memory devices. Figures 36 and 37 illustrate the processing characteristics of a 16-word line NAND device configured by the method described herein. As can be seen from Figure 36, when the device is in the erased state, the high voltage (V) is during the read process._READ) Is the first bit line (BL₁), The second layer bitline of the layered memory device layer is allowed to float, and the source line is tied to 0V. And the reading voltage (V_PASS) Can be read in cell (A) by adding) to the wordline in cell (A). + 7V V, as shown by the curve in Figure 36_PASSThe voltage produces a read current close to 1 μA, which is sufficient for NAND processing.

FIG. 37 illustrates a method of limiting program interference in cells adjacent to a cell in the program. In FIG. 37, cell (A) is programmed by applying a high voltage (eg, about + 17V) to the wordline of cell (A). BL₁Is tied to 0V, while the source line is allowed to float. BL₂Is raised to about + 8V, and the wordline associated with cells (C) (D) is raised to about + 9V. Therefore, cells (C) and (D) are subject to intermediate electric field gate interference, while cell (B) is program-suppressed by raising the channel potential of cell (B). The graph in FIG. 37 illustrates that the program processing performed under the above conditions does not cause much significant program interference.

Although certain embodiments of the present invention have been described above, it will be appreciated that the described embodiments are merely exemplary. Therefore, the present invention should not be limited based on the described embodiments. Instead, the scope of the invention described herein should be limited only in view of the subsequent claims combined with the above description and accompanying drawings.

<figref num="1">The conventional nitride read-only memory structure is illustrated.</figref>

<figref num="2">The laminated nitride read-only memory structure according to one embodiment is illustrated.</figref>

<figref num="3-21">An example of the progress of the manufacturing step of the laminated nitride read-only memory of FIG. 2 according to one embodiment is illustrated.</figref>

<figref num="22">The current path of the selected memory cell of the NAND array manufactured using the steps illustrated in Figure 3-21 is illustrated.</figref>

<figref num="23A-23H">An example structure that can be used to form the trap structure for the device of FIG. 2 is illustrated.</figref>

<figref num="23I-23J">It is a band diagram of the structure illustrated in FIG. 23C.</figref>

<figref num="24">Another example of a stacked non-volatile memory structure configured according to one embodiment is illustrated.</figref>

<figref num="25-35">A machining step with an example of a process of manufacturing the device of FIG. 24 according to one embodiment is illustrated.</figref>

<figref num="36-37">An example of operating characteristics of a TFT NAND device manufactured by the method illustrated in the above drawing is illustrated.</figref>