JP4846979B2

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Abstract

This record has no abstract on file.

JP4846979B2, drawing sheet 1 — Sheet 1 of 44

Term

Term ended

Expired 31 October 2022, 3.9 years ago.

12 claims: 3 independent, 9 dependent

1
不揮発性メモリセルアレイにおいて、個々のメモリセルからなるソース/ドレイン領域(152,153;185,186,187;341,343)間の半導体基板(163;183;257;301)の表面上の電荷格納誘電体(165;201;245,246,247,248,249;297;306)の中の水平で同一平面上の複数の隣接領域(171~174;211~214;265~267;269~272;327~330)にデータを表す電荷レベルを格納する方法であって、ソース側注入、ホットエレクトロン注入、ファウラー-ノルドハイムトンネリング、およびバリスティック注入からなるグループの中から選択された少なくとも2つの異なるメカニズムによって、前記複数の隣接領域(171~174;211~214;265~267;269~272;327~330)のうちの第1および第2の領域に電荷を格納するステップを含み、前記第1および第2の領域のうちの個々の領域に3以上の電荷レベルを格納し、それによって、前記第1および第2の領域のうちの個々の領域に2以上のビットデータを格納する方法。
2
請求項1記載の方法において、個々のメモリセルからなるソース/ドレイン領域(152,153;185,186,187;341,343)間の少なくとも1つの導電性制御ゲート(157,160;189~194;241~244;317~323,353,355)と半導体基板(163;183;257;301)の表面との間に誘電体が挟持され、ソース側注入により前記複数の隣接領域(171~174;211~214;265~267;269~272;327~330)のうちの第1の領域に電荷を格納するステップと、ホットエレクトロン注入により前記複数の隣接領域(171~174;211~214;265~267;269~272;327~330)のうちの第2の領域に電荷を格納するステップとをさらに有する方法。
3
導電性制御ゲート(157,160;189~194;241~244;317~323;353;355)と、ソース/ドレイン領域(152,153;185,186,187;341,343)間の表面にわたって延在する半導電性チャネル内の半導体基板(163;183;257;301)の表面との間に配置された電荷格納誘電体 (165;201;245,246,247,248,249;297;306) を個々に有するメモリセルアレイを含むタイプの不揮発性メモリであって、少なくとも前記導電性制御ゲート(157,160;189~194;241~244;317~323;353;355)と接続可能な電圧源とソース/ドレイン領域(152,153;185,186,187;341,343)とを含み、ソース側注入、ホットエレクトロン注入、ファウラー-ノルドハイムトンネリング、およびバリスティック注入からなるグループの中から選択されたメカニズムによって個々のアドレス指定されたメモリセルのチャネルにわたる電荷格納誘電体(165;201;245,246,247,248,249;297;306)の中の水平で同一平面上の複数の隣接領域 (171~174;211~214;265~267;269~272;327~330) のうちの少なくとも2つの重ならない領域に電荷が半導体基板(163;183;257;301)から注入される大きさで電圧を供給して、プログラムされるべきデータに従って3以上のレベルのうちの1つのレベルにチャネルのそれぞれの少なくとも2つの部分のしきい値を調整するレベルにし、それによって前記電荷格納誘電体(165;201;245,246,247,248,249;297;306)の中の前記複数の隣接領域 (171~174;211~214;265~267;269~272;327~330)のうちの少なくとも2つの規定された重ならない領域の個々の領域がそのような2以上のビットデータを格納することができるプログラミング回路と、読み出し用回路であって、前記少なくとも導電性制御ゲート(157,160;189~194;241~244;317~323;353;355)と接続可能な電圧源と、前記電荷格納誘電体(165;201;245,246,247,248,249;297;306)の中の前記複数の隣接領域 (171~174;211~214;265~267;269~272;327~330) のうちの重ならない領域に格納された電荷レベルを測定し、それによって前記電荷格納誘電体(165;201;245,246,247,248,249;297;306)の中の前記複数の隣接領域(171~174;211~214;265~267;269~272;327~330)のうちの個々の規定された領域から2以上のビットデータを読み出すための個々のアドレス指定されたメモリセルのソース/ドレイン領域 (152,153;185,186,187;341,343) のうちの少なくとも一方の領域と接続可能なセンス増幅器と、を含む読み出し用回路と、を備えるメモリ。
4
請求項3記載のメモリにおいて、前記電荷格納誘電体(165;201;245,246,247,248,249;297;306)は、窒化シリコンを含むメモリ。
5
請求項3~4のいずれか記載のメモリにおいて、前記電荷格納誘電体(165;201;245,246,247,248,249;297;306)は、シリコン・リッチ・シリコン二酸化物を含むメモリ。
6
請求項3~5のいずれか記載のメモリにおいて、前記電荷は、4つのしきい値レベルの範囲に注入されるメモリ。
7
請求項3~5のいずれか記載のメモリにおいて、前記電荷は、5以上のしきい値レベルの範囲に注入されるメモリ。
8
請求項3~7のいずれか記載のメモリにおいて、個々のメモリセルは、少なくともソース/ドレイン領域(152,153;185,186,187;341,343)間のチャネルに沿って連続して延在する前記電荷格納誘電体(165;201;245,246,247,248,249;297;306)をさらに含むメモリ。
9
請求項3記載のメモリにおいて、前記導電性制御ゲート(157,160;189~194;241~244;317~323;353;355)は、その下に前記電荷格納誘電体(165;201;245,246,247,248,249;297;306)の中の前記複数の隣接領域 (171~174;211~214;265~267;269~272;327~330) のうちの少なくとも2つの規定された重ならない領域を有するチャネルの別個のセグメントにわたって配置された少なくとも2つのゲートを含むメモリ。
10
請求項9記載のメモリにおいて、前記電荷格納誘電体(165;201;245,246,247,248,249;297;306)の中の前記複数の隣接領域(171~174;211~214;265~267;269~272;327~330)のうちの少なくとも1つの領域は、少なくとも2つのゲートのそれぞれの下に配置されるメモリ。
11
請求項9記載のメモリにおいて、前記少なくとも2つのゲートは、チャネルに対して垂直な方向に延在する長さを有する導電性ラインから形成された少なくとも2つのゲートを含むメモリ。
12
請求項9記載のメモリにおいて、前記少なくとも2つのゲートは、チャネルに対して垂直な方向に延在する長さを有する導電性ラインから形成された少なくとも1つのゲートと、チャネルと平行する方向に延在する長さを有する導電性ラインから形成された少なくとも1つのゲートとを含むメモリ。

Independent claims12

106 paragraphs, as filed

The present invention particularly relates to a type of non-volatile flash EEPROM (electrically erasable and programmable read-only memory) cell array that uses a dielectric charge storage element.

There are many commercially successful non-volatile memory products in use today, especially memory cells from commonly doped polysilicon materials.NaThere are non-volatile memory products in the form of small cards with conductive floating gates. This card has electricity according to the level of data status stored in it.KodenThe load is stored. In the general form of such a memory cell, a "split channel" is provided between the source spreading part and the drain spreading part. Floating gates of cells are placed over one part of the channel, and wordlines (also called control gates) are placed over the other part of the channel as well as floating gates. With this configuration, two series transistors can be used.PreparedCells are effectively formed. One transistor (memory transistor) is a channelToIt is a combination of the amount of charge applied to the floating gate, which controls the amount of current that can flow through the ranger section, and the voltage of the word line, and the other transistor (selective transistor) serves as the gate for this transistor. It has only the wordline to use.thisThe wordline extends over the floating gate row. In such cells and memory systemsthisSome examples showing how to use and make cellsThe whole is incorporated herein by reference.US Patent No. 5,070,032 (Patent Document 1), US Patent No. 5,095,344 (Patent Document 2), US Patent No. 5,315,541 (Patent Document 3), US Patent No. 5,343,063 (Patent Document 4), and US Patent No. 5,661,053. (Patent Document 5), and further described in US Pat. No. 6,281,075 (Patent Document 6).

As a modification of this split channel flash EEPROM cell, a steering gate placed between the floating gate and the word line.Toadd toTo do.. The individual steering gates in the array extend perpendicular to the wordline on one row of floating gates. As a result, read the selected cellMiAt the time of delivery or programmingTo 2This will ease the wordline from having to perform two functions at the same time. These two functions are (1) the function to be used as the gate of the selection transistor (thus, an appropriate voltage is required to turn the selection transistor on and off), and (2) the electromagnetic field between the word line and the floating gate. The function is to drive the voltage of the floating gate to a desired level through field (capacitive) coupling. Optimal performance of both of these functions at a single voltage is often difficult. With the addition of a steering gate, the wordline is sufficient to perform function (1), whereas, ChaseThe added steering gate performs function (2). In addition, such cellsToIt works by programming on the source sideAlsoPossible and with lower programming current and / or voltageSuIt has the advantage of For information on using the steering gate in a flash EEPROM arrayThe whole is incorporated herein by reference.US Pat. No. 5,313,421 (Patent Document 7), US Pat. No. 5,712,180 (Patent Document 8)、AndRiceIt is described in National Patent No. 6,222,762 (Patent Document 9). ..

Previously incorporated patentIn the literature, MeMorisels are connected in a configuration commonly referred to as a NOR configuration.。1Has one or two floating gate storage elementsThe individual memory cellsAdjacent cells that are connected between adjacent bitlines but in a cell rowAlso individualIt is connected to various memory cells. 1 bit lineIs, Called a virtual ground arrayTo beIn the array, the source diffuser of a row of cells and the drain diffuser of a row of cells that are directly adjacentWith bothConnectedWasTo Generally called NAND configurationTo beIn another type of array configuration, 8,16,Or more memory cells are connected in series with each otherhand,Select the transistors in the string connected between the individual bitlines and the common potential. Such an array andThatExample showing operationHowever, in its entirety is incorporated herein by reference.It is described in US Pat. No. 6,046,935 (Patent Document 10).

There are various programming techniques for injecting electrons from a substrate onto a floating gate via a gate dielectric. mostgeneralThe programming mechanism isThe whole is incorporated herein by reference.Book "Non-Volatile Semiconductor Memory Technology" edited by Brown and Brewer (IEEE Press, No.1.2Section, pp. 9-25 (1998)) (Non-Patent Document 1). "Fowler-NordheimTunneling "(No.1.2.1Section)To beControl gates and board channels by one techniqueWithUnder the influence of the high electric field established by the voltage difference between them, electrons are passed through the tunnel of the floating gate dielectric.Also,in general"Hot electronInjection "(No.1.2.3Channel in the drain area called section)Hot electroninjectionAnother techniqueInjects electrons from the cell's channels into the area of the floating gate adjacent to the cell's drain. "Source side injection" (No.1.2.4Section)To beYet another technique is to control the potential of the substrate surface along the length of the memory cell channel so as to create a condition for electron injection from the drain in the channel region. For source-side injection,The whole is incorporated herein by reference.Kamiya et al.'S paper "EPROM Cell with High Gate Injection Efficiency" (IEDM Technology Digest, 1982, pp. 741-744) (Non-Patent Document 2), US Pat. No. 4,622,656 (Patent Document 11) and US Pat. No. 5,313,421. It is also described in No. (Patent Document 7).The whole is incorporated herein by reference.It is described in "Low-voltage, low-current, high-speed program step-split gate cell by direct ballistic injection for EEPROM / flash" by Ogura et al. (IEDM Technology Digest, 1998, pp. 987-990) (Non-Patent Document 3). So called "ballistic injection"To beAnother programming technique creates a high electric field in a short channelhand、DirectlyOn charge storage elementElectricChildAccelerate。

Two techniques to remove charge from a floating gate and erase memory cellsTo、As mentioned aboveTwo types of memory cell arrayBothForIs.. One technique is to erase the substrate by applying the proper voltage to the source, drain, substrate, and another gate. Floating gates and boards with these gatesWithElectron tunneling takes place through a portion of the dielectric layer between them.

The other erasing technique is from a floating gate to another gate、Electrons are transferred through the tunnel dielectric layer arranged between these gates.thisFor the purposePreviousThe first type of cell described is provided with a third gate. Pre-equipped with 3 gates due to the use of steering gatesPreviousIn the second type of cell described, the floating gates are erased to the level of the wordline without the need to add a fourth gate. This latter technique re-adds a second function performed by the wordline, but at different times these two functionssoTo be executed, it is necessary to make a compromise to match the two functionssexButAvoided。

To increase the storage capacity of a memory card of a certain size or another type of package,IsOf increasing quantity and reducing sizeBothIn order to achieve this, it is desirable to continuously increase the amount of digital data that can be stored in a predetermined area of the silicon substrate.WasTo One way to increase the data storage density is to store more than one bit of data per memory cell.this thingIs achieved by fractionating the window of the voltage range of the floating gate charge level to 3 or more states. By using these four states, each cell has 2 bits.ofIt is possible to store data,Also16 states1 ofcellBut4 bitsofdataToStoringTo doAnd so onBecomes。ManyStateVoiceFor the structure and operation of the rush EEPROM,The whole is incorporated herein by reference.U.S. Pat. No. 5,043,940 (Patent Document 12)andNo. 5,172,338 (Patent Document 13)) ToDescriptionHas been。

Physical size of memory cells and / or physical size of the entire arrayToShrinkTo doBy dayDenseAchieving an increase in degreeCan also.. As processing techniques that allow smaller functional sizes to be achieved have improved over time, integrated circuit size reductions are generally performed for all types of circuits. However, we decided to scale by simple reduction.ThereforeThere is a limit to how much a given circuit layout can be reduced, so efforts are being made to redesign the cell so that one or more functions occupy a smaller area.Have been done。

In addition, various memory cell designs have been implemented to further increase the data storage density. As an example, each floating gateUpofManyStatusofStoringCan also work withThere are dual floating gate memory cells connected in a NOR configuration. In this type of cell, between the source diffuser and the drain diffuser, which have a selection transistor between the two floating gates.And thatTwo floating gates are provided on the channel. Steering gates are provided along each column of the floating gates, and word lines are provided along each row of the floating gates. When accessing a given floating gate for reading or programming, FuNo matter what charge level is present in the rotating gateBe targetedFloating gateHaveRaise the steering gate on another floating gate in the cell high enough to allow the channel under the other floating gate to be switched on. By doing this, in the same memory cellBe targetedWhen reading or programming a floating gateAhFactorOtherThe floating gate on the other side can be effectively removed. For exampleCan be used to read that stateThe amount of current flowing through the cell is, in this case,Be targetedIt is a function of the charge amount of the floating gate, not the charge amount of the other floating gate in the same cell. This cell arrayofComposition, its manufacturing method,andOperation techniqueofExampleBut、The whole is incorporated herein by reference.Described in US Pat. No. 5,712,180 (Fig. 9+) (Patent Document 8)Has been(In the present specification, this patent will be referred to as "dual storage element cell" hereafter).

Another type of memory cell useful in flash EEPROM systems is a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner.Use.. Such a cellHowever, in its entirety is incorporated herein by reference.Chan et al.'S paper "True Single Transistor Oxide Film / Nitride Film / Oxide Membrane EEPROM Device" (IEEE Electronic Device Letter, EDL Volume 8,No. 3, March 1987, pp. 93-95) (Non-Patent Document 4)Has been.. Silicon oxide, silicon nitride、And a three-layer dielectric formed of silicon oxide (ONO) is sandwiched between the conductive control gate on the memory cell channel and the surface of the semi-conductive substrate. The cell is made by injecting electrons from the cell channel into the nitride.ProgramThere, the electrons are trapped and stored in a limited area. ThenIn a detectable waySeLuciThe threshold voltage of some of the channelThis stored charge isChange. The cells are erased by injecting hot holes into the nitride.The whole is incorporated herein by reference.Nozaki et al.Paper"1Mb EEPROM with MONOS memory cells for semiconductor disk applications" (Semiconductor Device Circuit IEEE Journal, Vol. 26,No. 4, April 1991, pp. 497-501) (Non-Patent Document 5).This treatiseDescribes a cell similar to a split gate configuration in which a doped polysilicon gate extends over a portion of the memory cell channel to form separate selective transistors... BrNo. 1 of the book edited by own and Brewer1.2section(Non-Patent Document 1)Refer toPreviousDielectric also for the programming techniques describedbodyTo be applicable to charge trapping elementsNote inIt is listed.

As mentioned aboveIncorporated U.S. Pat. No. 5,851,881 (Patent Document 14) states that two storage elements (one of which is adjacent to each other on a memory cell channel) are located.As mentioned above(The other is a conductive floating gate)Has been described.. 2 bitsofThe data is stored, one in the form of a dielectric and the other in the form of a floating gate. Of the two gates2 eachIn one of two different charge level rangesprogramBy doing, MeMoriselToFor a combination of four different threshold levels that represent one of the four storage statesProgram。

eachAnother approach to storing 2 bits in a cell is Eitan et al., "NROM: New Localized Trapping, 2-Bit Non-Volatile Memory Cell" (IEEE Electronic Device Letter, Volume 21,No. 11, November 2000, pp. 543-545) (Non-Patent Document 6). The ONO dielectric layer extends across both ends of the channel between the source diffuser and the drain diffuser. 1Bit dataCharge is localized to the dielectric layer adjacent to the drain, another 1Bit dataDielectric with charge adjacent to the sourceIn layersBe localized. Multi-state data storage can be obtained by separately reading the binary states of the charge storage regions spatially separated in the dielectric.<patcit num="1"><text>U.S. Pat. No. 5,070,032</text></patcit><patcit num="2"><text>U.S. Pat. No. 5,095,344</text></patcit><patcit num="3"><text>U.S. Pat. No. 5,315,541</text></patcit><patcit num="4"><text>U.S. Pat. No. 5,343,063</text></patcit><patcit num="5"><text>U.S. Pat. No. 5,661,053</text></patcit><patcit num="6"><text>U.S. Pat. No. 6,281,075</text></patcit><patcit num="7"><text>U.S. Pat. No. 5,313,421</text></patcit><patcit num="8"><text>U.S. Pat. No. 5,712,180</text></patcit><patcit num="9"><text>U.S. Pat. No. 6,222,762</text></patcit><patcit num="10"><text>U.S. Pat. No. 6,046,935</text></patcit><patcit num="11"><text>U.S. Pat. No. 4,622,656</text></patcit><patcit num="12"><text>U.S. Pat. No. 5,043,940</text></patcit><patcit num="13"><text>U.S. Pat. No. 5,172,338</text></patcit><patcit num="14"><text>U.S. Pat. No. 5,851,881</text></patcit><patcit num="15"><text>U.S. Pat. No. 6,091,633</text></patcit><patcit num="16"><text>U.S. Pat. No. 6,103,573</text></patcit><patcit num="17"><text>U.S. Pat. No. 6,151,248</text></patcit><patcit num="18"><text>U.S. Patent Application No. 09 / 667,344</text></patcit><patcit num="19"><text>U.S. Patent Application No. 09 / 925,134</text></patcit><patcit num="20"><text>U.S. Patent Application No. 09 / 925,102</text></patcit><patcit num="21"><text>U.S. Patent Application No. 09 / 893,277</text></patcit><patcit num="22"><text>U.S. Patent Application No. 09 / 871,333</text></patcit><patcit num="23"><text>U.S. Pat. No. 5,887,145</text></patcit><nplcit num="1"><text>Brown and Brewer, Book "Non-Volatile Semiconductor Memory Technology", IEEE Press, Section 1.2, pp. 9-25 (1998)</text></nplcit><nplcit num="2"><text>Kamiya et al., Paper "EPROM Cell with High Gate Injection Efficiency", IEDM Technology Digest, 1982, pp. 741-744</text></nplcit><nplcit num="3"><text>Ogura et al., Paper "Low Pressure, Low Current, High Speed Program Step Split Gate Cell by Ballistic Direct Injection for EEPROM / Flash", IEDM Technology Digest, 1998, pp. 987-990</text></nplcit><nplcit num="4"><text>Chan et al., Paper "True Single Transistor Oxide Film / Nitride Film / Oxide Membrane EEPROM Element", IEEE Electronic Device Letter, EDL Vol. 8, No. 3, March 1987, pp. 93-95</text></nplcit><nplcit num="5"><text>Nozaki et al., Paper "1Mb EEPROM with MONOS Memory Cells for Semiconductor Disk Applications", IEEE Journal of Semiconductor Device Circuits, Vol. 26, No. 4, April 1991, pp. 497-501.</text></nplcit><nplcit num="6"><text>Eitan et al., Paper "NROM: New Localized Trapping, 2-Bit Non-Volatile Memory Cell", IEEE Electronic Device Letter, Vol. 21, No. 11, November 2000, pp. 543-545</text></nplcit><nplcit num="7"><text>DiMaria et al., Paper "Electrically Modifiable Read-Only Memory Using Si-Rich Si02 Syringe and Floating polycrystalline Silicon Storage Layer", Journal of Japan Society of Applied Physics 52 (7), July 1981, pp. 4825-4842</text></nplcit><nplcit num="8"><text>Hori et al., Paper "Si Injection Gates for Non-Volatile Memory Applications-MOSFETs with Si02 Insulators", IEDM92, April 1992, pp. 469-472</text></nplcit>

The present invention is integrated or independentdidIt includes two main aspects that can be achieved by either method. One major aspect is dielectric rather than conductive floating gates.bodyNew with charge storage elementNaThe purpose is a non-volatile memory cell structure. The other major aspect is dielectric on the channels of memory cell transistors.bodyThe purpose is to store charge in the form of one of three or more detectable levels in a region with one or more limits across both ends of the charge storage element. 2 or more bitsofData is on top of some of the channelsAhIt is stored in one local area of the dielectric. Two or more such independents arranged apart from each other along the length of the channeldo itProgrammable charge storage areas can be provided in individual memory cells of an array of such cells, and two or more bit data are stored in each such area.

The present inventionbeforeBackground of the inventionExplained in the column ofIt can be realized in a plurality of conventional flash memory systems as described above. When a conventional memory cell array utilizes a conductive floating gate as a storage element, a charge trapping dielectric material is used instead of the floating gate. How to create and process such a non-volatile memory system with a dielectric storage elementThatWith one pair of conductive floating gatesextremelySimilarTo do.. Since the charge does not travel across both ends of the dielectric container, it is usually possible for the dielectric to extend across almost another region of the memory cell array across both ends of the memory cell consisting of multiple rows and columns. But the memory cell chooses the transistorPrepareIf, in one embodiment, the gate dielectric is electronically stored within the selection transistor.On the materialWill be substituted. It is possible to provide two or more electronic storage elements in the storage dielectric of individual memory cells with a gate structure.thisThe gate structure allows independent control of the potential across the board surface at two or more portions along the length of the memory cell channel... GermanyStandingdo itProgrammed and read1 or 2The charge storage region may be utilized within the individual dielectric electron storage elements. The expansion and movement of the dielectric region of the injection destination where electrons are injected is performed as the number of erase / programming cycles increases, so that it does not affect adjacent regions in the same memory cell. This increases the number of erase / programming cycles that the memory can withstand, thus increasing the useful life of the memory. In one particular examplebeforeBackground of the inventionExplained in the column ofThe dual storage element cells are the two floating gates of the memory cells.RespectivelyIt is equipped with a charge storage dielectric used in place of. This dielectric is sandwiched between the conductive steering gate and the substrate,ThatTwo functionally separate charge storage elements are formed on the channel of the memory cell between the source and drain. One charge regionLocated on opposite sides of the selected transistor along the length of the cell channelOf these two storage elementsRespectivelySuitable for storageBut instead, Two such regions may be used to further increase the charge storage density. The charge level in a regionThatThe length of the cell channel below the areaSabeAffects the threshold level for minutes. 2 or more such charge levels, and therefore 2 or more different threshold levelsIs, Of the two charge storage areas of individual memory cellsTo be programmed for eachStipulatedWasTo Selected from two charge storage areas of the addressed cellTerritoryRegion programming and readout switch on the selected transistor as in the dual floating gate system.hand, It is done by driving another channel part strongly to be conductive. This causes the selected charge storage area of the addressed cell to react to the voltage across its source, drain and gate. Specific Examples of Dual Storage Element Arrays That Can Use Charge Storage Dielectrics Instead of Floating GatesHowever, in its entirety is incorporated herein by reference.US Pat. No. 6,091,633 (Patent Document 15), US Pat. No. 6,103,573 (Patent Document 16), US Pat. No. 6,151,248 (Patent Document 17), andYuan et al., Filed on September 22, 2000"Non-volatile memory cell array and forming method with discontinuous source diffuser and drain diffuser in contact with continuous bitline conductors"Person in chargeGenus pendingRiceNational Patent Application No. 09 / 667,344 (Patent Document 18),Harari et al., Filed on August 8, 2001"Non-volatile memory cell using substrate trench"RiceNational Patent Application No. 09 / 925,134 (Patent Document 19), andYuan et al., Filed on August 8, 2001"Scalable self-aligned dual floating gate memory cell array and method of forming the array"RiceDescribed in National Patent Application No. 09 / 925,102 (Patent Document 20)Has been。 Another aspect of the dual storage element cell according to the invention includes an aspect of providing a third dielectric storage element under the selection gate of each memory cell utilizing the charge storage area. by this,eachWhen the charge storage area is processed in two states (binary operation)eachIt is possible to store 3-bit data in a memory cell, but if some or all of the charge storage area is processed in a state of 3 or more, more data is stored in a single cell. In addition, a dielectric spacer in the mask to define the width of the control (steering) gate line.To useThe memory cell array manufacturing process may be used as an option to reduce the size of one memory cell to increase the data storage density of the array. In another embodiment, the NAND array has a memory cell floating gate of the NAND array replaced by a storage element region of the dielectric layer. This dielectric is sandwiched between the word line and the substrate surface.Otherwise,The array isThe whole is incorporated herein by reference.June 27, 2001ToapplicationWas doneDescribed in U.S. Patent Application No. 09 / 893,277 (Patent Document 21)Has beenIs processed as.RespectivelyThe storage element region of may be processed to store a charge level of 3 or higher, thereby allowing individual such areas.Within the regionTwo or more bit data are stored in. Adjacent wordlines and storage elements along the length of the NAND memory cell string with improvements to the NAND arrayWithEliminates the need for normal metallurgical source / drain areas in the substrate between. Instead, the wordline and the charge storage element are the charge storage elements along the NAND string.DenseAlmost double the degreeIn a wayPacked closer together. That is, the additional wordline and charge storage element are located in the space currently occupied by the source and drain diffusers in the NAND string of the memory cell. This improved array is a memory cellofIt is processed in the same way as for NAND arrays with source / drain regions. Additional aspects, advantages, and features of the invention are included in the following description of exemplary embodiments of the invention, which description should be read with the accompanying drawings.

Some specific memory cell configurations will be described with reference to the drawings.eachMemory cell structureIn Naru, Charges are stored in at least one region of the charge trapping dielectric placed between the conductive gate and the substrate... MeMorisel'stheseAn example is 1 bitofThe data isRespectivelyBinary mode stored in the charge storage area ofIs 2Bits aboveofThe data isRespectivelyMulti-state mode stored in the charge storage area ofOfIt can be processed in any of the modes.

Example of first memory cell (Figs. 1 to 6) Several cells in the two-dimensional cell array are shown in Figure 2A.FigureShown in 2BSectional viewIn plan view withis thereIt is shown in Figure 1. Elongated, parallel source diffuser and drain diffuser 103,104,105, ExpansionIt is formed in the surface 101 of the semiconductor substrate 100 which extends in the y direction of the scattered portion and has a length spaced apart in the x direction. A dielectric layer 107 containing a charge storage material is formed on the substrate surface 101. Elongated, parallel conductive control gate 109,110,111 isIt extends in the x direction and has a length separated in the y direction. thisRageToteTo, Generally can be made from doped polysilicon material.

The charge storage element of this simple structure (which is one of its advantages) is the region of the dielectric layer 107 between the source diffuser and the drain diffuser 103-105, the control gate 109. It is sandwiched between ~ 111 and the substrate surface 101. thisCaseThe delivery element area is marked with cross-hatching in Figure 1. This is a charge trapping material for the purpose of forming actuable memory cells.RyoAlthough needing to be located in the region only, the charge trapping material may extend over some of any other convenient structure, including the entire memory cell array.

This memory cell array is standardNaProcessing techniqueLaw,In particular, a standard developed to manufacture flash EEPROM arrays of the type that utilize floating gates.NaIt may be formed by a processing technique. The main processing step includes a step of forming an ion implantation mask on the substrate surface. Ions are then injected into the source / drain regions 103-105 through this injection mask. The mask is then removed and a dielectric layer 107 is formed over the entire array. Next, the doped conductive material layer such as polysilicon or polyside is a dielectric material.layerA film is formed on 107 and an etch mask is formed on the top surface of this derivative., PoResilicon etching is performed through the mask, and control gates 109 to 111rearLeft in. In the case of polysilicon, either the polysilicon is first deposited in a doped form, orOrBy injecting ions before the polysilicon is separated into elongated strips 109-111RipoResiliconafterwardsBy either method of dopingTo make these control gates conductiveThese control gates are doped. Polysilicon etchingI doWhen in the etched areaDielectricLayer 107 is also removed because it is not needed for memory operation, leaving a strip of dielectric layer 107 under control gates 109-111. Finally,To improve electrical insulation between adjacent cell rowsUsing a control gate as a mask, between control gate strips 109-111soAnother injection into the substrateTo be。

The programming and charge retention of such an array is shown in Figure 3.But,Part of Figure 2A, which contains one memory cell, is an enlargement.beforeBackground of the inventionExplained in the column ofChannelHot electronProgramming is done by the injection method. When proper voltage is applied to substrate 100, source 104, drain 105 and control gate 110, electrons are sufficiently accelerated in the cell channel from source to drain and the region in dielectric layer 107 adjacent to drain 105. It is injected into 115 and held there. The actual programming voltage applied depends on the details of the array structure, but board 100: 0 volts, source 104: 0 volts, drain 105: 5 volts, and control gate 110: 8 volts are typical examples.

The preferred programming technique isbeforeBackground of the inventionExplained in the column ofShiSentenceDescribed in the dedicationHas beenIt follows the technique of flash EEPROM using such a conductive floating gate.thisSimultaneous pulses of programming voltage are periodically applied to a plurality of cells at the same time, and the programmed state of the cells is read out between the programming pulses. Individual cells reach their programmed leveldidWhenthisThe application of the programming pulse to the cell ends. Note that the source and drain diffusers are shared between cells in adjacent columns and are processed in virtual ground mode, which is widely used in floating gate memory arrays.

The channel length of the memory cell in FIG. 3 is "L1", which represents the outer length portion of the charge storage area 115, andCharge storageIt is characterized by having two components, "L2", which represents the length portion below the region 115. Curve 117 shows the channel threshold voltage (V)T ) Show characteristics. This curve is at some level the channel length segment L1 depending on the impact of some threshold-altering injections that may have been made within board surface 101 or some previous channel erasure process (discussed later). Flat along. The charge stored in the region does not affect the threshold characteristics within the L1 segment. But within the L2 channel segment, the thresholdIs a caseSignificantly affected by the charged charge, and also this threshold, as in the case of one pair of floating gate systems.IsIt is a characteristic value measured to determine the stored state of the wheel.

Penetrate through the oxide layer formed on the channel regionFowler-NordheimProgramming by tunneling has its limits.thisProgramming is available only in certain memory array configurations such as NAND and AND configurations. 1stMemory cell arrayIt is impractical to program any of the examples, or any of the second or third memory cell array examples described below herein, by this technique. However, if it can be programmed in this way, it will be a dielectriclayerThe storage area in 107 isCharge storageInstead of being limited to region 115, it extends almost uniformly across both ends of the entire channel length (L1 + L2).

VT 1 bit by detecting whether is above or below one given threshold levelofBinary individual cells to store datamodeCan be processed with. However, according to one major aspect of the invention, Vs separated by a level of 3 or higher or a predetermined threshold level of 3 or higher.T Two or more bits in each cell by processing the cells to distinguish the range ofofIt is also possible to store data. As an example, the threshold level window in the L2 segment is divided into 4 states 0 to 3 that store 2 bits per cell, and is shown in FIG. To store 3 or more bits per storage element, 5 or more levels may be specified instead. The illustrated current / voltage characteristics are stored in the dielectric region 115.To beAs a result of the appropriate amount of chargeThat4 storage statesAbout eachCell in Figure 3To useIt is shown in Figure 4. Amount V along the X axis in Figure 4CGIs the voltage across the cell's control gate 110, the quantity I on the Y axisCELLIs the current passing through the channel of the cell.

The memory cell shown in FIG. 3 is actually a split channel cell. This is because the charge storage region 115 extends across only a portion of the channel at both ends... SeThe electrical equivalent circuit of Le is shown in Figure 5. Two transistors Q1 and Q2 are connected in series between the adjacent source spreading section 104 and the drain spreading section 105 (bit line). Transistor Q1 is provided with conductivity during programming or readout by making a sufficient combination of voltages across the elements of the cell. During reading, voltage source 121 (VCG ) Is connected to the control gate 110 (word line) and the voltage source 125 (V)S ) Is connected to the diffuser 104 and the voltage source 127 (V)D ) Is connected to the diffuser 105.

The cell of FIG. 3 can be read out in the same manner as the cell provided with the conductive floating gate. Two commonNaThere is a way. Control gate voltage VCGIs fixed and kept fixed, and the cell (I) is displayed by the sense amplifier circuit 129 as an indication of the stored state of the cell.CELL) May be measured. The actual programming voltage applied depends on the details of the array structure, but the board is 100: 0 Volts, the source is 104: 0 Volts, and the drain is 105: 1 Volts.、And control gate 110: A voltage of 3-5 volts is a typical example.instead of, Control gate voltage VCGWhen the sense amplifier 129 detects that the value of the cell current has crossed a certain threshold value, the control gate voltage VCGYou may let us know the value of.thisThe stored state of the cell is displayed according to the voltage value. This example utilizes a "forward" read. This is because the drain being programmed is also the drain being read.Besides this, Can be read in "reverse" mode. In that case, the drain and source during programming are reversed during reading.

The wiring diagram in Figure 5 shows the cell program, except that the sense amplifier 129 is not normally connected during programming.MingThe components used for are also included. The voltage sources 121, 125, 127 are connected during programming as shown in Figure 5, but the supply voltage values are different. Apply the proper voltage, dielectricbodyBy moving electrons from the charge trapping region to the substrate, it is possible to erase a plurality of cells along at least one word line at once. Examples of a set of erasing voltages are board 100: 0 volts, source 104: floating, drain 105: 5 volts, control gate 110: -8 volts.

FIG. 6 is described in the specification of the present application.Has beenTwo examples for charge storage dielectric layer 107 that can be used in all of the memory cell examplesofShow the structure. The first structure (FIG. 6A) includes silicon oxide (SiO) grown on substrate surface 101, commonly referred to simply as "oxide".2 ) Silicon nitride (Si), commonly referred to simply as "nitride", which includes layer 135 and is subsequently deposited over layer 135.3 N4 ) Layer 137 follows. Next, the oxide layer 139 is grown on the nitride layer 137, the oxide layer 139 is formed on the nitride layer 137, or a combination of the two is performed. This oxide film / nitride film / oxide film composition is known as "ONO". The electrons are trapped and stored in the nitride layer 137. Illustrative thisLayerThe thickness of is as follows: layer 135: 40-80 angstrom, layer 137: 50-80 angstrom, layer 139: 50-100 angstrom. Next, a conductive material layer, which is a source for forming the control gate, is formed on the ONO layer.

The second structure, shown in FIG. 6B, utilizes a special layer 141 of silicon-rich silicon dioxide to trap and store electrons. For such materials,The whole is incorporated herein by reference.The paper "Si Rich Si0" by Di Maria et al.2 "Electrically changeable read-only memory using an injector and a floating polycrystalline silicon storage layer" (JSAP Journal 52 (7), July 1981, pp. 4825-4842) (Non-Patent Document 7), Hori et al., "Si Injection Gate for Non-Volatile Memory Applications-Si02 Described in "MOSFET with insulator" (IEDM92, April 1992, pp. 469-472) (Non-Patent Document 8).Has been.. As an example, the thickness of layer 141 can be about 500 angstroms.

Second memory cell exampleDifferent from the first example due to the use of two sets of orthogonally arranged conductive gates instead of one set,Another exemplary memory array is shown in FIGS. 7-9. Figure 7IsSeveral cells of the ray are shown in plan view, with FIGS. 8A and 8B being two orthogonal cross-sections. The parallel source diffuser and drain diffuser 151,152,153 formed in the surface 164 of the substrate 163 are elongated in the y direction across both ends of the array and are spaced apart in the x direction. Conductive control gates 155, 156, 157, sometimes called steering gates, are also elongated in the y direction and spaced in the x direction. thisRageThe toes are arranged along the respective diffusers 151, 152, 153. thisExpandThe scatters are even more spaced than the spreads of the first example so that these control gates can be placed across the memory cell channels. The second set of conductive control gates 159,160,161 that form the wordline of the array are elongated in the x direction and spaced in the y direction. The conductive gate is generally formed from doped polysilicon, but may be formed from other low resistance materials.

With reference to the cross-sectional views of FIGS. 8A and 8B, a charge storage dielectric layer 165 is formed on the substrate surface 164 of the array. This dielectric is associated with FIGS. 6A-BPreviousIt may be one of the two specific dielectrics mentioned. Another dielectric layer 167 is formed between two sets of conductive gates that cross each other. For the purpose of maintaining the potential difference between the two sets of gates, this layer is made to be a relatively thick layer, such as a 250 angstrom thick oxide.

From the enlarged cross-sections of one memory cell in FIGS. 8A and 9, the length of each memory cell channel is different between the two sets of control gates.andTwo parts that are electromagnetically coupledIn minutesNote that it is fractionated. Wordline 160 is approximately 1/2 above the left side of the channel lengthAhThe control gate 157 is on the other channel lengthAhTo The charge storage dielectric 165 is the substrate surface 164 and thisRageIt is sandwiched between.. No.The main difference when processing this array, which differs from the processing of example 1, is that the two adjacent regions in layer 165 171,In addition to the fact that it is possible to store the charge in 173, thisRyoOf the regionRespectivelyIs individually programmed and independent of the other areado itThe point is that it can be read. Programming by source-side injection is preferred, by this programming, RyoRegion 171 is located adjacent to the inner end face of Gate 160, RyoRegion 173 is located adjacent to the inner end face of Gate 157. On the other hand, the channelHot electronWhen programmed by injection, the electrons are region 171,Region 172 in layer 165 instead of 173,Stored in 174. Area 172,174 is、Cell source / drain area 152,Adjacent to each of the 153 areas.

The cell in this example is between adjacent source / drain areas 152 and 153., SeIt effectively contains two charge storage elements on the channel, one of which is under the conductive gate 160.AhAnd the other element under the conductive gate 157AhTo Dielectric layer 165RyoIt may be limited to the region, or the dielectric layer 165 extends over more parts of the array.HowIs usually even more convenient. 7-9 show the charge storage layer 165 extending throughout the array.

Curve 175 in FIG. 9 shows region 171 due to source side injection.,Threshold voltage characteristics (V) that vary across the cell's channels when programmed within 173T ) Is shown. The amount of charge stored in region 171 is the threshold V below it.T Given the value 177, the amount of charge stored in region 173 is the threshold V below it.T Gives the value 179. Threshold 177,179EachIt may be held in one of the two stored states. In that case, this is one breakpoint thresholdLatterIt is set between states. 2 bits when this is doneofThe data is stored in individual cells.instead of, As shown in Figure 3 for the array in the first example,ThresholdValue 177,179RespectivelyMay be processed at 3 or higher levels. As shown in Figure 3,Threshold177,179EachProcess in 4 statesTo doIf 4 bitsofThe sum of the data is stored in individual memory cells. Needless to say, part or both parts of the channelToProcess at 5 or higher levelTo doIf 5 or more bitsofThe data is stored in individual cells. Charge storage area 171,It to guarantee the separation of 173RyoRemoved part of the interregional dielectric layer 165handPart of this can be replaced by a thermal oxide film or another relatively non-trapping dielectric. Also, channels instead of source-side injectionHot electronCurve level 178 when programming cells by injection,180 is the charge storage area 172,It shows the threshold voltage effect of 174.instead ofSource-side injection to further increase the amount of data stored in individual memory cellsAnd hot electronsOf injectionBothAll four charge storage regions 171 to 174 may be utilized by programming with.

Threshold 177,179Each oneSuitable for programmingShi, Independent of each otherdo itReadSu.. Of the cellon the other handSegmentTurn on stronglyRemoves any effect of its programmed threshold level by, while the other segment is programmed or read. The particular voltage applied to an array depends on the particular structure of that arrayAndHowever, the following values are approximate voltages that could be used to program the cell in Figure 9 with source-side injection. When programming the left segment, area 171: board 163: 0 volts, source 153: VS = 0 Volts, Drain 152: VD = 5 Volts, Wordline 160: VWL= 8 volts, and control gate 157: VSG= Threshold V for right elementT 179+ about 1 volt. When programming the right segment, area 173: board 163: 0 volts, source 152: VS = 0 Volts, Drain 153: VD = 5 Volts, Control Gate 157: VSG= 8.8 volts, and wordline 160: VWL= Threshold V for left elementT 177 + about 1 volt. channelHot electronThe approximate value of the programming voltage due to injection can be, for example, as follows. When programming the left segment, area 172: board 163: 0 volts, source 153: VS = 0 Volts, Drain 152: VD = 5 Volts, Control Gate 157: VSG= 8 volts, and wordline 160: VWL= 8 volts. When programming the right segment, area 174: board 163: 0 volts, source 152: Vs = 0 volts, drain 153: VD = 5 Volts, Control Gate 157: VSG= 8 volts, and wordline 160: VWL= 8 volts. Programming is thisRadenAlternate pulse output of multiple cells using pressure simultaneouslyRapBy reading the logged stateRikoReLatterIt is also suitably achieved in this example by verifying the state.thisProgramming is completed cell by cell after reaching the desired level, as in the case of floating gate / flash memory gate arrays.

PreviousAs mentionedIn a wayArea 171,When programming only 173, the exemplary read voltage for the cell of FIG. 9 would be: When reading the left area 171 the thresholds 177, 0 volts are applied to the board 163 and the source 152, the drain 153 is kept at a low voltage (1 volt, etc.) and the selection gate 157 is the area 173 its highest. The voltage is kept high enough to guarantee conduction when programmed to the threshold state. The voltage in wordline 160 is then changed and the bitline current is monitored to detect the threshold in region 171. Similarly, when reading the right region 173, thresholds 179,0 volts are applied to the substrate 163 and source 153, the drain 152 is kept at a low voltage and the wordline 160 is kept at a high voltage. The voltage at the selection gate is then changed and the bitline current is monitored to detect the threshold in region 173.In the manner described aboveCharge storage area 172,174 onlyToWhen programming, the exemplary read voltage for the cell in Figure 9 is:Become.. When reading the left region 172, thresholds 178, 0 volts are applied to the substrate 163 and source 152, 8 volts is applied to the selection gate 157, and a low voltage (such as 1 volt) is applied to the drain 153. The voltage in wordline 160 is then changed and the bitline current is monitored to detect the threshold in region 172. When reading the right region 174, thresholds 180, 0 volts are applied to the substrate 163 and source 153, 8 volts is applied to the wordline 160, and approximately 1 volt is applied to the drain 152. The voltage at select gate 157 is then changed and the bitline current is monitored to detect the threshold in region 174. This when all four regions 171-174 were programmed with an electric chargeRyoAreaToIt can be read at the same time as follows. Charge storage area 172,When reading 174, the read isPreviousProceed as described. When reading region 171, 0 volts is applied to board 163 and source 153, and the selection gate 157 is region 173.,The voltage is kept high enough to ensure that 174 conducts when programmed to its highest threshold, and is depleted through region 172.ButSufficient voltage (approximately 3 volts) is applied to the drain 152. The voltage in wordline 160 is then changed and the bitline current is monitored to detect the threshold in region 171. When reading region 173, 0 volts is applied to board 163 and source 152, and wordline 160 is region 171.,The voltage is kept high enough to ensure that the 172 conducts when programmed to its highest threshold, and is depleted through region 174.ButSufficient voltage (approximately 3 volts) is applied to the drain 153. The voltage at select gate 157 is then changed and the bitline current is monitored to detect the threshold in region 173.

In addition, to allow such reads of all four regions, they should have a predetermined relationship with each other., Each pair of areas(Left pair 171 and 172 and right pair 173 and 174)ToIt is desirable to constrain the charge level in the programmed state. As one such relationship,Each pairThe charge level is given to the charge storage area outside of, i.e. the paired area 172 on the left and the paired area 174 on the right.,versusThreshold voltage (V) well above each internal region 171 or 173 (eg, almost one state level higher)T ) Is obtained as a result... thisBy, without taking advantage of certain constraints on the combination of several thresholdsPreviousDescribedIn a way likeTwo areas under one gateEach ofIt becomes possible to read the threshold value of. This is because the internal area threshold is outsideSide territoryThis is due to the fact that it is not programmed for values that are equal to or greater than the threshold of the region.

Explain thisButGive an exampleIs useful.. LowHowYou can specify a range of five programmed threshold levels, starting at 0, 1, 2, and 3, with a maximum of 4. theserangeOfofThe four ranges are in the charge storage area 171 to 174RespectivelyUsed in, the upper set of threshold levels 1 to 4 is in the outer region 172,174Each territoryFor regionsAnd,Also,The lower set of threshold levels 0 to 3Internal area 171,For 173Is.. In this case, it is obtained from the allowed combination of threshold voltages in the individual charge storage regions.RudenLoad storageFor each pair, 10 storage states can be specified as follows.<img file="JP4846979B2_D0001.tif" /> Therefore,eachBy detecting 5 different charge (threshold) levels in the region, a total of 10 different states can be seen in the memory cells shown in FIG.RespectivelyWill be detectable on the side of the memory cell, resulting in 100 different storage state combinations for the memory cells. Needless to say, using a smaller number of threshold levels results in a smaller number of detectable states. Also, increasing the number of threshold levels will provide additional storage state.

4 areasRespectivelyThere is also a desirable order for programming threshold levels in. That is, the external area 172,Internal area 171 before programming 174,173BothIs to do programming. Of such cell rows that share a common wordlineeachRegion 173 is first programmed by performing a source-side injection into the cell. Region 173 below region 171 is then to allow source-side injection.ToVoltage V depending on the programmed charge levelSGThe area 171RespectivelyRegion 171 while applied to the control gate 157 ofToProgram along the line as wellTo do.. ThenHot electronRegion 172 in any order by injection,174programTo do。

In this example and the other two examples, itRadenErasing of memory cells is achieved by hole injection into the load trapping layer and / or by extracting electrons from the charge trapping layer. thisLahoDuring programming processToThe negative charge of the electrons injected into the charge trapping layer becomes invalid. It is layer 165 of this second example (FIGS. 7-9) that receives electrons during programming and holes during erasure. There are two unique erasing techniques. In one erasing technique called "channel erasing", the holes come into contact with the substrate surface.thisBy penetrating through the oxide portion of the layer, it is injected from the silicon substrate into the charge storage portion of the layer 165. With the same approach, some of the electrons stored in the charge storage portion of layer 165 can be extracted by a tunneling mechanism that penetrates the oxide portion of layer 165 to the silicon surface. To achieve this, in the case of the cell of FIG. 9, a negative potential is applied to the wordline and the selection gate with respect to the substrate. In this case, the drain and source are grounded or left in a floating state. In another technique, holes are injected into layer 165 from a region of the substrate near the drain or source, and / or electrons are extracted by tunneling between layer 165 and the source / drain region. In this second approach, referring to FIGS. 8 and 9, a combination of a negative voltage across both wordlines 159-161 and steering gates 155-157 and a positive voltage across drains and sources 151-153 is applied. Will be done. (PreviousIn the cell shown in FIG. 3 of the first example described above, a positive voltage is applied to the drain 105, the source 104 is left in a floating state, and a negative voltage is applied to the wordline 110.。)This second erasure approach is not utilized when the internal storage areas 171 and 173 of the cell of Figure 9 are in use.

When the cell is programmed by source-side injection, ChiChanel elimination technique is used.Hot electronIf only the storage area programmed by the injection method is used, either of these two erasure techniques can be used. But the cellHot electronWhen programmed by injection, this channel elimination has the problem of tunneling holes and / or electrons across the entire channel, and is one of the electron-free charge trapping layers trapped by conventional programming. This results in over-erasure of the part. This causes the flat zeros of curve 175 (Figure 9) across both ends of the cell channel to drop to the negative threshold.WhenConceivable.

In this second example、Board 163: 0 Volts, Source 152: V to erase multiple cells simultaneously in a cell blockS = 5 Volts, Drain 153: VD = 5 Volts, Control Gate 157: VSG= -8 volts, and wordline 160: VWLA voltage of = -8 volts is applied to the individual cells at the same time. thisRadenBy pressurePreviousThe second elimination approach described is performed.

StandardNaProcessing techniqueLaw,In particular, a standard developed for manufacturing flash EEPROM arrays of the type that utilize floating gates.NaThe memory cell array of FIGS. 7 to 9 may be formed by a processing technique. In one processing example, layer 165 is first formed over the entire substrate area of the memory cell array. A first polysilicon layer is then deposited over this region and the polysilicon is etched through a suitable mask, leaving control gates 155-157 behind. In one example, layer 165 between control gates 155 to 157 is removed as part of this etching process. Then another temporary than the control gateNaSource / drain regions 151,152,153 are injected through a mask formed by a masking material (not shown), which results in self-alignment with one end face of control gates 155-157. Layer 165 is between control gates 155 and 157AhFormed on the substrate surface 164AndAt the same time, over the top and sides of control gates 155 to 157AlsoIt is formed. This layer is a continuous layer consisting of ONO (Fig. 6A) or silicon-rich oxide (Fig. 6B). The layer 167 shown in FIGS. 8 and 9 may be a part of the same layer 165 or a combination of the layer 165 and another dielectric material. Such another dielectric is an oxide spacer formed along a vertical wall consisting of control gates 155 to 157 and / or a thick oxide layer (not shown) on the top surface of control gates 155 to 157. It may be in the form of (not shown). Oxide on this top, ControlSeparated into gates 155 to 157To doBy previously depositing an oxide on the top of the first polysilicon layerIt is preferable to form.. A second polysilicon layer is then formed over this continuous layer., DIt is hatched and converted to the wordline 159,160,161.

Due to the added control (steering) gates 155 to 157, the memory cells in this second example have dimensions larger than the first example in FIGS. 1 to 3 in the x direction by one resolution element. Note that it has. A second polysilicon layer is also needed in this second example. However, this added structure and size makes it possible to double the amount of data that can be stored in individual cells.

By effectively modifying the cells of FIGS. 7-9 for several purposes, the electron storage layer under the control gates 155-157 is usually a thin oxide (200) grown on the substrate surface 164. Replaced with gate dielectric (such as angstrom thickness). This removes the second electron storage region 173, but with an independent selection transistor function.ToAdd to individual cellTo do.. You can then limit the erasure to individual cell rows.

Example of third memory cell In this example shown in FIGS. 10 to 13, the background of the inventionBefore in the column ofThe dual storage element described aboveLuaIn connection with Ray, Figures 6A-6BPreviousDielectric mentionedbodyA conductive floating gate of the array is provided, which is replaced by a portion of the charge trapping material layer. The manufacture and processing of this arrayPreviousBackground of the invention describedColumnAnd disclosure of the inventionColumnThis is similar to the case of the dual storage element cell array described in the patents and patent applications incorporated in.

10 to 12 show an array. The source diffusing part and the drain diffusing part 185,186,187 are formed in the surface 181 of the semiconductor substrate 183, extend in the y direction, and are separated in the x direction.ExpansionIt has the length of the scattered part. As is clear from the plan view of FIG. 10, the conductive steering gates 189,190,191,192,193,194 are oriented in the same direction as the diffuser and are arranged in the x direction on any side of the diffuser. Conductive word lines 197 ~ 199、Oriented with a length extending in the x direction and oriented in the y directionIsolationWill be done. Generally thisGuideDenSexualThe line is made from doped polysilicon material.

Wordlines 197-199 are one filmed conductive layer, rather than as two pieces, one formed on top of the other at different processing steps to avoid extra processing steps.ShapeBe madeIs preferable.. However, such a two-piece structure is smaller than the doped polysilicon line desired for the wordline.IHaving conductivity can be an advantage. In that case, a second piece of material with even higher conductivity can be added that contacts the top surface of the doped polysilicon line. Such materialofAs two examples、Silicide and metalCan be mentioned。

Illustrated in the cross-sectional views of FIGS. 11A and 11BTo doAs such, steering gates 189-194 are arranged over layer 201 of the charge accommodating material corresponding to one of FIGS. 6A-6B. Steering gates 189-194 are formed on the charge storage layer 201 and then extend in the y direction.thisLayer strips are removed between every other steering gate in the x direction. Source / drain regions 185 to 187 are injected between the remaining regions between every other steering gate in the x direction. Oxide layer 203 from wordline 197-199thisFormed on the top and sides of steering gates 189-194 to insulate the steering gateAt the same timeOn the exposed substrate surface 181ShapeA gated oxide film is obtained below the word lines 197-199. An example of the thickness of the dielectric layer 203 is 200 angstroms over the doped polysilicon steering gates 189-194 and 150 angstroms on the substrate surface 181. For example, portion 198'of wordline 198 shown in FIG. 11A, which is formed directly on a portion of oxide layer 203 on substrate surface 181.IsFunctions as a selective transistor gate in the Moricel line.

To reduce the complexity of the decoder, multiple pairs of adjacent steering gates on any side of the diffuser 185-187 are electrically connected together by a steering gate decoder. Is desirable. Such a pairSteering gateIncludes steering gates 191 and 192. Described in some of the dual containment element cell patents and patent applications referenced earlierHas beenAs such, this over the intermediate diffuser of multiple pairs of such adjacent steering gates.RageBy joining theWhat was mentioned aboveApart from thisRageYou may merge the files physically together.

This is defined within the region of the dielectric trapping layer 201 under the steering gate of one of the steering gates 189-194, defining the individual storage elements.CaseThe delivery element can be made to exist.. SuTop view of Figure 10 at the tearing gateInOblique parallel line patternsoAs shown, one of the wordlines 197-199 intersects. Two such storage elements are provided per memory cell. To store 1 bit per storage element, each storage element can process one charge storage area in two states (binary).What was mentioned aboveApart from the dual storage element cellRegardingDescribed in US Pat. No. 6,151,248 (Patent Document 17)Has beenIn an embodiment similar to the embodiment, the charge storage region can be processed to individually store three or more states, such as four states per region. The processing of such a dielectric storage memory array isAs mentioned aboveSimilar to the process described in the patent, but one difference is the use of a lower voltage at the steering gate due to the lack of a floating gate.

Referring to FIG. 12, an enlarged view of one of the memory cells of FIG. 11A is shown. By processing this cell and programming it using the source-side injection method, the selective transistor gate 198'that is part of the word line 198RespectivelyAdjacent to the side ofIn the dielectric layer 201Two areas 211,213soCharges can be trapped.Thaton the other handso,channelHot electronCharge storage region 212 when programmed by the injection method,214 instead each source / drain area 186,Placed adjacent to 187.What was mentioned aboveApart from the source side injection methodHot electronUsing the injection method, the charge storage regions 211-214OurAll four areas may be utilized by sequentially programming all areas. For individual areas, see the example in Figure 9.BeforeIn the threshold relationship describedAgainstSame considerationTo doIt can be in either two states or three or more states, as limited by, but there are no restrictions on the order of writing. At any of the sides of the selected transistor gate 198', andBiwaUnder the drawline 198AhDielectric in a memory celllayerPart 201 defines the dual storage element cell array referenced earlier and the two storage elements of the cell that replace the two conductive floating gates of the system. However, this is the dielectric layer 201CaseIt can extend beyond the delivery element. In one form,DielectricLayer 201 is adjacentTo doIt is formed in the form of strips with individual widths extending in the x direction between selected transistors of memory cells in a column and lengths extending in the y direction across many memory cell rows. thisLasTrip, andtheseThe selective transistor gate dielectric between the strips is the steering gate 192 shown in FIG.,It can be self-aligned with the end face of the steering gate, such as the end face of 193.

Dielectric when programmed by source-side injectionlayerArea of 201 211,The effect of the charge stored in 213 isPreviousParts 217 and 219 of the threshold voltage curve 215 in Figure 12, similar to the other two examples described.WhenIs indicated by. Source-side programming is different from source-side programming in FIG. 9 in this cell by moving a terminal that gives a bias condition of threshold + 1v. In Figure 12, this terminal is the storage area 211.,213 dual-purpose selectionTransistorWordline 198 connected to Gate 198'. In addition, above the unprogrammed storage areaAhSteering gate、It is driven to a sufficiently high overdrive voltage level (eg 8 volts). For example, when programming storage area 211, steering gate 193 is driven to overdrive voltage and wordline 198.Is selectedIt is driven to about 1 volt above the threshold voltage of the alternative transistor 198'.

Song in Figure 12Line 217 is below the charge region 211AhMemory cell channel threshold voltage VT An example of fluctuation of is shown. Similarly, the effect of charge region 213 on the channel is shown by part 219 of curve 215. As mentioned earlier in connection with other examples, thisRyoEach region of the region may be processed in 2 states (stores 1 bit per cell) or in 3 or more states (stores 2 or more bits per cell). channelHot electronWhen programmed by injection, the charges are in regions 212 and 214WhenStored in. Effect on threshold voltageBut,Parts 216 and 218 of curve 215 in Figure 12 respectivelyWhenIs indicated by. Area 212,214EachIt can be processed in either two states or three or more specified states. During such programming, all three gates 192,193,198'are driven to high overdrive voltages (eg, assuming all three voltages are 8 volts). Data-dependent charges in the four regions 211-214RespectivelyIf stored in a cellofThe storage capacity is the cell shown in Fig. 9.ofDescribed storage capacityThe same as I didis there. The storage area erasure step of FIG. 12 is performed following the storage area erasure step of FIG. 9 as described above.

FIG. 13 shows the optional changes of the memory cells shown in the cross sections of FIGS. 11A and 12. The difference is that the selection gate part of wordline 198', GroupExtends into the groove or recess 221 in the plate 183AndA selective transistor gate dielectric 205 is formed between the bottom and the wall along the bottom and the wall of the groove 221.ThatCan be mentioned. Due to this structure, it is added across both ends of the board surface 181.ofChannel length of the selected transistor without any regionTolongit can。

PreviousThe gates in the described structure are preferably made from a doped polysilicon material, but instead of one or two layers of the described polysilicon layer, another suitable conductive material may be used. .. For example, Wordline 197 ~ 199ToFormationTo doThe second layer, which is a material, may be a polysilicon polyside material in which a conductive refracting metal silicide such as tungsten is provided on the top surface in order to increase its conductivity. Steering gate 189 ~ 194ToFormationTo doThe polyside material, which is the material, is usually not preferable for the first conductive layer. This is because oxides grown from polysides as interpolydielectricsButThis is because the quality is lower than that grown from polysilicon. Same considerationBeforeExample of the second memory cell describedAlsoapply. In the case of the first memory cell example, only one conductive gate layer is formed, sothisThe gate may be made of polyside material.

An example of structural modification shown in FIG. 11A across both ends of the cross section VV of FIG. 10 is shown in FIG. 14, and the same reference number is used in FIG. The main difference is the charge trapping conductive layer 204ToPlaced under the selection gate, which is part of wordlines 197-199do it, Another charge storage areaToFormationBy doingData storage capacity of one memory cell without increasing its sizeToFurther increaseTo doThe point can be mentioned. That is, as best shown in the enlarged view of FIG. 15, the relatively non-trapping selective gate dielectrics 203 (FIG. 12) and 205'(FIG. 13) between the substrate surface 181 and the selective gate 198'. Is the charge storage dielectric layer 204ToTherefore, it has been replaced. As a result, another charge storage region 401 is formed in the dielectric layer 204. As shown in the threshold voltage curve in Figure 15, the songLine 403 shows the effect of the charge storage area 401 on the memory cell channel. Region 401 is the electron from substrate 183Fowler-NordheimWell programmed by tunnelingSo selectSubstantially the same spread as the selection gate 198'HaveIt is a thing. Area 401(Stores one additional bit data)2VoiceOr(Stores 2 or more additional bits)It may be processed in 3 or more states. With separate charge storage regions 211 and 213ToCombinationLet meIf, FigureThe single memory cell shown in 15 can store a large amount of bit data.

Two additional charge storage areas 212,214Have14 and 15RespectivelyProcess memory cellsTo doByRespectivelyIt is also possible to provide five charge storage areas in the memory cell of. This is possibleofIs thisDifferentThere are three different programming mechanisms available to store the charge in the region, namely region 211.,Source-side injection for 213, region 212,Against 214Hot electronInjection, and into area 401versusTo doFowler-NordheimThis is because tunneling exists. Of these five areasRespectivelyMay be processed in two states (in this case, one cell stores 5-bit data). Alternatively, processing may be performed in a state of 3 or more (one cell stores 6 or more bit data). Or one or more of the five areasToProcess in 2 states (binary), remaining areaToAs described with respect to the charge storage region of the corresponding cell in FIG. 9, a state limit may be provided for the regions 211,212,213,214 to process in three or more states (multi-state).

Referring to FIG. 15, three charge storage areas 211,213,401 of the erased memory cells are programmed in sequence.WasTo When eliminated, the threshold curve 215、At 0 volts (not shown)AllStorage areaIn the areaIt's flat across. Areas of erased cells 211,212,213,214 are associated with Figure 12.PreviousIt is programmed first as described. Storage area 211 programmed by source-side injection,In the case of 213, the voltage across wordline 198 is kept slightly above the erased threshold of storage area 401 to facilitate source-side injection. Then, for example, by keeping the substrate 183 at about 0 volts, placing either the source / drain region 186 or 187 at about 0 volts, and further selecting gates 198'up to a programming potential of about 10-12 volts. By raisingFowler-NordheimCentral area 401 is programmed by tunneling. To pass this 0 volt bias level, the steering gates 192 or 193 corresponding to the 0 volt drive source or drain area are sufficient above the maximum possible storage threshold level (eg about 6 volts). Overdrive voltage can be biasedWill be.. At the same time, another steering gate consisting of 192,193 pairs is biased to maintain a cutoff between its associated source or drain or this central region 401 (eg, about 0 volts). If region 401 is programmed to be 3 or greater, the voltage at select gate 198'may fluctuate accordingly. When programming is finished in one cell in a cell row, by raising its source or drain area from a programming level of 0 volts to a prohibition level of about 5 volts.thisFurther programming of the cell is prohibited. In this way, programming in this cell ends, whereas programming in another cell along the same row continues.

With a voltage of about 8 volts applied to the wordline 198, the charge storage region 211, as in the corresponding region of the example in Figure 12.,213 charge level statesToReadSu.. The board 183 is then kept at about 0 volts and the 0 volt source / drain region 186,Apply a voltage in one area of 187, about 1 voltofApplying voltage in the other area, steering gate 192 of about 8 volts,By applying the voltage at 193, the charge level in the central storage area 401ToReadSu.. The voltage across the wordline 198 fluctuates, the bitline current is monitored and the threshold 403 of the charge storage region 401 is detected. The erasing step of the sub-steering gate storage area 211,212,213,214 of FIG. 15 is performed following the erasing step of the storage area of FIG. 12 as previously shown. The erasure of the storage area 401 of FIG. 15 is performed by channel erasure, for example, by applying a sufficiently large negative voltage to the word line 198.

The different steering gate voltage levels imposed on the two steering gates during programming of the central region 401 of the memory cells in Figure 15As mentioned aboveDue to its use, as illustrated by elements 189-194 of the array in FIG. 10, of the control (steering) gateRespectivelyVoltageToIndependencedo itControllableTo dothingToRequired. Since it is usually not feasible to have a large decoder on the same circuit chip as an array, which is required to process multiple steering gates consisting of a large array, several memory cells in a row are outlined in FIG. As shown in thisLasIt is desirable to connect the tearing gates integrally. About such a connectionhand,May 31, 2001 referenced earlierToapplicationWas doneU.S. Patent Application No. 09 / 871,333(Patent Document 22)See Figure 6 inhandFurther descriptionHas been.. In this example, the steering gate is connected to a common steering gate line for each fourth steering gate along the row, which allows simultaneous programming and reading of one charge storage area for every other cell along the row. Is possible. Steering gate line 411IsWith tearing gate 191 and other steering gatesConnected, Line 412 with Gate 192 and other gatesConnected, Line 413 with gates 189,193 and other gatesConnected, Line 414 is connected to steering gates 190,194 and other steering gatesWasTo Wordline 198 has selection gates 198'and 198'PrepareOf cells in a rowRespectivelyConnected to the selection gate of. Other rows in the array have separate wordlines as well.

See FIG. 16 under the steering gates 190,194 and other steering gates connected to line 414.AhProcessing that is programming the charge storage areaBetweenHigh programming voltage for line 414OverUnder the steering gate 191 and other steering gates connected to line 411AhConductive in the channelSexualAreaProvideSufficient bypass voltageToFor line 411Keru。Otherwise not selectedFlow in the middle cellWillLine 412 connected to the steering gate in an unprogrammed intermediate cell to reduce current,Voltage sufficiently low for 413 (eg negative voltage of a few volts)multiply.. In connection with Figure 15PreviousAs mentioned, the wordline 198 is set to the proper voltage. In this way, from the step of performing separate programming processes up to 5 for the corresponding storage areas up to 5.NaIn one first pass, it is possible to program and read all even-numbered cells along the wordline. Similarly, one second pass allows you to program and read all odd-numbered cells along the same wordline.

See Figures 10-13PreviousThis is the processing process for forming the memory cell array described above.Ruga, Processing process with increased storage density in the x directionofExamples from Fig. 17 to Fig. 2To 0Shown. thisFigureIs a view cut along the x-direction cross section of the array, showing a series of processing steps.

The first series of processing steps shown in FIG. 17 includes the step of forming a layer 419 of ONO or another charge trapping dielectric on the surface 421 of the substrate 423 in the substrate region where the array is formed. Is done.Then, The doped polysilicon layer 425 is formed on the layer 419 in this region. Film formation of silicon nitride layer 427 on polysilicon follows this step.Then, A photoresist strip 429 extending in the y direction and having a length spaced in the x direction.HaveAn etch mask is formed over the nitride layer strip 427. The pitch of these strips in the x direction is reduced to the same resolution as the lithography usually used to expose photoresists.

The following series of processing steps can be described with reference to FIG. Between mask elements 429 (Fig. 17)NitrogenAn isotropic etching process of the compound layer 427 is performed.hand, A portion of the nitride, ie strip 427 extending in the y direction, is left under the mask element. Figure 18ARay's x wayIn the directionWataRuthisShow strip.. The resulting width of the strip 427 is narrower than the width of the photoresist mask strip 429 due to the undercutting step during the etching of the nitride. A thick layer of silicon dioxide was then formed over this structure and the nitride strip 429MaoYoAnd nitrogenFilled over compound strip 429. Anisotropic etching of the oxide is then performed to provide a space between the nitride strips 427 in the x direction along the lateral wall of the nitride strip 427, which is smaller than the minimum lithographic dimension of the process. Spacer 431 is left behind. The width of the spacer 431 and the space between the spacers 431 are controlled by utilizing the control of the height of the nitride layer 427 and the thickness of the formed silicon dioxide.

Next, etching of the polysilicon layer 425 is performed through the space between the oxide spacers 431. Generally for this etching, the y directionofThe result is a continuous trench that exists between the strips and extends in the y direction.WillEtching of any field insulation is also included. This process leaves a polysilicon strip 425'continuing in the y direction. It is possible to remove the charge trapping conductive layer 419 between the segments 425'through this mask, but this removal is not necessary and in FIG. 19, the charge trapping conductive layer 419 remains intact.TteiTo In any case, the source / drain region 433 is then injected into the substrate 423 through these trenches by directly irradiating the structure with ions... SoThe source / drain region extends continuously in the y direction across both ends of the array. The oxide spacer 431 is then removed by a selective etching step. A thick layer of silicon dioxide is then formed into the trench over the remaining nitride strip 427. This oxide is then chemically mechanicalTargetNitride is used as a polishing (CMP) stop material and is removed by the bottom-to-top CMP process of the nitride strip 427. The result is an oxide filling section 435 between the polysilicon segment 425'and the nitride strip 427.

In Figure 20IllustratedIn the next series of steps, the nitride 427 is removed by a selective etching step that leaves the oxide filling 435 in a substantially suitable position. Further etching of polysilicon is then performed through the resulting openings between the oxide fillings 435. This etching process leaves behind a doped polysilicon control (steering) gate 425 with a length extending in the y direction.RageThe area of charge trapping dielectric 419 exposed between the tubes is also removed.Then, Oxide layer 437 is grown and / or filmedhand, As a selective gate dielectric within the area of interest under the select gate, and as a target insulator between the steering gate and the wordline.This layer 437Function. A second doped polysilicon layer is deposited over the region of the array, then extending in the x direction and spaced in the y direction.HaveLine 439 etc. by removing the second doped polysilicon layer through a mask that leaves the wordline stripWaA drawline is formed.

A major advantage of the structure of FIG. 20 compared to the advantages of FIG. 11A is its compactness along the x direction. As a result, the number of charge storage regions of a predetermined length in a row is dramatically increased by a factor of two.

General operation of memory system An example of a memory system capable of realizing various aspects of the present invention is generally shown in the block diagram of FIG. Specifically, this system is provided with a control (steering) gate formed elongated in the y direction.PreviousAlthough the purpose is to utilize the arrays of the second and third examples described above, this system includes circuits that connect to the steering gate.ToUnnecessaryToEspeciallyThereforeIn the first exampleAgainstApplications are also includedWill be。

Another physical in the cellNaArrangement configurations are certainly possible, but a large number of individually addressable memory cells 11 are arranged in an array of rows and columns with equal pitch. The bit lines specified herein to extend along the rows of cell array 11 are electrically connected to the bit line decoder and driver circuit 13 via the line 15. The word line specified in this application to extend along the rows of cell array 11 is electrically connected to the word line decoder and driver circuit 19 via line 17. The steering gate extending along the row to the memory cells in the array 11 is electrically connected to the steering gate decoder and driver circuit 21 via line 23. Steering gates and / or bit linesThe whole is incorporated herein by reference.Simultaneous continuation of Harari et al.'S segmentation of steering gate and bitline in non-volatile memoryapplicationMay 31, 2001 inToapplicationWas doneDescribed in U.S. Patent Application No. 09 / 871,333 (Patent Document 22)Has beenBy technique, SoIt may be connected to each decoder. Decoder 13,19,21RespectivelyReceives memory cell addresses from memory controller 27 via bus 25. The decoder / driver circuit is also connected to the controller 27 via the respective control signal lines and status signal lines 29, 31, 33. The voltage applied to the steering gate and bit line is the steering gate decoder and bit line decoder, as well as the driver circuits 13 and 21.WhenAre tuned via bus 22 that interconnects the.

The controller 27 can be connected to a host device (not shown) via line 35. The host may be a personal computer, a notebook computer, a digital camera, an audio player, various other handheld electronic devices, and the like. The memory system in Figure 21 is PCMCIA, CompactFlash (RegistrationTrademark) Association, MMC (RegistrationTrademark) Association,OrCards obtained from otherssuch asIn-card that complies with one of several existing physical and electrical standardssoGenerally realized. In the form of card format, line 35 is the complementary connector on the host device.And iTerminate with a connector that connects to the interface card. The electrical interface of many cards complies with the ATA standard, and the memory system is to the host as if it were a magnetic disk drive.appear.. There are other memory card interface standards as well.What was mentioned aboveApart from that, the card-formatted memory system of the type shown in FIG. 21 is permanently embedded in the host device.

Decoder circuits / driver circuits 13,19,21 are addressed when addressed via bus 25ToAccording to the control signals in each control line and state line 29,31,33 to perform programming, read and erase functions, that of array 11TimeGenerate proper voltage on each line of the roadLet.. Any state signal, including voltage level and different array parameters, is output to controller 27 by array 11 via the same control and state lines 29,31,33. A plurality of sense amplifiers in circuit 13 receive current or voltage levels indicating the state of addressed memory cells in array 11 and span line 41 during read operation.thisProvides state information to controller 27. A large number of such sense amplifiers are commonly used so that the states of a large number of memory cells can be read simultaneously. Read processing and programMingDuring processing, on the addressed line, circuit 13,One row of cells at a time through circuit 19 to access multiple cells 21 selectedNormalThe address is specified. In one embodiment, many rows of rows are being erasedOf eachAll cells are collectively addressed as one block for simultaneous erasure.

Memory cell array of the system in Figure 21ToIt is desirable to fractionate into segments.PreviousFrom the second and third examples described aboveUnderstandSo, unless segmented, the source, drain and steering gates are all in the y direction.On the bodyIt can be extended without restrictions. Maximum areOver iPart of the distanceToIsKe yIn the directionEachThis for the extending segmentInvitationThe electric body array can be fractionated. The source and drain at the ends of the segment are connected via switching transistors to a global bitline, typically made of metal. The steering gate can be connected via the switching transistor in the same manner as the global steering line.What was mentioned aboveApart from that, in connection with Figure 16PreviousIn the manner described, the steering gate can be connected to the steering gate line bus corresponding to the segment. During the programming process, read process, or erase process, one selected segment may be used, depending on the segmentation embodiment utilized.、With a set of global bitlinesUsually connected at the same time, With either a set of global steering lines or a corresponding steering gate line busAlsoUsually connected at the same time. About such segmentationBeforeIn connection with Figure 10C of US Pat. No. 5,712,180 8 (Patent Document 8) described above.Described and alsoMay 31, 2001ToapplicationWas doneDescribed in US Pat. No. 09 / 871,333 (Patent Document 22)Has been。

Regarding the processing of the memory system as shown in Fig. 21hand,Previously identified patents and pendingapplicationPatent application in, and another patent and pending transfer to SanDisk Corporation, the assignee of this application.applicationDescribed in the patent application insideHas been.. Describes the structure, process or process of a memory system that uses a floating gate as a storage elementHas been usedReference patents and patent applications are recognized as relating to the realization of systems that utilize dielectric storage elements instead of floating gates.Should be.. further,The whole is incorporated herein by reference.February 26, 2001ToapplicationWas doneU.S. Patent Application No. 09 / 793,370 describes data programming methods applicable to either floating gate systems or dielectric storage element systems.Has been described。

Fourth memory cell example The fourth example shown in FIGS. 22 to 24 applies a dielectric storage technique to a NAND array. Floating gate of this techniqueofFor the version,beforeBackground of the inventionColumnGenerally explained in. Cross section of FIG. 23AFromAs you can see best, the conductive wordlines 241-244, which are elongated in the x-direction and spaced in the y-direction, are the charge-storing dielectric strips 245-249 and the dielectric in the trench of the semiconductor substrate 257. Extends across both ends of the intermediate insulation region 251-254 formed from. The dielectric strips 245 to 249 are elongated in the y direction and are spaced in the x direction so that one of the dielectric insulating regions 251 to 254 is located.ThatPlaced in between. TypicalShallow trench isolation(STI) ToMore dielectric region 251 ~ 254Is preferable to form.. Alternatively, another technique of electrical insulation between adjacent rows of memory cells may be used.

Dielectric strips 245 to 249 are formed directly on the surface of substrate 257. Dielectric material and other properties in relation to FIGS. 6A and 6BPreviousOf the two mentionedEither is preferable.. Word lines 241 to 244 are arranged in order directly on the tops of these dielectric strips within the region that will be the charge storage region. Charge storage regions 265-267 are shown in FIG. 23A along wordline 242. Regions 269,265,271,272 are also shown in FIG. 23B along the dielectric strip 246. A doped source / drain region is formed within the surface region of substrate 257 between the wordline and the insulating dielectric. For example, source / drain regions 261-263 are located between the word lines of the column formed between the dielectric insulation regions 251 and 252.WasTo As shown in the cross section of FIG. 23B and as represented by the electrical equivalent circuit diagram of FIG. 24, this column forms one string of serially connected memory cells. As shown in FIG. 23B, at the individual ends of this string, there are switching select transistors at one end with gate 275 and the other end with gate 277. Terminal 279,The 281 forms an electrical termination of a string consisting of a storage transistor and a selection transistor. thisEndOne terminal of the childUsually eachIt is connected to the bit line of, and the other terminal is connected to the common potential. A large number of such strings of such transistor trains are provided in a row extending in the y direction in a typical memory cell array.

Figures 22-23B show the use of dielectric charge storage in one particular NAND memory cell array structure. It should be recognized that the dielectric charge storage material may function as a charge storage element within another particular NAND array structure.

In general, existing NAND memory cell arrays with conductive floating gate storage elements have several such column strings in a common selected row.Inside eachOne cell inAhOne group of memory cells is selected for simultaneous reading or programming. Rows are selected by applying the appropriate voltage to the wordline. During the read operation, the related stringRespectivelyBe to that very a row of the memory cell transistor is conductive along in order, with the exception of the cells in one row to the desired readout, associated NAND strings withinLineWordline is boosted to a relatively high voltage. During the programming process, the voltage of the wordline of the selected line in the associated NAND string is the associated NAND string.SelectionChoiceIt has not beenIt is boosted to a higher voltage compared to the line wordline. Similarly, the selection transistor at the end of the string consisting of the selected cell sequence is properly biased to perform the desired read or programming function.EndAn appropriate voltage is applied to the terminals of the unit. Dielectric storage media such as the dielectric storage media of FIGS. 22 to 24HaveThe same processing procedure can be applied to the NAND memory cell array.

As in the other examples aboveTo, The charge stored in the dielectric of the memory cellthisAffects the cell threshold voltage. For example, the charge level stored in region 265 of dielectric strip 246 isthisThe threshold voltage level of the memory cell transistor formed by the region and the adjacent source / drain region 261,Establish 262 and a portion of the substrate between the source and drain forming the channel of the cell and part of the word line 242 located on the channel. In connection with other examplesPreviousAs mentioned, memory cellsofOf the charge storage areaEachIt can be processed in 2 states or 3 or more states.

One step of forming the NAND structure shown in FIGS. 22 to 23B involves first forming a layer of charge storage dielectric material such as ONO over the entire substrate area occupied by the array. A mask of silicon nitride is formed at the top of the ONO layer to define parallel elongated trenches within the substrate used to insulate adjacent NAND strings. The dielectric layer is then removed by an etching step to form a trench in the substrate through the opening of the mask. Next, a silicon oxide is formed over the structure, and the trench and the opening of the mask are filled. Excess oxides are removed, followed by removal of the silicon nitride mask material. As a result, the structure without the word line (WL) shown in FIGS. 23A and 23B is obtained. The doped polysilicon layer is then deposited over at least the array region., AnotherBy etching and removing part of the material through the mask of Figure 23AFigureThe wordline is formed so as to leave the wordline behind as shown in 23B. Ion implantation can then be performed through the charge-storing dielectric layer into the substrate region that remains exposed between the thick insulating dielectric and the wordline, thereby forming a source / drain region.

Another step in forming a slightly different NAND dielectric storage array is shown in Figure 25A,Figure25B andFigure25CExampleIt is shown. thisFigureShows the development of the structure along cross-sections VII-VII in the plan view of FIG. The reference numbers of the elements of FIGS. 25A to 25C corresponding to the elements of FIGS. 22 to 23B are the same although the double prime symbol (") is added.

In the first series of processing steps shown in FIG. 25A, a thin film layer 296 of silicon dioxide on the substrate surface 257 "is usually grown, and then a silicon nitride layer is formed on the surface of the substrate 257". Next, a mask provided with an opening (FIG. 22) elongated in the y direction is formed on the nitride layer, and the nitride layer is removed by etching through the mask to be elongated in the y direction and elongated in the x direction. Nitride strips 291 to 295 spaced in are left behind. The substrate is then etched in the space between the nitride strips used as a mask.ButThis is done, thereby forming an insulating trench in the substrate. Then, by forming a thick oxide layer over the structureThoseThe trench (Fig. 25B) is filled with silicon oxide, KoSilicon oxide removed from the substrate trenchTofillingShi, The portions 251 ", 252", 253 "and 254" that extend slightly above the substrate surface are left behind.

The next series of steps is shown in Figure 25C.ExampleIt is shown. Nitride strips 291 to 295 are removed by selective etching, which leaves behind the trench oxide between the nitride strips and the substrate surface underneath the nitride strips, which is largely unaffected. Next, the exposed substrate surface area and the substrate surfaceofA charge-storing dielectric layer 297, such as an ONO, is formed over the entire memory cell array region that covers a portion of the insulating dielectric that extends upward. Next, a doped polysilicon material layer is formed, and a mask formed elongated in the x direction and provided with openings spaced in the y direction is formed on the top of the polysilicon layer., KoBy removing the polysilicon through the mask opening of the, a wordline is formed over the entire area. This step extends across both ends of the structure, leaving behind a wordline containing the wordline 242 of FIG. 25C, followed by the source / drain region of the substrate (not shown in FIGS. 25A-25C). It is injected through the charge storage dielectric layer 297 between the wordline and the insulating oxide film used as the injection mask.

As mentioned aboveThe resulting structure of FIG. 25C includes its charge-storing dielectric layer 297 extending over the entire array region, whereas FIG. 23A andFigureIt is clear that the structure of 23B limits this dielectric layer to strips within thick insulating dielectric layers. In either case, a charge-storing dielectric layer is provided on the channel of the NAND-storing transistor that needs to store the charge.

Yet another process to form a slightly different NAND array is shown in Figures 26A-26D.ExampleIt is shown. 26A-26C show the development of the structure along the cross-sections VII-VII of the plan view of FIG. 22, while FIG. 26D shows the intermediate structure of FIG. 26C along the straight cross-sections VIII-VIII. The main difference in the processing of FIGS. 26A to 26D is the formation of a substrate etch mask provided with a strip of polysilicon instead of nitride.Can be mentioned. MeWithin the area of MoricelSuThe trip portion is retained as part of the wordline. Also the resultAsThe resulting charge-storing dielectric layer is not contiguous throughout the memory cell array. Reference numbers for the elements in Figures 26A-26D that correspond to the elements in Figures 22-25CTo 3The heavy prime symbol (''')AddedHave beenIs the sameIt is the same.

The first series of processing steps is shown in Fig. 26A.ExampleIt is shown. A charge trapping dielectric layer 469, such as an ONO, is formed on the surface of the silicon substrate 257'''. The doped polysilicon layer is then deposited on the dielectric layer 469 over the area of the memory cell array.ThenA silicon nitride layer is formed on polysilicon. Next, a mask is formed to etch the nitride layer and the openings in the polysilicon layer (FIG. 22) elongated in the y direction. This etching is then performed. As shown in FIG. 26A, this leaves behind a polysilicon strip 471-475 with a top that is elongated in the y direction and contains a nitride 477 spaced in the x direction.

As shown in FIG. 26B, the next step is to etch the dielectric layer 469 with the substrate 257'''in the space between the polysilicon / nitride strips used as a mask, thereby An insulating trench is formed inside. Then thisRatThe wrench is filled with silicon oxide by forming a thick oxide layer that extends into the trench through the space between the polysilicon / nitride strips and over the polysilicon / nitride strips. .. This oxide is then removed downwards to the nitride layer 477 by the CMP, thereby filling the substrate trench with the oxide moiety 251'''.,252''' ,253'''and 254''' are left up to the top of the remaining nitride 477.

The next series of steps is shown in Figure 26CExampleIt is shown. Nitride 477 is first removed by selective etching, which leaves the tops of polysilicon strips 471-475 exposed. A second doped polysilicon layer is then deposited over the array structure and the oxide strips 251'''to 254' rising above the exposed tops of the polysilicon strips 471-475 and the polysilicon strips. Direct contact with part of''. As a result, Figure 26DMostAs is also well shown, the wordline 241'''~ 244 by etching this second polysilicon layer into strips 481 ~ 484 that are elongated in the x direction and spaced in the y direction. '''Is formed. By this etching process, in the space between strips 481 to 484AhPart of the polysilicon strips 471 to 475 is also removed, thereby leaving separated portions 471'to 474' of these strips connected by the coated strips 481 to 484 from the second polysilicon layer. The source / drain regions, such as region 261'''~ 263''' (Fig. 26D), are then placed on the substrate 257'via the charge-storing dielectric in the space between the wordlines 241'''~ 244'''. '' Injected into.

Example of fifth memory cell Another NAND array is shown in Figures 27 and 28ExampleIt is shown. The structure of this fifth example removes the source spread and drain spread along the NAND memory cell sequence between wordlines.Also thosepositionsoBy adding another set of wordlines、It is essentially different from the fourth example. As a result, using a process with the same minimum decomposable element size, almost double the number of independent addresses along the same length NAND string in the y direction across both ends of the array.DesignationPossible dielectricbodyA charge storage region will be obtained. The number of wordlines, and therefore the independently programmable dielectric within the individual NAND stringsbodyThe number of charge storage regions should be 3 or more and 8,16,32 or more.AlsoIt is possible, and it should be about half the length of a conventional NAND string that contains the same number of charge storage regions.AlsoIt is possible.

FIG. 27 is a plan view showing a narrow portion of the array of the fifth example, and FIG. 28 penetrates one of the memory cell strings of this array and the selection transistors at the individual ends of this string. Show the cross section.. ARay has surface 303HaveIt is formed on the semiconductor substrate 301. A plurality of charge storage dielectric strips 305 to 309 are spaced in the x direction between deep oxide insulating regions 311 to 314 that are elongated in the y direction across both ends of the array and are also elongated in the y direction. ing. The insulated regions 311 to 314 can be substantially the same as the regions 251 to 254 (Fig. 23A) or 251 "to 254" (Fig. 25C) in the fourth example. The charge storage dielectric strips 305 to 309 are the same as those shown in FIG. 23A of the fourth example.To, The oxide insulating region may be physically separated in the x direction. Alternatively, it may be part of a continuous dielectric layer extending over the oxide insulating region as shown in FIG. 25C. The cross section IX-IX across both ends of Figure 27 is not clearly shown.、2It can be almost the same as one of the two figures. This in the 4th and 5th examplesSpecialThe signs may be the same.

But,As mentioned above2HornWhat is essentially different between the examples is a wordline that is elongated in the x direction as in the previous case, but is packed in the y direction directly adjacent to each other with the appropriate dielectric in between. There are 317 to 323 configurations. Wordline, No.Unlike the case of example 4, it is not separated by the source / drain area of the memory cell. In particular, since the word lines are arranged side by side in the y direction, the source / drain areaIsIt becomes unnecessary. thisRyoThe region is not directly connected to the external voltage of the fourth example, instead the individual NAND strings between the charge storage elements.BetweenConductive paths are provided along the gap.. WaDrine andthisBelow the wordlineAhCharge storage area、Below the wordlineAhControl the continuity of the board channels together. This fifth example of substituting an additional wordline for the source / drain areasoIs, WaDrine andthisBelow the wordlineAhCharge storage areaIs soThe boot / drain areaIn the fourth example aboveThe result is that the conductivity of the existing substrate channels is controlled. In addition, the recording density of the charge storage area along the dielectric strip is doubled, as shown by the charge storage areas 327-333 in one NAND string of FIGS. 27 and 28.

Referring to FIG. 28, the external connection terminals of the memory cell string are at the opposite ends of the string connected to the common potentials such as global bitline (not shown) and ground at terminals 345 and 347, respectively.AhSource diffuser and drain diffuser 341,343WhenIs included.thisThe connections are at the opposite ends of the string, respectively, at the control gates 349.,It can be operated by the voltages GC0 and GC1 applied to 351. Control gate 349,351 at both ends of the stringAhWordline 353,It is desirable to be placed directly adjacent to the 355.

Figures 27 and 28OneGenerallyExampleOne processing technique for forming the structures shown will be described with reference to the cross-sectional views of FIGS. 29A and 29B. The starting point is the alternative structure of the fourth example shown in Figure 23A or Figure 25C.RukoHowever, source and drain injections are omitted. At that stage, the wordlines 317,319,321,323 are in the proper position over the continuous charge storage dielectric strips 305-309, but by the first additional step.RiwaDielectric is removed from the substrate surface 303 between the disks, thereby resulting in a new dielectric layer 361 (PreferablyONO) will be able to be formed on all structures.. layer361 acts as a charge storage dielectric under the additional wordline formed by this layer 361., ChaseAdditional wordlines and existing wordlines 317,319,321,323ofA dielectric layer is provided between them.

The next step is to dope the polysilicon layer 365 or another on the top of the dielectric layer 361 in a form that is compatible with the dielectric layer 361 over the entire array region.preferableThis is the step of forming a conductive material... PoThe etching mask for the resilicon layer 365thisFormed at the top of the layer. In making this mask, oxides or nitrides were provided with lengths extending in the x direction and spaced in the y direction to cover the portion of polysilicon layer 365 between the wordlines 317,319,321,323. Dielectric parallel strips 367 may be formed first. By forming a dielectric layer over the entire polysilicon layer 365, then using a photoresist mask on top of the oxide layer.thisDielectric strip 367 is formed by etching the layer and converting it to strip 367.It is preferable to do. acidThe compound spacer 369 is theirAmongIt is formed along the end face of strip 367 to narrow the space. Standard to form spacer 369NaAs a method, another dielectric layer is formed on the dielectric strip 367, and then anisotropic etching of this other layer is performed to remove this layer so that the spacer 369 is left behind. is there.

The next step is to etch the polysilicon layer 365 through masks 367,369, leaving behind wordlines 318,320,322 arranged in the y direction between wordlines 317,319,321,323, as shown in FIG. 29B... FigureTo remove the dielectric masks 367,369 as shown inAlsoYou can, but you don't have to. Since the photoresist mask used to form the dielectric strip 367 for masks is not self-aligned with the wordlines 317,319,321,323 in the y direction, the space between the dielectric strips 367 is the smallest lithography process to be processed by the use of spacer 369. Made narrower than the disassembleable dimensions of. However, even with the occasional slight misalignment of the photoresist mask, the resulting wordlines 318,320,322 completely fill the space between adjacent wordlines of the wordlines 317,319,321,323 when coated by the dielectric layer 361. It will be filled. This is due to the fact that wordlines 318,320,322 individually widen the width in the y direction beyond the width required to fill the space between wordlines 317,319,321,323 when perfect alignment can be guaranteed. Is.

Another technique for forming additional wordlines is in Figures 30A and 30B.ExampleIt is shown. Several steps are taken before forming the second layer 371 of doped polysilicon. The polysilicon wordline 317,319,321,323 is provided by the oxide layer strip 373.RespectivelyCovered with,acidThe compound layer strip 373 is covered with the nitride strip 375. Strip 373,375 is etched,RespectivelyFormed by covering the entire first polysilicon layer with these two layers before changing to the wordline 317,319,321,323It is preferable to be done. SuEtching of all three layers (polysilicon, oxide and nitride) is performed together, resulting in the multi-wordline strip shown in Figure 30A... AAn ONO-like dielectric layer 373 is formed to match the exposed surface over the ray region. It is exactly on this dielectric layer 377 that the second layer 371 of the doped polysilicon is formed.

The second polysilicon layer 371 is made thick enough to completely fill the space between the wordlines 317,319,321,323. The surplus polysilicon then uses the nitride strip 375 as the stop material in the chemical machine.TargetRemoved by the polishing (CMP) process. The result is an additional wordline of 318,321,322 as shown in FIG. 30B. In addition to the CMP process, an etching process may be subsequently performed to ensure that the polysilicon strips 318,321,322 are completely electrically isolated from each other. As a result, thisLasTrip thickness is slightly thinnerTo

A memory system that utilizes the memory cell array of the 4th or 5th example An example of another memory system capable of realizing various aspects of the present invention is shown in the block diagram of FIG. 31.ExampleIt is shown. A memory cell array 1 containing a plurality of memory cells configured in the form of a matrix is controlled by a column control circuit 2, a row control circuit 3, a c source control circuit 4, and a cp well control circuit 5. This systemPreviousIt is particularly suitable for using the NAND type memory cell array 1 of the 4th and 5th examples described above.

The control circuit 2 is a program for reading data stored in a memory cell.MingFor establishing the state of the memory cell being processedAlsoConnected to the bit line (BL) of memory cell array 1 for controlling the potential level of the bit line (BL)hand, Programming is promoted or programming is prohibited. For examplePreviousOf the NAND memory cell mentionedRespectivelyOne terminal of the string can be connected to one of the bit lines and the other terminal of the string can be connected to a common potential such as ground. The row control circuit 3 is connected to the word line (WL) and applies a read voltage or a programming voltage to the word line. thisRadenThe pressure is combined with the bitline potential level controlled by column control circuit 2 to select memory cells along one of the wordlines.Read toHave them perform squeezing and programming at the same time. Memory cells are formed pformThe erasing voltage is also applied to the region by circuit 2. The c-source control circuit 4 controls a common source line (labeled c-source in FIG. 31) connected to the memory cell. The cp well control circuit 5 controls the cp well voltage.

The data stored in the memory cell is read by the column control circuit 2 and output to the external I / O line 51 via the internal I / O line 53 and the data input / output buffer 6. The target program data stored in the memory cell is input to the data input / output buffer 6 via the external I / O line 51 and transferred to the column control circuit 2. The external I / O line 51 is connected to the controller 43. The controller includes various types of registers as well as other memory including volatile random access memory (RAM) 45.

The command data for controlling the flash memory element is input to the command circuit 7 via the internal control line 55 via the external control line 57 connected to the controller 43. The command data gives the flash memory information about what kind of processing is required. The input command is transferred to the state machine 8 that controls the column control circuit 2, the row control circuit 3, the c source control circuit 4, the cp well control circuit, and the data input / output buffer 6. The state machine 8 can output the state data of the flash memory such as READY / BUSY and PASS / FAIL.

Controller 43 is a personal computer, digital camera, or personalPersonal Digital Assistant (PDA)Connected to a host system such asKaOrThose devicesCan be connected to. Memory array 1Store data orMemory array 1La deDataToreadingOrIt is the host that initiates such commands and outputs and receives such data respectively. The controller has command circuit 7InterpretationAnd convert such a command into a command signal that can be executed. In addition, the controller generally includes a buffer memory for writing user data to the memory array and reading user data from the memory array. A typical memory system consists of one integrated circuit chip 47, including a controller 43, and a memory array, related control circuits, input / output circuits, and state machine circuits.PrepareIncludes one or more integrated circuit chips 49. Needless to say, there is a trend to integrate the memory array of a system and a control circuit on one or more integrated circuit chips.

Inside a memory card that can be detachably inserted into the host system's connection socket or by incorporating either of the memory systems in Figure 21 or Figure 31 as part of the host system.ToIt may include a moly system. The entire memory system may be included in such a card.What was mentioned aboveSeparately, the controller (with associated peripherals) and memory array may be on separate cards. The implementation configuration of some cards、For exampleThe whole is incorporated herein by reference.It is described in US Pat. No. 5,887,145 (Patent Document 23).

Configuration of other memory cells Same as other configurations of memory cell array utilizing conductive floating gateYoReplace the floating gate with a charge trapping dielectric、2Array in either forward (2 states) or multi-states (3 or higher states)RespectivelyYou may want to process the charge storage area of. For example, in the patents and patent applications referenced earlier, either the containment element or the source / drain diffuserThe cross section is rectangular or V-shapedPlaced in the trenchTo doA configuration is described. In these embodiments, it is also possible to replace the conductive storage element with a charge trapping dielectric.

Conclusion Although various aspects of the invention have been described in connection with specific examples thereof, the invention should be protected to the maximum extent of the appended claims.

<figref num="1">The plan view of the first example of a memory cell array is shown.</figref><figref num="2A">FIG. 5 is a cross-sectional view of the array of FIG. 1 cut out in section II.</figref><figref num="2B">It is sectional drawing of the array of FIG. 1 cut out in sectional section II-II.</figref><figref num="3">1 memory cell andthisCross section of FIG. 2A showing an exemplary threshold voltage characteristic across the cellFigureIt is an enlarged view of.</figref><figref num="4">It is a set of exemplary current / voltage characteristic curves for the memory cells of FIG. 3 that are processed in four states.</figref><figref num="5">It is a schematic representation of the equivalent electric circuit of the memory cell and some processing elements shown in FIG.</figref><figref num="6A">The configurations of different specific dielectrics that can be used in charge trapping memory cells are shown.</figref><figref num="6B">The configurations of different specific dielectrics that can be used in charge trapping memory cells are shown.</figref><figref num="7">The plan view of the second example of the memory cell array is shown.</figref><figref num="8A">FIG. 5 is a cross-sectional view of the array of FIG. 7 cut out in cross-sections III-III.</figref><figref num="8B">FIG. 5 is a cross-sectional view of the array of FIG. 7 cut out in section IV-IV.</figref><figref num="9">1 memory cell andthisFIG. 5 is an enlarged view of a cross section of FIG. 8A showing an exemplary threshold voltage characteristic across the cell.</figref><figref num="10">A plan view of the third example of the memory cell array is shown.</figref><figref num="11A">FIG. 5 is a cross-sectional view of the array of FIG. 10 cut out with a cross section VV.</figref><figref num="11B">FIG. 10 is a cross-sectional view of the array of FIG. 10 cut out by cross-section VI-VI.</figref><figref num="12">1 memory cell andthisFIG. 5 is an enlarged view of a cross section of FIG. 11A showing an exemplary threshold voltage characteristic across the cell.</figref><figref num="13">It is a cross section which shows the change of the memory cell shown in FIG. 11A.</figref><figref num="14">It is a cross-sectional view of the array of FIG. 10 cut out with a cross section VV modified from that shown in FIG. 11A.</figref><figref num="15">1 memory cell andthisIt is an enlarged view of the cross section of FIG. 14 which shows the example threshold voltage characteristic over both ends of a cell.</figref><figref num="16">It is the schematic which shows the connection embodiment of one gate of the array shown in FIGS. 10 to 15.</figref><figref num="17">It is sectional drawing which shows one processing process which forms the memory cell array shown in FIG. 10 to FIG.</figref><figref num="18">It is sectional drawing which shows one processing process which forms the memory cell array shown in FIG. 10 to FIG.</figref><figref num="19">It is sectional drawing which shows one processing process which forms the memory cell array shown in FIG. 10 to FIG.</figref><figref num="20">It is sectional drawing which shows one processing process which forms the memory cell array shown in FIG. 10 to FIG.</figref><figref num="21">A flash EEPROM system capable of implementing a memory cell array according to the first, second and third examples is shown in the form of a block diagram.</figref><figref num="22">It is a top view of the 4th example of a memory cell array.</figref><figref num="23A">It is sectional drawing of the array of FIG. 15 cut out in sectional sections VII-VII.</figref><figref num="23B">FIG. 5 is a cross-sectional view of the array of FIG. 15 cut out in cross sections VIII-VIII.</figref><figref num="24">It is an electrical equivalent circuit of the string of the memory cell of the fourth example.</figref><figref num="25A">One processing step for forming the memory array of the type shown in FIGS. 15 to 17 is shown.</figref><figref num="25B">One processing step for forming the memory array of the type shown in FIGS. 15 to 17 is shown.</figref><figref num="25C">One processing step for forming the memory array of the type shown in FIGS. 15 to 17 is shown.</figref><figref num="26A">Another processing step of forming the memory array of the type shown in FIGS. 22 to 24 is shown.</figref><figref num="26B">Another processing step of forming the memory array of the type shown in FIGS. 22 to 24 is shown.</figref><figref num="26C">Another processing step of forming the memory array of the type shown in FIGS. 22 to 24 is shown.</figref><figref num="26D">Another processing step of forming the memory array of the type shown in FIGS. 22 to 24 is shown.</figref><figref num="27">It is a top view of the 5th example of a memory cell array.</figref><figref num="28">It is sectional drawing of the array of FIG. 27 cut out in section XX.</figref><figref num="29A">It is a figure of the array of FIG. 27 over both ends of the cross section XX which shows the step of the 1st process embodiment.</figref><figref num="29B">It is a figure of the array of FIG. 27 over both ends of the cross section XX which shows the step of the 1st process embodiment.</figref><figref num="30A">It is a figure of the array of FIG. 27 over both ends of the cross section XX which shows the step of the 2nd process embodiment.</figref><figref num="30B">It is a figure of the array of FIG. 27 over both ends of the cross section XX which shows the step of the 2nd process embodiment.</figref><figref num="31">A flash EEPROM system capable of implementing a memory cell array according to the 4th and 5th examples is shown in the form of a block diagram.</figref>

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Document	Relation	Office	Cited during
JP2001102466A	Cites	Japan	Examiner
JP2001110918A	Cites	Japan	Examiner
JP2001148434A	Cites	Japan	Examiner
JP2001237330A	Cites	Japan	Examiner
JPH05129564A	Cites	Japan	Examiner
JPH05129624A	Cites	Japan	Examiner
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JP2001102466A	Cites	Japan	–
JP2001237330A	Cites	Japan	–
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10002696	United States of America	–	2001-10-31
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16123502	United States of America	A	2002-05-31
16123502	United States of America	A	2002-05-31
10280352	United States of America	–	2002-10-25
28035202	United States of America	A	2002-10-25
28035202	United States of America	A	2002-10-25
0235132	United States of America	W	2002-10-31
0235132	United States of America	W	2002-10-31
2001002696	–	–	–
2002161235	–	–	–
2002280352	–	–	–
2002035132	–	–	–
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US2003080370A1	United States of America	A1	2003-05-01
US2003082871A1	United States of America	A1	2003-05-01
WO03038907A1	World Intellectual Property Organization (WIPO)	A1	2003-05-08
US2003109093A1	United States of America	A1	2003-06-12
TW200406887A	Taiwan Province of China	A	2004-05-01
KR20040068923A	Republic of Korea	A	2004-08-02
EP1446840A1	European Patent Office (EPO)	A1	2004-08-18
JP2005508094A	Japan	A	2005-03-24
CN1610976A	China	A	2005-04-27
US6897522B2	United States of America	B2	2005-05-24
US2005157551A1	United States of America	A1	2005-07-21
US6925007B2	United States of America	B2	2005-08-02
US2005180210A1	United States of America	A1	2005-08-18
EP1446840A4	European Patent Office (EPO)	A4	2005-09-07
EP1446840B1	European Patent Office (EPO)	B1	2007-04-18
EP1777750A2	European Patent Office (EPO)	A2	2007-04-25
EP1777751A2	European Patent Office (EPO)	A2	2007-04-25
EP1777752A2	European Patent Office (EPO)	A2	2007-04-25
EP1777751A3	European Patent Office (EPO)	A3	2007-05-09
AT360262T	Austria	T	2007-05-15
ATE360262T1	Austria	T1	2007-05-15
EP1777750A3	European Patent Office (EPO)	A3	2007-05-16
EP1777752A3	European Patent Office (EPO)	A3	2007-05-16
DE60219666D1	Germany	D1	2007-05-31
DE60219666T2	Germany	T2	2007-11-29
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AT493763T	Austria	T	2011-01-15
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JP4846979B2This record	Japan	B2	2011-12-28
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