Involatile semconductor storage and method of operating the same

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

In the present invention, a charge storage means (for example, a charge trap in a nitride film in a MONOS type or a MNOS type, a top insulating film) dispersed in a plane is formed inside a gate insulating film between a channel forming region and a gate electrode. It has a charge trap near the interface between the and the nitride film, a small particle size conductor, etc.), and for the charge storage means, a channel hot electron, a ballistic hot electron, a secondary impact ionization hot electron, a substrate hot electron, or the like. The present invention relates to a non-volatile semiconductor storage device whose basic operation is to mainly inject and store or withdraw hot electrons caused by an interband tunnel current, and an operation method thereof.

【0002】

[Conventional technology]

Non-volatile semiconductor memory is expected as a large-capacity and small-sized information recording medium, but in recent years, along with widening the bandwidth of information networks, writing speeds equivalent to the transmission speed of networks (for example, carrier frequency: 100 MHz) are required. Is becoming. Therefore, the non-volatile semiconductor memory is required to have good scaling property and to improve the writing speed by an order of magnitude or more than the conventional writing speed of 100 μsec / cell.

【0003】

Non-volatile semiconductor memory has FG (Floating Gate) type in which charge storage means (floating gate) for holding charges are continuously connected in a plane, and charge storage means are discrete in a plane, for example, MONOS (Metal-). Oxide-Nitride-Oxide Semiconductor) type and so on.

【0004】

In the MONOS type non-volatile semiconductor memory, carriers in the nitride film [Six Ny (0 <x <1, 0 <y <1)] film, which is mainly responsible for charge retention, or at the interface between the top oxide film and the nitride film. Due to the spatially discrete spread of the trap (ie, in the plane and film thickness directions), the charge retention properties are not only the tunnel insulation film thickness, but also the charge trapped by the carrier trap in the Six Ny film. Depends on the energetic and spatial distribution of.

【0005】

When a leak current path occurs locally in this tunnel insulating film, a large amount of charge leaks through the leak path in the FG type, and the charge retention characteristics tend to deteriorate, whereas in the MONOS type, the charge storage means is a space. Therefore, the local charge around the leak path only leaks locally through the leak path, and the charge retention characteristic of the entire storage element is unlikely to deteriorate. Therefore, in the MONOS type, the problem of deterioration of the charge retention characteristic due to the thinning of the tunnel insulating film is not as serious as in the FG type. Therefore, the MONOS type is superior to the FG type in the scaling property of the tunnel insulating film in the fine memory transistor having an extremely short gate length. Further, when a charge is locally injected into the distribution plane of the carrier trap that is discretized in a plane, the charge is retained without being diffused in the plane and in the film thickness direction unlike the FG type.

【0006】

It is important to improve the disturb characteristics in order to realize a fine memory cell in the MONOS type non-volatile memory, and for that purpose, it is necessary to set the tunnel insulating film thicker than the normal film thickness (1.6 nm to 2.0 nm). .. When the tunnel insulating film is made relatively thick, the writing speed is about 0.1 to 10 msec, which is still not sufficient. That is, in the conventional non-volatile memory such as MONOS type, the writing speed is limited to 100 μsec when the reliability (for example, data retention characteristic, read disturb characteristic, data rewrite characteristic, etc.) is sufficiently satisfied.

【0007】

It is possible to increase the speed by considering only the writing speed, but this time it is not possible to sufficiently reduce the reliability and voltage. For example, a source-side injection MONOS transistor that injects channel hot electrons (CHE) from the source side has been reported (IEEE Electron Device Letter 19, 1998, pp153), but this source-side injection MONOS transistor writes the operating voltage. It is as high as 12V at the time and 14V at the time of erasing, and the reliability such as read disturb characteristics and data rewriting characteristics is not sufficient.

【0008】

On the other hand, recently, focusing on the fact that the charge can be injected into a part of the discrete trap by the conventional CHE injection method, by writing binary information independently on the source side and the drain side of the charge storage means. A technology that can record 2 bits per memory cell has been reported. For example, in Extended Abstract of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, pp.522-523, 2-bit information is written by CHE injection by switching the voltage application direction between the source and drain, and when reading. The so-called "reverse read" method, in which a predetermined voltage is applied between the source and drain in the direction opposite to that at the time of writing, makes it possible to reliably read 2-bit information even when the writing time is short and the amount of accumulated charge is small. In addition, erasing is performed by hot hole injection. This technology has made it possible to increase the writing time and significantly reduce the bit cost.

【0009】

[Problems to be Solved by the Invention]

However, in this conventional CHE injection type MONOS type non-volatile memory, electrons are accelerated in the channel to generate high energy electrons (hot electrons), so a voltage of about 4.5 V is applied between the source and drain. It was necessary, and it was difficult to reduce the applied voltage between the source and drain. Therefore, there is a problem that the punch-through effect at the time of writing is limited and it is difficult to scale the gate length.

【0010】

An object of the present invention is to suppress punch-through that occurs when hot electrons are injected into a charge storage means such as a planarly discretized carrier trap to scale the gate length by a high-speed writing method, and the gate length is suppressed. It is an object of the present invention to provide a non-volatile semiconductor storage device having a good scaling property of a gate insulating film and an operation method thereof.

【0011】

[Means for solving problems]

The non-volatile semiconductor storage device according to the first aspect of the present invention is formed on the substrate surface with the substrate, the semiconductor channel forming region provided on the surface of the substrate, and the channel forming region interposed therebetween, and is a source or a source during operation. A gate insulating film composed of a first and second impurity region serving as a drain, a plurality of films laminated on the channel forming region, a gate electrode provided on the gate insulating film, and facing the channel forming region. The gate insulating film is formed by being separated in the plane and in the film thickness direction and formed in the gate insulating film, and has a charge accumulating means for injecting hot electrons excited by an applied electric field during operation. The bottom insulating film of the bottom layer includes a dielectric film that makes the energy barrier between the bottom insulating film and the substrate smaller than the energy barrier between silicon dioxide and silicon. Preferably, the bottom insulating film includes a dielectric film in which the energy barrier between the bottom insulating film and the substrate is smaller than the energy barrier between the nitrided oxide film formed by nitriding silicon dioxide and silicon. Here, preferably, the nitrogen content of the oxide nitride film is 10% or less. Further, preferably, when in the writing state or the erasing state, any one of the channel hot electron, the ballistic hot electron, the secondary impact ionization hot electron, the substrate hot electron, and the hot electron caused by the interband tunnel current has the above-mentioned charge. It is mainly injected into the storage means.

【0012】

Preferably, the bottom insulating film exhibits Fowler Nordheim (FN) tunneling electrical conductivity characteristics. Suitable film materials include silicon nitride, silicon oxide nitride, tantalum oxide, zirconia oxide, aluminum oxide, titanium oxide, hafnium oxide, and barium strontium titanium oxide (BST: Ba)._XSr_X-1TiO₃), Yttrium oxide is included as the above-mentioned dielectric film alone or in combination. When silicon oxide nitride is used, its nitrogen content is larger than 10%. Preferably, as a film constituting the gate insulating film, a nitride film or an oxide nitride film exhibiting pool frenkel (PF) electrical conduction characteristics is provided on the bottom insulating film. One of the features of the insulating film exhibiting FN tunneling electrical conduction characteristics is that the amount of carrier traps in the insulating material is significantly reduced as compared with the insulating film exhibiting PF tunneling electrical conduction characteristics.

【0013】

The gate insulating film preferably has a first region in which hot electrons are injected from the first impurity region side, a second region in which hot electrons are injected from the second impurity region side, and the first and first regions. It is sandwiched between two regions and has a third region in which hot electrons are not injected. Alternatively, the gate insulating film has a first region on the first impurity region side, a second region on the second impurity region side, and a third region between the first and second impurities regions. The charge storage means are formed in the first and second regions, and the distribution region of the charge storage means is spatially separated via the third region. In the latter case, for example, the first and second regions have a laminated film structure in which a plurality of films are laminated, and the third region is an insulating film made of a single material. Further, the gate electrode formed on the first and second regions and the gate electrode formed on the third region are spatially separated.

【0014】

In this non-volatile semiconductor storage device, a common line connected to a first impurity region (for example, a drain impurity region) and a second impurity region (for example, a source impurity region) are connected to each other, such as a separated source wire type and a virtual ground wire type. A NOR type memory cell system in which the common line can be controlled independently is preferable. In the separation source linear type, the common line to which the first impurity region is connected is called the first common line, and the common line to which the second impurity region is connected is called the second common line. In that case, the first and second common lines may be layered respectively. In the so-called AND type, memory transistors are connected in parallel to the first and second sub-lines as internal connection lines in the memory block.

【0015】

Further, as the memory transistor, various memory transistors such as so-called MONOS type and nanocrystal type in which the charge storage means are discretized in the plane direction and the film thickness direction can be adopted. Further, in the present invention, for example, the bottom insulating film may be thickened to omit the intermediate nitride film or the oxide nitride film in the MONOS type. In that case, in order to reduce the interface state on the semiconductor surface, it is desirable to thinly interpose the buffer oxide film with the channel forming region.

【0016】

The non-volatile semiconductor storage device according to the second aspect of the present invention is formed on the substrate surface with the substrate, the semiconductor channel forming region provided on the surface of the substrate, and the channel forming region interposed therebetween, and is a source or a source during operation. A gate insulating film composed of a first and second impurity region serving as a drain, a plurality of films laminated on the channel forming region, a gate electrode provided on the gate insulating film, and facing the channel forming region. It was separated in the plane and in the film thickness direction and formed in the gate insulating film, and was caused by channel hot electrons, ballistic hot electrons, secondary impact ionization hot electrons, substrate hot electrons, or interband tunnel current during operation. The bottom insulating film of the lowermost layer constituting the gate insulating film, which has a charge accumulating means in which hot electrons are mainly injected, is made of a material having a higher dielectric constant than silicon dioxide. Preferably, the SiH bond density of the bottom insulating film is lower than the SiH bond density of the nitride film constituting the top insulating film and exhibiting PF conduction characteristics (for example, by an order of magnitude or more). For example, the SiH bond density of the bottom insulating film is 1 × 10.²⁰atms / mm³Lower.

【0017】

The non-volatile semiconductor storage device according to the third aspect of the present invention is formed on the substrate surface with the substrate, the semiconductor channel forming region provided on the surface of the substrate, and the channel forming region interposed therebetween, and is a source or a source during operation. A gate insulating film composed of a first and second impurity region serving as a drain, a plurality of films laminated on the channel forming region, a gate electrode provided on the gate insulating film, and facing the channel forming region. It is discrete in the plane and in the film thickness direction and is formed in the gate insulating film, and is caused by channel hot electrons, ballistic hot electrons, secondary impact ionization hot electrons, substrate hot electrons, or interband tunnel current during operation. The gate insulating film has a charge storage means in which hot electrons are mainly injected, and the gate insulating film has a first region on the first impurity region side, a second region on the second impurity region side, and the first 1, It has a third region between the second regions, the charge storage means are formed in the first and second regions, and the distribution region of the charge storage means is spatially separated via the third region. .. Preferably, the first and second regions have a laminated film structure in which a plurality of films are laminated, and the third region is composed of an insulating film made of a single material.

【0018】

The operation method of the non-volatile semiconductor storage device according to the fourth aspect of the present invention is that the non-volatile semiconductor storage device is formed on the substrate surface, the semiconductor channel forming region provided on the surface of the substrate, and the channel forming region, and operates. The first and second impurity regions, which sometimes serve as sources or drains, a gate insulating film composed of a plurality of films laminated on the channel forming region, a gate electrode provided on the gate insulating film, and the channel forming. It is formed in the gate insulating film in the plane facing the region and in the film thickness direction, and has a charge accumulating means in which hot electrons are mainly injected during operation, and constitutes the gate insulating film. The lower bottom insulating film is a method of operating a non-volatile semiconductor storage device including a dielectric film in which the energy barrier between the bottom insulating film and the substrate is smaller than the energy barrier between silicon dioxide and silicon. The voltage applied between the 1st and 2nd impurity regions is set to be lower than when the writing speed is constant and the bottom insulating film is silicon dioxide. Preferably, the applied voltage between the first and second impurity regions is 3.3 V or less. Further, preferably, the applied voltage is made smaller than the energy barrier on the conduction side between the silicon dioxide and the substrate.

【0019】

When writing a plurality of bits, the bias application conditions of the first and second impurity regions are preferably reversed, and the writing is performed again, and the above writing is performed among the first impurity region side and the second impurity region side. Hot electrons are injected into the charge storage means from the opposite side of the time.

【0020】

The hot electrons injected from the first impurity region side are localized and retained on the first impurity region side in the plane of the charge storage means facing the channel forming region. When writing is performed by reversing the bias application direction of the first and second impurity regions for writing a plurality of bits, the hot electrons injected from the second impurity region side are transferred to the channel of the charge storage means. It is localized and retained on the second impurity region side in the plane facing the formation region. In this case, the holding region of the hot electron injected from the first impurity region and the holding region of the hot electron injected from the second impurity region are intermediate regions in which the hot electron is not injected in the charge storage means. It is separated on both sides in the channel direction.

【0021】

At the time of reading, a predetermined read-out drain voltage is applied between the first and second impurity regions so that the impurity region on the accumulated charge side of the read target becomes the source, and a predetermined read-out gate voltage is applied to the gate electrode. Further, when reading a plurality of bits, multi-valued data of 2 bits or more based on hot electrons injected from the first and second impurity regions is read by changing the voltage application direction to the first and second impurity regions. ..

【0022】

Preferably, at the time of erasing, the charge injected from the first impurity region side and held in the charge storage means is pulled out to the first impurity region side by direct tunneling or FN tunneling. Alternatively, it is eliminated by hot hole injection due to the interband tunnel current. When erasing a plurality of bits, preferably, the charges injected from the first or second impurity region side and held separately on both sides in the channel direction by the charge storage means are individually tunneled or FN tunneled. Alternatively, pull it all together toward the board side.

【0023】

In this non-volatile semiconductor storage device and its method of operation, at the time of writing, channel hot electrons, ballistic hot electrons, secondary impact ionization hot electrons, substrate hot electrons, or hot electrons caused by interband tunnel currents are used as sources or drains. It is injected into the charge storage means from the first or second impurity region, or from the entire channel. At that time, the hot electrons are injected over the energy barrier between the bottom insulating film, which is the lowest layer of the tunnel insulating film, and the substrate such as a silicon wafer. In the present invention, the energy barrier between the bottom insulating film and the substrate is lower than that of silicon dioxide and silicon. Further, as the material of the bottom insulating film, a material of a dielectric film that lowers the energy barrier of the bottom insulating film, for example, a material exhibiting FN tunneling electrical conduction characteristics such as a low trap nitride film is used. Therefore, the energy barrier between the bottom insulating film and the substrate that the hot electron must overcome is reduced from 3.2V, which is the energy barrier between silicon dioxide and silicon, which is a conventional insulating material, to 2.1V, for example. Since the energy barrier of the bottom insulating film is low, the charge injection efficiency is improved, and the drain applied voltage at the time of writing can be reduced to, for example, 3.3 V or less. A buffer oxide film may be interposed under the bottom insulating film, but since the film thickness is thin, it can be almost ignored in terms of energy barrier. Further, when the drain voltage at the time of writing is reduced, the average energy of the hot electrons injected into the charge storage means can be reduced, and as a result, the damage to the bottom insulating film is reduced.

【0024】

At the time of reading, the reading drain voltage is applied so that the impurity region on the side where the accumulated charge to be read is held becomes the source. At this time, the presence or absence of the accumulated charge on the high voltage side of the first and second impurity regions has almost no effect on the channel electric field, and the channel electric field changes under the influence of the presence or absence of the accumulated charge on the low voltage side. Therefore, the threshold voltage of the memory transistor reflects the presence or absence of accumulated charges on the low voltage side.

【0025】

At the time of erasing, for example, a positive voltage is applied to the first or second impurity region, and the accumulated charge on the source side or the drain side is pulled out to the substrate side by direct tunneling or FN tunneling. Further, at the time of erasing, for example, a positive voltage may be applied to the first or second impurity region, and a negative voltage may be applied to the word line (gate electrode) so that the surface of the impurity region to which the positive voltage is applied can be inverted. .. In this case, the surface of the inversion layer is depleted deeply, an interband tunnel current is generated, and the generated holes become hot holes by electric field acceleration and are injected into the charge storage means. Blocks can be erased all at once in any tunneling.

【0026】

BEST MODE FOR CARRYING OUT THE INVENTION

1st Embodiment The first embodiment relates to a virtual ground NOR type non-volatile memory device. FIG. 1 is a circuit diagram showing a virtual ground NOR type memory cell array configuration. In this memory cell array, a memory cell is composed of a single memory transistor. For example, m × n memory transistors M11, M21, ..., Mm1, M12, M22, ..., M1n, ..., Mmn are arranged in a matrix. Note that FIG. 1 shows only 2 × 2 memory transistors M11, M21, M12, and M22.

【0027】

The gates of each memory transistor are connected to the same word line line by line. That is, in FIG. 1, the gates of the memory transistors M11, M21, ... Belonging to the same row are connected to the word line WL1. Also, the gates of the memory transistors M12, M22, ... Belonging to the other rows are connected to the word line WL2.

【0028】

The source of each memory transistor is connected to the drain of another memory transistor adjacent to one side in the word direction, and the drain of each memory transistor is connected to the source of another memory transistor adjacent to the other side in the word direction. .. The commonly connected source and drain are connected to the common lines BL1, BL2, BL3, ... in the bit direction. These common lines function as a source line to which a reference voltage is applied when operating one memory transistor in which the source and drain are commonly connected, and a drain voltage is applied when operating the other memory transistor. It is used to function as a bit line. Therefore, in this memory cell array, the common lines BL1, BL2, ... in the bit direction are all referred to as "bit lines".

【0029】

FIG. 2 is a plan view showing 4 × 4 memory cells of this memory cell array. Each bit line BL1 to BL3 is connected to each sub bit line SBL1, SBL2, ... via a diffusion layer wiring (sub bit line SBL1, SBL2, ...) composed of an impurity region of a semiconductor and a bit contact (not shown). It consists of connected metal wiring (main bit wire MBL1, MBL2, ...). The main bit lines MBL1, MBL2, ... Are wired in parallel to the upper layers of the corresponding sub-bit lines SBL1, SBL2, ..., And have a parallel stripe shape as a whole. The word lines WL1, WL2, ... Are arranged in parallel stripes perpendicular to these bit lines BL1 to BL3, respectively. In this pattern of the memory cell array, there is no element separation insulating layer at all, and the cell area is correspondingly small. It should be noted that every other sub-bit wire, for example, the sub-bit wires SBL1 and SBL3 may be connected to the upper metal wiring via a bit contact (not shown).

【0030】

FIG. 3 is a cross-sectional view of an n-channel MONOS type memory transistor constituting each memory cell. In FIG. 3, n-type impurities are introduced and diffused on the surface side of a semiconductor substrate (or p-well) SUB such as a p-type silicon wafer to form a sub-bit line SBL and a sub-source line SSL at predetermined intervals. Has been done. The portion sandwiched between the sub-bit line SBL and the sub-source line SSL and where the word line WL intersects becomes the channel formation region of the memory transistor.

【0031】

A gate electrode (word line WL) of a memory transistor is laminated on the channel forming region via a gate insulating film 10. Ward wire WL generally consists of polysilicon (doped poly-Si), which is conductive by introducing high concentrations of p-type or n-type impurities, or a laminated film of doped poly-Si and a refractory metal VDD. .. The effective part of this word line WL, that is, the length (gate length) in the channel direction corresponding to the distance between the source and drain is 0.25 μm or less, for example, about 0.18 μm.

【0032】

The gate insulating film 10 is composed of a bottom insulating film 11, a nitride film 12, and a top insulating film 13 in this order from the lower layer. As the bottom insulating film 11, a nitride film having FN tunneling electrical conduction characteristics or an oxysilicon nitride film (FN tunnel nitride film) is used. This FN tunnel nitride film is produced by, for example, the JVD (Jet Vapor Deposition) method or a method of heating a CVD film in an atmosphere of a reducing or oxidizing gas to change the quality (hereinafter referred to as a heated FN tunneling method). It is a silicon nitride film or a film mainly composed of silicon nitride (for example, an oxysilicon nitride film). Whereas silicon nitride films made by normal CVD show pool-Frenkel (PF) -type electrical conductivity, this FN tunnel nitride film has fewer carrier traps in the film than when made by normal CVD. Therefore, it exhibits Fowler Nordheim (FN) type electrical conduction characteristics. The film thickness of the bottom insulating film (FN tunnel nitride film) 11 can be determined within the range of 2.0 nm to 6.0 nm depending on the intended use, and is set to 4.0 nm here.

【0033】

The nitride film 12 is composed of, for example, a 5.0 to 8.0 nm silicon nitride (Six Ny (0 <x <1,0 <y <1)) film. A small amount of oxygen may be doped in the silicon nitride film exhibiting PF electrical conduction. The nitride film 12 is produced by, for example, reduced pressure CVD (LP-CVD), and contains a large amount of carrier traps in the film. The nitride film 12 exhibits a pool frenkel (PF) type electrical conduction property.

【0034】

The top insulating film 13 needs to form a deep carrier trap at a high density in the vicinity of the interface with the nitride film 12, and for this reason, for example, it is formed by thermally oxidizing the nitride film after film formation. SiO in which the top insulating film 13 is formed by the HTO (High Temperature chemical vapor deposition Oxide) method.₂It may be a film. When the top insulating film 13 is formed by CVD, this trap is formed by heat treatment. The film thickness of the top insulating film 13 is at least 3.0 nm, preferably 3.5 nm or more, in order to effectively prevent injection of holes from the gate electrode (word wire WL) and prevent a decrease in the number of times data can be rewritten. is required.

【0035】

In the manufacture of a memory transistor having such a configuration, first, a p-well W is formed on the prepared semiconductor substrate SUB, and then an impurity region to be a sub-bit line SBL and a sub-source line SSL is formed by an ion implantation method. In addition, ion implantation for threshold voltage adjustment is performed as necessary.

【0036】

Next, the gate insulating film 10 is formed on the semiconductor substrate SUB. Specifically, first, the bottom insulating film 11 is formed, for example, about 4.0 nm by using the JVD method or the heated FN tunneling method. In the JVD method, Si and N molecules or atoms are released from a nozzle into a vacuum at extremely high speed, and this high-speed flow of molecules or atoms is guided on a semiconductor substrate SUB to deposit, for example, an oxysilicon nitride film. .. In the heating FN tunneling method, first, as a treatment before forming the bottom insulating film 11, the semiconductor substrate SUB is heat-treated at 800 ° C. for about 20 seconds in an NO atmosphere, for example. Next, for example, a silicon nitride (SiN) film is deposited by the LP-CVD method. Then, for this CVD film, for example, ammonia (NH)₃) Heat treatment at 950 ° C for 30 seconds in a gas atmosphere, followed by N₂Heat treatment is performed at 800 ° C. for 30 seconds in an O gas atmosphere, and immediately after the CVD film formation, the SiN film exhibiting PF conduction characteristics is modified into an FN tunnel nitride film.

【0037】

Next, the nitride film 12 is deposited on the bottom insulating film 11 by the LP-CVD method so that the final film thickness is 5 nm. This CVD is carried out, for example, using a gas in which dichlorosilane (DCS) and ammonia are mixed, at a substrate temperature of 730 ° C. Here, if necessary, it is advisable to optimize the pretreatment of the base surface (wafer pretreatment) and the film forming conditions in advance in order to suppress an increase in the roughness of the surface of the finished film. In this case, if the wafer pretreatment is not optimized, the surface morphology of the nitride film is poor and accurate film thickness measurement cannot be performed. Therefore, after sufficiently optimizing this wafer pretreatment, the film is reduced in the next thermal oxidation step. The film thickness is set in consideration of the decrease in the nitride film. The formed nitride film surface is oxidized by, for example, a thermal oxidation method to form a top insulating film 13 of about 3.5 nm. This thermal oxidation is, for example, H₂O Perform at a furnace temperature of 950 ° C in an atmosphere. As a result, a deep carrier trap with a trap level (energy difference from the conduction band of the silicon nitride film) of 2.0 eV or less is approximately 1 to 2 × 10.¹³/cm² It is formed at the interface between the top insulating film and the nitride film at the density of. Further, a thermal silicon oxide film (top insulating film 13) is formed at 1.6 nm with respect to 1 nm of the nitride film 12, and the nitride film thickness of the base film is reduced at this ratio, and the final film thickness of the nitride film 12 is 5 nm.

【0038】

A conductive film to be a gate electrode (word wire WL) is laminated, and the conductive film and the gate insulating film 10 are collectively processed in the same pattern. Subsequently, an interlayer insulating film is deposited, bit contacts are formed as necessary, a main bit wire MBL is formed on the interlayer insulating film, and then the non-volatile memory cell array is subjected to an overcoat film formation, a pad opening step, and the like. To complete.

【0039】

By the way, when the bottom insulating film of the ONO film (bottom insulating film / nitride film / top insulating film) of the MONOS type non-volatile memory transistor is thickened to, for example, about 4 nm, the film thickness specification of the conventional ONO film is specified. Typical values were 4.0 / 5.0 / 3.5 nm. This ONO film thickness is 10 nm in terms of silicon oxide film.

【0040】

Next, an example of bias setting and operation of the non-volatile memory having such a configuration will be described by taking the case of writing 2-bit data to the memory transistor M21 as an example. Writing is performed using, for example, channel hot electron injection. When writing 2-bit data, as shown in FIG. 3, the gate insulating film 10 of the memory transistor has the first region on the sub-bit line SBLi + 1 side, the second region on the sub-bit line SBLi side, and the first and first regions. It can be divided into a third area between the two areas. Hot electrons generated on the sub-bit line SBLi + 1 side are injected into the first region, hot electrons generated on the sub-bit line SBLi + side are injected into the second region, and hot electrons are injected into the third region in between. No electrons are injected.

【0041】

When writing to the memory transistor M21, for example, 3.3V for the metal wiring to which the selected bit line BL3 is connected, 0V for the bit line BL2 that functions as the source line, 5V for the selected word line WL1, and not selected. Apply 0V to the metal wiring to which the bit line BL1 is connected and the non-selection word line WL2. As a result, 3.3V is applied between the source and drain of the memory transistor M21, so electrons are supplied from the source impurity region (secondary bit line SBL2) into the channel to accelerate the electric field. The accelerated electrons become hot electrons near the end of the horizontal channel, and a part of them crosses the energy barrier of the bottom insulating film 11 and is injected into the carrier trap in the first region in the gate insulating film 10.

【0042】

On the other hand, when writing to the opposite side, that is, the local part (second region) of the bit line BL2 side of the charge storage means of the memory transistor M21, the applied voltage direction between the source and the drain is reversed from that at the time of writing, and the other The voltage conditions are the same. As a result, charge is injected into the second region on the bit line BL2 side of the distribution region of the charge storage means of the memory transistor M21 by channel hot electron injection.

【0043】

At the time of reading, a predetermined read-drain voltage is applied between the source and the drain with the side where the charge to be read of the memory transistor M21 is accumulated (for example, the bit line BL3 side) as the source and the bit line BL2 as the drain. Further, a predetermined read gate voltage is applied to the word line WL1. At this time, although not shown, the potential of the bit line BL4 further to the right is set so that the memory transistor M31 further to the right of the memory transistor M21 does not turn on. As a result, a potential change corresponding to the threshold voltage of the memory transistor M21 appears on the bit line BL3, and this is detected by the sense amplifier. When reading out the charge on the opposite side, the same reading can be performed by reversing the voltage application direction between the source and drain.

【0044】

Erasing is performed by extracting charges from the entire channel or from the sub-bit line SBL side using FN tunneling or direct tunneling. For example, when the electrons held in the charge storage means are extracted directly from the entire channel by tunneling, all word lines WL1, WL2, ... have -5V, for example, odd-numbered bit lines BL1, BL3, ... 5V, even-numbered bit lines BL2, BL4, ... are opened, and a voltage of 5V is applied to the p-well SUB. As a result, the electrons held in the first region of the charge storage means are drawn out to the substrate side, so that the cells are erased. At this time, the erasing speed was about 1 msec. Erasing on the second region side can be realized by exchanging the odd-numbered and even-numbered bit line set voltages. When erasing the first and second regions at once, all bit lines have the same potential at 5V.

【0045】

Erasing can also be performed by hot hole injection due to interband tunneling current. For example, with the well W held at 0, a predetermined negative voltage, for example -6V, is applied to all word line WLs, and a predetermined negative voltage, for example 6V, is applied to all sub-bit line SBLs. As a result, the surface of the n-type impurity region forming the sub-bit line SBL becomes a deep depletion state, and the bending of the energy band becomes steep. At this time, due to the interband tunnel effect, electrons are tunneled from the valence band to the conduction band and flow to the n-type impurity region side, and as a result, holes are generated. The generated hole drifts slightly toward the central part of the channel formation region, where the electric field is accelerated, and a part of the hole becomes a hot hole. The high-energy charge (hot hole) generated at the end of the n-type impurity region is efficiently injected into the carrier trap, which is a charge storage means, and recombines with the electrons held therein. At the same time, holes are injected, which causes the memory transistor to shift to the erased state.

【0046】

By the way, in the MONOS type memory transistor having a conventional structure using an oxide film as the bottom insulating film, it is necessary to apply a voltage of about 4.5 V between the source and the drain when injecting channel hot electrons, and high-speed writing of about 1 μs is required. It was difficult to reduce the source-drain voltage of 4.5V in order to obtain speed. When the gate length is scaled in such a state, the memory cell operation becomes difficult due to the punch-through generated between the source and the drain, which is a factor that hinders the scaling of the gate length.

【0047】

FIG. 4 shows the gate length dependence of the punch-through characteristic of the conventional MONOS type memory transistor in which the silicon oxide film is used as the bottom insulating film. Assuming that the maximum permissible value of drain current per unit gate width is about 500 pA / μm, conventionally, when the gate length is 0.22 μm, the drain voltage can only be applied up to about 5 V. When the gate length is 0.18 μm, the drain voltage of about 3.6 V is the maximum voltage value that can be applied.

【0048】

On the other hand, in the present embodiment, since the bottom insulating film 11 is made of an FN tunnel nitride film, the energy barrier between the bottom insulating film 11 and silicon that the hot electrons should overcome is reduced from 3.2V to 2.1V as described above. ing. Therefore, the injection efficiency of hot electrons is increased, and the drain voltage for obtaining the same writing speed as the conventional one is reduced from 4.5V to 3.3V. By reducing the drain voltage, it is possible to suppress an increase in the drain current due to punch-through, and as a result, the gate length can be easily scaled. For example, in the past, a drain voltage of about 5 V was required to increase the writing speed to some extent, but at this time, the leak current was too large to achieve a gate length of 0.18 μm, as shown in Fig. 4. However, in the present embodiment, since the drain voltage can be set to 3.3 V, the leakage current is reduced to a practical range of 500 pA / μm or less, as can be read from the graph line of the gate length of 0.18 μm in FIG. That is, in the present embodiment, by forming the bottom insulating film 11 from the FN tunnel nitride film, the drain voltage can be lowered while the writing speed is maintained at a high speed of about 1 μs. Therefore, punch-through is less likely to occur, and there is an advantage that the length of the gate can be shortened accordingly. Although not described in detail here, in order to further scale the gate length, it is necessary to increase the channel impurity concentration in order to suppress the short channel effect in addition to reducing the leakage current.

【0049】

Further, in the present embodiment, the drain applied voltage at the time of writing is changed from the conventional 5V to the power supply voltage V._CCIt is reduced to (3.3V), and the write voltage can be reduced. Therefore, it is not necessary to boost the bit line by using a charge pump circuit at the time of writing, and the bit line precharge time is short, so that the writing operation cycle of one page can be shortened accordingly.

【0050】

In the present embodiment, the bottom insulating film 11 is a single layer of the FN tunnel nitride film, but in the present invention, the bottom insulating film is composed of a plurality of films, and the FN tunnel that reduces the energy barrier with silicon in the laminated film. By including the insulating film (dielectric film), the same effect as described above can be obtained.

【0051】

5 and 6 show a modified example of the memory transistor structure in this embodiment. The bottom insulating film 11 in the memory transistor shown in FIG. 5 compares the energy barrier with silicon on the first film 11c and the first film 11c having a relatively low energy barrier with silicon on the channel forming region. Although it is highly targeted, it consists of a second film 11d, which is effective for reducing the number of carrier traps in the first film 11c. Specifically, as the first film 11c, for example, NH₃Use RTN-SiON film. In the formation of this film, the surface of silicon is thermally oxidized to form a silicon oxide film, and the silicon oxide film is subjected to RTN treatment in an ammonia atmosphere. This NH₃The RTN treatment replaces the dangling bonds in the thermal oxide film with nitrogen, reducing the number of carrier traps to some extent. Further, as the second film 11d, for example, NH₃RTN-SiON film surface N₂N formed by reoxidation in O atmosphere₂O reoxidized SiO₂Use a membrane. In the process of this reoxidation, NH₃Hydrogen in the RTN-SiON membrane dissipates, resulting in a further reduction in the number of carrier traps in the membrane.

【0052】

The bottom insulating film 11 in the memory transistor shown in FIG. 6 compares the energy barrier with silicon on the first film 11c and the first film 11c having a relatively low energy barrier with silicon on the channel forming region. It consists of the second and third films 11e and 11f, which are high in target but have a small number of carrier traps. The third membrane 11f has a particularly small number of carrier traps, and the second membrane 11e is a thinly intervening membrane for the formation of the third membrane 11f. Specifically, as the first film 11c, for example, NH₃Use RTN-SiON film. Further, as the second film 11e, for example, a silicon nitride film (DCS-SiN film) formed by the LP-CVD method using DCS is used. Further, as the third film 11f, a silicon nitride film (TCS-SiN film) formed by the LP-CVD method using tetrachlorosilane (TCS) is used.

【0053】

Figures 7 and 8 show the FTIR spectra of DCS-SiN and TCS-SiN. In DCS-SiN, Si-H vibration (wave number: 2200 cm)^-1Near) and NH vibration (wave number: 3300 cm)^-1(Nearby) has been observed. On the other hand, in TCS-SiN, NH oscillation was observed, but Si-H oscillation was hardly observed.

【0054】

Figure 9 shows the results of calculating the bond density. When comparing TCS-SiN and DCS-SiN, it was found that the NH bond density was not so different, but the Si-H bond density was about an order of magnitude lower in the TCS system. Generally, the charge trap in the SiN film is formed from Si dangling bonds and has a positive correlation with the Si-H bond density. Therefore, it was found that TCS-SiN can be applied as a low trap nitride film.

【0055】

In the above modification, the bottom insulating film 11 is an insulating film suitable for hot carrier injection, which has a low energy barrier with silicon and a small number of carrier traps. As the bottom insulating film 11, in addition to the silicon nitride film, the silicon oxide film, and the above-mentioned modified examples, a tantalum oxide film, a zirconia oxide film, an aluminum oxide film, a titanium oxide film, a hafnium oxide film, and barium strontium titanium oxide ( BST: Ba_XSr_X-1TiO₃) Membrane or yttrium oxide film can be used alone or in combination.

【0056】

Second Embodiment The second embodiment relates to the deformation of the gate insulating film structure of the memory transistor in the virtual ground NOR type non-volatile memory device. Also in the second embodiment, the circuit diagram of FIG. 1 and the plan view of FIG. 2 can be applied as they are.

【0057】

FIG. 10 shows a cross-sectional view showing the memory transistor structure according to the second embodiment. The gate insulating film of this memory transistor is composed of a gate insulating film 10a on the sub-bit wire SBLi side and a gate insulating film 10b on the sub-bit wire SBLi + 1 side. Both gate insulating films 10a and 10b are spatially separated with a single-layer insulating film on the central portion of the channel. Both gate insulating films 10a and 10b each have a film structure similar to that of the gate insulating film 10 in the first embodiment. That is, the gate insulating film 10a is composed of a bottom insulating film 11a (FN tunnel nitride film), a nitride film 12a, and a top insulating film 13a in this order from the lower layer. Similarly, the gate insulating film 10b is composed of a bottom insulating film 11b (FN tunnel nitride film), a nitride film 12b, and a top insulating film 13b in this order from the lower layer. The bottom insulating film 11a, 11b, the nitride film 12a, 12b, and the top insulating film 13a, 13b have the same materials and thicknesses as those of the bottom insulating film 11, the nitride film 12, and the top insulating film 13 in the first embodiment, respectively. It is formed by the film forming method of.

【0058】

The insulating film 14 between the two gate insulating films 10a and 10b is made of, for example, a silicon oxide film formed by a CVD method, and is formed so as to embed between the two gate insulating films.

【0059】

The gate insulating film structure is formed by first forming a laminated film of a bottom insulating film (FN tunnel nitride film), a nitride film, and a top insulating film on the entire surface as in the first embodiment, and then on the central portion of the channel. A part of this laminated film is removed by etching. As a result, the gate insulating films 10a and 10b are spatially separated and formed. A silicon oxide film is thickly deposited on the entire surface, and etching back is performed from the surface of the silicon oxide film. Then, when the insulating film on the gate insulating films 10a and 10b is removed and the etchback is stopped when the space between the gate insulating films 10a and 10b is filled with the insulating film 14, the gate insulating film structure is completed. In order to prevent over-etching at the time of etching back, an etching stopper film, for example, a silicon nitride film may be thinly formed on the gate insulating films 10a and 10b in advance. After that, the memory transistor is completed through the process of forming the word line WL and the like in the same manner as in the first embodiment.

【0060】

The memory transistor can be written, read or erased in the same manner as in the first embodiment. That is, 3.2V is applied to one bit line to which the selected memory transistor to be written is connected, 0V is applied to the other bit line, 5V is applied to the selected word line, and 0V is applied to the other bit line and the non-selected word line. To do. As a result, electrons are electrically accelerated in the channel created by applying 3.3V between the source and drain of the selected memory transistor, which becomes hot electrons near the end of the horizontal channel, and a part of them is formed by the bottom insulating film 11a or 11b. It is injected into the carrier trap in the gate insulating film 10a or 10b across the energy barrier.

【0061】

Now, it is assumed that the gate insulating film 10a is written by such a method. When writing to the gate insulating film 10b on the opposite side, the applied voltage direction between the source and the drain is reversed from that at the time of writing, and other voltage conditions are the same. As a result, writing to the gate insulating film 10b is realized by the same principle.

【0062】

At the time of reading, a predetermined read-drain voltage is applied to the sub-source lines SSLi and SSLi + 1 with the side on which the charge to be read of the memory transistor is accumulated as the source and the other as the drain. Further, a predetermined read gate voltage is applied to the word line WL. As a result, a potential change corresponding to the threshold voltage of the memory transistor appears on the bit line on the drain side, and this is detected by the sense amplifier. When reading out the charge on the opposite side, the same reading can be performed by reversing the voltage application direction between the source and drain.

【0063】

In elimination, as in the first embodiment, hot hole injection due to withdrawal of charge from the entire channel or from the sub-bit line SBL side using FN tunneling or direct tunneling, or due to interband tunneling current. Erase using.

【0064】

Also in the second embodiment, since the bottom insulating films 11a and 11b are made of the FN tunnel nitride film, the same effect as that of the first embodiment can be obtained. That is, the energy barrier of the bottom insulating films 11a and 11b that the hot electrons (or hot holes) should overcome during writing (or erasing) is reduced as compared with the case where the bottom insulating film is formed from the conventional oxide film. The injection efficiency of hot electrons is increased, and the drain voltage for obtaining the same writing speed as before is reduced from 4.5V to 3.3V. Further, by reducing the drain voltage, an increase in the drain current due to punch-through can be suppressed, and as a result, the gate length can be easily scaled. Further, since the write voltage can be lowered, it is not necessary to boost the bit line by using a charge pump circuit at the time of writing, the bit line precharge time is short, and the write operation cycle can be shortened accordingly. Since 2 bits can be written in 1 memory cell, the effective memory cell area per bit is small.

【0065】

Also in the second embodiment, the modified examples (FIGS. 5 and 6) in the first embodiment can be similarly applied as the film structure of the gate insulating films 10a and 10b.

【0066】

Third Embodiment The third embodiment applies the FN tunnel low barrier technology to a transistor structure having a second gate electrode on the source and / or drain side, which is a so-called control gate.

【0067】

11 and 12 are circuit diagrams showing a configuration example of the memory cell array according to the third embodiment. This memory cell array is basically a virtual ground NOR type memory cell array similar to the first and second embodiments. However, in this memory cell array, each memory transistor is provided with a control gate so as to partially overlap the channel formation region from the source / drain impurity region side. Then, the memory transistors M11, M12, ..., which are connected in the bit direction, are the control line CL1a that connects one control gate in common, the control line CL1b that connects the other control gate in common, and the memory that belongs to the other row and is connected in the bit direction. A control line CL2a for connecting one control gate of the transistors M21, M22, ... In common, and a control line CL2b, ... for connecting the other control gate in common are provided. Each control line is controlled independently of the word line. In FIG. 11, each control line partially overlaps the channel formation region, so that a selection transistor having a MOS structure is formed on both sides of the central memory transistor. On the other hand, in FIG. 12, the center is a selection transistor having a MOS structure, and memory transistors having gates connected to control lines are formed on both sides of the selection transistors.

【0068】

13 and 14 show an example of the transistor structure according to the third embodiment. In the memory transistor shown in FIG. 13, the gate electrode 15 of the selected transistor is laminated in the central portion of the channel forming region via a gate insulating film 19 composed of a bottom insulating film 11, a nitride film 12, and a top insulating film 13 from the lower layer. There is. The gate electrode 15 is connected to an upper wiring layer forming a word line WL (not shown), and is commonly connected between memory cells in the word direction.

【0069】

The bottom insulating film 11 of the bottom layer of the gate insulating film 10 extends on the sub-bit lines SBLi, SBLi + 1 on both sides in the channel direction, and the control gate CG is formed on the extending portion of the bottom insulating film. .. The control gate CG and the gate electrode 15 are insulated and separated by a spacer insulating layer 16.

【0070】

In the formation of this memory transistor, for example, after forming the gate insulating film 10 and the conductive film to be the gate electrode on the entire surface, the top insulating film 13 and the nitrided two layers from the upper side of the gate insulating film 10 are nitrided at the time of patterning the gate electrode. The film 12 is processed in a batch. Next, this pattern is covered with an insulating film to be the spacer insulating layer 16 and then anisotropically etched. As a result, the spacer insulating layer 16 is formed on the side wall side of the gate electrode. A conductive film to be a control gate CG is deposited, and this conductive film is anisotropically etched to leave it in a sidewall shape, thereby forming a control gate CG.

【0071】

The transistor formed in this way is a so-called source-side injection operation memory transistor. Since this operation is known, details will not be described here, but during operation, the control gate CGs at both ends of the channel formation region function as gate electrodes of the selection transistor. However, in the present embodiment, the bottom insulating film of the bottom layer of the gate insulating film is formed of a dielectric film such as an FN tunnel nitride film that lowers the energy barrier with silicon, or has a multilayer structure including the dielectric film. Therefore, the same effect as that of the first embodiment is obtained, such as improvement of the injection efficiency of hot electrons.

【0072】

On the other hand, in the memory transistor shown in FIG. 14, the gate electrode structure itself is the same as that in FIG. That is, it has a gate electrode 15 formed on the central portion of the channel formation region and connected to the word line WL, and a control gate CG isolated from the gate electrode 15 and provided on both sides in the channel direction. However, unlike the case of FIG. 13, this memory transistor has a gate insulating film 10 formed between the control gate CG and the sub-bit line SBLi.SBLi + 1 or the end of the channel formation region. The gate electrode 15 is embedded via an insulating film 17 between two control gate CGs spatially separated on the source side and the drain side and a laminated pattern of the gate insulating film 10.

【0073】

In the formation of the memory transistor, for example, after forming the gate insulating film 10 and the conductive film to be the control gate CG on the entire surface, the gate insulating film 10 is collectively processed at the time of patterning the two control gate CGs. As a result, the sub-bit wire SBLi side and the sub-bit wire SBLi + 1 side are spatially separated to form a laminated pattern of the two control gate CG and the gate insulating film 10. After that, the insulating film 17 and the conductive film to be the gate electrode 15 are deposited on the entire surface, and these films are etched back. As a result, the insulating film 17 and the gate electrode 15 are formed so as to be embedded between the laminated patterns of the two control gate CGs and the gate insulating film 10.

【0074】

In the memory transistor formed in this way, a selective MOS transistor connected to the word line is formed in the central portion of the channel formation region. Further, high concentration regions (pocket regions) Pi and Pi + 1 of P-type impurities are formed at the opposite ends of the sub-bit lines SBLi and SBLi + 1. In the pocket region formed by this oblique ion implantation and the upper part of the diffusion layer, the control gate CG is arranged via the ONO film type gate insulating films 10a and 10b including the charge storage means. The combination of the selection gate 15 and the control gate CG is basically the same as that of the source side injection type memory cell having a split gate structure.

【0075】

The memory transistor of the present embodiment has a silicon nitride film and a silicon oxide nitride film exhibiting the FN tunneling characteristics shown in the first embodiment as the bottom insulating film 11 of the lowermost layer of the gate insulating film, as shown in FIGS. 5 and 6. Either a multilayer film or another dielectric film such as a tantalum oxide film may be used. Therefore, in the source side injection, the energy barrier on the conduction band side is reduced from 3.2 eV in the case of the oxide film, and the injection efficiency of hot electrons is improved. As the nitride film 12 on the bottom insulating film 11, a nitride film produced by the LP-CVD method using a gas in which DCS and ammonia are mixed is used as in the first embodiment.

【0076】

Selective gate MOS transistors are used to efficiently perform source-side injection during writing. Further, at the time of erasing, even if the charge storage means is excessively erased, it plays a role of keeping the threshold voltage Vth in the erased state of the memory transistor constant. Therefore, the threshold voltage of this selective gate MOS transistor is set between 0.5V and 1V.

【0077】

This memory transistor can be written, read or erased in the same manner as in the first embodiment. That is, 3.3V is applied to one bit line to which the selected memory transistor to be written is connected, 0V is applied to the other bit line, 5V is applied to the selected word line, and 0V is applied to the other bit line and the non-selected word line. To do. Also, the gate of the selective gate MOS transistor is biased to about 3V. As a result, 3.3V is applied between the source and drain of the selected memory transistor, and the selection gate in the center of the channel formation region is turned on, so that electrons are supplied into the channel from the sub-bit line side that is the source. The electric field is accelerated in the channel. The accelerated electrons become hot electrons near the end of the channel, and a part of them is injected into the carrier trap in the gate insulating film 10a or 10b over the energy barrier of the bottom insulating film 11a or 11b. In this case, the control gate CG optimizes the electric field under the charge storage means to optimize the balance between the generation efficiency of the source side hot electrons and the injection efficiency into the charge storage means. As a result, the hot electrons are efficiently injected from the source side into the charge storage means. In this source-side injection operation, the injection efficiency of hot electrons is improved by about 2 to 3 orders of magnitude as compared with the hot electron injection of the first embodiment.

【0078】

Now, it is assumed that the gate insulating film 10a is written by such a method. When writing to the gate insulating film 10b on the opposite side, the applied voltage direction between the source and the drain is reversed from that at the time of writing, and other voltage conditions are the same. As a result, writing to the gate insulating film 10b is realized by the same principle.

【0079】

In this writing, the writing time on one side of the memory cell is 1 μsec or less, which is extremely high, and the current required for writing can be reduced to 10 μA or less. When writing pages in this memory cell array, it is difficult to write all the memory cells connected to the same word line at the same time. Therefore, for example, the control gate CG is controlled to divide the memory cells in the same row into a plurality of memory cells. Then, the page is written by writing a plurality of times.

【0080】

At the time of reading, a predetermined read-drain voltage is applied to the sub-source lines SSLi and SSLi + 1 with the side on which the charge to be read of the memory transistor is accumulated as the source and the other as the drain. Further, a predetermined read gate voltage is applied to the word line WL. As a result, a potential change corresponding to the threshold voltage of the memory transistor appears on the bit line on the drain side, and this is detected by the sense amplifier. When reading out the charge on the opposite side, the same reading can be performed by reversing the voltage application direction between the source and drain.

【0081】

In elimination, as in the first embodiment, hot hole injection due to withdrawal of charge from the entire channel or from the sub-bit line SBL side using FN tunneling or direct tunneling, or due to interband tunneling current. Do it using.

【0082】

Also in the third embodiment, since the bottom insulating films 11a and 11b are made of the FN tunnel nitride film, the same effect as that of the first embodiment can be obtained. That is, the energy barrier of the bottom insulating films 11a and 11b that the hot electrons (or hot holes) should overcome during writing (or erasing) is reduced as compared with the case where the bottom insulating film is formed from the conventional oxide film. The injection efficiency of hot electrons is increased, and the drain voltage for obtaining the same writing speed as before is reduced from 4.5V to 3.3V. Further, by reducing the drain voltage, an increase in the drain current due to punch-through can be suppressed, and as a result, the gate length can be easily scaled. Further, since the write voltage can be lowered, it is not necessary to boost the bit line by using a charge pump circuit at the time of writing, the bit line precharge time is short, and the write operation cycle can be shortened accordingly. Since 2 bits are written to 1 memory cell, the memory cell area per bit can be reduced. In addition, it is possible to reduce the damage caused by hot carrier injection into the bottom insulating film.

【0083】

The following embodiments describe other memory cell array and memory transistor structures to which the present invention is applicable.

【0084】

Fourth Embodiment FIG. 15 is a circuit diagram of the NOR type memory cell array according to the fourth embodiment, FIG. 16 is a plan view of the memory cell array, and FIG. 17 is a cross-sectional side taken along the line B-B'of FIG. A bird's-eye view is shown.

【0085】

In this non-volatile memory device, the bit line (first common line) is layered into the main bit line (first main line) and the sub bit line (first sub line), and the source line (second common line) is the main source. It is layered into a line (second main line) and a sub source line (second sub line). The sub-bit line SBL1 is connected to the main bit line MBL1 via the selection transistor S11, and the sub-bit line SBL2 is connected to the main bit line MBL2 via the selection transistor S21. Further, the sub-source line SSL1 is connected to the main source line MSL1 via the selection transistor S12, and the sub-source line SSL2 is connected to the main source line MSL2 via the selection transistor S22.

【0086】

Memory transistors M11 to M1n (for example, n = 128) are connected in parallel between the sub-bit line SBL1 and the sub-source line SSL1, and memory transistors M21 to M2n are connected between the sub-bit line SBL2 and the sub-source line SSL2. Are connected in parallel. The n memory transistors connected in parallel to each other and two selection transistors (S11 and S12, or S21 and S22) form a unit block constituting the memory cell array.

【0087】

The gates of the memory transistors M11, M21, ... Adjacent to each other in the word direction are connected to the word line WL1. Similarly, the gates of the memory transistors M12, M22, ... Are connected to the word line WL2, and the gates of the memory transistors M1n, M2n, ... Are connected to the word line WLn. The selection transistors S11, ... Adjacent in the word direction are controlled by the selection line SG11, and the selection transistors S21, ... Are controlled by the selection line SG21. Similarly, the selection transistors S12, ... Adjacent in the word direction are controlled by the selection line SG12, and the selection transistors S22, ... Are controlled by the selection line SG22.

【0088】

In this NOR type cell array, as shown in FIG. 17, n-well W is formed on the surface of the semiconductor substrate SUB. The n-well W is insulated and separated in the word direction by an element separation insulating layer ISO in which an insulator is embedded in a trench and arranged in a parallel stripe shape.

【0089】

Element Separation Insulation Layer Each n-well portion separated by ISO becomes the active region of the memory transistor. High concentrations of p-type impurities are introduced in parallel stripes on both sides of the active region in the width direction, thereby causing sub-bit lines SBL1, SBL2 (hereinafter referred to as SBL) and sub-source lines SSL1. , SSL2 (hereinafter referred to as SSL) is formed. Each word line WL1, WL2, WL3, WL4, ... (hereinafter referred to as WL) is wired at equal intervals on the sub-bit line SBL and the sub-source line SSL via an insulating film. These word line WLs are in contact with each other on the n-well W and the element separation insulating layer ISO via an insulating film containing a charge storage means inside. The intersection of the n-well W part between the sub-bit line SBL and the sub-source line SSL and each word line WL becomes the channel formation area of the memory transistor, and the sub-bit line part in contact with the channel formation area is the drain. The sub-source line part functions as the source.

【0090】

The upper surface and side walls of the word line WL are covered with an offset insulating layer and a sidewall insulating layer (in this example, a normal interlayer insulating layer is also possible). In these insulating layers, a bit contact BC that reaches the sub-bit line SBL and a source contact SC that reaches the sub-source line SSL are formed at predetermined intervals. These contacts BC and SC are provided for every 128 memory transistors in the bit direction, for example. Further, on the insulating layer, the main bit wires MBL1, BL2, ... in contact with the bit contact BC and the main source wires MSL1, BL2, ... in contact with the source contact SC are alternately arranged in a parallel stripe shape. Is formed in.

【0091】

In this NOR type cell array, the first common line (bit line) and the second common line (source line) are layered, and it is not necessary to form a bit contact BC and a source contact SC for each memory cell. Therefore, there is basically no variation in the contact resistance itself. The bit contact BC and the source contact SC are provided for every 128 memory cells, for example, but the offset insulating layer and the sidewall insulating layer are not required when the plug formation at this time is not performed in a self-aligned manner. That is, after a normal interlayer insulating film is thickly deposited and a memory transistor is embedded, the contact is opened by normal photolithography and etching.

【0092】

Since there is almost no wasted space as a pseudo contactless structure in which the sub lines (sub bit lines, sub source lines) are composed of impurity regions, when each layer is formed with the minimum line width F of the wafer process limit, it is 8F.² It can be manufactured with a very small cell area close to. Further, the bit line and the source line are layered, and the selection transistor S11 or S21 separates the parallel memory transistor group in the non-selected unit block from the main bit line MBL1 or MBL2, so that the capacity of the main bit line is significantly reduced. It is advantageous for high speed and low power consumption. Further, by the action of the selection transistor S12 or S22, the sub-source line can be separated from the main source line to reduce the capacitance. In order to further increase the speed, it is preferable to form the sub-bit line SBL and the sub-source line SSL in the impurity region to which the silicide is attached, and to use the main bit line MBL and the main source line MSL as metal wiring.

【0093】

In the fourth embodiment, as will be described later, the writing is performed by hot electron injection caused by the interband tunnel current. Therefore, each memory cell is composed of a p-channel MONOS type memory transistor. The memory transistor structure itself is the same as in FIG. 3 (or FIGS. 5, 6) according to the first embodiment. However, the conductive type of the impurities introduced into the well W and the sub-bit wires SBLi and SBLi + 1 is opposite to that of the first embodiment. Further, in relation to the memory cell array structure, in this memory transistor, a source impurity region and a drain impurity region (secondary bit line SBLi, SBLi + 1) are formed on both sides in the width direction of the word line WL. Similar to the first embodiment, the bottom insulating film 11 in the present embodiment also has other components such as a silicon nitride film exhibiting FN tunneling characteristics, a silicon oxide nitride film, a multilayer film shown in FIGS. 5 and 6, and a tantalum oxide film. Any of the dielectric films may be used.

【0094】

Further, in the formation of the memory cell array, a p-type impurity region serving as a sub-bit wire is formed in the well W by the same method as in the first embodiment, the gate insulating film 10 is formed, and then the gate electrode (word wire) is formed. A laminated film of a conductive film to be a WL) and an offset insulating layer (not shown) is laminated, and the laminated film is collectively processed in the same pattern. Subsequently, in order to obtain the memory cell array structure of FIG. 17, a self-aligned contact is formed together with the sidewall insulating layer, and the bit contact BC and the source are formed on the sub-bit line SBL and the sub-source line SSL expressed by the self-aligned contact. Form contact SC. After that, the periphery of these plugs is embedded with an interlayer insulating film, the main bit wire MBL and the main source wire MSL are formed on the interlayer insulating film, and then the upper layer wiring and overcoat formation via the interlayer insulating layer are performed as necessary. The non-volatile memory cell array is completed through a film and pad opening step and the like.

【0095】

Next, an example of bias setting and operation at the time of writing to the non-volatile memory having such a configuration will be described by taking the case of writing data to the memory transistor M11 as an example.

【0096】

At the time of writing, the program voltage is applied after setting the writing intrinsic voltage as necessary. For example, with the selected word line WL1 open, the substrate potential set to 0V, and the selected main source line MSL1 open, apply, for example, -4V to the selected main bit line MBL1.

【0097】

Under this writing condition, an n-type inversion layer is formed on the surface of the p-type impurity region forming the sub-bit line SBL1, and a voltage between the gate and the drain is applied to this inversion layer, so that the energy band bends in this portion. Inter-band tunnel currents are easily generated as they increase and reduce the effective bandgap. The interband tunnel current is accelerated by the voltage between the gate and drain to obtain high energy and become hot electrons. When the momentum (magnitude and direction) of the hot electron is maintained and the energy is higher than the energy barrier of the bottom insulating film 11, the hot electron crosses the energy barrier of the bottom insulating film 11 and is a carrier trap (charge) in the nitride film 12. It is injected into the storage means). In writing using this interband tunnel current, since the generation of hot electrons is limited to the sub-bit line SBL1, the electric charge is applied to the local part (first region) of the charge storage means centered on the upper side of the sub-bit line SBL1. Is injected.

【0098】

In the present embodiment, since the bottom insulating film 11 is formed from the FN tunnel nitride film, the energy barrier that the hot electrons jump over during this writing is reduced from the conventional 3.2V to about 2.1V, and as a result, the hotness is high. Electron injection efficiency can be obtained. Further, if the selected cell to be written and the non-selected cell to be prohibited from writing are set by the bias condition, the cells connected to the word line WL1 can be written on the page at once. However, in the present embodiment, the injection efficiency is improved as described above. The write current per bit is orders of magnitude smaller, and as a result, the number of cells that can be written in parallel can be increased.

【0099】

In reading, the bias value is changed to the extent that a channel is formed according to the writing state. For example, with the sub-bit line SBL1 grounded, a negative voltage of -1.5V is applied to the sub-source line SSL1 and a read-out word line voltage of -2V is applied to the word line WL1. As a result, in the case of page reading performed on the memory transistors M11, M21, ... Connected to the selected word line WL1, the channel is changed in the erased memory transistor in which electrons are not injected into the first region of the charge storage means. No channel is formed in the written memory transistor that is formed and has electrons injected into the first region of the charge storage means. Therefore, in the main bit lines MBL1, MBL2, ..., the potential change appears depending on the presence or absence of the channel formation. When this potential change is detected by the sense amplifier, the stored data in the page is collectively read out.

【0100】

Erasing is performed by extracting charges from the entire channel or from the sub-bit line SBL1 side using FN tunneling or direct tunneling. For example, when the electrons held in the charge storage means are extracted directly from the entire channel by tunneling, the voltage of -5V for the word line WL, 5V for the main bit line MBL1, the main source line MSL1 is open, and the voltage of 5V for the n-well W. Is applied. As a result, the electrons held in the first region of the charge storage means are drawn out to the substrate side, so that the cells are erased. At this time, the erasing speed was about 1 msec.

【0101】

Similar to the case of FIG. 3, after writing to the first region of the charge storage means by the same method as in the first embodiment, the same writing is performed to the sub source line SSL side. In this second write, the applied voltages of the source and drain are reversed from the first. That is, 4V is applied to the selected word line WL and 0V is applied to the substrate potential, and -4V is applied to the sub source line SSL with the sub bit line SBL open. As a result, as in the first time, hot electrons caused by the interband tunnel current are injected into the area (second area) on the side of the secondary source line SSL of the charge storage means.

【0102】

As a result, in the cell in which both bits are written, hot electrons are injected and held in the first region of the charge storage means, and independently of this, hot electrons are injected and held in the second region. That is, since a third region in which hot electrons are not injected is interposed between the first region and the second region of the charge storage means, the electrons corresponding to this 2-bit information are surely distinguished.

【0103】

The reading is performed by reversing the voltage direction between the source and the drain depending on whether the binary data corresponding to the accumulated charge in the first region is read or the binary data corresponding to the accumulated charge in the second region is read. As a result, 2-bit data can be read independently. Erasing is also performed by reversing the above-mentioned erasing on the first region side and the applied voltages of the source and drain (sub-bit line SBL and sub-source line SSL). When erasing the entire channel, the data on the first area side and the data on the second area side are erased at once.

【0104】

Next, the current-voltage characteristics of the memory transistor in the write state and the erase state were examined. As a result, the off-leakage current value from the non-selected cell at the drain voltage of 1.5 V was about 1 nA. Since the read current in this case is 10 μA or more, erroneous read of the non-selected cell does not occur. Therefore, it was found that the MONOS type memory transistor with a gate length of 0.18 μm has a sufficient margin of punch-through withstand voltage at the time of reading. We also evaluated the read-disturbing characteristics at a gate voltage of 1.5V, which was 3x10.⁸It was found that reading is possible even after a lapse of more than sec.

【0105】

The number of data rewrites is good because the carrier traps are spatially discretized, 1x10.⁶It turned out to be satisfied with the times. In addition, the data retention characteristics are 1 x 10⁶After rewriting the data once, I was satisfied with 85 ° C for 10 years.

【0106】

From the above, it was confirmed that sufficient characteristics were obtained as a MONOS type non-volatile memory transistor with a gate length of 0.18 μm. Further, by forming the bottom insulating film 11 with an FN tunnel nitride film, it becomes easy to realize or improve the characteristics of a MONOS type non-volatile memory transistor having a gate length of 0.13 μm.

【0107】

Also in the fourth embodiment, since the bottom insulating film 11 is made of an FN tunnel nitride film or the like, the same effect as that of the first embodiment can be obtained. That is, the energy barrier of the bottom insulating film 11 that the hot electrons (or hot holes) should overcome during writing (or erasing) is reduced as compared with the case where the bottom insulating film is formed from the conventional oxide film, and therefore the hot electrons are reduced. The injection efficiency is increased, and the drain voltage for obtaining the same writing speed as before is reduced from 4.5V to 3.3V. Further, by reducing the drain voltage, an increase in the drain current due to punch-through can be suppressed, and as a result, the gate length can be easily scaled. Further, since the write voltage can be lowered, it is not necessary to boost the bit line by using a charge pump circuit at the time of writing, the bit line precharge time is short, and the write operation cycle can be shortened accordingly. Since 2 bits can be written in 1 memory cell, the effective memory cell area per bit is small. By reducing the drain voltage, damage to the bottom insulating film from hot electrons can be reduced.

【0108】

In the NOR type memory cell array according to the fourth embodiment, each memory cell may be a three-transistor type having a cross section of FIG. 13 or FIG.

【0109】

Fifth Embodiment FIG. 18 shows a cross-sectional view of the memory transistor according to the fifth embodiment. In the gate insulating film 20 of this memory transistor, the bottom insulating film 21 is thickly deposited, and the intermediate nitride film 12 in the first embodiment is omitted. The bottom insulating film 21 is formed in the same manner as in the first embodiment. The initial film thickness of the bottom insulating film 21 after film formation is set to, for example, 6 nm, and the surface thereof is thermally oxidized to form the top insulating film 13. The gate insulating film 20 (film thickness specification: bottom insulating film / top insulating film = 3.8 / 3.5 nm) formed in this way has a silicon oxide film equivalent value of 5.4 nm, and the effective film thickness is further reduced. Other configurations and forming methods are the same as those in the first embodiment. Further, the basic operations of writing, reading, and erasing are the same as those of the first embodiment. Before the bottom insulating film 21 is deposited, a thin buffer oxide film may be formed on the silicon surface for the purpose of reducing the interface state of the silicon surface in the channel forming region.

【0110】

In the present embodiment, the bottom insulating film 21 is thickly deposited and the top insulating film 13 is directly formed on the bottom insulating film 21, so that all the nitride films are FN tunnel nitride films. Since the number of carrier traps in the FN tunnel nitride film is relatively small, the carriers near the interface between the nitride film (bottom insulating film 21) and the oxide film (top insulating film 13) are deeper than in the case of the first embodiment. The trap can be effectively used for charge storage. As a result, the effective film thickness of the gate insulating film 20 is reduced, and it becomes possible to further reduce the voltage.

【0111】

6th Embodiment A sixth embodiment is a non-volatile semiconductor storage device (hereinafter, Si) using a large number of mutually insulated Si nanocrystals embedded in a gate insulating film as a charge storage means for a memory transistor and having a particle size of, for example, 10 nanometers or less. (Nanocrystal type).

【0112】

FIG. 19 is a cross-sectional view showing the element structure of the Si nanocrystal type memory transistor. In the Si nanocrystal non-volatile memory of the present embodiment, the gate insulating film 30 is composed of a bottom insulating film 31, a Si nanocrystal 32 as a charge storage means on the bottom insulating film 31, and an oxide film 33 covering the Si nanocrystal 32. Become. Other configurations, that is, the semiconductor substrate SUB, the channel formation region, the well W, the sub-source line SSL (source impurity region), the sub-bit line SBL (drain impurity region, and the source / drain impurity region), and the word line WL are the first. 1 Same as the embodiment.

【0113】

The size (diameter) of the Si nanocrystals 32 is preferably 10 nm or less, for example, about 4.0 nm, and individual Si nanocrystals are spatially separated by an oxide film 33 at intervals of, for example, about 4 nm. .. The bottom insulating film 31 in this example is slightly thicker than the first embodiment because the charge storage means (Si nanocrystal 32) is closer to the substrate side, and ranges from 2.6 nm to 5.0 nm depending on the intended use. Can be selected as appropriate within. Here, the film thickness was set to about 4.0 nm.

【0114】

In the manufacture of a memory transistor having such a configuration, after the bottom insulating film 31 is formed, a plurality of Si nanocrystals 32 are formed on the bottom insulating film 31 by, for example, the LP-CVD method. Further, the oxide film 33 is formed by LP-CVD, for example, about 7 nm so as to embed the Si nanocrystal 32. In this LP-CVD, the raw material gases are DCS and N.₂ It is assumed that the mixed gas of O and the substrate temperature are, for example, 700 ° C. At this time, the Si nanocrystal 32 is embedded in the oxide film 33, and the surface of the oxide film 33 is flattened. If the flattening is insufficient, a new flattening process (for example, CMP) may be performed. After that, a conductive film to be a word line is formed, and the gate laminated film is collectively patterned to complete the Si nanocrystal type memory transistor.

【0115】

The Si nanocrystals 32 thus formed function as carrier traps discretized in the plane direction. The trap level can be estimated by the band discontinuity value with the surrounding silicon oxide, and the estimated value is about 3.2 eV. Individual Si nanocrystals 32 of this size can hold several injected electrons. The Si nanocrystal 32 may be made smaller to hold a single electron.

【0116】

The data retention characteristics of the Si nanocrystalline non-volatile memory having such a configuration were examined by the back tunneling model of Landkist. In order to improve the data retention characteristics, it is important to deepen the trap level and increase the distance between the center of gravity of the charge and the semiconductor substrate. Therefore, we examined data retention at trap level 3.2 eV by simulation using the Landquist model as the physical model. As a result, it was found that by using a deep carrier trap with a trap level of 3.2 eV, good data retention is exhibited even when the distance from the charge retention medium to the channel formation region is relatively close to 4.0 nm.

【0117】

Seventh Embodiment A seventh embodiment relates to a non-volatile semiconductor storage device (hereinafter, referred to as a finely divided FG type) using a large number of finely divided floating gates embedded in an insulating film and separated from each other as a charge storage means of a memory transistor.

【0118】

FIG. 20 is a cross-sectional view showing the element structure of the finely divided FG type memory transistor. In the finely divided FG type non-volatile memory of the present embodiment, a memory transistor is formed on an SOI substrate, and the gate insulating film 40 thereof is a bottom insulating film 41, a finely divided floating gate 42 as a charge storage means on the bottom insulating film 41, and a finely divided floating gate 42. It is composed of an oxide film 43 in which a finely divided floating gate 42 is embedded. The finely divided floating gate 42, together with the Si nanocrystal 22 of the sixth embodiment, corresponds to a specific example of the small particle size conductor in the present invention.

【0119】

As an SOI substrate, a SIMOX (Separation by Implanted Oxygen) substrate in which oxygen ions are implanted into a silicon substrate at a high concentration to form an oxide film embedded deeper than the substrate surface, or an oxide film is formed on the surface of one of the silicon substrates. A bonded substrate or the like that is bonded to another substrate is used. The SOI substrate formed by such a method and shown in FIG. 20 is composed of a semiconductor substrate SUB, a separation oxide film 44, and a silicon layer 45, and in the silicon layer 45, a sub-source line SSL (source impurity region S), A sub-bit line SBL (drain impurity region D) is provided. The channel formation region is between the two impurity regions. A glass substrate, a plastic substrate, a sapphire substrate, or the like may be used instead of the semiconductor substrate SUB.

【0120】

The finely divided floating gate 42 is a normal FG type floating gate processed into fine poly Si dots having a height of, for example, about 5.0 nm and a diameter of, for example, up to 8 nm. The bottom insulating film 41 in this example is slightly thicker than that of the first embodiment, but is formed to be much thinner than the normal FG type, and can be appropriately selected within the range of 2.5 nm to 4.0 nm depending on the intended use. Here, the thinnest film thickness is 2.5 nm.

【0121】

In the manufacture of a memory transistor having such a configuration, after the bottom insulating film 41 is formed on the SOI substrate, a polysilicon film (final film thickness: 5 nm) is formed on the bottom insulating film 41 by, for example, the LP-CVD method. A film is formed. In this LP-CVD, the raw material gas is a mixed gas of DCS and ammonia, and the substrate temperature is, for example, 650 ° C. Next, the polysilicon film is processed into fine poly Si dots having a diameter of, for example, up to 8 nm by using, for example, an electron beam exposure method. The poly-Si dots function as a finely divided floating gate 42 (charge storage means). After that, the oxide film 43 is formed by LP-CVD, for example, about 9 nm so as to embed the finely divided floating gate 42. In this LP-CVD, the raw material gases are DCS and N.₂ It is assumed that the mixed gas of O and the substrate temperature are, for example, 700 ° C. At this time, the finely divided floating gate 42 is embedded in the oxide film 43, and the surface of the oxide film 43 is flattened. If the flattening is insufficient, a new flattening process (for example, CMP) may be performed. After that, a conductive film to be a word line WL is formed, and the gate laminated film is collectively patterned to complete the finely divided FG type memory transistor.

【0122】

Regarding the fact that the floating gate is finely divided using the SOI substrate in this way, as a result of trial production of the element and evaluation of the characteristics, it was confirmed that good characteristics as expected can be obtained.

【0123】

Modification example In the first to seventh embodiments described above, various modifications as described below are possible in addition to those specified in each embodiment.

【0124】

In the above embodiment, only the channel hot electron injection method including the hot electron injection method due to the interband tunnel current and the source side injection method is shown as the hot electron injection method at the time of writing. In the present invention, in addition, a ballistic hot electron injection method in which electrons travel in a ballistic manner in a channel, a secondary impact ionization hot electron injection method, or a substrate hot electron injection method can be adopted.

【0125】

Further, the present invention can be applied to other NOR type cells such as DINOR type (not shown), and further to AND type cells. The present invention is applicable not only to a stand-alone type non-volatile memory but also to an embedded type non-volatile memory integrated on the same substrate as a logic circuit.

【0126】

[Effect of the invention]

According to the non-volatile semiconductor storage device and the operation method thereof according to the present invention, the bottom insulating film is composed of a dielectric film that reduces the energy barrier with silicon, or is composed of a multilayer film containing the dielectric film. Therefore, the energy barrier that the charge should jump over during hot electron injection is reduced, and the injection efficiency is improved. Therefore, in addition to increasing the writing speed, there is room for reducing the drain voltage, and as a result, punch-through is less likely to occur, and the gate length can be easily shortened. Further, by reducing the drain voltage, the bit line charging time can be shortened, and the write cycle can be shortened accordingly. On the other hand, since the effective film thickness of the gate insulating film can be reduced by the amount that the bottom insulating film thickness can be reduced, it becomes easy to reduce the gate applied voltage. When the drain voltage is reduced, the damage to the bottom insulating film is reduced and the reliability is improved. Further, if the charge is locally stored separately on the source side and the drain side of the charge storage means, it is possible to store a plurality of bits of data in one memory cell.

[Simple explanation of drawings]

[Figure 1]

It is a circuit diagram which shows the virtual grounded NOR type memory cell array configuration of the non-volatile memory apparatus which concerns on 1st and 2nd Embodiment.

[Figure 2]

It is a top view of the virtual ground NOR type memory cell array which concerns on 1st to 3rd Embodiment.

[Fig. 3]

It is sectional drawing of the memory transistor which concerns on 1st to 3rd Embodiment.

[Fig. 4]

It is a graph which shows the gate length dependence of the punch-through characteristic about the conventional MONOS type memory transistor used for explaining the effect of the memory transistor which concerns on 1st Embodiment.

[Fig. 5]

It is sectional drawing which shows the 1st modification of the gate insulating film structure of the memory transistor which concerns on 1st to 4th Embodiment.

[Fig. 6]

It is sectional drawing which shows the 1st modification of the gate insulating film structure of the memory transistor which concerns on 1st to 4th Embodiment.

[Fig. 7]

It is a graph which shows the FTIR spectrum of DCS-SiN about the modification of the gate insulating film structure of the memory transistor which concerns on 1st to 4th Embodiment.

[Fig. 8]

It is a graph which shows the FTIR spectrum of TCS-SiN about the modification of the gate insulating film structure of the memory transistor which concerns on 1st to 4th Embodiment.

[Fig. 9]

It is a table which compares and shows the bond density of DCS-SiN and TCS-SiN about the modification of the gate insulating film structure of the memory transistor which concerns on 1st to 4th Embodiment.

[Fig. 10]

It is sectional drawing of the memory transistor which concerns on 2nd Embodiment.

[Fig. 11]

It is an equivalent circuit diagram which shows the 1st configuration example of the virtual ground NOR type memory cell array which concerns on 3rd Embodiment.

[Fig. 12]

It is an equivalent circuit diagram which shows the 2nd configuration example of the virtual ground NOR type memory cell array which concerns on 3rd Embodiment.

[Fig. 13]

It is sectional drawing which shows the 1st structure of the memory transistor which concerns on 3rd Embodiment.

[Fig. 14]

It is sectional drawing which shows the 2nd structure of the memory transistor which concerns on 3rd Embodiment.

[Fig. 15]

It is a circuit diagram which shows the NOR type memory cell array structure which concerns on 4th Embodiment.

[Fig. 16]

It is a top view of the NOR type memory cell array which concerns on 4th Embodiment.

[Fig. 17]

FIG. 5 is a bird's-eye view of the NOR type memory cell array according to the fourth embodiment as viewed from the cross-sectional side along the B-B'line of FIG.

[Fig. 18]

It is sectional drawing of the MNOS type memory transistor which concerns on 5th Embodiment.

[Fig. 19]

It is sectional drawing of the nanocrystal type memory transistor which concerns on 6th Embodiment.

[Fig. 20]

It is sectional drawing of the nanocrystal type memory transistor which concerns on 7th Embodiment.

[Explanation of symbols]

10,10a, 10b, 20,30,40 ... Gate insulating film, 11,11a, 11b, 21,31,41 ... Bottom insulating film, 11c ..., 11d ..., 11e ... , 11f ..., 12 ... nitride film, 13 ... top insulating film, 15 ... gate electrode, 16 ... spacer insulating layer, 17 ... insulating film, 32 ... Si nanocrystal , 33,43 ... oxide film, 42 ... poly Si dot, 44 ... separation oxide film, 45 ... silicon layer, SUB ... semiconductor substrate, W ... well, ISO ... Element separation insulating layer, M11 etc ... Memory transistor, S11 etc ... Selective transistor, BL1 etc ... Bit wire, MBL1 etc ... Main bit wire, SBL1 etc ... Sub bit wire, SL1 etc. .. Source line, MSL ... Main source line, SSL1 etc ... Secondary source line, WL1 etc ... Word line, SG11 etc ... Select gate line, CL1a, CL1b etc ... Control line, BC ... bit contact, SC ... source contact.