Data latch circuit and electronic device

[Technical field] [0001] The present invention relates to a data latch circuit that captures digital signals. The present invention also relates to an active matrix type display device using the data latch circuit as a part of a drive circuit. The present invention also relates to an electronic device using the active matrix type display device. [Background technology] [0002] In recent years, active matrix type display devices such as liquid crystal display devices and light emitting devices have been developed due to an increase in demand for mobile devices and the like. In particular, a pixel circuit and a drive circuit (hereinafter collectively referred to as "internal circuit") are integrated by using a thin film transistor (TFT) formed of polycrystalline semiconductor (poly-Si) on an insulator. The forming technology is being actively developed. The internal circuit has a source signal line drive circuit, a gate signal line drive circuit, and the like, and these drive circuits and the like control pixel circuits arranged in a matrix. [0003] The internal circuit is FPC (Flexible Printed). It is connected to a controller IC or the like (hereinafter referred to as an "external circuit") via a Circuit) or the like, and its operation is controlled. Generally, the drive voltage of an IC used in an external circuit (that is, the amplitude of a signal) is smaller than the drive voltage of an internal circuit from the viewpoint of reducing power consumption. At present, ICs that operate at a voltage of 3.3V are generally used for external circuits, but the operating voltage of internal circuits is about 10V, which is higher than that of external circuits. Therefore, when a 3.3V signal is input from an external circuit to an internal circuit, it is necessary to convert the amplitude of the signal to about 10V by a level shift circuit or the like. [0004] However, when the level is shifted in the external circuit, problems such as an increase in parts such as a level shift IC and a power supply IC and an increase in power consumption occur. On the other hand, when the level is shifted before being input to the shift register or the data latch circuit in the internal circuit, problems such as an increase in layout area, an increase in power consumption, and difficulty in high frequency operation occur. Therefore, there is a demand for a method in which a low-voltage amplitude signal from an external circuit is directly input to a shift register, a data latch circuit, or the like that constitutes a drive circuit of an internal circuit to operate accurately (hereinafter, this method is used. It is referred to as "low voltage drive"). [0005] There are a digital drive system and an analog drive system as a drive method in the active matrix type display device. When the digital drive system is used, a data latch circuit that sequentially captures digital video signals by sampling pulses from the shift register is required in the source signal line drive circuit that constitutes the internal circuit. [0006] Some data latch circuits consider low-voltage signal input (see Patent Document 1 below). [0007] However, a data latch circuit that supports low-voltage signal input may malfunction due to the effects of variations in various TFT characteristics. Here, a general conventional data latch circuit is shown in FIG. 2 (A). The data latch circuit has a clocked inverter 2005 and an inverter 2006, and the clocked inverter 2005 has P-type TFT 2001 and 2002 and N-type TFT 2003 and 2004 connected in series. A sampling pulse (LAT) from the shift register is input to the gate electrode of the P-type TFT 2001, and the source electrode has a connection structure such that power supply VDD is supplied. A sampling pulse (LAT) inversion pulse (LATB) is input to the gate electrode of the N-type TFT2004, and the source electrode has a connection structure such that power supply VSS is supplied. A digital signal (DATA) is input to the gate electrodes of the P-type TFT2002 and the N-type TFT2003. Further, the drain electrodes of the P-type TFT2002 and the N-type TFT2003 are connected to the inverter 2006. [0008] FIG. 2 (B) shows a timing chart of the conventional data latch circuit of FIG. 2 (A). The operation of the conventional data latch circuit will be described with reference to FIGS. 2 (A) and 2 (B). The input digital signal (hereinafter referred to as "data signal") is in a digital format and is a signal having a potential expressing "1" and a potential expressing "0". In the present specification, in any case, the potential level expressing "1" is referred to as "H level" and the potential level expressing "0" is referred to as "L level" regardless of the potential. Unless otherwise specified, the high and low potentials shall be L level <H level. [0009] First, in the period T1, the L level sampling pulse (LAT) is input from the shift register, LAT becomes the L level, LATB becomes the H level, and P-type TFT 2001 and N-type TFT 2004 are turned on. At this time, if DATA is at H level, P-type TFT2002 is off and N-type TFT2003 is on, and the clocked inverter 2005 outputs VSS. Conversely, when DATA is at the L level, the P-type TFT2002 is on and the N-type TFT2003 is off, and the clocked inverter 2005 outputs VDD. [0010] [Patent Document 1] Japanese Unexamined Patent Publication No. 11-184440 [Disclosure of Invention] [Problems to be Solved by the Invention] [0011] In the conventional data latch circuit, a case where a low voltage drive is performed, that is, a case where a digital signal DATA from an external circuit is input as it is will be described with reference to FIGS. 2 (A) and 2 (B). Here, VSS is -2V, VDD is 5V, H level of LAT and LATB is 5V, L level is -2V, H level of DATA is 3V, and L level is 0V. [0012] First, in the period T1, the sampling pulse and LAT are input from the shift register, LAT becomes H level (5V), LATB becomes L level (-2V), and P-type TFT2001 and N-type TFT2004 are turned on. At this time, if DATA is H level (3V), P-type TFT2002 is off and N-type TFT2003 is on, and the clocked inverter 2005 outputs VSS. However, at this time, the threshold voltage of P-type TFT2002 | V_THIf | is 2V or less, P-type TFT2002 is also turned on and leak current flows. [0013] Furthermore, various characteristics of P-type TFT2002 and N-type TFT2003, especially threshold characteristics, vary, and as a result, | V of P-type TFT2002._gsThe on-current at | = 2V is | V of N-type TFT2003._gsIf the on-current at | = 5V is exceeded, the logic is reversed, and the output of the clocked inverter 2005 becomes VDD instead of VSS. [0014] On the contrary, when DATA is L level (0V), | V of N type TFT2003_THIf | is 2V or less, N-type TFT2003 will also turn on and leak current will flow, and further, | V of N-type TFT2003 will flow._gsThe on-current at | = 2V is | V of P-type TFT2002._gsIf the on-current at | = 5V is exceeded, the logic is reversed, and the output of the clocked inverter 2005 becomes VSS instead of VDD. [0015] The present invention has been made in view of the above problems, and an object of the present invention is to provide a data latch circuit capable of low power consumption and high frequency operation, which is not easily affected by variations in TFT characteristics. [Means for solving problems] [0016] The present invention has means for short-circuiting the input terminal and the output terminal of the inverter in the data latch circuit for determining whether the data signal is at the H level or the L level, and the inverter. Is connected to one electrode of the capacitance, and the other electrode of the capacitance is configured to capture a data signal or a reference potential. First, by short-circuiting the input terminal and the output terminal of the inverter, the input terminal of the inverter and one electrode of the capacitance are set to the threshold potential of the inverter, and at the same time, the other electrode of the capacitance is set to the reference potential. Keep it. Next, the data signal is taken into one of the electrodes of the capacitance set to the reference potential. As a result, the potential of the input terminal of the inverter via the capacitance fluctuates up and down from the threshold potential, and the H level or L level of the data signal can be discriminated. [0017] Therefore, even if the amplitude of the data signal is small with respect to the power supply voltage width, it can operate accurately without being affected by the variation in the characteristics of the TFT. [0018] Here, the configuration of the present invention will be described below. The data latch circuit of the present invention is a data latch circuit that captures a digital signal, and is a capacitance means having first and second electrodes, an inverter having an input terminal connected to the first electrode, and the inverter. It has a switch connected between the input terminal and the output terminal, and during the reset period, the switch is turned on, and the first potential is input to the second electrode of the capacitance means to perform the reset. In the uptake period after the period, the digital signal is input to the second electrode of the capacitive means. [0019] Further, the data latch circuit of the present invention is a data latch circuit that captures a digital signal, and includes a capacitive means having first and second electrodes, an inverter having an input terminal connected to the first electrode, and the above. It has a first switch connected between the input terminal and the output terminal of the inverter, and a second switch and a third switch connected to the second electrode. By turning on the switch 1 and turning on the second switch, the first potential is input to the second electrode of the capacitance means, and in the uptake period after the reset period, the third switch A data latch circuit characterized in that the digital signal is input to the second electrode of the capacitance means by turning on. [0020] Further, the data latch circuit of the present invention is a data latch circuit that captures a digital signal, and is a capacitance means having first and second electrodes and a first inverter in which an input terminal is connected to the first electrode. A switch connected between the input terminal and the output terminal of the first inverter, a second inverter having an input terminal connected to the output terminal of the first inverter, and the second inverter. It has a clocked inverter in which an output terminal and an input terminal are connected to the input terminal and the output terminal of the inverter, respectively, and during the reset period, the switch is turned on and the first electrode of the capacitance means is connected to the second electrode. The digital signal is input to the second electrode of the capacitive means in the uptake period after the reset period. [0021] [0021] Further, a data latch circuit that captures a digital signal, that is, a capacitance means having first and second electrodes, a first inverter having an input terminal connected to the first electrode, and the first inverter. Input to the output terminal of the first switch connected between the input terminal and the output terminal, the second switch and the third switch connected to the second electrode, and the output terminal of the first inverter. It has a second inverter to which terminals are connected and a clocked inverter in which an output terminal and an input terminal are connected to the input terminal and the output terminal of the second inverter, respectively, and during the reset period, the first By turning on the switch and turning on the second switch, the first potential is input to the second electrode of the capacitance means, and the third switch is turned on in the uptake period after the reset period. The digital signal is input to the second electrode of the capacitance means. [0022] Further, the data latch circuit of the present invention is a data latch circuit that captures a digital signal, and is a capacitance means having first and second electrodes and a first inverter in which an input terminal is connected to the first electrode. A switch connected between the input terminal and the output terminal of the first inverter, a second inverter having an input terminal connected to the output terminal of the first inverter, and the first It has an input terminal of the inverter and a clocked inverter in which an output terminal and an input terminal are connected to the output terminal, respectively, and during a reset period, the switch is turned on and the second electrode of the capacitance means has a second electrode. It is characterized in that the potential of 1 is input and the digital signal is input to the second electrode of the capacitance means in the capture period after the reset period. [0023] Further, the data latch circuit of the present invention is a data latch circuit that captures a digital signal, and is a capacitance means having first and second electrodes and a first inverter in which an input terminal is connected to the first electrode. A first switch connected between the input terminal and the output terminal of the first inverter, a second switch and a third switch connected to the second electrode, and the first switch. It has a second inverter in which an input terminal is connected to the output terminal of the first inverter, and a clocked inverter in which an output terminal and an input terminal are connected to the input terminal and the output terminal of the first inverter, respectively. , In the reset period, the first potential is input to the second electrode of the capacitance means by turning on the first switch and turning on the second switch, and the uptake period after the reset period. The digital signal is input to the second electrode of the capacitance means by turning on the third switch. [0024] Further, the data latch circuit of the present invention is a data latch circuit that captures a digital signal, and has a first capacitance means having first and second electrodes and a second capacitance means having third and fourth electrodes. It has means, an inverter in which an input terminal is connected to the first electrode and the third electrode, and a switch connected between the input terminal and the output terminal of the inverter, and during a reset period, The switch is turned on, the first potential is input to the second electrode of the first capacitance means, and the second potential is input to the fourth electrode of the third capacitance means. During the uptake period after the reset period, the digital signal is input to the second electrode of the first capacitance means and the fourth electrode of the second capacitance means. [0025] Further, the data latch circuit of the present invention is a data latch circuit that captures a digital signal, and has a first capacitance means having first and second electrodes and a second capacitance means having third and fourth electrodes. Means, an inverter having input terminals connected to the first electrode and the third electrode, a first switch connected between the input terminal and the output terminal of the inverter, and the second switch. It has a second switch and a third switch connected to the electrode, and a fourth switch and a fifth switch connected to the fourth electrode, and during the reset period, the switch is turned on and the switch is turned on. By turning on the second switch, a first potential is input to the second electrode of the first capacitance means, and by turning on the fourth switch, the third capacitance means is described. A second potential is input to the fourth electrode, and during the uptake period after the reset period, the third switch is turned on to connect to the second electrode of the first capacitance means and to the fifth electrode. The digital signal is input to the fourth electrode of the second capacitance means by turning on the switch. [0026] Further, the data latch circuit of the present invention is a data latch circuit that captures a digital signal, and has a first capacitance means having first and second electrodes and a second capacitance means having third and fourth electrodes. Between the means, the first inverter in which the input terminal is connected to the first electrode and the output terminal is connected to the third electrode, and the input terminal and the output terminal of the first inverter. The first switch connected, the third capacitive means having the fifth and sixth electrodes, the fourth capacitive means having the seventh and eighth electrodes, and the input terminal on the fifth electrode A second inverter connected and having an output terminal connected to the seventh electrode, a second switch connected between the input terminal and the output terminal of the second inverter, and the fourth It also has a third inverter with an input terminal connected to the eighth electrode and a third switch connected between the input terminal and the output terminal of the third inverter, and during the reset period. , The first and second switches are turned on, the first potential is input to the second electrode of the first capacitance means, and the fourth electrode of the third capacitance means is input. It is indicated that the potential of 2 is input, and the digital signal is input to the second electrode of the first capacitance means and the fourth electrode of the second capacitance means in the uptake period after the reset period. It is a feature. [0027] Further, the data latch circuit of the present invention is a data latch circuit that captures a digital signal, and has a first capacitance means having first and second electrodes and a second capacitance means having third and fourth electrodes. Between the means, the first inverter in which the input terminal is connected to the first electrode and the output terminal is connected to the third electrode, and the input terminal and the output terminal of the first inverter. The first switch connected, the third capacitive means having the fifth and sixth electrodes, the fourth capacitive means having the seventh and eighth electrodes, and the input terminal on the fifth electrode A second inverter connected and having an output terminal connected to the seventh electrode, a second switch connected between the input terminal and the output terminal of the second inverter, and the fourth A third inverter having an input terminal connected to the eighth electrode, a third switch connected between the input terminal and the output terminal of the third inverter, and the first electrode. It has a fifth capacitance connected to the fifth electrode, and during the reset period, the first and second switches are turned on, and the second electrode of the first capacitance means has a second electrode. The potential of 1 is input, and the second potential is input to the fourth electrode of the third capacitance means, and in the uptake period after the reset period, the second electrode of the first capacitance means is input. The digital signal is input to the fourth electrode of the second capacitance means. [0028] Further, the first potential may be a potential of 1 or a potential of 0 of the digital signal. Further, the reset period may be determined by using the sampling pulse from the shift register of the previous stage, and the acquisition period may be determined by using the sampling pulse from the shift register of the own stage. Further, the amplitude of the digital signal may be smaller than the power supply voltage width used in the data latch circuit. Further, the output pulse from the shift register in the previous stage may be used for the control terminal of the clocked inverter. Further, the data latch circuit may be formed by a thin film transistor. [Effect of the invention] [0029] The data latch circuit of the present invention can operate accurately even if the amplitude of the input signal is small with respect to the power supply voltage width, without being affected by variations in various characteristics of the TFT. Therefore, it is not necessary to level-shift the signal from the external circuit, and it is possible to realize low power consumption, reduction of layout area, and cost reduction. [Best mode for carrying out the invention] Embodiments of the present invention will be described below. [0030] (Embodiment 1) FIG. 1A shows the configuration of the data latch circuit of this embodiment. [0031] The data latch circuit of this embodiment includes a data capture switch 1001, a reference switch 1002, a threshold set switch 1003, a capacitance means 1004, and a correction inverter 1005. In the data latch circuit of the present embodiment, the circuit block including the data capture switch 1001, the reference switch 1002, and the capacitance means 1004 is referred to as block x. Further, if necessary, an inverter 1006 may be provided. [0032] The data acquisition switch 1001 is controlled to be turned on or off by LAT, and the input DATA is input to the connection portion (hereinafter referred to as node a) between the reference switch 1002 and the second electrode of the capacitance means 1004. The reference switch 1002 is controlled to be turned on or off by LAT-1, captures the first potential (here referred to as "reference potential"), and connects the data capture switch 1001 to the second electrode of the capacitive means 1004. The reference potential is output to the unit, that is, the node a. The input terminal and output terminal of the correction inverter 1005 are electrically connected via the threshold set switch 1003. The connection portions between the input terminal and output terminal of the correction inverter 1005 and the threshold value set switch 1003 are referred to as "node b" and "node c", respectively. Further, on or off of the threshold value setting switch 1003 is controlled by LAT-1. The correction inverter 1005 outputs data to the inverter 1006 connected to the node c. [0033] FIG. 1B shows a timing chart of the data latch circuit of this embodiment. The operation when the data latch circuit of this embodiment is driven at a low voltage will be described with reference to FIGS. 1 (A) and 1 (B). In this embodiment, VSS is -2V, VDD is 5V, LAT, LATB, LAT-1 and LAT-1B each have an H level of 5V, an L level of -2V, a DATA of H level of 3V, and an L level of 0V. , The reference potential is 1.5V, which is the intermediate potential between the L level and H level of DATA. Further, it is desirable that the LAT input in the period T1 and the pulse of the LAT-1 input in the subsequent period T2 do not overlap. [0034] First, the reset work is performed in the period T1. The sampling pulse LAT-1 (5V) is input to the data latch circuit from the shift register in front of the data latch circuit, and the reference switch 1002 and the threshold set switch 1003 are turned on. As a result, node a becomes the reference potential (1.5V). Since node b works in the direction in which the potential of node c is fed back and the potential does not move, it becomes the threshold potential of the correction inverter 1005 (here, it is set to 2V). [0035] Then, in the period T2, the data latch circuit determines the H level and L level of the input DATA. The sampling pulse LAT (5V) from the shift register is input to this data latch circuit, and the data acquisition switch 1001 is turned on. When the input DATA is H level (3V), the potential of node a changes from 1.5V to 3V. Since the potential difference between both ends of the capacitance means 1004 is maintained, the node b changes by the voltage change of the node a. Therefore, node b rises from 2V to about 1.5V to about 3.5V. [0036] Here, Fig. 3 shows the V of a general inverter._IN(Input signal voltage) -V_OUT(Output signal voltage) Indicates the characteristics. V as shown in Figure 3_INIf even a little fluctuates above or below the threshold, V_OUTIs very close to VDD or VSS. [0037] Therefore, since the node b is set to the threshold potential of the correction inverter 1005 in the period T1, the node c reacts sensitively to the change in the potential of the node b. In this case, since the potential of node b has risen from 2V to about 3.5V, the potential of node c greatly approaches VSS. The potential of node c is further shaped by the inverter 1006, and VDD (H level) is output to its output OUT. [0038] On the contrary, when DATA is L level (0V) in the period T2, the potential of node a changes from 1.5V to 0V, and the potential of node b drops by about 2V to 1.5V to about 0.5V. As the node b descends from the threshold potential in this way, the node c approaches VDD significantly. The potential of node c is further shaped by the inverter 1006, and VSS (L level) is output to its output OUT. [0039] When the reference potential is a fixed potential, an intermediate potential of the amplitude of the data signal (DATA in this case) is ideally desirable, but it does not have to be exactly an intermediate potential, and the maximum potential or the minimum potential of the data signal is not required. It is possible to make some fluctuations within a range that is different from the electric potential and does not produce the amplitude of the data signal. [0040] Further, the inverted signal of the data signal DATA may be shifted to the reference potential by one data and input. In this case, for example, if DATA is H level (3V), node a becomes L level (0V) in reset period T1, and if H level (3V) DATA is input in capture period T2, node a and Node b fluctuates by about 3V, making it easier for the correction inverter 1005 to operate accurately. Even if the DATA is L level (0V), node a becomes H level (3V) in the reset period T1 and L level (0V) DATA is input in the capture period T2. Therefore, node a and node b are similarly input. Fluctuates by about 3V. [0041] As in the present embodiment, in the data latch circuit, the threshold potential of the inverter that determines and outputs the H level or L level of the data signal DATA is acquired in advance, and the data signal is H depending on whether the data signal fluctuates up or down from the threshold potential. By determining whether it is a level or an L level, even if the amplitude of the input signal is small with respect to the power supply voltage width, it operates accurately without being affected by threshold fluctuations due to variations in various characteristics of the TFT. can do. Therefore, low power consumption and high frequency operation are possible. In particular, it is desirable to use it for a data latch circuit using a polysilicon TFT, which has many variations in various characteristics of the TFT. Further, in the present invention, as the crystallization method for producing the polysilicon TFT, a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, and a thermal crystallization method using a metal element that promotes crystallization , Or a combination of these crystallization methods can be used. [0042] (Embodiment 2) When using the data latch circuit shown in FIG. 1 (A), a clocked inverter 6002 or the like may be used as shown in FIGS. 6 (A) and 6 (B) for holding, or a capacitance means 6003 or the like may be used. , May be held. A general clocked inverter may be used for the clocked inverter 6002. [0043] A typical clocked inverter is shown in Fig. 10. The clocked inverter 10001 has a first P-type TFT10002, a second P-type TFT10003, a first N-type TFT10004, and a second N-type TFT10005 connected in series. The terminal input to the gate electrode of the first P-type TFT10002 is used as the control terminal 1, and the terminal input to the gate electrode of the second P-type TFT10003 and the first N-type TFT10004 is used as the input terminal. The terminal input to the gate electrode of the N-type TFT10005 is used as the control terminal 2, and the connection terminal of the second P-type TFT10003 and the first N-type TFT10004 is used as the output terminal. [0044] FIG. 6 (A) shows that the capacitance means 6003 and the clocked inverter 6002 are added to FIG. 1 (A), and the clocked inverter 6002 is connected to the inverter 6001 in a loop. The holding pulse HOLD is input to the control terminal 1 of the clocked inverter 6002, and the inverting pulse HOLD B of the HOLD is input to the control terminal 2. Other parts are the same as in Fig. 1 (A). [0045] FIG. 6B shows a clocked inverter 6102 added to FIG. 1A, and the clocked inverter 6102 connected to the correction inverter 6101 in a loop. The holding pulse HOLD is input to the control terminal 1 of the clocked inverter 6102, and the inverting pulse HOLD B of the HOLD is input to the control terminal 2. Other parts are the same as in Fig. 1 (A). [0046] The HOLD pulse is preferably a pulse such as 6201 or 6202 shown in FIG. 6C of the timing chart, and it is preferable to use the output pulse of the shift register or the like. As an operation, after the capture period T2 is completed, the clocked inverter 6002 or 6102 is turned on and the holding operation is started. [0047] As in this embodiment, by holding using a clocked inverter or the like, the H level and L level can be held accurately for a desired period. [0048] (Embodiment 3) Two blocks x in the data latch circuit of Fig. 1 (A) are connected in parallel, and the two reference potentials input to each of the two reference switches are set, one of which is the same as the maximum potential of the data signal (the same as the H level of DATA). FIG. 7 shows the case where the other is the lowest potential of the data signal (the same potential as the L level of DATA). [0049] The data latch circuit of the present embodiment is connected in series with the correction inverter 7008 and the correction inverter 7008 in which the input unit is connected to one of the connection portions of the block y and the block y ́ and the block y and the block y ́ connected in parallel. It has an inverter 7009, a threshold set switch 7007 connected to the input terminal and the output terminal of the correction inverter 7008, and a clocked inverter 7009. The block y is a first data capture switch 7001 and a first capacitance means 7005 connected in series, and a first input DH for inputting a signal DH to their connection (hereinafter referred to as "node a"). It has a reference switch 7003, and the block y ́ is connected in series to the second data acquisition switch 7002 and the second capacitance means 7006, and their connection (hereinafter referred to as node a ́). ) Has a second reference switch 7004 that inputs the signal DL. [0050] Further, the first data acquisition switch 7001 and the second data acquisition switch 7002 are controlled on or off by LAT to acquire DATA. The first reference switch 7003, the second reference switch 7004, and the threshold set switch 7007 are controlled on or off by LAT-1. The threshold set switch 7007 is provided between the input terminal and the output terminal of the correction inverter 7008. The connection portions between the input terminal and output terminal of the correction inverter 7008 and the threshold value set switch 7007 are referred to as "node b" and "node c", respectively. Further, in the present embodiment, VSS is -2V, VDD is 5V, LAT, LATB, LAT-1 and LAT-1B each have an H level of 5V, an L level of 0V, and a DATA H level (DH) of 3V. The L level (DL) is 0V. [0051] Since the timing chart in the present embodiment is the same as the timing chart in the first embodiment shown in FIG. 1 (B), the timing chart in FIG. 1 (B) will be used for description. First, in the reset period T1, LAT-1 becomes H level (5V), the first reference switch 7003, the second reference switch 7004, and the threshold set switch 7008 are turned on, and the node a is the potential of DH (3V). ), And node a ́ becomes the DL potential (0V). Further, the node b is the threshold voltage of the correction inverter 7008 (here, it is set to 2V). [0052] After that, in the data acquisition period T2, LAT becomes H level (5V) and LAT-1 becomes L level (0V), and the first data acquisition switch 7001 and the second data acquisition switch 7002 are turned on. .. If DATA is H level (3V), node a remains at 3V and node a ́ changes from 0V to 3V. Therefore, node b rises from 2V to about 1.5V to 3.5V. As a result, node c comes very close to VSS (-2V). [0053] On the contrary, when DATA is L level (0V), node a changes from 3V to 0V, and node a ́ remains 0V. Therefore, node b drops from 2V by about 1.5V to about 0.5V. Therefore, node c comes very close to VDD (5V). [0054] As described above, the data latch circuit of the present embodiment can operate accurately without being affected by variations in various characteristics of the TFT even if the amplitude of the input signal is small with respect to the power supply voltage width, and consumes low power. Power consumption and high frequency operation are possible. Further, in the data latch circuit of the present embodiment, the two reference potentials input to the two reference switches are set to the maximum potential (DH) of the data signal and the minimum potential (DH) of the data signal. ), It is not necessary to provide an intermediate potential to be used as the reference potential, which is effective in reducing the number of power sources. [0055] (Embodiment 4) FIG. 8A shows a data latch circuit of the present invention having a configuration different from that of the first to third embodiments. [0056] The data latch circuit of the present embodiment includes a block z and a block z ́ connected in parallel, and the block z and the block z ́. ́ The first correction inverter 8001 whose input terminal is connected to one of the connection parts, the inverter 8002 which is connected in series with the first correction inverter 8001, and the input terminal and output terminal of the first correction inverter 8001. It has a first threshold set switch 8003 provided between the two. [0057] Further, the block z includes a first capture switch 8004, a first capacitance means 8008, a second compensation inverter 8010 and a third capacitance means 8012 arranged in series, and a first capture switch 8004 and a first. The input terminal and output of the first reference switch 8006 that captures DH (the same potential as the H level of DATA) and the second correction inverter 8010 at the connection with the capacitance means 8008 (hereinafter referred to as "node a"). It has a second threshold set switch 8014 provided between the terminals. Block z ́ is the second capture switch 8005, the second capacitance means 8009, the third correction inverter 8011 and the fourth capacitance means 8013, the second capture switch 8005 and the second, which are arranged in series. Connection with capacity means 8009 (hereinafter referred to as "node a" ́ ". ) To capture DL (the same potential as the L level of DATA), the second reference switch 8007, and the third threshold set switch 8015 provided between the input terminal and output terminal of the third correction inverter 8011. And have. [0058] [0058] DATA is input to the other connection between the block z and the block z ́, that is, the connection between the first capture switch 8004 and the second capture switch 8005. The first capture switch 8004 and the second capture switch 8005 are turned on or off by LAT, respectively. The first reference switch 8006, the second reference switch 8007, the second threshold set switch 8014, and the third threshold set switch 8015 are turned on or off by LAT-1, respectively. [0059] Further, the connection portions between the input terminal and the output terminal of the first correction inverter 8001 and the first threshold value set switch 8003 are referred to as "node b" and "node c", respectively. Further, the connection portions between the input terminal and the output terminal of the second correction inverter 8010 and the second threshold value set switch 8014 are referred to as "node a2" and "node a3", respectively. Further, the connection portions between the input terminal and the output terminal of the third correction inverter 8011 and the third threshold value set switch 8015 are referred to as "node a2 ́" and "node a3 ́", respectively. Further, since the timing chart of the present embodiment is the same as the timing chart of the first embodiment shown in FIG. 1 (B), the operation will be described using the timing chart of FIG. 1 (B). [0060] First, in the reset period T1, LAT-1 becomes the H level (VDD), node a is the potential of DH, node a ́ is the potential of DL, node a2 and node a3 are the threshold potentials of the second correction inverter 8010, and the node. a2 ́ and node a3 ́ are the threshold potentials of the third correction inverter 8011. [0061] Then, in the data acquisition period T2, LAT becomes H level (VDD) and DATA is acquired. When DATA is H level, the potentials of node a and node a2 do not change, node a ́ changes from DL to H level, and node a2 ́ rises by about the amplitude of DATA. Node a3 ́ gets very close to VSS, and the potential of node b also drops. Therefore, node c comes very close to VDD. [0062] On the contrary, when DATA is L, the potentials of node a ́ and node a2 ́ do not change, node a changes from DH to L level, and node a2 drops by about the amplitude of DATA. Node a3 gets very close to VDD, and the potential of node b also rises. Therefore, node c comes very close to VSS. [0063] In addition, if node a2 when DATA is H level and node a2 ́ when DATA is L level fluctuates due to switching noise when importing DATA, etc., and malfunctions occur, Fig. 8 As shown in (B), it is preferable to provide a fifth capacitance means 8016 between the node a2 and the node a2 ́. Node a2 and node a2 by capacity means 8016 ́ fluctuates in the same direction to prevent malfunction. [0064] As described above, even if the amplitude of the input signal with respect to the power supply voltage width is smaller than that of the other embodiments, the data latch circuit of the present embodiment is accurately unaffected by various characteristics of the TFT. It can operate, and it enables low power consumption and high frequency operation. Further, in the data latch circuit of the present embodiment, the two reference potentials input to the two reference switches are set to the maximum potential (DH) of the data signal and the minimum potential (DH) of the data signal. ), It is not necessary to provide an intermediate potential to be used as the reference potential, which is effective in reducing the number of power sources. [0065] In the first to fourth embodiments, the case where the data acquisition switch, the reference switch, and the threshold set switch are N-type TFTs has been described here as an example, but all of them may be changed depending on the power supply voltage value, the signal voltage value, and the signal amplitude. It may be replaced with an analog switch having a P-type TFT or an N-type TFT and a P-type TFT, or some may be replaced. [0066] Further, although the reset pulse LAT-1 is a sampling pulse from the shift register one step before, it may be a sampling pulse from a shift register one step before, or a pulse may be input for reset. Further, all stages may be reset at once. The voltage setting is also not limited to this. [Example 1] [0067] Here, the configuration and drive when the data latch circuit of the present invention is used in an active matrix type display device will be described. [0068] Figure 4 shows a block diagram of the external circuit and a schematic diagram of the panel. Here, as an example, an active matrix type organic EL display device is used. [0069] As shown in FIG. 4, the active matrix display device has an external circuit 4004 and a panel 4010. The external circuit 4004 has an A / D conversion unit 4001, a power supply unit 4002, and a signal generation unit 4003. The A / D conversion unit 4001 converts the video data signal input as an analog signal into a digital signal and supplies it to the source signal line drive circuit 4006. The power supply unit 4002 generates a power supply with a desired voltage value from the power supply supplied from the battery or the outlet, and supplies the power supply to the source signal line drive circuit 4006, the gate signal line drive circuit 4007, the EL element 4011, the signal generation unit 4003, and the like. To do. A power supply, a video signal, a synchronization signal, etc. are input to the signal generation unit 4003, and in addition to converting various signals, a clock signal, etc. for driving the source signal line drive circuit 4006 and the gate signal line drive circuit 4007 is generated. To do. [0070] The signal and power supply from the external circuit 4004 pass through the FPC and are input to the internal circuit, EL element 4011, etc. from the FPC connection part 4005 in the panel 4010. [0071] Further, the panel 4010 has an FPC connection portion 4005 and an internal circuit arranged on a glass substrate 4008, and also has an EL element 4011. The internal circuit has a source signal line drive circuit 4006, a gate signal line drive circuit 4007, and a pixel unit 4009. [0072] A pixel unit 4009 is arranged in the center of the substrate, and a source signal line drive circuit 4006 and a gate signal line drive circuit 4007 are arranged around the pixel unit 4009. The EL element 4011 and the counter electrode of the EL element are formed on the entire surface of the pixel portion 4009. [0073] In more detail, FIG. 5 shows a block diagram of the source signal line drive circuit 4006. [0074] Source signal line drive circuit 4006 is a D-flip-flop (Delayed) It has a shift register 5002 using multiple stages of Flip-Flop (D-FF) 5001), a data latch circuit 5003, a latch circuit 5004, a level shifter 5005, a buffer 5006, and the like. The data latch circuit of the present invention can be used for the data latch circuit 5003, and any of the data latch circuits described in the embodiment can be adopted. Here, the case where it is adopted in the data latch circuit 5003 will be described, but the data latch circuit may be adopted in the latch circuit 5004. [0075] The input signals are a clock signal line (S-CK), an inverted clock signal line (S-CKB), a start pulse (S-SP), a digital video signal (DATA) and a latch pulse (Latch Pulse), and also. An intermediate potential of the amplitude of the digital video signal shall be input as the reference potential. [0076] First, sampling pulses are sequentially output from the shift register 5002 according to the timings of the clock signal, the clock inversion signal, and the start pulse. The sampling pulse is input to the data latch circuit 5004. The data latch circuit 5004 is reset by the sampling pulse input from the D-FF5001 one stage before, and then captures and holds the digital video signal at the timing when the sampling pulse is input from the D-FF5007 of the own stage. This operation is performed in order from the first row. [0077] When the holding of the digital video signal in the final stage data latch circuit 5003 is completed, the latch pulse is input during the horizontal return period, and the digital video signals held in the data latch circuit 5003 are transferred to the latch circuit 5004 all at once. Will be done. After that, the level is shifted by the level shifter 5005, shaped by the buffer 5006, and then output all at once from the source signal lines S1 to Sn. At that time, the H level and the L level are input to the pixels in the row selected by the gate signal line drive circuit 4007, and the light emission and non-light emission of the EL element 4011 are controlled. [0078] In the active matrix type display device shown in this embodiment, the panel 4010 and the external circuit 4004 are independent, but these may be integrally formed on the same substrate. Further, although the display device uses an organic EL as an example, a light emitting device using a light emitting element other than the organic EL may be used, or a liquid crystal display device may be used. Further, the level shifter 5005 and the buffer 5006 may not be included in the source signal line drive circuit 4006. [Example 2] [0079] As described in the first embodiment, the data latch circuit of the present invention can be used for various display devices, and the display devices can be used for display units of various electronic devices. In particular, it is desirable to use the display device of the present invention for mobile devices that require low power consumption. [0080] [0080] Specific examples of the electronic device include a mobile information device (mobile phone, mobile computer, portable game machine, electronic book, etc.), a video camera, a digital camera, a goggle type display, a display display, a navigation system, and the like. Specific examples of these electronic devices are shown in FIGS. 9 (A) to 9 (D). [0081] FIG. 9A shows a display, which includes a housing 9001, an audio output unit 9002, a display unit 9003, and the like. The display device using the data latch circuit of the present invention can be used for the display unit 9003. The display device includes all information display devices such as those for personal computers, those for receiving TV broadcasts, and those for displaying advertisements. [0082] FIG. 9B shows a mobile computer, which includes a main body 9101, a stylus 9102, a display 9103, an operation button 9104, an external interface 9105, and the like. The display device using the data latch circuit of the present invention can be used for the display unit 9103. [0083] FIG. 9C shows a game machine, which includes a main body 9201, a display unit 9202, an operation button 9203, and the like. The display device using the data latch circuit of the present invention can be used for the display unit 9202. [0084] FIG. 9D shows a mobile phone, which includes a main body 9301, a voice output unit 9302, a voice input unit 9303, a display unit 9304, an operation switch 9305, an antenna 9306, and the like. The display device using the data latch circuit of the present invention can be used for the display unit 9304. [Industrial applicability] [0085] As described above, the data latch circuit of the present invention can be applied to all circuits that capture digital data, and is particularly suitable for a drive circuit of a display device. Further, the range of application of the display device using the data latch circuit of the present invention as a part of the drive circuit is extremely wide, and it can be used for electronic devices in all fields. [Simple explanation of drawings] [0086] FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing a conventional data latch circuit. [Fig. 3] Fig. 3 shows the V of a general inverter._IN-V_OUTIt is a figure which shows the characteristic. FIG. 4 is a diagram showing an outline of an external circuit and a display panel. FIG. 5 is a diagram showing a configuration example of a source signal line drive circuit. FIG. 6 is a diagram showing an embodiment of the present invention. FIG. 7 is a diagram showing an embodiment of the present invention. FIG. 8 is a diagram showing an embodiment of the present invention. FIG. 9 is a diagram showing an example of an electronic device to which the present invention can be applied. FIG. 10 is a diagram showing a general clocked inverter.