Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric

(Cross-reference of related applications) This application claims the priority of US application series No. 09 / 955,641 filed on September 18, 2001, entitled "Semiconductor Memory Cells and Memory Arrays Utilizing Breakdown Phenomena of Ultra-Thin Film Dielectrics" under 35USC120. Is what you do.

(Technical field) The present invention relates to a reprogrammable non-volatile memory, and more particularly to a non-volatile reprogrammable semiconductor memory that stores digital information using a breakdown phenomenon of an ultrathin film dielectric such as a MOS gate dielectric.

Non-volatile memory retains stored data when power is cut off, and this property is required, or at least strongly desired, in many different types of computers and other electronic devices. A commonly available type of non-volatile memory is programmable read-only memory (PROM), which is a floating gate with elements such as fuses and antifuse located at the intersection of wordlines and bitlines. Avalanche-injected metal oxide semiconductor (FAMOS) Transistors and other charge-capturing devices are used to store logical information. PROMs are usually not rewritable.

An example of a type of PROM cell that stores digital data using the breakdown of the silicon dioxide layer of a capacitor is disclosed in Patent Document 1 issued on April 10, 2001 by Lysinga et al. The basic PROM disclosed by Lysinga et al. Uses a series connection of an oxide capacitor and a junction diode as an intersection element. Unstressed capacitors represent a logical value of 0, and capacitors that have undergone electrical breakdown represent a logical value of 1. The thickness of the silicon dioxide layer is adjusted to obtain the desired operating characteristics. Silicon dioxide is about 10 C / cm²(Coulomb / cm²) Has a fracture life. When a voltage of 10 volts is applied to a capacitor dielectric with a thickness of 10 nm (the electric field strength is 10 mV / cm), it is about 1 mA / cm.²Current flows. When a voltage of 10 volts is applied, it takes a corresponding amount of time to write to the memory cell. However, a greater advantage can be gained by designing the capacitor dielectric to be thinner to reduce the large power loss that occurs during electrical failure. For example, a memory cell structure with a capacitor dielectric with a thickness of 3-4 nm can operate at about 1.5V. 1.5V is sufficient to read data from a memory cell, as the capacitor dielectric is not yet destroyed at that voltage. When data is stored at 5V, for example, it is possible to write to one cell aggregate of the memory cell structure within about 1 ms. Capacitor dielectric 1 cm produced in this case²The energy loss per hit is about 50 watts (10 coulombs * 5V). Assuming the desired power loss is about 0.5 watts, it takes about 100 seconds to write to 1 Gigabit of memory. If the allowable power loss is larger, the writing can be performed at a correspondingly higher speed.

Certain types of non-volatile memory can be repeatedly written and erased, and includes an erasable programmable read-only semiconductor memory known as EPROM and an electrically erasable programmable read-only semiconductor memory known as EEPROM. The EPROM memory is erased by ultraviolet light irradiation and written by applying various voltages, whereas the EEPROM memory is erased and written by applying various voltages. EPROM and EEPROM have a suitable structure commonly known as a floating gate However, this floating gate is charged and discharged depending on the stored data. The charge of the floating gate is the threshold voltage V of the device._TIs determined, and this value is sensed when reading from memory to obtain the data stored in it. Usually, energy is devoted to minimizing the gate oxide stress of these types of memory cells.

The device, known as a metal oxynitride silicon (MNOS) device, is located in the silicon between the source and drain and has a channel covered by a gate structure containing a silicon dioxide layer, a silicon nitride layer and an aluminum layer. The MNOS device applies an appropriate voltage pulse to the gate to trap the electrons in the oxynitride gate (V)._{TH (high)}), Or emit an electron from the oxynitriding gate (V)_{TH (low)}) By two threshold voltage states, (V_{TH (high)}) And (V_{TH (low)}) And. Usually, energy is devoted to minimizing the gate oxide stress of these types of memory cells.

A junction breakdown memory cell that stores logical values 0 and 1 using the charge stored in the gate of a gate control diode is disclosed in Patent Document 2 issued by Hoffman et al. On July 19, 1977. The charge is stored in the gate by using the capacitance formed between the p-type electrode and the gate electrode of the gate control diode. Charge conservation is accelerated by using a composite dielectric of the capacitor formed from the silicon dioxide layer and the silicon nitride layer instead of silicon dioxide. When an erasing voltage is applied to the electrodes of the gate control diode, the oxide film-nitride film interface is filled with a negative charge, and this negative charge is retained even after the erasing operation is completed. Due to this negative interfacial charge, the gate control diode can operate in the induced junction mode even after the supply of the erasing voltage is stopped. After that, when reading from the gate control diode is performed, the channel of this diode causes an electric field-induced junction breakdown, and a saturation current flows. The field-induced junction breakdown voltage is lower than the metallurgical junction breakdown voltage. However, when a write voltage is applied to the electrodes of the gate control diode, the silicon dioxide film / silicon nitride film interface is filled with a positive charge, which is retained even after the write operation is complete. Subsequent reads from the gate control diode will not cause the diode to break down because there are no channels. Only a small amount of current flows. Since different current flows are perceived, they show different logical states.

Improving the various processes used to form different types of non-volatile memory tends to delay the improvement of widely used processes such as advanced CMOS logic processes. Processes, such as those for devices in flash EEPROM devices, tend to use 30% more masking processes than standard advanced CMOS logic processes, and the use of these masking processes results in the high voltage commonly found in such devices. It forms generator circuits, triple wells, floating gates, ONO layers, and various special regions and structures required for special source and drain junctions. Therefore, processes for flash devices are one or two generations behind standard advanced CMOS logic processes and tend to be about 30% more expensive on a cost-per-wafer basis. As another example, the process for antifuse must also be suitable for the formation of various antifuse structures and high voltage circuits, which also tends to lag about a generation behind standard advanced CMOS processes. is there.

In general, great care is required in the formation of silicon dioxide layers used in metal-oxide-silicon (MOS) devices such as capacitors and transistors. Care must be taken at a high level to ensure that the silicon dioxide layer is not stressed during the manufacture or subsequent normal operation of the integrated circuit, thereby achieving the desired device characteristics. , Stable for a long period of time. An example of how much attention should be paid during manufacturing is disclosed in Patent Document 3 issued by Kuroda on August 31, 1993. Kuroda expands It shows that a layer and shunt is used to discharge the charge accumulated in the word line during the wafer manufacturing process. By avoiding this charge accumulation, it is guaranteed that fluctuations in the characteristics of the transistor using the word wire as the gate wiring and deterioration and breakdown of the gate insulating film can be prevented without applying a large electric field to the gate insulating film. An example of how much care should be taken in circuit design to prevent stress on the silicon dioxide layer of a transistor during normal circuit operation is disclosed in Patent Document 4 issued by Tamura et al. On June 19, 2001. Has been done. Tamura et al. Disclose an antifuse circuit having an antifuse connected in series with a p-channel MOS transistor in one embodiment and in series with an n-channel MOS transistor in another embodiment. Although antifuse is formed without the addition of the film-forming process normally required to form antifuse circuits, Tamura et al. Have encountered another problem. Once the antifuse is short-circuited, the transistor connected in series with it is exposed to a voltage high enough to break down the silicon dioxide layer of the transistor. Tamura et al. Show that another transistor is added to the circuit to avoid exposing the first transistor to breakdown potential.<patcit num="1"><text>U.S. Pat. No. 6,215,140</text></patcit><patcit num="2"><text>U.S. Pat. No. 4,037,243</text></patcit><patcit num="3"><text>U.S. Pat. No. 5,241,200</text></patcit><patcit num="4"><text>U.S. Pat. No. 6,249,472</text></patcit>

The present invention is a reprogrammable non-volatile memory cell and memory array. The non-volatile memory consists of a semiconductor memory cell having a data storage element formed around an ultra-thin film dielectric such as a gate oxide film, and this ultra-thin film dielectric stresses the ultra-thin film dielectric to break down (soft or soft or). It is used to store information by making it (hard breakdown) and setting the leak current level of the memory cell. Reading from a memory cell is performed by sensing the current drawn by the cell. Suitable ultra-thin film dielectrics are, for example, high quality gate oxides with a thickness of about 50 angstroms or less, which are commonly used, for example, in currently available advanced CMOS logic processes. Such oxide films are generally formed by membrane deposition, oxide growth in the silicon active region, or a combination thereof. Other suitable dielectrics include oxide film-nitriding film-oxide film composites, composite oxide films and the like.

A memory cell can be rewritten by increasing the magnitude of the dielectric breakdown transition from the "soft" breakdown to the "hard" breakdown when the memory cell is rewritten. This phenomenon can be used to rewrite the memory cell a finite number of times.

In the following description, the embodiments of the present invention can be fully understood by giving a lot of details in a particular form. However, one of ordinary skill in the art of this art can implement the invention without any explanation of one or more specific forms of detail, or any other method, component or material. You can understand that it can be carried out by such means. In other examples, known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the invention.

By the expression "one embodiment" or "an embodiment" throughout this specification, certain performances, structures, or properties described in a manner related to an embodiment are included in at least one embodiment of the present invention. It suggests. Thus, the expressions "in one embodiment" or "in an embodiment" that appear in various places throughout this specification do not necessarily all refer to the same embodiment. Also, a particular performance, structure, or characteristic is one or more embodiments. Can be combined in any form as appropriate.

First, a detailed description of a memory cell and a memory array incorporated in a smart card will be disclosed. Next, a description of a smart card incorporating a memory cell and a memory array will be disclosed.

An example of an arbitrary 4 × 4 portion of the memory array 100 including some such memory cells is shown in the schematic diagram of FIG. FIG. 1 shows 16 memory cells, each of which contains one MOS transistor and one MOS half transistor. A memory cell contains, for example, an n-channel MOS transistor 115 at the intersection of row 1 R1 and column C1, whose gate is row 1 line R1, its source is source line S1, and its drain is MOS half. It is connected to one terminal of transistor 111.

The MOS transistor 115, also referred to herein as a selective transistor, is used to "select" a particular memory cell to write or read. As can be seen from the following description, a large voltage is applied to the selection transistor and the MOS half transistor 111 during the write step to break down the gate oxide film of the MOS half transistor 111. However, it is not desirable to break down the gate oxide film of the selection transistor. Therefore, the gate oxide film of the selection transistor is formed so as to be a thicker oxide film than the gate oxide film of the MOS half transistor 111 in some other embodiments. In addition, or in another form, the selective transistor can be replaced with an I / O device that is more resistant to breakdown.

The gate of the MOS half transistor 111 is connected to the row line C1. Other memory cells shown in FIG. 1 are from half-transistor-transistor pairs 112 and 116,113 and 117,114 and 118,125 and 121,126 and 122,127 and 123,128 and 124,131 and 135,132 and 136,133 and 137,134 and 138,145 and 141,146 and 142,147 and 143, and 148 and 144. It is formed.

The MOS half transistor operates as follows. During writing or reading, a positive voltage (for the p-type active region) is applied to the gate, which is one terminal of the capacitor. The gate functions as a plate of the capacitor, and also has the function of forming an n-type inversion layer under the gate. The inverting layer acts as the other plate of the capacitor and together with the source / drain region forms the second terminal of the capacitor.

Using the half-transistor data storage device of Array 100 in Figure 1, half-transistors can be formed using many conventional MOS and CMOS processes without adding any masking process to this process. It is advantageous. However, other types of ultra-thin dielectric data storage devices can be used as needed. For example, capacitor-type data storage devices have the advantage of being able to write in either direction and reducing resistance when stress is applied to the ultrathin film dielectric, but some processes require extra masking steps. You will need it. The half-transistor type data storage element is shown in the cross-sectional view of FIG. 3, and the capacitor type data storage element is shown in the cross-sectional view of FIG.

Only the 4x4 portion of the memory array 100 is shown, but in reality such a memory array contains about 1 gigabit order of memory cells when formed using, for example, a tip 0.13 micrometer CMOS logic process, and CMOS logic. If the process is further improved, larger memory can be realized. Memory 100 is actually arranged in bytes, pages, and redundant lines (not shown), but whatever the desired shape. It may be arranged in a sea urchin. Many suitable memory allocation methods are known in the art.

FIG. 2 shows a partial layout of memory array 100, FIG. 200, and FIG. 3 shows a cross section of an exemplary MOS integrated circuit 300, which allows the transistor-half transistor pairs 115 and 111 to follow the layout diagram of FIG. , And the basic structural form of the MOS integrated circuit corresponding to the paired memory cells formed by 121 and 125 is shown. The layout diagram of FIG. 2 is suitable, for example, for advanced CMOS logic processes. The term "MOS" as used herein literally means metal-oxide-silicon. The letter "M" stands for "metal" gate structure, and the letter "O" stands for oxide, and the term MOS refers to impurity-doped polysilicon and other good conductors. It is generally understood as relating to all different types of gate dielectrics, including but not limited to silicon dioxide, and the term is used herein in that sense. For example, the dielectric can be any type of dielectric, such as an oxide film or a nitride film, which has a hard or soft breakdown when a voltage is applied over a period of time. Wake up. In one embodiment, a heat-growth gated silicon oxide film with a thickness of about 50 angstroms is used.

The memory array 100 is preferably laid out in a grid shape, in which case column lines such as C1 and C2 are orthogonal to row lines such as R1, R2, R3 and R4 as well as diffusion source lines. An active region mask containing pattern 213 (Fig. 2) is used to form an oxide insulating structure containing oxide trenches 302 and 314 (Fig. 3), and an active region such as 313 (Fig. 3) is defined. This active region will include the various transistors, half transistors and diffusion source lines of the memory array. The MOS half transistor 111 and MOS transistor 115 at the intersection of row line R1 and column line C1, and the MOS half transistor 125 and MOS transistor 121 at the intersection of row line R2 and column line C1 are formed in the p-well active region 313 by the following method. Will be done.

The formation of the ultra-thin gate oxide layer 312 was followed by the formation of polysilicon and the doping of polysilicon, which was the gates 311 and 301 (as well as the half) of the half-transistors 111,125, such as 211,214,221 and 224. Patterns for transistors 112 and 126, and other half-transistor gates (not shown), and rows such as R1 and R2 that also serve as gates for selective transistors 115, 121, 116 and 122 (as well as other selective transistors). Patterned using a gate mask containing patterns such as R1 and R2 for lines R1 and R2. NLDD (negative lightly doped drain) process steps (injection, spacers, and n) for various source and drain regions⁺Formed by source / drain injection), n⁺It forms regions 306, 308 and 310. Region 308 is also part of the diffusion source line. Contact masks containing patterns 210, 215, 220 and 225 (FIG. 2) are used to form contact vias that contact gates 301 and 311 (FIG. 3) and other gates (not shown). The metal mask contains the dashed pattern shown by C1 and C1 (Fig. 2) forming column lines such as C1 and C2, which are not only polysilicon row lines such as R1, R2, R3 and R4. Orthogonal to the diffusion source line. Other transistor-half transistor pairs in memory 100 are formed simultaneously in the same way.

FIG. 4 shows a cross section of the MOS integrated circuit 400 as an example, and this cross section shows the basic structural form of the MOS integrated circuit. The cross section 400 is similar to the cross section 300 of FIG. 3 except that the half transistors 125 and 111 of FIG. 3 are replaced with another type of ultrathin film dielectric data storage device, namely capacitors 425 and 411. Capacitor 411 at the intersection of row line R1 and column line C1 is formed by polysilicon gate 311 and this polysilicon The gate is contacted by a metal contact defined by pattern 210, and this polysilicon gate is deeply diffused with the gate oxide film 312.⁺Cover area 410. Similarly, the capacitor 425 at the intersection of row line R2 and column line C1 is formed by a polysilicon gate 301, which is contacted by a metal contact defined by pattern 215, and this polysilicon gate is gate oxidized. Membrane 312 and deeply diffused n⁺Cover area 406.

n⁺The regions 406 and 410 allow the capacitors 425 and 411 to have a very low resistance conductive state as compared to the half transistors 125 and 111 of FIG. 3, which depend on the forming state of the inversion layer to carry current. Another advantage of capacitors 425 and 411 is that writing can be done to them by passing a current in either direction. The disadvantage of capacitors 406 and 410 is that they require changes in the processes that are typically used at the commercial level and require the addition of masking and / or injection steps. For example, n⁺As a technique suitable for forming regions 406 and 410, embedding before gate polysilicon deposition n⁺An injection layer is formed, or after polysilicon film formation and etching, injection impurities are diffused laterally and embedded.⁺The method of forming an injection layer is used. n⁺Regions 406 and 410 are shown to diffuse deeper than the impurity regions 306 and 310 integrated with them, but the diffusion depth can be varied as desired.

A variant of the memory array 100 is the memory array 500 shown in FIG. 5, which shows any 4x4 portion of a large memory array of memory cells, each of which is a single MOS transistor and Contains one MOS half transistor. For example, the memory cell at the intersection of row R1 and column C1 contains an n-channel MOS transistor 515, which has its gate at row line R1, its drain at column C1, and its source at the MOS half transistor. It is connected to one terminal of 511. The gate terminal of the MOS half transistor 511 is connected to the source line S1. Other memory cells shown in Figure 1 are similar half-transistor-transistor pairs 512 and 516,513 and 517,514 and 518,521 and 525,522 and 526,523 and 527,524 and 528,531 and 535,532 and 536,533 and 537,534 and 538,541 and 545,542 and 546,543 and 547, and 544 and 548 Is formed by.

As in the case of the memory array of FIG. 1, the MOS capacitor can be used in place of the MOS half transistor 511 of the memory array of FIG. FIG. 6 shows a partial layout of the memory array 500, FIG. 600, and FIG. 7 shows a cross section of the MOS integrated circuit 700 as an example, which allows the transistor-half transistor pair 515 and according to the layout diagram of FIG. The basic structural form of the MOS integrated circuit corresponding to the paired memory cells formed by 511 and 525 and 521 is shown. The layout diagram of FIG. 6 is suitable, for example, for advanced CMOS logic processes. The memory array 500 is preferably laid out in a grid shape, in which case column lines such as C1 and C2 are orthogonal to row lines such as R1, R2, R3 and R4 as well as source lines such as S1. .. N including patterns 612,614,622 and 624 (Fig. 6)⁺A diffusion and active region mask is used to form an oxide insulating structure containing an oxide trench 704 (Fig. 7), and an active region such as 710 (Fig. 7) is defined, in which the memory array Various transistors and half transistors will be included. The MOS half transistor 511 and MOS transistor 515 at the intersection of row line R1 and column line C1 and the MOS half transistor 521 and MOS transistor 525 at the intersection of row line R2 and column line C1 are formed in the p-well active region 710 by the following method. Will be done. After forming the ultra-thin gate oxide film layer 702, polysilicon film formation and polysilicon doping Subsequently, this polysilicon is patterned using a gate mask containing patterns such as R1, S1 and R2 that act as gates for the selective transistors 515,525,516 and 526, and the half transistors 511,521,512 and 522. NLDD (negative lightly doped drain) process steps (injection, spacers, and n) for various source and drain regions⁺Formed by source / drain injection), n⁺Regions 712,714,716 and 718 are formed (Fig. 7). Contact masks containing patterns 610, 616, 620 and 626 (FIG. 6) are used to form contact vias that contact drains 712 and 718 (FIG. 7) as well as other drains (not shown). The metal mask contains the dashed patterns shown by C1 and C2 (Fig. 6), which form column lines such as C1 and C2, which are polysilicon such as R1, R2, R3 and R4. It is orthogonal not only to the row line but also to the polysilicon source line such as S1. Other transistor-half transistor pairs in memory 500 are formed simultaneously in the same way.

Next, the operation of the memory array 100 will be described with reference to the voltage as an example shown in FIG. These voltages are exemplary, and different voltages may be used in different applications or when using different process techniques. During the write operation, one of the four possible voltage combinations shown in rows 801, 802, 803 and 804 of FIG. 8 is applied to the various memory cells of the memory array 100. The read voltage is shown in lines 805, 806, 807 and 808.

It is assumed that the selected row and the selected column (SR / SC) are R1 and C1, and the memory cell composed of the transistor 115 and the half transistor 111 is written by these. As shown in line 801, the voltage on line R1 is 2.5V, and the voltage on source line S1 is 0V, which is sufficient to turn on transistor 115 and bring the drain of transistor 115 to 0V. is there. The voltage of row line C1 is 7.0V, which causes a potential difference of 7V across the half transistor 111. The gate oxide film 212 of the half transistor 111 is designed to break down due to this potential difference, and this breakdown causes writing to the memory cell. When the half transistor 111 breaks down, the resulting conductive path exhibits sufficient resistance and the gate oxide 212 of the transistor 115 does not deteriorate or break down. As an example, in some devices, the channel resistance of the transistor 115 is on the order of about 10 KΩ and the resistance of the broken down oxide film is on the order of more than about 100 KΩ.

When R1 and C1 are the selected row and the selected column, consider the impact that the transistor 116 and the half transistor 112 constitute and gives to the memory cell located at the intersection of the selected row and the non-selected column (SR / UC). As shown in line 802, the voltage on line R1 is 2.5V, and the voltage on source line S1 is 0V, which turns transistor 116 on and drains transistor 115 to 0V. Sufficient for. However, the voltage of the column line C2 is 0V, and this voltage causes the potential difference between both ends of the half transistor 112 to be 0V. No writing is done to the memory cells.

When R1 and C1 are the selected row and the selected column, consider the impact that the transistor 121 and the half transistor 125 make up and give to the memory cell located at the intersection of the non-selected row and the selected column (UR / SC). As shown in line 803, the voltage on line R2 is 0V, and the voltage on source line S1 is 0V, so transistor 121 does not turn on, and the node between the drain of transistor 121 and the half transistor 125. Is floating. The voltage of row line C1 is 7.0V, which causes a potential difference of less than about 4V across the half-transistor 125. No writing is done to the memory cell, A potential difference of less than about 4 V, which does not allow current to flow, is not sufficient for either the half transistor 125 or the transistor 121 to damage the gate oxide or degrade the gate oxide.

When R1 and C1 are the selected row and the selected column, consider the impact that the transistor 122 and the half transistor 126 form and give to the memory cell located at the intersection of the non-selected row and the non-selected column (UR / UC). As shown in line 804, the voltage on line R2 is 0V, and the voltage on source line S1 is 0V, so transistor 122 does not turn on. Since the voltage of the row line C2 is also 0V, there is no potential difference across the half transistor 126. No writing is done to the memory cells.

Reading from the memory array 100 is performed as follows. A 2.5 V read selection voltage is applied to the selection row (SR), and a 1.5V read column selection voltage is applied to the selection column (SC). Set all other rows that are non-selected rows (UR) and all other columns that are non-selected columns (UC) to 0V. It is assumed that R1 and C1 are selected rows and selected columns (SR / SC), and writing is performed to the memory cells composed of the transistor 115 and the half transistor 111. As shown in row 805, 2.5V (reading selective voltage) is applied to the gate of transistor 115 through row line R1 and 0V is applied from source through source line S1 to draw current from column line C1 with a potential of 1.5V. By pulling, it is found that the memory cell is being written. When the memory cell is not written, it is found that the memory cell is not written because no current flows.

Memory cells at intersections with either non-selected rows or non-selected columns do not draw current. As shown in row 806 corresponding to the case of the selected row line and the non-selected column line, 2.5V is applied to the gate of the transistor of the memory cell, but when 0V is applied to the column line, no current flows. 0V is applied to the gate of the transistor in the memory cell, as shown in row 807, which corresponds to the non-selected row line and the selected column line. 1.5V is applied to the row line, but no current flows because the transistor remains off. No current flows because 0V is applied to the gate of the transistor in the memory cell and 0V is applied to the column line, as shown in row 808, which corresponds to the non-selected row line and the non-selected column line.

Next, the operation of the memory array 500 will be described with reference to the voltages shown in FIGS. 9 and 10. These voltages are exemplary, and it is possible to use different voltages in different applications or when using different process techniques. It may also be understood that although the voltages shown in the tables 8, 9 and 10 are different, the principles behind the various voltages are the same and suggest a useful voltage range. ..

First, consider the write voltage as an example shown in the table of FIG. These voltages are suitable when the half transistor contains an ultrathin gate oxide film while the selected transistor is an input / output device with a gate oxide film thickness greater than 50 angstroms. During the write operation, one of the four possible voltage combinations shown in rows 901, 902, 903 and 904 of FIG. 9 is applied to the various memory cells of the memory array 500. What is common to all voltage combinations is that the source line S1 voltage value is 0V.

It is assumed that the selected row and the selected column (SR / SC) are R1 and C1, and thereby writing to the memory cell composed of the transistor 515 and the half transistor 511. As shown in row 901, the voltage on row line R1 is 7.0V, and the voltage on column line C1 is 7.0V, so a voltage of 7.0V is applied to the gate and drain, which is sufficient to turn on transistor 515. .. Transistor 515 source is from 7.0V transistor The voltage is obtained by subtracting a slight voltage drop across the 515, which creates a potential difference of 6.6 V across the half transistor 511. The gate oxide film 712 of the half transistor 511 is designed to break down due to this potential difference, and this breakdown causes writing to the memory cell. When the half transistor 511 breaks down, the resulting conductive path exhibits sufficient resistance and the gate oxide 712 of the transistor 515 does not deteriorate or break down.

When R1 and C1 are the selected row and the selected column, consider the impact that the transistor 516 and the half transistor 512 constitute and give to the memory cell located at the intersection of the selected row and the non-selected column (SR / UC). As shown in row 902, the voltage on row line R1 is 7.0V, and the voltage on column line C1 is 0V, so 7.0V is applied to the gate, and it is enough to turn on transistor 516, transistor. The source of 516 is set to the voltage of the column line C2, that is, 0V. Since the potential difference between both ends of the half transistor 512 is about 0V, no writing is performed on the memory cell.

When R1 and C1 are the selected row and the selected column, consider the impact that the transistor 525 and the half transistor 521 make on the memory cell located at the intersection of the non-selected row and the selected column (UR / SC). As shown in row 903, the voltage on row line R2 is 0V, and the voltage on column line C1 is 7.0V, so 0V is applied to the gate and 7.0V is applied to the drain. The 7.0V difference between the drain potential and the source line S1 potential is approximately split between the transistor 525 and the half transistor 125, producing a voltage of less than 4V across the gate oxide film of the half transistor 521. 525 does not turn on. No writing is done to the memory cells, and a potential difference of less than 4V that does not carry current can damage or degrade the gate oxides of either the half-transistor 512 or the transistor 525. Is not enough.

When R1 and C1 are the selected row and the selected column, consider the impact that the transistor 526 and the half transistor 522 configure and give to the memory cell located at the intersection of the non-selected row and the non-selected column (UR / UC). As shown in line 904, the voltage on line R2 is 0V, and the voltage on drain line C2 is 0V, so transistor 526 does not turn on. Since the voltage of the source line S1 is also 0V, there is no potential difference across the half transistor 522. No writing is done to the memory cells.

Next, consider the write voltage as an example shown in the table of FIG. These voltages are suitable when both the half transistor and the selective transistor contain an ultrathin gate oxide film. During the write operation, one of the four possible voltage combinations shown in rows 1001, 1002, 1003 and 1004 of FIG. 10 is applied to the various memory cells of the memory array 500. Common to all voltage combinations is that the source line S1 voltage value is -4.5V.

It is assumed that the selected row and the selected column (SR / SC) are R1 and C1, and thereby writing to the memory cell composed of the transistor 515 and the half transistor 511. As shown in row 1001, the voltage on row line R1 is 2.5V, and the voltage on column line C1 is 2.5V, so a voltage of 2.5V is applied to the gate and drain, which is sufficient to turn on the transistor 515. .. The source of the transistor 515 is 2.5V minus a small voltage drop across the transistor 515, which creates a potential difference of 6.6V across the half transistor 511. The gate oxide film 712 of the half transistor 511 is designed to break down due to this potential difference, and this breakdown causes writing to the memory cell. When the half-transistor 511 breaks down, the resulting conductive path will exhibit sufficient resistance. The gate oxide film 712 of the Langista 515 does not deteriorate or break down.

When R1 and C1 are the selected row and the selected column, consider the impact that the transistor 516 and the half transistor 512 constitute and give to the memory cell located at the intersection of the selected row and the non-selected column (SR / UC). As shown in row 1002, the voltage on row line R1 is 2.5V, and the voltage on column line C1 is 0V, so 2.5V is applied to the gate, and it is enough to turn on transistor 516, transistor. The source of 516 is set to the voltage of the column line C2, that is, 0V. Since the potential difference between both ends of the half transistor 512 is about 4.0 V, writing is not performed to the memory cell.

When R1 and C1 are the selected row and the selected column, consider the impact that the transistor 525 and the half transistor 521 make on the memory cell located at the intersection of the non-selected row and the selected column (UR / SC). As shown in row 1003, the voltage on row line R2 is 0V, and the voltage on column line C1 is 2.5V, so 0V is applied to the gate and 2.5V is applied to the drain. The 6.5V difference between the potential of the drain and the potential of the source line S1 is almost divided between the transistor 525 and the half transistor 125, and a voltage of less than about 4V is generated across the oxide film of the half transistor 521. 525 does not turn on. No writing is done to the memory cells, and a potential difference of less than 4V that does not carry current can damage or degrade the gate oxides of either the half-transistor 512 or the transistor 525. Is not enough.

When R1 and C1 are the selected row and the selected column, consider the impact that the transistor 526 and the half transistor 522 configure and give to the memory cell located at the intersection of the non-selected row and the non-selected column (UR / UC). As shown in line 904, the voltage on line R2 is 0V, and the voltage on drain line C2 is 0V, so transistor 526 does not turn on. Since the voltage of the source line S1 is -4.5V, the potential difference between both ends of the half transistor 522 is less than about 4V. No writing is done to the memory cells, and a potential difference of less than about 4V that does not carry current can damage or degrade the gate oxides of either the half-transistor 522 or the transistor 526. Not enough for.

Whether or not the write voltage in the table of FIG. 9 or the table of FIG. 10 is used, the read from the memory array 500 is performed as follows. A 2.5V read selection voltage is applied to the selection row (SR), and a 1.5V read column selection voltage is applied to the selection column (SC). All other rows that are non-selected rows (UR) and all other columns that are non-selected columns (UC) are set to 0V. It is assumed that R1 and C1 are selected rows and selected columns (SR / SC), and the memory cells composed of the transistor 515 and the half transistor 511 are written. Applying 2.5V (read-selective voltage) to the gate of transistor 515 through row line R1 and 1.5V to drain through column line C1 as shown in rows 905 and 1005 to draw current from column line C1. It turns out that the memory cell is being written. When the memory cell is not written, it is found that the memory cell is not written because no current flows.

Memory cells at intersections with either non-selected rows or non-selected columns do not draw current. As shown in rows 906 and 1006 corresponding to the case of the selected row line and the non-selected column line, 2.5V is applied to the gate of the transistor of the memory cell, but since 0V is applied to the column line, the current flows. Absent. 0V is applied to the gate of the transistor in the memory cell, as shown in rows 907 and 1007, which correspond to the non-selected row line and the selected column line. 1.5V is applied to the row line, but no current flows because the transistor remains off. Shown in rows 908 and 1008 corresponding to non-selected row lines and non-selected column lines. As such, 0V is applied to the gate of the transistor of the memory cell, and 0V is applied to the column line, so no current flows.

Various studies on oxide film breakdowns performed on arrays different from the memory cells shown in Array 100 (Fig. 1) and Array 500 (Fig. 5) have resulted in breakdown of the ultrathin gate oxide film. Appropriate voltage levels are shown that allow controllable breakdown. When the ultrathin gate oxide film is exposed to voltage-induced stress, breakdown occurs in the gate oxide film. Although the actual mechanism leading to the breakdown inherent in the gate oxide film is not well understood, the breakdown process is a progressive process, through a soft breakdown (SBD) stage and a hard breakdown (SBD). HBD ") to the stage. One of the causes of the breakdown is considered to be a defective site of the oxide film. Only these defective sites act to cause breakdowns, or these defective sites create a positive feedback state that traps charges and leads to local high electric and high currents and thermal runaway. .. An improved formation process that achieves fewer oxide defects can reduce the occurrence of this type of breakdown. Another cause of breakdown is thought to be electron and hole traps at various sites that are also found in defect-free oxides, which also leads to thermal runaway.

Rasras et al. Conducted carrier separation experiments and showed that the electron shock ionization phenomenon in the substrate at positive gate bias is the dominant source of substrate Hall current--Mahmoud Rasras, Ingrid De Wolf, Guido Groeseneken, Robin. Degraeve, Herman e. See "Substrate Hall Current Sources After Oxide Breakdown" by Maes IEDM 00-537 2000--. A constant voltage stress experiment was performed on an ultra-thin oxide film in an array containing channel inversion, and this experiment used both SBD and HBD for data storage, and the desired level of SBD or HBD was achieved by the gated oxide storage device. It was confirmed that it can be obtained by controlling the time of stress. FIG. 11 shows a schematic cross-sectional view of the experimental device. When a constant voltage stress is applied to the ultra-thin gate oxide film, the phenomenon shown in the graph in Fig. 12 is observed. In Fig. 12, the x-axis represents the time in seconds and the y-axis represents the current in logarithms in amperes. .. FIG. 12 shows the gate-to-board hall current measured before and after soft and hard breakdown under constant voltage stress. Over approximately 12.5 seconds, the total current is substantially constant, I_gThe electron current measured by is dominant. Leaks are thought to be due to Fowler-Nordheim (FN) tunneling and stress-induced leak currents (SILC). At about 12.5 seconds, a large jump was observed in the measurement board hole current, indicating the start of soft breakdown (SBD). The total current remains substantially constant at this new level from about 12.5 seconds to about 19 seconds, although there are fluctuations in the substrate current. Large jumps in both the electron current and the substrate hole current at about 19 seconds indicate the onset of a hard breakdown (HBD). FIG. 10 shows that the desired level of SBD or HBD is obtained by controlling the amount of time the gate oxide memory device is stressed.

Sune et al. Studyed the conduction of ultrathin silicon dioxide films after SBD--Jordi Sune, Enrique Miranda's "SiO"₂Conduction after soft breakdown of gate oxide film, see IEDM 00-533, 2000-. Figure 13 shows the various stages of the current-voltage (IV) characteristics of the ultra-thin gate oxide film as it deteriorates. In this figure, the x-axis represents the voltage in volts and the y-axis represents the current. Is expressed as a logarithmic unit in amperes. FIG. 13 shows that a wide range of voltages is used to write to the gate oxide storage device and either SBD or HBD is used to store information in the gate oxide storage device. The figure also includes some IV characteristics after breakdown, showing the progression from SBD to HBD. These two extremes as well as SBD and HBD The amount of leakage current in the intermediate state of the above changes linearly depending on the magnitude of the voltage in the range of about 2.5V to 6V when viewed roughly.

Wu et al. Studyed the voltage dependence of voltage acceleration on ultrathin oxides--see EYWu et al., "Voltage Dependence of Voltage Acceleration Oxide Breakdown in Ultrathin Oxides", IEDM 00-541, 2000. Figure 14 shows the 63% confidence level (T)._BDIs obtained as a measured value with a variation (distribution), and indicates the time at 63% in order from the smallest value). The graph of the time to the breakdown at the gate voltage is shown on a half-logarithmic scale. It was obtained by measuring an n-channel FET (inversion) whose oxide film thickness changes in the range of 2.3 nm to 5.0 nm. The distributions are roughly consistent and linear, indicating that the process is controllable.

Miranda et al. Detected continuous breakdown, with an oxide film thickness of 3 nm, 6.4 x 10^-5cm²Measured the IV characteristics of nMOSFET devices in the area of--Miranda et al., "SiO"₂Analytical Modeling of Leakage Currents Through Multiple Breakdown Paths of Membranes, IEEE 39^th See Annual International Reliability Physics Symposium, Orlando, FL, 2001, pp 367-379. FIG. 15 shows the results corresponding to the linear region, where N is the number of conductive channels. The results are quite linear, indicating that the path is essentially resistant.

The memory array 100 shown in FIG. 1 is actually part of a memory integrated circuit that includes many other known components such as sense amplifiers, pull-up circuits, wordline amplifiers, sense amplifiers, decoders, and voltage multipliers. .. An exemplary memory 1600 is shown in FIG. 16, which includes control logic 1602, address latch 1604, high voltage pump 1606, Y decoder 1608, X decoder 1610, I / O buffer 1612, sense amplifier 1614, and memory array 100. Alternatively, it includes a memory cell array 1616 similar to the memory array 500. The high voltage pump 1606 is shown in the tables of Figures 8 and 9 and is useful in some arrays that require a high write voltage, such as 7.0V. High voltage is delivered to the line as required. In FIG. 16, high voltage is required only in the column or Y line, as the numerical arrangement in the table in FIG. 8 shows. The use of these components, and their use in the context of well-defined memory arrays with well-defined operating parameters, is otherwise known in the art and will be discussed further here. do not do. The memory 1600 is just an example and requires many other techniques such as addressing the memory array, transferring data to and from the memory array, and supplying the various operating voltages required by the memory array. It will be appreciated that it can be used according to.

The memory incorporating the memory array 100 is preferably formed using an advanced process, which in this case forms an n-type gate element, a p-type gate element, or both types of elements. Can be a gate dielectric thin enough to produce an SBD or HBD in a practical time when stressed using a voltage lower than the junction voltage or the maximum film thickness oxide breakdown voltage available. Any process can be used as long as it can realize the above. Advanced CMOS logic processes are just right and are described in the literature, see, for example, US Pat. No. 5,700,729 by Lee et al., Issued December 23, 1997. Processing services using such processes are available through a variety of manufacturers, Taiwan Semiconductor Manufacturing Company, Ltd. of Taiwan Hsinchu and California San Jose. ("TSMC"); United Microelectronics Corporation (UMC) in Hsinchu, Taiwan; and Cartered Semiconductor Ltd. in Singapore and San Jose, California. Which can be mentioned. However, any of a large number of different MOS processes that use different lithography may be used, and these lithographys are not limited to the currently generally available 0.25 μm, 0.18 μm, 0.15 μm, 0.13 μm, and the like. Included in form, it is expected that lithography of 0.10 μm or less will be generally available in the future.

All of the various MOS transistors, MOS half transistors, and MOS transistors used in the various memory cells described herein are, in most cases, ordinary low voltage logic transistors, which are eg, for example. It has an ultrathin gate oxide film thickness on the order of 50 angstroms for a 0.25 μm process or 20 angstroms for a 0.13 μm process. The voltage applied to such an ultra-thin gate oxide film is temporarily V during the writing operation._CCMuch higher than this V_CCIs typically 2.5 V for integrated circuits formed using the 0.25 μm process and 1.2 V for integrated circuits formed using the 0.13 μm process. Such ultrathin oxides can usually withstand voltages up to 4 or 5V and do not cause significant degradation in transistor performance. Exposing the cell selection transistor to a voltage greater than about 4V--this corresponds to the voltage shown in the table in Figure 9--when using a voltage for the memory array, the cell selection transistor has a thicker gate oxide film. It is preferable to form the half transistor or the capacitor so as to have an ultra-thin gate oxide film. Many CMOS logic processes allow the formation of both ultrathin gate oxides and thick oxides for input / output (I / O), in which case thick oxides are formed, for example for 3.3 volt I / O. It is about 70 angstroms in the integrated circuit to be used, and about 50 angstroms in the integrated circuit formed for 2.5 volt I / O.

Reprogrammable memory cells can be formed using the principles and structures discussed above. Therefore, reprogrammable memory cells can be used to form reprogrammable memory arrays. In particular, by controlling the degree of breakdown of the ultra-thin film dielectric of a half transistor or capacitor, it is possible to show the data stored in the memory cell by utilizing the amount of current drawn by the memory cell during the read operation. .. In this way, the memory cell can be rewritten by continuously increasing the degree or magnitude of the breakdown of the ultrathin film dielectric.

As mentioned above, the amount of current drawn during memory cell readout depends on the degree of breakdown of the ultrathin film dielectric. In this way, the current drawn from the memory cell is greater in the hard breakdown state, followed by the soft breakdown state. Similarly, the current drawn from the memory cell is greater in the soft breakdown state, followed by the no breakdown state. Further, as shown above, the ultrathin film dielectric can be placed in any one of several (or multiple) breakdown states ranging from no breakdown to hard breakdown.

As an example for further explanation, it is considered that the current is drawn during the read operation in the soft breakdown state. However, if the memory cells are not written, the ultrathin film dielectric is not stressed by breakdown at all, and no current is drawn during the read operation. When a memory cell is written for the first time in this state, the current drawn from the unwritten memory cell is extremely small, probably on the order of less than 1 picoamper (pA). For these memory cells, which are written for the first time and are normally in the first soft breakdown state, the current drawn during the write operation is several discontinuities, probably on the order of more than 10 picoamps. .. Therefore, unwritten memory cells that draw very little current (less than 1pA) and written memory cells that draw more than 10pA by the read operation after the first write. Can be distinguished from Le. It should be understood here that the drawn current depends in large part on the planar shape of the memory cell, and the example discussed above is merely an example. Therefore, there is no problem even if the lead-in current has another magnitude. What is important is that there is a difference between the amount of current drawn from the written memory cell and the amount of current drawn from the unwritten memory cell. This difference must be large enough for the current sense device.

Such reprogrammable memory cells (and the individual memory cells that make up the memory array) are rewritten by gradually increasing the stress applied to the ultrathin film dielectric layer to bring it into the second state of breakdown. Can be done (ie, a second write and a subsequent number of writes are made). This is achieved by using a higher write voltage or by writing to a selected memory cell that is writable by applying the write voltage over a longer period of time. Either technique can be used, but the important thing is to put the dielectric in a more stressed state because the ultrathin film dielectric of the cell in which it is being written causes greater breakdown.

It has been found that an increase in the stress voltage of 1 volt shortens the breakdown time by about 3 orders of magnitude. As an example, for a 20 angstrom thick gate oxide, a breakdown at 4 volts takes about 1 second, while a breakdown at 5 volts takes about 1 millisecond.

According to the present invention, the breakdown of the gate oxide film can be controlled by controlling the voltage applied to the gates of the row selection transistors 115, 116, 117, and 118 of FIG. The row selection transistor is a transistor that selects a specific row to be written. These row selection transistors are controlled by lines R1, R2, R3, and R4 in FIGS. 1 and 5.

By controlling the gate voltage, the amount of current used for writing to the half transistor can be finely controlled. In this way, by applying different levels of gate bias to the row selection transistor during writing, the amount of current that causes breakdown can be controlled. For example, the voltage applied to the gate oxide film can be kept constant, and the write time can be kept constant, but the gate bias for the row selection transistor is used to control the amount of current that causes the gate oxide film to break down. be able to. In this way, the magnitude of breakdown with respect to the gate oxide film can be controlled more accurately.

In fact, the amount of current during the readout operation has been found to be related to the amount of current used to break down the gate oxide film. In other words, the post-breakdown current is related to the current used to initially break down the gate oxide film.

As can be seen from FIG. 13, by putting the ultra-thin film dielectric in different breakdown states, it is possible to make the current characteristics when reading the memory cells different. In the example shown in FIG. 13, five distinct breakdown states can be seen between the soft breakdown and the hard breakdown. For example, when a read voltage of 2 volts is used, the amount of current drawn by the memory cell changes from 5 nanoamperes (nA) in the memory cell in the first soft breakdown state. This is indicated by reference number 1301 in FIG. In the second breakdown state, the current drawn by the memory cell at a read voltage of 2 volts is on the order of 15 nA. This is indicated by reference number 1303. Moving further, in the third breakdown state, the current drawn by the memory cell is on the order of 1 microamp, as indicated by reference number 1305. In the fourth breakdown state, note The current drawn by the resell is on the order of 5 microamps, as indicated by reference number 1307. Finally, in the fifth breakdown state (hard breakdown), the current drawn by the memory cells is on the order of 0.5mA as indicated by reference number 1309.

Although five breakdown states are shown in FIG. 13, less or more discontinuous breakdown states can be executed in the rewrite process to increase the number of potentials in the rewrite cycle. A major limitation in increasing the number of rewrite cycles is that a current detection circuit must be formed that has the ability to distinguish between the various amounts of current drawn by the memory cell.

From one point of view, it is possible to "erase" a memory cell simply by increasing the current detection threshold. For example, if a current exceeding 15 nA is detected after the first write, it is considered that the memory cell is being written. If a current of less than 15 nA is detected, it is considered that the memory cell has not been written. By simply increasing the amount of current that the current detection circuit reacts to, the entire memory cell array can be erased to bring it into a "clean state." In this way, it is believed that all memory cells can be erased by raising the threshold to, for example, 5 microamps. This is because no memory cell (even a memory cell that has already been written) draws more than 5 microamps during the read operation.

As described above, in summary, each memory cell can be written to one of a plurality of breakdown states. When rewriting is performed, various memory cells are written and a plurality of breakdown states can be obtained, so that the current drawn by the memory cells gradually increases. The current is detected by the sense amplifier 1614 to determine if a write has been made to the memory cell. Judging that all cells hold one data state when no current can be drawn from the cell above a given threshold (which changes as the voltage on and off the memory array is repeated throughout the rewrite procedure). Will be done. All memory cells that exhibit a draw current that exceeds a predetermined threshold will indicate a different memory state.

The description of the present invention and its applications shown in this specification is an example, and is not made to limit the technical scope of the present invention. It will be apparent to those skilled in the art that the embodiments disclosed herein can be modified and modified, and that, in practice, alternatives and equivalents of the various components of the embodiment can be implemented. Is. For example, when it comes to the exact voltage, it is somewhat free to choose within a certain voltage range, and in any case the voltage depends on the device characteristics, so the various examples shown in the various examples. Voltage is just an example. The terms row line, column line, and source line have been used to describe the types of lines commonly used in memory, but do not apply to some memory alternatives to the above memory. Generally speaking, row lines can be thought of as a special type of selection line, and column lines and source lines can be thought of as a special type of access line. These and other modifications and variations of the embodiments disclosed herein can be made without departing from the technical scope and ideas of the present invention.

<figref num="1">Schematic circuit diagram of a part of the memory array according to the present invention.</figref><figref num="2">Partial layout diagram of the memory array shown in Figure 1.</figref><figref num="3">Sectional drawing of a part of the integrated circuit structure of the memory array corresponding to FIG.</figref><figref num="4">FIG. 3 is a cross-sectional view of a modified example of the integrated circuit structure of FIG.</figref><figref num="5">Schematic schematic of a portion of another type of memory array according to the present invention.</figref><figref num="6">A partial layout diagram of a part of the memory array shown in FIG.</figref><figref num="7">Sectional drawing of a part of the integrated circuit structure of the memory array corresponding to FIG.</figref><figref num="8">A table showing the voltage.</figref><figref num="9">A table showing the voltage.</figref><figref num="10">A table showing the voltage.</figref><figref num="11">Sectional view of the experimental device.</figref><figref num="12">The graph which shows the effect when the stress of a constant voltage is applied to the ultra-thin gate oxide film.</figref><figref num="13">A graph showing various stages of the current-voltage characteristics of an ultrathin gate oxide film as deterioration progresses.</figref><figref num="14">A graph showing the characteristics of the time-to-gate voltage at a breakdown level of 63% reliability measured for an n-channel field effect transistor (inversion) on a half-logarithmic scale for each of various oxide film thicknesses.</figref><figref num="15">The graph which shows the current-voltage characteristic of an n-type element measured after detecting the continuous breakdown phenomenon.</figref><figref num="16">Schematic diagram of a block of semiconductor memory.</figref>