Computational resource allocation in an information stream decoder
14 claims: 11 independent, 3 dependent
- 1圧縮ビデオストリームを復号化するシステムにおいて、 前記圧縮ビデオストリームのソース ビデオ フォーマットを識別するステップと、 少なくとも前記識別されたソース ビデオ フォーマット と生成すべき解凍ビデオストリームの出力ビデオフォーマットであって記憶又は受信された該出力ビデオフォーマットと に基づいて、 前記ソースビデオフォーマット及び前記出力ビデオフォーマットを表す 信号を生成するステップと、 生成された前記信号に応じて、少なくとも逆離散コサイン変換(IDCT) 関数 と、前記IDCT 関数によって復号された 画素ブロックを 構成する 信号を受信してリサイズされた画素ブロックを構成する信号を提供するよう構成された補間関数 とを実行するよう、割当可能計算リソースのうち 計算リソースを割り当てるステップ であって、前記ソースビデオフォーマットのソース画像サイズの増加に応じて、前記IDCT関数を実行するよう割り当てられる計算リソースを増加させ、前記ソースビデオフォーマットのソース画像サイズに対する前記出力ビデオフォーマットの出力画像サイズの増加に応じて、前記補間関数を実行するよう割り当てられる計算リソースを増加させる、該ステップ と、 割り当てられた前記計算リソースを用いて、 前記圧縮ビデオストリームを 復号 して、前記出力 ビデオ フォーマットを有する前記解凍ビデオストリームを生成するステップと、を含む方法。
- 2前記IDCT 関数 が、複数のIDCT関数ソフトウエアルーチンに関連付けられており、前記複数のIDCT関数ソフトウエアルーチンの各々が一以上のソース ビデオ フォーマットに関連付けられており、 前記計算リソースが、前記識別されたソース ビデオ フォーマットに関連付けられている前記IDCT関数ソフトウエアルーチンの少なくとも一つを実行することによって割り当てられる、請求項1に記載の方法。
- 3前記IDCT 関数 が、複数のIDCT関数ソフトウエアルーチンに関連付けられており、前記複数のIDCT関数ソフトウエアルーチンの各々が一以上のソース ビデオ フォーマットに関連付けられており、 前記補間関数が、複数の補間関数ソフトウエアルーチンに関連付けられており、前記複数の補間関数ソフトウエアルーチンの各々が一以上の出力 ビデオ フォーマットに関連付けられており、 前記計算リソースが、前記識別されたソース ビデオ フォーマットに関連付けられているIDCT関数ソフトウエアルーチンと前記出力 ビデオ フォーマットに関連付けられている補間関数とを実行することによって割り当てられる、請求項1に記載の方法。
- 4前記割当可能計算リソースのうちの 計算リソースが、 更に、走査線への変換関数に割り当てされ 、 前記IDCTが複数のIDCT関数ソフトウエアルーチンに関連付けられており、前記複数のIDCT関数ソフトウエアルーチンの各々が一以上のソース ビデオ フォーマットに関連付けられており、 前記ブロックから走査線への変換関数が、複数のブロックから走査線への変換関数ソフトウエアルーチンに関連付けられており、前記複数のブロックから走査線への変換関数ソフトウエアルーチンの各々が一以上のソース ビデオ フォーマットと一以上の出力 ビデオ フォーマットに関連付けられており、 前記計算リソースが、前記識別されたソース ビデオ フォーマットに関連付けられているIDCT関数ソフトウエアルーチンと、前記識別されたソース ビデオ フォーマットと前記出力 ビデオ フォーマットに関連付けられているブロックから走査線への変換関数とを実行することによって割り当てられる、請求項1に記載の方法。
- 5前記識別されたソース ビデオ フォーマットがソースピクチャ解像度を含み、 前記ソースピクチャ解像度の増加に応じて、前記IDCTに割り当てられる前記計算リソースが増大し、また前記補間関数に割り当てられる前記計算リソースが減少する、 請求項1に記載の方法。
- 6圧縮ビデオストリームを復号化するシステムにおいて、 割当可能 計算リソースを割り当てする方法であって、 前記圧縮ビデオストリームのソース ビデオ フォーマットを識別するステップと、 少なくとも前記識別されたソース ビデオ フォーマット と記憶又は受信された出力ビデオフォーマット に基づいて、 前記ソースビデオフォーマットと前記出力ビデオフォーマットと を示す信号を生成するステップと、 生成された 前記信号 に応じて、 逆離散コサイン変換(IDCT)関数と、前記IDCT関数によって復号された画素ブロックを含む信号を受信するよう構成された補間関数とを実行するよう、 前記 割当可能 計算リソースから計算リソースを割り当てるステップ であって、前記ソースビデオフォーマットのソース画像サイズが増加する場合に、前記IDCT関数を実行するよう割り当てられる計算リソースを増加させ、前記ソースビデオフォーマットのソース画像サイズに対して前記出力ビデオフォーマットの出力画像サイズが増加する場合に、前記補間関数を実行するよう割り当てられる計算リソースを増加させる、該ステップ と、 割り当てられた 前記計算リソース を使用して、前記圧縮ビデオストリームを 復号 し解凍ビデオストリームを生成するステップと、を含む方法。
- 7前記IDCT関数が、前記圧縮ビデオストリーム内の離散コサイン変換(DCT)ブロックを 前記 画素ブロックに変換するように動作し、 前記補間関数は、前記画素ブロックを受信してリサイズされた画素ブロックを構成する信号を提供し、 第1操作モードにおいて、前記補間関数が前記画素ブロックのライン数とライン当りの画素数の少なくとも一つを増大するよう動作し、 第2操作モードにおいて、前記補間関数が、前記画素ブロックのライン数とライン当りの画素数 のいずれも 増大させるように動作しない、請求項 6 に記載の方法。
- 8前記識別されたソースフォーマットが、第1値によって規定されたライン数と第2値によって規定されたライン当りの画素数とを有するビデオ画像に関連付けられており、 前記出力フォーマットが、第3値によって規定されたライン数と第4値によって規定されたライン当りの画素数とを有するビデオ画像に関連付けられており、 前記第1操作モードが、前記第3値よりも小さい前記第1値と前記第4値より小さい第2値の少なくとも一つに応じて入る、請求項 7 に記載の方法。
- 9前記第2操作モードが、前記第3値以上の前記第1値 、且つ、 前記第4値以上の第2値に応じて入る、請求項 8 に記載の方法。
- 10前記IDCT関数が、前記圧縮ビデオストリーム内のDCT係数ブロックを 前記 画素ブロックに変換するように動作し、 前記補間関数が、前記画素ブロックの 各々の ライン数を増大させるように動作し、 前記ライン数の前記増大が、前記ソース ビデオ フォーマットと表示デバイスの 前記出力ビデオ フォーマット間の垂直方向サイズの増大に関連する、請求項 6 に記載の方法。
- 11前記 割当可能 計算リソースから割り当てられていない計算リソースを使用して、前記割り当てられた計算リソースによって 復号 された 前記 画素ブロックの垂直サイズと水平サイズの少なくとも一つをリサイズするステップを更に含む請求項 7 に記載の方法。
- 12圧縮ビデオストリームを復号化するシステムにおいて、割当可能計算リソースを割り当てする方法であって、 前記圧縮ビデオストリームのソースビデオフォーマットを識別するステップと、 前記ソースビデオフォーマットと記憶又は受信された出力ビデオフォーマットとを示す信号を生成するステップと、 生成された前記信号に応じて、割当可能計算リソースを、 逆離散コサイン変換(IDCT)関数と補間関数とブロックから走査線への変換関数とのうちの少なくとも一つを実行するように割り当て るステップであって 、 前記ソースビデオフォーマットのソース画像サイズが増加する場合に、前記IDCT関数を実行するよう割り当てられる計算リソースを増加させ、前記ソースビデオフォーマットのソース画像サイズに対して前記出力ビデオフォーマットの出力画像サイズが増加する場合に、前記補間関数を実行するよう割り当てられる計算リソースを増加させる、該ステップと、 割り当てられた前記計算リソースを使用して、前記圧縮ビデオストリームを復号し解凍ビデオストリームを生成するステップと、 を含み 前記IDCT関数が前記圧縮ビデオストリーム内の複数のDCT係数ブロックを複数の変換された画素ブロックへと変換し、 前記補間関数が、前記複数の変換された画素ブロックのライン数とライン当たりの画素数の少なくとも一つを増加させることによって複数の補間された画素ブロックを作り出し、 前記ブロックから走査線への変換関数が、前記複数の変換画素ブロック又は前記複数の補間された画素ブロックの何れかを複数のビデオ走査線に変換する、方法。
- 13ソースビデオフォーマットを有する圧縮ビデオストリームを処理して出力ビデオフォーマットを有する解凍ビデオストリームを生成する装置であって、 少なくとも逆離散コサイン変換(IDCT)関数 と前記IDCT関数によって復号された画素ブロックを含む信号を受信してリサイズされた画素ブロックを構成する信号を提供するよう構成された補間関数 を実行するための割当可能計算リソースを含むデコーダであって、複数の画素ブロックを含む前記解凍ビデオストリームを生成するよう前記圧縮ビデオストリームを復号化するためのデコーダと、 少なくとも ソースビデオフォーマットを受信し、 該ソースビデオフォーマットを示す 信号を 前記デコーダに対して 生成し、前記生成された信号と前記解凍ビデオストリームの前記出力フォーマットに応じて前記割当可能計算リソースを適合させるコントローラ であって、前記ソースビデオフォーマットのソース画像サイズの増加に応じて、前記IDCT関数を実行するよう割り当てられる計算リソースを増加させ、前記ソースビデオフォーマットのソース画像サイズに対する前記出力ビデオフォーマットの出力画像サイズの増加に応じて、前記補間関数を実行するよう割り当てられる計算リソースを増加させる、該コントローラ と、を具備する装置。
- 14前記IDCT関数が 圧縮比1:SFを有する 縮小サイズ画素ブロックを生産するように動作し、 前記SFは、前記ソースビデオフォーマットの前記ソース画像サイズの前記出力ビデオフォーマットの前記出力画像サイズに対する比を示すスケーリングファクタであり、 予測画素ブロックに関連する動きベクトル情報を受信し、該動きベクトル情報から前記スケーリングファクタに応じてスケーリングされた動きベクトルを生成するための動きベクトルプロセッサを更に含む請求項 13 に記載の装置。
Independent claims14
1 paragraph, as filed
[0001] The present invention claims the benefit of US Patent Provisional Application No. 60/060112 filed on September 26, 1997, which is incorporated herein by reference in its entirety. [0002] The present invention relates generally to video processing systems, more specifically video processing systems capable of receiving and processing multiple video signal formats such as various high-definition and standard-grade formats. [0003] (Background of invention) Current television receivers, such as NTSC (National Television Standards Committee) television receivers, generally have to process video signals that are compatible with only a single given video format. Includes a video processing circuit that does not have to be. Future Digital Television (DTV) receivers will be the Advanced Television Standards It is expected to be implemented substantially based on the transmission criteria established by the Committee) (ATSC). Similar standards are in the European Digital Video Broadcasting (DVB) standards. Compressed digital video systems are disclosed in ATSC Digital Television Standards A / 53, the contents of which are incorporated herein by reference. In addition, the Moving Picture Experts Group (MPEG) has promulgated several standards for digital data delivery systems. The first standard, known as MPEG-1, is ISO / IEC standard 11172, which is incorporated herein by reference. The second standard, known as MPEG-2, is ISO / IEC standard 13818, which is incorporated herein by reference. [0004] The new DTV standard allows broadcasters to visually deliver formats up to 1920 x 1080 pixels. In particular, DTV receivers have spatial resolution (480 lines, 720 lines or 1080 lines),<u style="single">Time</u>It must be able to receive source video consisting of image sequences that vary in resolution (60fps, 30fps or 24fps) and scanning format (2: 1 interlaced or progressive scan). In addition, it is desirable to convert the format of the received video signal to the preferred format of the display device used with respect to the receiver (ie, the "native format"). [0005] In one prior art approach, the format of the received television signal is subject to electronic scanning transformations (interpolation, filtering and / or decimation) to format the television signal within a particular DTV receiver. Conforms to the "native display format" of the display device used. Conventional techniques that utilize this approach first decode the received television signal and then decompress the video information within that signal to provide a video information stream. The video information stream is subject to, for example, vertical and / or horizontal interpolation or filtering or digitization to adapt the format of the video signal to the native format of the display device. Further, it is known to use frame rate conversion processing to adapt the frame rate (ie, 24Hz, 30Hz, 60Hz) to the frame rate native to the display processing circuit. [0006] The prior art described above, which applies a large number of format television signals to a particular native display format,<u style="single">Unfortunately,</u>Use the same computational resources regardless of the format of the received television signal or the native format of the display device. Therefore, even when applying a low resolution television signal to a low resolution native display format, the computational resources used by the video decoder mediate the high resolution format television signal, the low or high resolution native display format television signal. It is the same as used to apply to. [0007] Therefore, the computational resources of the video decoder (ie, processing and memory resources), the type of signal received, and<u style="single">、</u>Native display format for DTV receivers<u style="single">To</u>Or the native processing format of a video processing system such as a video editing system<u style="single">Adapt to its proper decoding to</u>Seems desirable. [0008] (Outline of the invention) The present invention provides a format indicia contained within a compressed information stream.<u style="single">Depending on</u>Includes methods and equipment for allocating processing resources within the information stream decoder. In particular, the present invention decodes video streams with related video formats in the same or different formats.<u style="single">Includes devices and methods for producing decrypted video streams with. Here, computational resources are allocated according to format changes between the associated video format and the resulting video format.</u>[0009] The present invention formats a received video or television signal.<u style="single">Efficient allocation of processing resources according to</u>Provides a multi-format video signal processing system. The present invention relates to, for example, various storage media, video or television.<u style="single">Standard</u>And / or can be used to reformat or transcode video information between formats.<u style="single">The present invention is advantageously used within a digital television (DTV) system to adapt the received video format to the native display format.</u>[0010] The present invention is of the inventor<u style="single">Findings</u>Is based on a part of<u style="single">To. This finding is</u>Compressing different image sizes requires different computational resources, and larger interpolation (more) when smaller image sizes are decoded (using less IDCT resources), especially for high resolution native display formats. Filter tap calculation) is required<u style="single">Is that</u>.. [0011] In one embodiment of the invention, the video decoder architecture senses the format of the received television signal and<u style="single">Depending on</u>, Between inverse discrete cosine transform (IDCT operation) and vertical and / or horizontal interpolation and / or decimation operation<u style="single">Arithmetic logic</u>Allocate resources. [0012] In the present invention<u style="single">Is a based method</u>A good method to use for systems to decrypt compressed video streams is to identify the source format of the compressed video stream, and<u style="single">Identified</u>Using the source format,<u style="single">Determine suitable computational resource requirements to process a compressed video stream to produce a decompressed video stream with an output format</u>Steps and determined resources<u style="single">required amount</u>To<u style="single">Depending on</u>Includes at least the step of allocating computational resources to perform the Inverse Discrete Cosine Transform (IDCT) and the step of processing the compressed video stream to generate a decompressed video stream with an output format. [0013] The teachings of the present invention can be easily understood by considering the following detailed description of the accompanying drawings. [0014] The same reference numbers are used for the same elements throughout the figure for ease of understanding. [0015] (Detailed explanation) The present invention claims the benefit of US Patent Provisional Application No. 60/060112 filed on September 26, 1997, and is incorporated herein by reference in its entirety. [0016] The present invention will be described within the concept of MPEG-like decoders and format converters. Although the present invention is extremely useful in digital television (DTV) receivers, eg ATSC television receivers, the present invention applies to DVB, MPEG-1, MPEG-2 and other information streams. It is clear to those skilled in the art that it is applicable to multi-format video processing systems including. For example, the present invention relates to various storage media, video or television.<u style="single">Standard</u>It can also be used to reformat video information between and / or formats or to transcode receivers. [0017] FIG. 1 shows a high-level block diagram of a video decoder based on the present invention. In particular, the video decoder and processing apparatus of FIG. 1 consists of an MPEG-like decoder that receives a compressed video information stream IN and decodes it to generate a video output stream OUT on a block-by-block basis. The video output stream OUT is suitable, for example, to be coupled to a display driver circuit of a presentation device (not shown). The display format of the video output stream is adjusted by a resizing operation in either the Discrete Cosine Transform (DCT) domain or the Pixel domain. [0018] The MPEG-like decoder 100 includes an input buffer memory module 111, a variable length decoder (VLD) module 112, an inverse quantizer (IQ) module 113, a block memory module 114, and movement.<u style="single">compensation</u>It includes module 116, anchor frame memory module 117, assignable processor 120, optional vertical resizer module 142, optional horizontal resizer module 143 and controller 130. The assignable processor 120 has an inverse discrete cosine transform (IDCT) function 122,<u style="single">Addition</u>The function 124, the interpolation function 126, and the block-to-scan line conversion function 128 are executed. The assignable processor 120 also includes a block memory module 129 and works with various elements within the allocateable processor 120 to provide, for example, intermediate storage of block domain and / or scan line domain video information. [0019] Vectors are all of the same type and are a series of scalar data items stored in memory. Vector elements are ordered to have a fixed addressing increment between consecutive elements called strides. A vector processor is a group of hardware resources that includes vector registers, function pipelines, processing elements and / or register counters to perform vector operations. Vector processing operations occur when arithmetic or logical operations are applied to a vector. Vector processing operations are distinguished from scalar processing operations and are calculated on one or a pair of data. In general, vector processing operations are faster and more effective than scalar processing operations, as is well known to those skilled in the art of advanced computer architectures. This type of data can be modified to uniquely order the video data (ie, rows, columns, frames, fields, etc.) and the compressed video data (ie, slices, macroblocks, blocks, etc.). Vector processing is operated. [0020] The assignable processor 120 is a vector processor, a plurality of scalar processors in a multiprocessor environment, or<u style="single">any</u>It includes many assignable processing resources such as other processing systems, the arithmetic and / or logical processing resources of which can be allocated using hardware, software or a combination of hardware and software. Therefore, the assignable processor 120 will be described first within the context of the vector processing apparatus, but this description is for illustrative purposes only, and the present invention is not limited to the vector processing configuration. I want you to understand. [0021] [0021] The assignable processor 120 of a typical embodiment has IDCT function 122,<u style="single">Addition</u>It should be noted that the function 124, the interpolation function 126 and the block-to-scan line conversion function 128 are executed, but not all of these functions need to be included in the assignable processor 120. Allocable processor 120<u style="single">But</u>Including these functions<u style="single">What you are doing</u>Of the typical MPEG-like encoder 100 in Figure 1.<u style="single">In the situation, by such inclusion,</u>Regarding the semiconductor field, system complexity, and therefore unit cost<u style="single">do it,</u>MPEG-like encoder<u style="single">Implementation</u>Low total cost<u style="single">Because it becomes</u>.. Similarly, the block memory 129 can also be a separate module. [0022] In one embodiment of the invention, the assignable processor 120 includes only the IDCT function 122 and the interpolation function 126.<u style="single">Addition</u>The function 124 and the block-to-scan line conversion function 128 are executed by dedicated hardware. Similarly, the interpolation function 126 is a vertical interpolation function only, a horizontal interpolation function only, or a vertical interpolation function and a horizontal interpolation function.<u style="single">of</u>Offer both. [0023] The input buffer memory module 111 outputs a compressed video stream IN, for example, a high definition television signal (HDTV) or standard definition television signal (SDTV) output from a transport demultiplexer / decoder circuit (not shown). Receives the represented variable length encoded bitstream. The input buffer memory module 111 is used to temporarily store the received compressed video stream IN until the variable length decoder module 112 is ready to allow video data for processing. The VLD 112 has an input coupled to the data output of the input buffer memory module 111, for example searching for variable length encoded video data stored as data stream S1. [0024] VLD112 decodes and quantizes search data<u style="single">Forecast</u>Generates a constant length bitstream S2 containing the error DCT coefficient, motion vector stream MV and block information stream DATA. IQ module 113 is a constant length bitstream S2<u style="single">Against</u>Perform an inverse quantization operation to quantize in the standard form, ie the DCT coefficient<u style="single">Forecast</u>Generate a DCT coefficient vector S3 containing the error coefficient. [0025] The IDCT function 122 of the assignable processor 120 has a DCT coefficient vector S3.<u style="single">Against</u>Perform an inverse discrete cosine operation,<u style="single">Pixel by pixel</u>of<u style="single">Forecast</u>Generates the data vector S4 containing the error. Assignable processor 120<u style="single">arithmetic</u>And / or logical resources are based on several factors<u style="single">Be</u>Assigned to IDCT function 122. This will be described in detail below. Briefly, resources are, for example,<u style="single">Received video signals, native video formats such as native display device formats, some combinations of received video formats and native video formats, and other elements</u>Assigned based on. [0026] Assignable processor 120<u style="single">Addition</u>Function 124 moves<u style="single">compensation</u>Motion generated by module 116<u style="single">Compensation forecast</u>Pixel value stream S6 and error stream S4 for each pixel<u style="single">Addition</u>Perform the operation. Therefore,<u style="single">Addition</u>The output of function 124 is, in a typical embodiment, a video stream S5 containing the reconstructed pixel values in the pixel block format.<u style="single">Addition</u>The video stream S5 generated by function 126 is combined with anchor frame memory 117 and interpolation function 126 of allocatable processor 120. The anchor frame memory module 117 receives and stores these pixel blocks associated with the anchor frame in the compressed video stream S5. [0027] Movement<u style="single">compensation</u>The module 116 receives the motion vector stream MV from the VLD 112 and accesses the image information stored in the memory module 117 via the signal path S7. Motion vector stream MV is motion<u style="single">compensation</u>Each macroblock contains motion vector information used by module 116 and is based on image information stored in anchor frame memory module 117.<u style="single">Forecast</u>To do. Movement<u style="single">compensation</u>Module 116 is one or more stored anchor frames (eg,<u style="single">Addition</u>Multiple block of pixels generated for the most recent I-frame or P-frame of the video signal generated at the output of function 124) and the motion vector MV received from VLD112.<u style="single">Forecast</u>Calculate the value for each of the blocks. plural<u style="single">Forecast</u>Each of the blocks moves<u style="single">Compensation forecast</u>As pixel value stream S6<u style="single">Addition</u>Combined with the input of function 124. [0028] Interpolation function 126 of assignable processor 120 performs vertical and / or horizontal interpolation operations.<u style="single">Addition</u>Resize the pixel block in the video stream S5 generated by function 124. The amount of resizing given to the pixel block is determined with respect to the control signal SIZE generated by controller 130. The interpolation function can also include a vertical interpolation function, a horizontal interpolation function, or both a vertical interpolation function and a horizontal interpolation function. Interpolation function 126 of the assignable processor 120 is used to increase the vertical and / or horizontal dimensions of the pixel block. For example, a relatively low resolution (eg, SDTV) input video signal can be displayed on a relatively high resolution (eg, HDTV) display device using a more available display area that is practically possible. [0029] Vertical interpolation, for example, within a pixel block<u style="single">Additional</u>It can be executed so as to increase the vertical dimension of the pixel block by calculating and inserting the pixel line. For example, an 8x8 block for a 480-line image can be increased to an 8x18 pixel block for display on a 1080-line display device. [0030] Horizontal interpolation, for example, in each line of pixels in a pixel block<u style="single">Additional</u>This is done by increasing the horizontal dimension of the pixel block by calculating and inserting pixels. For example, an 8x8 pixel block for 640 pixels per line video would be increased to a 16x8 pixel block to display on 1280 pixels per line display device. [0031] Vertical and horizontal interpolation is performed, eg in a pixel block<u style="single">Additional pixels</u>Calculate and insert lines and in pixel blocks<u style="single">Additional within each pixel line</u>The vertical and horizontal dimensions of the pixel block are increased by calculating and inserting the pixels. For example<u style="single">For 480-line pictures with 640 pixels per line</u>8x8 pixel block,<u style="single">For 1080 line displays with 1280 pixels per line</u>It can be increased to a 16x18 pixel block. [0032] Block-to-scan line conversion function of assignable processor 120 128<u style="single">Is</u>, Interpolation from block domain<u style="single">Was done</u>block<u style="single">Base of</u>Performs a conversion of the video stream S8 to the scanline domain. That is, the block-to-scan line conversion function 128 of the assignable processor 120.<u style="single">Is</u>Block generated by interpolation function 126<u style="single">Base of</u>Scan line video stream S8<u style="single">Base of</u>Convert to video stream S9. Scan line<u style="single">Base of</u>Video stream S9<u style="single">Is</u>, Optional vertical resizer 142, optional horizontal resizer 143 or output OUT. [0033] The optional vertical resizer 142 has a scanning line.<u style="single">Base of</u>Receives video stream S9 and also to signal VS from controller 130<u style="single">Depending on</u>, Scanning line<u style="single">Base of</u>Selectively change the number of vertical scan lines per frame of the video information contained in the video stream S9. Optional vertical resizer 142<u style="single">、</u>vertical<u style="single">Resized in the direction</u>Generate video signal S10. The optional vertical resizer 142 can increase the number of lines per video frame, for example by using interpolation techniques, and calculate the luminance and chrominance information of one or more new lines to be inserted between two existing lines. .. The optional vertical resizer 142 can also decimate video frames, for example, reduce the number of lines per video frame by using interpolation techniques, and calculate new scan lines at reduced line densities. [0034] In one embodiment of the invention, the optional vertical resizer 142 is used only to provide simple 2: 3 vertical interpolation to convert 720 line video to 1080 line video. In this embodiment, all other vertical interpolation functions (eg, 480 to 720, 480 to 1080, etc.) are performed by the interpolating function 126 of the assignable processor 120. [0035] The optional horizontal resizer 143 is a vertically resized video signal S10 (or scan line).<u style="single">Base of</u>Receives the video stream S9) and also to the control signal HS from the controller 130<u style="single">Depending on</u>, The number of image elements (pixels) per line of video information contained in the received video signal S10 or S9 is selectively changed. The optional horizontal resizer 143 produces a horizontally resized video signal OUT. The optional horizontal resizer 143 can be used, for example, by using interpolation techniques.<u style="single">Number of pixels per line</u>It is possible to calculate the luminance and chrominance information of one or more new pixels to be inserted between two existing pixels. The optional horizontal resizer 143 desimates the video line, for example by using interpolation techniques.<u style="single">hand</u>Reduce the number of pixels in the line<u style="single">By,</u>It is also possible to reduce the number of pixels per line. [0036] Controller 130<u style="single">Is</u>, Format (eg number of lines, number of pixels per line, frame rate, etc.), colorimetry<u style="single">、</u>And other information about the decrypted video signal S4 from VLD112<u style="single">, Header data signal via HD</u>Receive. Controller 130<u style="single">、</u>Utilizing this information and additional information such as the display or native display or processing format of the display or video processor (not shown) used in the present invention, the optional vertical size control signal VS for the optional vertical resizer 142, Generates the optional horizontal size control signal HS for the optional horizontal resizer 143. The controller 130 provides a control signal FR to a frame rate converter (not shown) to match the display or video processor native display or processing format used in the present invention with the frame rate of the output signal OUT. Used to convert to different frame rates (eg 60 frames per second to 30 frames per second). This native format information<u style="single">、</u>It can be stored in the controller 130 or optionally provided to the controller 130 via the control signal NATIVE FORMAT. [0037] Allocable processor 120<u style="single">Is</u>, To control signal A from controller 130<u style="single">Depending on</u>, Processing resources, for example vector processing resources, are allocated between the IDCT function 122 and the vertical interpolation function 126. Controller 130<u style="single">Is</u>For example, for input video signal IN formats and display or video processor native display or processing formats using the present invention.<u style="single">Depending on</u>, Vector processing resources<u style="single">But</u>Allocation between two functions<u style="single">To be able to</u>.. [0038] Allocable processor 120 also<u style="single">Addition</u>It provides virtually constant resources for function 124 and block-to-scanline conversion function 128. However, in one embodiment of the present invention, the resources allocated to the block-to-scan line conversion function 128 are not constant.<u style="single">this</u>In embodiments<u style="single">Is</u>, The resource was generated by the interpolation function 126<u style="single">Block-based video stream</u>To the size of the pixel block in S8<u style="single">To fit</u>Assigned. That is, as the size of the block increases, the resources allocated to the block-to-scan line conversion function 128 increase correspondingly to provide sufficient processing power. [0039] Allocable processor 120 to control signal SIZE from controller 130<u style="single">Depending on</u>, The size or resolution parameter of the block to be processed<u style="single">Adapt</u>.. That is, the received N × M (or N × N) DCT coefficient block imposed on the IDCT process generally produces an N × M (or N × N) pixel block. Controller 130<u style="single">Is</u>, The generated pixel block must be magnified, for example, in the vertical direction (ie, the 480 line block is magnified for use in 1080 line display).<u style="single">When</u>When determining, the control signal SIZE is used to support this type of expansion. to this<u style="single">Depending on</u>, Vertical interpolation function<u style="single">like this</u>It will provide enlargement (eg, 8x8 pixel blocks are converted to 8x18 blocks). [0040] The inventor notes that decompressing an information stream consisting of video information with different image sizes requires different computational resources. For example, as the image size of the video stream decreases, so does the computational resource required to perform the IDCT functions described above (ie, used to represent the pixel information within the frame of the reduced resolution video. A smaller DCT coefficient is processed over time due to the reduced number of DCT coefficient blocks). Similarly, as the image size of the video stream increases, so does the computational resource required to perform the IDCT functions described above (ie, to represent the pixel information within the frame of the increased resolution video). More DCT coefficients are processed over time due to the increasing number of DCT coefficient blocks used). The relationship between IDCT processing resources and image formats can be determined computationally or empirically. [0041] The inventor further resizes the decrypted video stream so that the display or native display or processing format of the video processor utilizing the decrypted video stream does not generally change so that, for example, a display device can be used. We are paying attention to the need to provide images that make the most of the display area. For example, assuming an HDTV display device is used to display a decoded video stream, it is required to perform the vertical and / or horizontal interpolation functions described above as the image size of the video stream decreases. Computational resources will increase (ie, compute more filter taps). Similarly, as the image size of the video stream approaches the native display format (or "letterbox" or if cropping techniques are used), the vertical and / or horizontal described above<u style="single">interpolation</u>The computational resources needed to execute the function will be close to zero (ie, no calculated filter taps are needed). [0042] Vertical and / or horizontal as described above<u style="single">Decimation</u>The computational resources required to execute the function are also the image size relative to the native format.<u style="single">Ratio</u>It should be noted that it changes with.<u style="single">Also,</u>The difference in frame rate between the transmitted video format and the native display format is a computational resource<u style="single">required amount</u>To<u style="single">Impact</u>To do<u style="single">Also paying attention to</u>.. For example, if the transmitted video format consists of 24 frames per second (fps) (eg movie), more time will be available to perform the interpolation, so an interpolation filter with more taps will be used. it can. [0043] In one embodiment of the invention, the IDTC function 122 of the assignable processor 120 comprises a vector processor (ie, the allocated portion of the available allocatable vector processing resource 120), exemplarily a multiple / accumulation of 8 taps. Execute the function. A local block of memory (ie, block memory module 114), actually an 8x8 pixel block, is used, which allows horizontal and vertical vector operations to be performed. When the transmitted video format does not require a large number of IDCT operations that consume all processing time (such as the received SDTV video stream), unused computational resources are allocated to perform the interpolation filter function. [0044] Horizontal interpolation function<u style="single">Is</u>, Block level<u style="single">so</u>, 8x8 blocks as an example<u style="single">To</u>One of the multiple block formats shown in Table 1 below<u style="single">To</u>interpolation<u style="single">Performed by</u>.. For example, referring to Table 1, the transmission video format (ie, source format) is the 480 line format (ie, SDTV) represented by 8x8 pixel blocks, and the display format is the 1080 line format (ie, SDTV). , HDTV)<u style="single">Conversion factor to view of source</u>Is 4: 9. In this way, the vector processor resources are used to be a 4: 9 interpolation function (ie, 480 lines vs. 1080 lines). This is achieved by changing the size of the blocks from 8x8 blocks to 8x18 blocks in the actual embodiment. It should be noted that the same method can be applied in the case of interpolated video, which is actually represented by an 8x4 pixel block. [table 1]<img file="JP4344472B2_D0001.tif" /> It should be noted that the 1280 * 720 and 1920 * 1080 modes make maximum use of IDCT processing resources. That is, in these modes, the assignable processor 120 has a resource in the IDCT function 122.<u style="single">Mostly</u>allocation<u style="single">Represents the situation</u>, Also this<u style="single">Mostly represent the allocation of resources for the largest IDCT function 122 based on the decision that the largest IDCT resources load the high resolution to be processed.</u>No resources are allocated to the interpolation function 126 because it is not necessary to execute the vertical interpolation function in this mode of operation (eg, depending on the native display format). [0045] Resize generated by interpolator function 126 of assignable processor 120<u style="single">Was done</u>Pixel block<u style="single">Is</u>, The block-to-scan line conversion function 128 is converted into a plurality of scan lines. For example, in the case of an 8x8 pixel block interpolated into an 8x18 pixel block, the block-to-scan line conversion function 128 has 18 video scan lines instead of 8 video scan lines due to the pixel block. To generate. Formed using interpolated pixel blocks in this method<u style="single">Picture</u>The vertical dimension of is increased in the vertical direction, for example, until the entire display area of the HDTV display device is used. In order to utilize the entire horizontal display area, the horizontal resizer 143 is placed within each scan line.<u style="single">Additional</u>Used to interpolate pixels, which increases the length or pixel count of each scanline<u style="single">May</u>.. [0046] Controller 130<u style="single">Is</u>The operation of the vertical interpolation function 126 and the horizontal resizer 143 of the assignable processor 120<u style="single">Adapt</u>Generate the output signal OUT. This output<u style="single">Is</u>It maximizes the display area of the display device or is adapted to the native or desired video format for the next processing. Controller 130 utilizes the vertical resizer 142 to vertically resize the previously resized scan mode video data by the vertical interpolation function 126 of the assignable processor 120.<u style="single">You have to be careful that you may</u>.. Therefore, the controller 130 can be assigned the processor 120<u style="single">Resource utilization</u>And the output video stream OUT quality level is arbitrarily balanced to match the input video signal to the native display or processing format to achieve the desired video decoding and formatting objectives. [0047] The interpolation function 126 of the assignable processor 120 is described in terms of increasing the number of pixels in the pixel block and / or the pixels per line. It should be noted that the interpolating function 126 of the assignable processor 120 can also reduce the number of pixels in the pixel block and / or the number of pixels per line. In one embodiment of the invention, reducing the number of lines and / or pixels per line in this way desimates the number of lines and / or pixels per line to reduce the vertical and / or horizontal resolution pixel block. Is executed by generating. This decimation is integer-based (ie,<u style="single">Every other or every three lines and / or pixels per line</u>), Or non-integer base (ie)<u style="single">Every other half line and / or pixels per line</u>)<u style="single">so</u>Can be executed. In the latter case, a combination of decimation and interpolation is needed to produce the desired vertical and / or horizontal resolution for the pixel block. This function processing will be further described in the embodiment of FIG. [0048] In the MPEG-like decoder 100 described above, the IDCT function 122 of the assignable processor 120 operates on a standard size DCT coefficient block, such as an 8 × 8 DCT coefficient block. Therefore, regardless of the received video format, such as the native display format, the IDCT function 122 is executed in the same way with a consistent block size. Therefore, the MPEG-like decoder 100 includes image resizing function processing. Such function processing works<u style="single">compensation</u>Not in a loop. [0049] Move image reduction function processing when it is desirable to reduce the memory required to run anchor frame memory 117 (eg, SDTV display devices do not require HDTV motion accuracy and resolution).<u style="single">compensation</u>It can also be included in a loop. Embodiments of this type of invention will be described below with reference to FIG. [0050] FIG. 2 shows a high-level block diagram of a video decoder based on the present invention. In particular, like the decoder 100 of FIG. 1, the video decoder and processor of FIG. 2 includes an MPEG-like decoder that receives and decodes the compressed video information stream IN on a block-by-block basis to generate a video output OUT. The video output stream OUT is suitable, for example, to be connected to a display drive circuit in a display device (not shown). The display format of the video output stream is adjusted by resizing operations in either the Discrete Cosine Transform (DCT) domain or the Pixel domain. [0051] The MPEG-like decoder 200 in Figure 2 has memory and memory bandwidth.<u style="single">Required amount</u>It includes a device for reducing the cost and complexity of the decoder. In particular, memory and memory bandwidth<u style="single">Required amount</u>Is<u style="single">The reduced image information frame is stored so that it can be used next by the motion compensation module 116 of the decoder 200.</u>It is reduced by compressing the image information before storing it in the anchor frame memory 117. The present invention<u style="single">Includes motion vector processor 118, which motion vector processor predicts.</u>Image information frame<u style="single">The amount of compression and prediction given to</u>Used to form the information frame<u style="single">Forecast</u>To the type of<u style="single">Consistent</u>The method processes the motion vector information received from the VLD112. [0052] The MPEG-like decoder 200 includes an input buffer memory module 111, a variable length decoder (VLD) module 112, an inverse quantizer (IQ) module 113, a block memory module 114, and movement.<u style="single">compensation</u>It includes module 116, anchor frame memory module 117, assignable processor 120, optional vertical resizer module 142, optional horizontal resizer module 143, controller 130 and motion vector processor 118. The assignable processor 120 has an inverse discrete cosine transform (IDCT) function 122,<u style="single">Addition</u>The function 124, the interpolation function 126, and the block-to-scan line conversion function 128 are executed. The assignable processor 120 also includes a block memory, a module 129, and cooperates with various elements in the allocateable processor 120 to provide an intermediate storage device for, for example, block domain and / or scan line domain video information. [0053] Since the majority of the elements of the MPEG-like decoder 200 of FIG. 2 operate in substantially the same way as the corresponding elements in the MPEG-like decoder of FIG. 1, only the differences between the two figures will be described in detail. For example, the MPEG-like decoder 200 of FIG. 2 includes a motion vector processor 118, but the MPEG-like decoder 100 of FIG. 1 does not. This is because in the MPEG-like decoder 200 of FIG. 2, the interpolating function 126 of the assignable processor 120 is in the loop (ie, the IDCT function 122 and the assignable processor 120.<u style="single">Addition</u>This is because it is between functions 124). Conversely, in the MPEG-like decoder 100 of FIG. 1, the interpolating function 126 of the assignable processor 120 is "outside the loop" (ie, the IDCT function 122 and the assignable processor 120.<u style="single">Addition</u>(After function 124). Interpolation function 126 sets other blocks based on each motion vector<u style="single">Forecast</u>Used to<u style="single">Be done</u>Since it increases or decreases the size of the anchor blocks, these motion vectors are increased or decreased in size for each block.<u style="single">Adapt</u>There is a need. [0054] Input buffer memory module 111<u style="single">Is</u>Temporarily stores the received compressed video stream IN until the variable length decoder module 112 is prepared to allow video data for processing. The VLD 112 has an input connected to the data output of the input buffer memory module 111 and retrieves the stored variable length encoded video data, for example as the data stream S1. The VLD112 decodes the search data to generate a constant length bitstream S2. This bitstream is quantized<u style="single">Forecast</u>Includes error DCT coefficient, motion vector stream MV and block information stream DATA. IQ module 113 performs an inverse quantization operation on the constant bitstream S2 to quantize in standard form.<u style="single">Forecast</u>Generate an error coefficient, i.e., a DCT coefficient vector S3 with a DCT coefficient. [0055] IDCT function 122 for assignable processor 120<u style="single">Is</u>Perform the inverse discrete cosine transform operation on the DCT coefficient vector S3 for each pixel<u style="single">Forecast</u>Generate the data vector S4 containing the error. Assignable processor 120<u style="single">Arithmetic and / or logic</u>resource<u style="single">Is</u>, Is assigned to the IDCT function 122 based on the factors described so far and some of the factors described in more detail below. [0056] Interpolation function 126 for assignable processor 120<u style="single">Is</u>Perform vertical and / or horizontal interpolation operations, pixel by pixel<u style="single">Forecast</u>Resize the pixel block in the error data vector S4 for each pixel<u style="single">Forecast</u>Generate the error data vector S11. The amount of resizing given to the pixel block is determined with respect to the control signal SIZE generated by the controller 130. Resizing is vertical and / or horizontal of the pixel block<u style="single">Size</u>Consists of an increase (eg, through interpolation) or a decrease (eg, by decimation or decimation and interpolation) of. Reducing the size of the pixel block will reduce the amount of memory resources used by the anchor frame memory 117. [0057] Assignable processor 120<u style="single">Addition</u>Function 124<u style="single">Is</u>, For each resized pixel<u style="single">Forecast</u>Error data vector S11 and movement<u style="single">compensation</u>Motion generated by module 116<u style="single">Compensation forecast</u>The addition operation of the pixel value data vector S6 is executed. Therefore,<u style="single">Addition</u>The output of function 124 is the resized video data vector S12 consisting of the reconstructed resized pixel values in the actual embodiment of FIG.<u style="single">Addition</u>Resized video data vector S12 generated by function 124<u style="single">Is</u>, Anchor frame memory 117 and block-to-scan line conversion function 128 of allocatable processor 120. Anchor frame memory module 117<u style="single">Is</u>Receives and stores these resized pixel blocks associated with the anchor frame in the resized video data vector S12. [0058] [0058] Block-to-scan line conversion function of assignable processor 120 128<u style="single">Is</u>,block<u style="single">Base of</u>Performs a conversion from the block domain of the resized video data vector S12 to the scanline domain. That is, the block-to-scan line conversion function 128 of the assignable processor 120.<u style="single">Is</u>, The block generated by the interpolation function 126<u style="single">Base of</u>Scan lines of resizing video data vector S12<u style="single">Base of</u>Convert to video stream S9. Scan line<u style="single">Base of</u>Video stream S9<u style="single">Is</u>Connected to any vertical resizer 142, any horizontal resizer 143 or output OUT. [0059] Any vertical resizer 142 and any horizontal resizer 143 operate in substantially the same manner as previously described. Controller 130<u style="single">Is</u>, Interpolation function 126 of assignable processor 120<u style="single">Both</u>, Arbitrarily utilize any of these resizers to achieve an appropriate video output signal OUT. [0060] See Figure 2 here<u style="single">To do.</u>Allocable processor 120<u style="single">Is</u>, To control signal A from controller 130<u style="single">Depending on</u>, At least allocate processing resources between the IDCT function 122 and the interpolation function 126. The controller 130 allows allottable processing resources, such as vector processing resources, to, for example, format the input video signal IN and the native display or processing format of the display or video processor using the present invention.<u style="single">Depending on,</u>Assigned between two functions<u style="single">Be</u>.. [0061] Allocable processor 120<u style="single">Is</u>, To the control signal SIZE from controller 130<u style="single">Depending on</u>, The size or resolution parameter of the block to be processed<u style="single">Adapt</u>.. That is, IDCT processing<u style="single">But</u>Imposed<u style="single">Ru</u>The received N × M (or N × N) DCT coefficient block generally produces an N × M (or N × N) pixel block. Controller 130<u style="single">Is</u>If it is determined that the generated pixel blocks must be reduced in size both horizontally and vertically (ie, the HDTV blocks are reduced for use in SDTV display), then the control signal SIZE will be such. It will be used to indicate shrinkage. to this<u style="single">Depending on</u>, IDCT function to this kind of reduction (eg, 8x8 pixel block to 4x4, 4x8, 2x4 or other reduced resolution pixel block such as M'xN' pixel block To convert). This adoption of the IDCT function will be described in detail below. [0062] The IDCT function 122 of the assignable processor 120 is used to provide a reduced resolution pixel block by executing the IDCT function on a subset of the DCT coefficients within the received DCT coefficient block. In this method, the interpolation function 126<u style="single">Is</u>, Needless to be used to provide reduced size pixel blocks. This is because the IDCT function 122 does not generate this kind of block. [0063] In one embodiment of the invention, some of the IDCT coefficients are truncated prior to the actual IDCT operation. The rest of the DCT coefficient block (eg, relatively low order coefficients) is imposed on the inverse DCT to reduce the resolution pixel block.<u style="single">But</u>Generate<u style="single">Be done</u>.. The actual reduction in resolution is used to reconstruct the truncated pixel block<u style="single">Be done</u>Determined by the number of DCT coefficients. This truncation amount is determined by the appropriate resolution level of the pixel resolution and is also displayed by the control signal SIZE, as determined by the controller for the received video format and native display format. [0064] Thus, the IDCT function 122 of the assignable processor 120 produces a compressed video data vector S4 with a compression ratio of 1: SF according to the scale factor SF (indicated by the control signal SIZE). IDCT function 122 for assignable processor 120<u style="single">Is</u>, The resulting compressed anchor frame is manipulated on a pixel block basis (eg, 4x4, 4x8 or 8x8 pixel block) to provide anchor frame memory such as compressed video data vector S5, and anchor frame. Each pixel block that forms is compressed. Therefore, the memory of the anchor frame memory module 117<u style="single">required amount</u>Is reduced by the SF factor. [0065] In another embodiment of the invention, if half of the DCT coefficient is truncated and the remaining DCT coefficient is imposed on the IDCT process, the resulting pixel block will be an initial pixel block (ie, 4x8 or 8x4 pixels). It is almost half the resolution (ie, 2: 1 compression ratio) of the block). Similarly, when 3/4 of the DCT coefficient is truncated and the remaining DCT coefficient is imposed on the IDCT process, the resulting pixel block is the resolution of the initial pixel block (ie, 4x4 pixel block) (ie 4: 4 :. It becomes 1/4 of the compression ratio of 1). It is important to note that the amount of reduction need not be a two factor (ie 1/2, 1/4, etc.). Rather, the amount of reduction can be explained in a number of ways that are considered optimal for the application. For example, in the case of an HDTV video format stream reduced for display on an SDTV format display device, the amount of reduction (ie, scale factor SF) is 9: 4 vertical reduction (ie 1080 to 480 lines). ) And the horizontal reduction of 3: 1 (ie, from 1920 pixels to 640 pixels). [0066] Motion vector processor 130<u style="single">Is</u>, Receives the motion vector stream MV from VLD112 and the control signal SIZE generated by controller 130. Motion vector stream MV<u style="single">To predict each macroblock based on the image information stored in the anchor frame memory module</u>Movement<u style="single">compensation</u>Consists of motion vector information to be used by module 116. However, the image information stored in the anchor frame memory module 117 is stored by the IDCT function 120 of the assignable processor 120 as described above.<u style="single">scaling</u>Be done<u style="single">Was</u>So<u style="single">scaling</u>Use the pixel information<u style="single">do it</u>Used to predict macroblocks<u style="single">Be done</u>Motion vector data<u style="single">Scale</u>necessary<u style="single">But</u>is there.<u style="single">Scaled</u>Motion vector MV<u style="single">Is</u>Moves through the path MV'<u style="single">compensation</u>Combined with module 116. [0067] Movement<u style="single">compensation</u>Module 116<u style="single">Is</u>, Compressed (ie, stored in memory module 117) via signal path S7'and scale motion vector MV'<u style="single">scaling</u>Access the image information (which was done),<u style="single">Scaled forecast</u>Generate a macroblock. That is, movement<u style="single">Compensation module</u>116 is one or more memorized anchor frames (<u style="single">For example</u>、<u style="single">Addition</u>Occurs with respect to the recent I-frame or P-frame of the video signal generated at the output of function 124<u style="single">Reduced resolution pixel block</u>) And the motion vector received from the motion vector processor 130,<u style="single">scaling</u>Was done<u style="single">Forecast</u>Multiple forming information data vector S6<u style="single">Scaled forecast</u>Calculate each value of the macroblock. [0068] As we have noticed so far, the interpolation function 126 is in the pixel domain.<u style="single">Working</u>、<u style="single">Within the pixel block to be processed</u>Existing<u style="single">line</u>、<u style="single">That is,</u>Of the pixel line<u style="single">home</u>chosen<u style="single">Between the lines</u>One or more<u style="single">Additional pixels</u>Insert a line. The number of lines inserted depends, for example, on the difference between the input video format and the native display format or video processing format. For example, the conversion from 480 lines to 1080 lines has a conversion ratio of 4: 9, and the conversion between 480 lines and 720 lines has a conversion ratio of 2: 3. [0069] In one embodiment of the invention, the IDCT function 122 and the interpolating function 126 of the assignable processor 120 are tightly integrated.<u style="single">mainly</u>Within the DCT domain<u style="single">motion</u>To do. In this embodiment, the interpolating function 126 of the assignable processor 120 is within the DCT domain.<u style="single">motion</u>And before executing the IDCT function, for example<u style="single">Additional</u>"Padding" DCT coefficient to receive DCT coefficient block<u style="single">add to</u>By doing so, the vertical dimension of the pixel block is increased. For example, 8x8 DCT coefficient block<u style="single">To</u>, 8x12 or 8x18 DCT coefficient block<u style="single">Padding, padding</u>It may be processed using a DCT-based function (ie, a coefficient matrix) suitable for the DCT size obtained. [0070] ATSC television receivers must process the input video signal at least based on the ATSC recommended compression format. These formats are shown in Table 2 below. In Table 2, "P" indicates non-interlaced (progressive) scanning, and "I" indicates interlaced scanning. The frame rate numbers shown in Table 2 are integer values.<u style="single">However, it should be noted that ATSC standards also allow frame rate values multiplied by 1000/1001 (ie 59.94Hz instead of 60Hz).</u>[Table 2]<img file="JP4344472B2_D0002.tif" /> The present invention focuses on the vertical interpolation problem of converting an input video format to a native display format. Since vertical interpolation of scan mode video necessarily requires storage of at least two lines of video, the block mode approach possible by the present invention provides significant memory and memory bandwidth savings. Further, the shared resource approach of the present invention is, for example, a total computational resource in ATSC or other video processing systems.<u style="single">required amount</u>To reduce. [0071] FIG. 3 shows a flowchart of the method 300 based on the present invention. In particular, the method 300 of FIG. 3 is suitable for use with, for example, the controller 130 of FIG. 1 or FIG. Further, it is easy for those skilled in the art to apply the method 300 of FIG. 3 to various other embodiments of the present invention described with respect to FIGS. 1 and 2. [0072] Method 300 enters from step 310 and proceeds to step 320, where the source format of the received video stream is determined. The source format is determined with respect to the format instruction information provided to the controller 130 via the header data signal HD, for example as described above. This method 300 proceeds to the next step 330. [0073] At step 330, the controller processes a video stream with the source format determined in step 320.<u style="single">Required processing resources for</u>To decide. That is, the controller 130<u style="single">Which processing resources should be assigned to the IDCT function 122, which processing resources should be assigned to the interpolation function 126, and optionally which processing resources should be assigned to the block-to-scanline conversion function 128.</u>To decide. For example, the SDTV video stream has a reduced number of DCT coefficients to be processed.<u style="single">Is</u>Requires less IDCT resources compared to HDTV video streams. However, as described above, SDTV video streams require up-conversion or interpolation to fully utilize the display area of the HDTV display device. Similarly, it is received as an input video stream IN to a system that uses the HDTV native display format or native video processing format.<u style="single">Ru</u>For HDTV video streams<u style="single">To</u>, A large amount of processing resources are allocated to the IDCT function 122 of the assignable processor 120.<u style="single">If the input video stream IN has low resolution images (eg, 480 or 720 line images), it is sufficient to handle the reduced number of DCT coefficients for such reduced resolution images. Allocable processing resources are</u>Assigned to IDCT function 122. Some or the remaining allocatable processing resources 120<u style="single">Is</u>It is assigned to the interpolation function 126, and optionally to the block-to-scan line conversion function 128. Method 300 then proceeds to step 340. [0074] In step 340, the allocateable processing resources of the assignable processor 120 are allocated between the IDCT function 122 and the interpolation function 126 based on the decision made in step 330. Method 300 then proceeds to step 350. [0075] At step 350, the bitstream is processed. That is, the DCT coefficient block currently stored in the block memory module 114 is processed by the IDCT function 122 or by the interpolating function 126 of the assignable processor 120.<u style="single">Of the processing result</u>Pixel block<u style="single">But</u>Generate<u style="single">Be done</u>.. this<u style="single">Of the processing result</u>Pixel block<u style="single">Is</u>, As video stream S4, in the way described so far<u style="single">Addition</u>Combined with function 124. The routine thus arbitrarily proceeds to step 360. [0076] In the input video stream at any step 360<u style="single">of</u>Whether the format change has been reached<u style="single">Is inquired</u>.. That is, the sequence header, the start of the I-frame.<u style="single">、</u>Or<u style="single">, In an input stream suitable for use as a format change</u>Other points<u style="single">To</u>Whether it has been reached<u style="single">Is inquired</u>.. For example, a new tuner / demodulator pair (not shown) or transform stream demultiplexer (not shown) has a different format than the current video input stream IN (eg, through user interaction with a remote control device). Combine video input stream IN with MPEG-like decoder 100 in Figure 1 or MPEG-like decoder 200 in Figure 2.<u style="single">Be forced to</u>If this format is changed<u style="single">obtain</u>.. In step 360<u style="single">Inquiry</u>If is a negative answer, the routine proceeds to step 350, where the bitstream continues to be processed (ie, the next block is processed). This in step 360<u style="single">Inquiry</u>If is a positive answer, the routine proceeds to arbitrary step 370. [0077] Formatting in the input video stream in optional step 370<u style="single">of</u>Whether there was an actual change<u style="single">Is inquired</u>.. This in step 370<u style="single">Inquiry</u>If is a negative answer, the routine proceeds to step 350, where the bitstream continues to be processed (ie, the next block is processed). This in step 360<u style="single">Inquiry</u>If is a positive answer, the routine proceeds to arbitrary step 330 and into the new format.<u style="single">Therefore</u>Process the input video stream<u style="single">Needed for</u>resource<u style="single">required amount</u>The decision is calculated. Steps 360 and 370 are often ignored. For example, every time a new channel is selected, all routines 300 are automatically executed. [0078] In one embodiment of the invention, the allocation of processing resources is the inverse discrete cosine transform (IDCT) function 122, described above with respect to the assignable processor 120.<u style="single">Addition</u>It is achieved using the execution of one or more software of function 124, interpolation function 126 and block-to-scan line conversion function 128. In this embodiment, each function to be assigned (eg, IDCT function 122 and interpolation function 126) is assigned to a plurality of software routines.<u style="single">Associated</u>.. Each of the software routines allocates itself an appropriate amount of processing resources at run time. [0079] For example, in the source video format (eg, received video format)<u style="single">Associated</u>The IDCT function software routine is executed to convert the DCT coefficient block into a pixel block. Similarly, to the source video format and the output video format (eg, the native format of the display device)<u style="single">Associated</u>The interpolation function software routine determines the size of the pixel block to be combined with the block-to-scan line conversion function 128.<u style="single">Adapt</u>Is executed. The executed IDCT function and<u style="single">interpolation</u>Each of the function software routines<u style="single">Is</u>, At runtime<u style="single">Appropriate</u>Allocate the amount of processing resources to itself. Reserved by various software routines<u style="single">Computational resources to be</u>Total amount of other resources<u style="single">Is</u>, Tends to be somewhat balanced. this is<u style="single">、</u>Routine<u style="single">、</u>Selected based on source and output video format, designed to allocate only resource requirements<u style="single">Teori</u>, And in an inversely proportional manner (ie, IDCT function resource)<u style="single">required amount</u>Interpolation resources tend to increase while interpolation resources tend to decrease)<u style="single">Reserve</u>Because. Therefore, software allocation of resources for vector processing, multiple processors or other assignable computing architectures can be advantageously utilized to carry out the present invention. [0080] [0080] In one embodiment of the invention, the inverse discrete cosine transform (IDCT) function 122,<u style="single">Addition</u>Function 124, interpolation function 126 and block-to-scan line conversion function 128<u style="single">Our</u>One or more<u style="single">Provided to</u>The amount of processing resources is substantially fixed. this is,<u style="single">For processing</u>Intermediate video format<u style="single">Select and allocate various processing resources based on the intermediate video format</u>Achieved by In this method, the allocation of processing resources to memory between the various functions is constant. This assignment can be made, for example, in the factory or at power-up of the video decoder based on the present invention. [0081] The MPEG-like decoder 100 in FIG. 1 is one or more integrated circuits.<u style="single">To be equipped. The one or more integrated circuits are, for example,</u>Required by a combination of transmitted video format and native display format<u style="single">like,</u>Vector processing resource or other<u style="single">arithmetic</u>And / or logical processing resources<u style="single">To</u>IDCT and interpolation operations<u style="single">What</u>Controllable<u style="single">To</u>allocation<u style="single">To enable</u>Designed in a way. As a practical matter, allocation of resources such as vector processing resources requires a slight increase in intermediate storage, which is an interpolated (ie, up-converted) pixel block (eg, 8x12 or 8). This is because the x18 pixel block) contains more pixels than the original pixel block (eg, 8x8 pixel block). But,<u style="single">arithmetic</u>Resource reduction and memory<u style="single">The required amount is</u>The increasing net result is<u style="single">Required to implement the required video decoder functionality on an integrated circuit</u>semiconductor<u style="single">area</u>Is a net decrease in<u style="single">Ru</u>.. That is,<u style="single">IDCT resource</u>Resources are reduced depending on the format of the input image<u style="single">, Adapt</u>By<u style="single">The total required to implement an integrated circuit, at the expense of a small amount of additional memory</u>Less "real estate" of semiconductors, for example less complexity<u style="single">To do</u>By reducing the die size<u style="single">Substantial savings</u>, The yield will be high. [0082] Although various embodiments teaching the present invention have been shown and described in detail herein, those skilled in the art will readily consider many other modified embodiments included in these teachings. Can be<u style="single">so</u>There will be. [Simple explanation of drawings] FIG. 1 is a high-level block diagram of a video decoder based on the present invention. FIG. 2 is a high-level block diagram of another embodiment of a video decoder based on the present invention. FIG. 3 is a diagram showing a flowchart of a resource allocation method based on the present invention.
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|---|---|---|---|
| 60060112 | United States of America | – | |
| 6011297 | United States of America | P | |
| 09160729 | United States of America | – | |
| 16072998 | United States of America | A | |
| 9820319 | United States of America | W |
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| EP1025537A1 | European Patent Office (EPO) | A1 | |
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| EP1025697A1 | European Patent Office (EPO) | A1 | |
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| US6118486A | United States of America | A | |
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| KR20010030721A | Republic of Korea | A | |
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| EP1050162A4 | European Patent Office (EPO) | A4 | |
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| EP1025697A4 | European Patent Office (EPO) | A4 | |
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| KR100635687B1 | Republic of Korea | B1 | |
| EP1025709B1 | European Patent Office (EPO) | B1 | |
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Numbers
- Publication
- 4344472
- Application
- 2000513402
Titles2
- Japanese
- 情報ストリームデコーダへの計算リソース割当
- English
- Computational resource allocation to information stream decoder
Classification
- CPC, 21
- H04N21/4383
- G06T2207/10016
- G06T2207/20052
- H04N19/176
- H04N19/134
- H04N19/61
- H04N19/103
- H04N19/107
- H04N19/124
- H04N19/127
- H04N19/137
- H04N19/186
- H04N19/146
- H04N19/152
- H04N19/42
- H04N19/428
- H04N19/523
- H04N19/85
- H04N19/40
- H04N19/59
- G06T7/223
- IPC, 15
- H04N7 30
- H04N19 102
- G06T7 20
- G06T9 00
- H04N19 117
- H04N19 136
- H04N19 157
- H04N19 169
- H04N19 44
- H04N19 503
- H04N19 513
- H04N19 59
- H04N19 61
- H04N19 625
- H04N21 438
