Format and frame rate comversion for display of 24 hz source video

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

This application relates to US Patent Application Serial No. 09 / 001,952 (Patent Attorney Reference No. 12713). This is filed on the same day as the present application. [0002]

This application relates to US Patent Application Serial No. 09 / 001,620 (Patent Attorney Reference No. 12669). This is filed on the same day as the present application. [0003]

[Technical field to which the invention belongs]

The present invention generally relates to video processing systems, specifically video processing systems capable of receiving and processing multiple video signal formats, including various high-definition and standard-grade formats. Is related to. [0004]

Background of the Invention

Today's television receivers, such as NTSC (US Television Commission) television receivers, include video processing circuits, which typically can only process video signals that fit only a single predetermined video format. .. Future digital television (DTV) receivers are expected to be mostly implemented in accordance with broadcasting standards set by the Next Generation Television Standards Board (ATSC). Similar standards include the European Digital Video Broadcasting (DVB) standard. Compressed digital video systems are described in ATSC Digital Television Standard Document A / 53, which is included in this application as a reference. In addition, the Color Video Code Standardization Working Group (MPEG) has published several standards for digital data transmission systems. The first, known as MPEG-1, relates to ISO / IEC standard 11172, which is included in this application as a reference. The second, known as MPEG-2, relates to ISO / IEC standard 13818, which is included in this application as a reference. The new DTV standard will allow broadcasters to transmit in virtually any format up to 1920 x 1080 pixels. Specifically, DTV receivers are images of various spatial resolutions (480, 720, 1080), time phase resolutions (60fps, 30fps, 24fps), scanning formats (2: 1 interlaced or progressive scanning). You must be able to receive the source video with the sequence. [0005]

The computer industry is known to display multiple image formats on so-called "multi-sync" display devices. Specifically, the multi-sync display changes the horizontal scan frequency and the vertical scan frequency in response to changes in the graphic format. Such a multi-sync approach can be implemented in a video or television environment, such as by using a studio equipment raster format standardized by the Society of Motion Picture and Television Engineers (SMPTE). Unfortunately, the multi-sync approach leads to increased costs due to complex deflection circuits, increased power consumption, and long latency between formats due to the long time constant associated with the deflection coil inductance. [0006]

A better approach is disclosed by Lee in US Pat. No. 5,485,216, "High Quality Television Video Converter," issued January 16, 1996. In Lee's patent, a high-definition television signal is decoded and then converted to a 30Hz frame rate, with vertical and horizontal reductions in sequence, interleaving to produce a 30Hz, 1050 vertical scanline video signal. Therefore, Lee's method uses a brute force technique to convert high-definition television signals into 30Hz, 1050 vertical scanline video signals. The converted television signal is processed in a conventional manner to form an image. [0007]

Unfortunately, Lee's method has the drawback of requiring complex timing, switching, and video processing circuitry. In addition, the television signal produced by Lee's method has the property of causing video and video defects in the case of 24Hz source video (film, etc.). This is because Lee's method uses a well-known 3: 2 pull-up sequence to convert 24 frames per second video to 60 frames per second, and as a result, when viewing the converted video. Video jitter problems occur. Since most Golden Hour television shows are mastered on film, most of the video data will continue to be transmitted in 24Hz progressive scanning format. [0008]

Therefore, for example, there is a demand for a cost-effective video processing system technology suitable for use in a television receiver that supports a plurality of formats. In addition, it would be desirable to provide a video processing system suitable for the use of 24Hz source video. [0009]

[Summary of Invention]

The present invention triples the frame rate of the source video and reactively adjusts the format of the resulting video signal to avoid video display problems due to 3: 2 conversion of 24Hz source video. Electronic format and frame rate conversion methods and associated equipment in adapted multi-format video processing systems. [0010]

Specifically, the present invention is a method used in a video processing system including a format converter and a frame rate converter, which formats the input video signal vertically and horizontally in response to a format control signal. The frame rate converter adapts the frame rate of the input video signal in response to the frame rate control signal. The steps provided by this method are to check the format and frame rate of the input video signal, adapt the input video signal to the native display format, and if the frame rate of the input video signal is the first value, eg about 24Hz. Triples the frame rate of the input video signal. [0011]

The present invention is also a device for processing an input video signal having one of a plurality of video formats to produce an output video signal. This device combines to receive the input video signal and combines with a format converter, a format converter that adapts the vertical and horizontal formats of the input video signal in response to the format control signal, and the frame rate control signal. It includes a frame rate converter, a format converter and a frame rate converter that adapts the frame rate of the input video signal in response to the above, and transmits a format control signal and a frame rate control signal. For input video signals with a first value frame rate, this controller causes the frame rate converter to triple the frame rate of the input video and the format converter to format the input video signal vertically and horizontally. Is adapted to a format suitable for use in display devices. [0012]

The content of the present invention can be easily understood by examining the following detailed description together with the accompanying drawings. The drawings are as follows. [0013]

[Detailed Description of Preferred Embodiment]

The present invention has the advantage of US Provisional Patent No. 60/060112 filed on September 26, 1997, which is included in the present application as a reference. [0014]

The present invention describes the case of a digital television (DTV) receiver, such as an ATSC television receiver. However, it will be apparent to those skilled in the art that the present invention will be applicable to any multi-format video processing system, including systems suitable for DVB, MPEG-1, MPEG-2 and other information streams. [0015]

FIG. 1 shows a high level block diagram of the DTV receiver 100 according to the present invention. Specifically, the DTV receiver 100 includes a video processing portion and a timing portion. The video processing part includes a video decoder 120, an optional deinterlacer 130, a vertical resizer 140, a horizontal resizer 150, and a frame buffer 160. The timing portion includes a clock circuit 110, a raster generator 190, a display clock 195, a read address generator 180, and a write address generator 185. The video signal S2 processed by the video processing portion is received by a DTV front end including an antenna 102, a tuner 104, a demodulator 106, and a transport multiplexing separator 108. The processed video signal S8 is displayed on the display device 175 or the like (after appropriate color matrix processing) according to the horizontal and vertical timing signals H-DEF and V-DEF transmitted by the raster generator 190. [0016]

The RF source 102 (eg, antenna or cable television distribution network) is a radio frequency with multiple television signals modulated according to residual sideband (VSB), quadrature amplitude modulation (QAM) and other optimal modulation schemes. RF) Signal RF is supplied. The supplied RF television signal is combined with the tuner 104, which downconverts the requested television signal to produce a first intermediate frequency (IF) television signal IF. The demodulator 106, such as VSB or QAM, demodulates the IF television signal IF to generate the digital information stream S1. An example of a digital information stream S1 is an MPEG-like system stream S1 that includes one or more MPEG-like program transport streams. [0017]

Program transport streams such as MPEG are similar to NTSC channels in that each program transport stream usually carries the audiovisual portion of a single program, such as a movie or other audiovisual program. Each program transport stream comprises a plurality of basic streams associated with the audiovisual portion of the audiovisual program being carried. [0018]

The transport demultiplexer 108 operates in a known manner to demultiplex a particular program transport stream from a system stream S1 such as MPEG. The basic audio stream S3 associated with the demultiplexed program transport stream is combined with the audio decoder 115 and decoded before being processed by the audio driver circuit (not shown). The basic video stream S2 associated with the heavily separated program transport stream is combined with the video decoder 120. [0019]

The transport demultiplexer 108 also contains the program clock reference (PCR) contained in what is called the adaptation field of the selected transport stream packet (reference packet) of the demultiplexed program transport stream. Extract. This PCR is a sample of a 27 MHz clock used to encode a demultiplexed program transport stream before it is transmitted. The extracted PCR is coupled to the clock circuit 110. [0020]

The clock circuit 110 includes, for example, a phase-locked loop (PLL) 112 and a voltage controlled oscillator (VCO) 114. The clock circuit 110 transmits a system clock fSYS, a 27 MHz system clock suitable for processing information streams such as MPEG. The clock circuit 110 utilizes PCR extracted from the demultiplexed program transport stream to demultiplex the decoder system clock (ie, system clock fSYS) of the DTV receiver into a demultiplexed program transformer. Lock to the system clock of the encoder that produces the port stream. [0021] [0021]

The PLL 112 operates in a known manner and emits the control signal C1 in response to a comparison (eg) of the 27 MHz output of the VCO 114 with the PCR received from the transport demultiplexer 108. The VCO114 responds to control signal C1 and operates in a known manner to increase or decrease the frequency of the 27MHz system clock fSYS. [0022]

The video decoder 120 decodes the video stream S2 in a standard way to produce a decoded video signal S4 with a constant transmission format and frame rate. The video decoder 120 examines the sequence header of the video stream S2 to determine the format, colorimetric determination (if possible), and other information related to the video signal encoded in the video stream S2. After examining the sequence header, the video decoder 140 combines the format, colorimetric quantity, and other information with the output into the header data signal HD. [0023]

The optional deinterlacer 130 receives at least the input of the decoded video signal S4 and the header data signal HD. If the decoded video signal S4 has video information with an interlaced format (as the HD signal shows), the deinterlacer 130 converts the decoded video signal S4 to a progressive scan format video signal, combines it with the output, and video. Let the signal be S5. If the decoded video signal S4 comprises video information having a progressive scanning format, the deinterlacer 130 combines the decoded video signal S4 with the direct output to give the video signal S5. The deinterlacer 130 is implemented using, for example, a video adaptation approach that requires frame storage, or a direct vertical interpolation or line iteration approach. [0024]

The horizontal resizer 150 receives the video signal S5 and responds to the control signal HS from the controller 200 to selectively change the number of pixels per line of video information contained in the video signal S5. The horizontal resizer 150 produces a horizontally resized video signal S6. The horizontal resizer 150 can increase the number of pixels per line, for example, by using an interpolation technique that calculates the brightness and chrominance information of a new pixel inserted between two existing pixels. Further, the horizontal resizer 150 can reduce the video line by removing all the Nth pixel contained in the line, for example, and reduce the number of pixels per line. [0025]

The vertical resizer 140 receives the horizontally resized video signal S6 and responds to the control signal VS from the controller 200 to selectively select the number of vertical scanning lines per frame of the video information contained in the video signal S6. change. The vertical resizer 140 produces a vertically resized video signal S7. The vertical resizer 140 can increase the number of lines per video frame, for example, by using an interpolation technique that calculates the brightness and chrominance information of new lines inserted between two existing lines. The vertical resizer 140 can also reduce the number of lines per video frame by, for example, using an interpolation technique that computes new scan lines at reduced line densities. [0026]

If the optional deinterlacer 130 is implemented using the vertical interpolation or line iteration approach, the deinterlacing function can be incorporated into the vertical resizing unit 140. In this case, the horizontal resizer 150 is coupled to receive the decoded video signal S4 directly from the video decoder 120, as shown by the dotted line in FIG. [0027]

The frame buffer 160 selectively receives the horizontally and vertically resized video signal S7. The frame buffer 160 is a double buffering type frame buffer, which includes an input frame store buffer 162 and an output frame store buffer 164. The video information in the video signal S7 is stored in the input frame store buffer 162 in response to the buffer input control signal IN. When the contents of the output frame store buffer 164 are completely read, the contents of the input frame store buffer 162 are used as the output frame store buffer 164. That is, the input buffer and the output buffer are functionally swapped, avoiding the need to transfer the information in the input buffer to the output buffer. The video information stored in the output frame store buffer 164 responds to the buffer output control signal OUT and is combined with the frame buffer output to become the buffered video signal S8. Because the frame buffer 160 is a double buffering type frame buffer, it outputs the output data to the output frame store at a faster (or slower) rate than the input data is stored in the input frame store buffer 162. -Can be fetched from buffer 164. That is, the clock frequency associated with the video signal S7 does not have to be the same as the clock frequency associated with the buffered video signal S8. To utilize 30Hz video information on a 60Hz display, each video frame is read from the output framestore buffer 164 twice before the next video frame enters the output framestore buffer 164. .. [0028]

The frame buffer 160 is preferably a double buffering device as shown in FIG. Although a single buffering device can be used, the single buffering device tends to cause a "tearing" problem in the displayed image when the buffer read speed and the buffer write speed are different. In the embodiment of the example, the buffer read speed (determined by the OUT signal) and the buffer write speed (determined by the IN signal) are likely to be different, and in the case of 24Hz source video, the differences as described below occur. The use of low transmission frame rate video signals (such as 24 or 30Hz) causes a wide range of unwanted flicker in images displayed using most display technologies, so such display rate conversion is required. Become. [0029]

The RGB matrix and driver 170 receive the buffered video signal S8. The RGB matrix and driver 170 operate in a known manner to process the buffered video signal S8 according to the matrix coefficients, transmission characteristics, and color primary information contained in the sequence header of the basic video stream S2. Specifically, the RGB matrix and driver 170 convert the transmitted Y, Cr, and Cb color components into the red (R), green (G), and blue (B) color signals required for display. Perform the color conversion process required for. The three color signals R, G, B are coupled to the display device 175, where each color signal is used to drive, for example, an associated electron gun (not shown) in the receiver tube. Note that the RGB matrix and the three color signals R, G, and B transmitted by the driver 170 need to be further amplified by an appropriate driver circuit (not shown) before being combined with the display device 175. May occur. [0030]

The raster generator 190 responds to the raster clock signal fRAST by transmitting a fixed frequency horizontal deflection signal H-DEF and a vertical deflection signal V-DEF in a conventional manner. The raster clock signal fRAST is transmitted by the display clock circuit 195 in a conventional manner. The horizontal and vertical deflection signals H-DEF, V-DEF are used, for example, to drive the relevant horizontal and vertical deflection coils in the receiver tube, respectively. As a caveat here, the horizontal and vertical deflection signals H-DEF and V-DEF transmitted by the raster generator 190 need to be amplified by an appropriate driver circuit (not shown) before being combined with the display device 175. In some cases. [0031]

The write address generator 180 transmits a frame buffer input control signal IN in response to the control signal WRITE from the controller 200 and the clock signal fSYS. Similarly, the read address generator 185 transmits the frame buffer output control signal OUT in response to the control signal READ from the controller 200 and the clock signal fRAST. Importantly, the video information for the video signal S7 is stored in the input framestore buffer 162 at a speed determined by the system clock fSYS. Similarly, the video information in the output framestore buffer 164 is captured at a rate determined by the raster clock fRAST. So, for example, with a 27MHz display clock (such as when selectively associated with the 27MHz system clock fSYS) and an 81MHz raster clock fRAST, the rate at which data is fetched from framebuffer 160 is three times faster than the storage rate. [0032]

The controller 200 can be implemented in a standard manner using a standard microprocessor, built-in memory unit, I / O ports and associated support circuitry. Further, the controller 200 can be provided with a special purpose digital signal processing circuit. The controller 200 receives the format, colorimetric quantity, and other information regarding the decoded video signal S4 from the video decoder 120 through the header data signal HD. The controller 200 uses this information and additional information about the display device 175 (such as the native format of the display device) to generate a vertical size control signal VS to the vertical resizer 140, a horizontal size control signal HS to the horizontal resizer 150, and a write address. The write address control signal WRITE is sent to the device 180, and the read address control signal READ is sent to the read address generator 185. [0033]

In one of the embodiments of the present invention, all the processing and storage operations are performed using a 4: 2: 0 sampling (ie, MPEG YUV) component format to minimize processing and storage conditions. .. [0034]

ATSC receivers, such as the DTV receiver 100 illustrated in FIG. 1, must process video signals at least according to ATSC's recommended compression formats. This format is shown in Table 1 below. In Table 1, "P" represents a progressive scan and "I" represents an interlaced scan. Furthermore, the number of frame rates shown in Table 1 is an integer value. The ATSC standard also allows frame rate values to be multiplied by 1000/1001 (that is, 59.94Hz instead of a 670Hz base). [0035]

[table 1]

<img file="JP2002500480A_D0001.tif" /> In the DTV receiver of FIG. 1, the usual independent video format conversion and display rate conversion processes are controlled and adjusted according to the present invention. That is, the video format of the input video signal is controlled using a deinterlacer 130, a vertical resizer 140, and a horizontal resizer 150. Similarly, the display rate conversion process is controlled using the write address generator 180 and the read address generator 185. Controller 200 controls both processes and coordinates the use of the processes so that the image displayed on display 175 does not contain video glitches due to the use of 24Hz source data on the 60Hz display. To do. [0036]

Therefore, in one of the embodiments of the DTV receiver 100 shown in FIG. 1, the display device 175 implements one of the transmission formats (so-called native display format) at a frame refresh rate of 60 Hz (or 59.94 Hz). Operates according to the horizontal deflection frequency selected to do so. Transmission with a field or frame rate of 60Hz (or 59.94Hz) feed video information can not be the target of the frame rate conversion. In contrast, transmitted video information with a frame rate of 30Hz (or 29.97Hz) is converted to 60Hz (or 59.94Hz) using 2: 1 frame iteration. That is, the controller 200 causes the output frame store buffer 164 of the frame buffer 600 to be read twice for each frame. [0037]

The DTV receiver 100 in Figure 1 because the 24Hz frame rate cannot be displayed on a 60Hz (or 30Hz) display device without the unwanted video glitches caused by the typical 3: 2 frame rate conversion process. Works differently when 24Hz video is decoded. Specifically, the 24Hz (or 24 * 1000 / 1001Hz) video is resized according to the needs of the format conversion process and eventually converted to 72Hz (or 72 * 1000 / 1001Hz) by the frame rate conversion process. Will be done. Display device 175 operates at a 72Hz refresh rate in the presence of 24Hz video. Note that the format conversion process is adapted by the controller 200 to a 72Hz frame rate, as described below. [0038]

Alternatively, the 24Hz (or 24 * 1000 / 1001Hz) video is finally converted to 48Hz (or 48 * 1000 / 1001Hz) video by the format conversion process, depending on the needs of the format conversion process. When operating at 48 Hz, those skilled in the art utilizing the present disclosure may adapt various parameters related to the implementation of the 72 Hz method and device described described to the 48 Hz method and device. This 48 Hz operation may be desirable when the display device is a liquid crystal display device. As an important note, by using a multiple of an integer (3 at 72Hz, 2 at 48Hz), the present invention avoids the 3: 2 problem described here. [0039]

FIG. 2 is a high level block diagram of a DTV receiver including a light valve display according to the present invention. Since the DTV receiver 200 of FIG. 2 operates in much the same way as the DTV receiver 100 of FIG. 1, only the differences between the two figures will be described. Specifically, the DTV receiver 200 includes, for example, a display 175 with a light valve or digital micromirror display (DMD) type or liquid crystal display (LCD) type projection display. Therefore, the DTV receiver 200 of FIG. 2 does not include a circuit that emits horizontal and vertical deflection signals. In this embodiment, the read address generator 185 is switched to a frequency 6/5 (ie, 72/60) higher to provide a 72 Hz read of the double buffered frame display in the presence of a 24 Hz transmission format. .. Note that spatial format adjustment of the 24Hz transmission format is usually not required for such displays. [0040]

In the following description, it is assumed that the display device 175 includes a cathode ray tube (CRT) display. In order to carry out the present invention in a CRT-based receiver in a cost-effective manner, the horizontal deflection frequency of the CRT display should be kept constant, so that the number of scanning lines is 5/6 (that is, 60/72). ) Need to be changed. To change the number of scan lines, controller 200 causes the vertical resizer 140 to reduce the number of lines in the video signal S5. In order to iterate over a frame (2: 1 iterative), controller 200 causes two reads from the output framestore buffer 164 before receiving the next frame. Also, in order to iterate the frame twice (3: 1 iteration), the controller 200 ensures that the output frame store buffer 164 is read three times before receiving the next frame. [0041]

Table 2 lists the video transmission and display formats and the processing parameters suitable for processing such video signals in the case of the DTV receiver 100. Specifically, this processing parameter is suitable for processing such a video signal in the case of a display device 175, which is a 1920 pixel × 1080 line progressive scanning display with a horizontal scanning frequency of 64.8 kHz. .. Note that this display 175 operates in 900 line mode for 24Hz source video. [0042]

The vertical interpolation parameter (vertical interpolation), horizontal interpolation parameter (horizontal interpolation), and frame repetition parameter (frame repetition) are the vertical resizing coefficient, horizontal resizing coefficient, and frame that are used by the controller 200 in response to a specific transmission format. Each has a rate conversion coefficient. The controller 200 modifies these parameters as previously described to maintain a fixed horizontal display frequency and avoid video glitches for 24Hz source video. [0043]

[Table 2]

<img file="JP2002500480A_D0002.tif" />Table 3 shows the same type of information as Table 2 above, but Table 3 shows the case of display device 175, which is a 1280 pixel x 720 line progressive scanning display with a horizontal scanning frequency of 45 kHz. [0044]

[Table 3]

<img file="JP2002500480A_D0003.tif" />Table 4 shows the same type of information as Tables 2 and 3 above, but Table 4 shows the case of display device 175, which is a 1920 pixel x 1080 line interlaced scanning display with a horizontal scanning frequency of 32 kHz. There is. Note that this display operates in 900 line mode for 24Hz source video. The approach described above (Table 2) in 1920x1080 progressive scanning is used, with modifications appropriate to the fact that the displays are interlaced. [0045]

In this case, maximum speed deinterlacing is only required when running on 480 line format video, which can significantly reduce the complexity and memory required when implementing deinterlacer 130. As a further note, the dual frame buffer 160 can transmit the interlaced scan format output signal S8. [0046]

[Table 4]

<img file="JP2002500480A_D0004.tif" />Table 5 shows the same type of information as Tables 2-4 above, but Table 5 shows the case of display device 175, which is an interlaced scanning display of 1280 pixels x 720 lines with a horizontal scanning frequency of 22.5 kHz. ing. Note that this display operates in 600 line mode for 24Hz source video. The approach (Table 3) for 1280 x 720 progressive scanning is used, with modifications appropriate to the fact that the displays are interlaced. Also, as mentioned with respect to Table 4, the complexity and required memory of the deinterlacer 130 can be significantly reduced and the read address generator circuit 185 must be modified. [0047]

[Table 5]

<img file="JP2002500480A_D0005.tif" />In Tables 2 to 5, interpolation ratios such as 30/11, 20/11, and 15/11 occur several times. These ratios can be simplified to 3/1, 2/1, and 3/2, respectively, to reduce the complexity of interpolation. Such simplification, of course, leads to a reduction in the active image range. [0048]

FIG. 3 is a flowchart of a method 300 for processing a video signal according to the present invention. Specifically, FIG. 3 is a flowchart showing a method of optimally formatting a video signal so that defects due to 3: 2 pull-up do not propagate to a display device such as the display device 175 shown in FIGS. 1 and 2. is there. The routine 300 of FIG. 3 can be implemented, for example, by a combination of hardware, software, hardware and software using the controllers 200 of FIGS. 1 and 2. [0049]

Routine 300 of FIG. 3 is initiated in step 302, where the input video signal is received by either the DTV receiver of FIG. 1 or the DTV receiver 200 of FIG. In step 304, the format and frame rate of the video signal are specified and this routine continues to step 306. At step 306, a question is asked whether the received video signal is compatible with the native format of display device 175. If the answer to the question in step 306 is negative, the routine proceeds to step 308 to match the format of the video signal with the native format of the display device. Routine 300 then proceeds to step 310. If the answer to the question in step 306 is affirmative, routine 300 proceeds to step 310. [0050]

In step 310, a question is asked if the frame rate of the received video signal is approximately equal to 24Hz (24Hz, 23.97Hz, etc.). If the answer to the question in step 310 is negative, routine 300 proceeds to step 312, where it triples the frame rate of the received video signal. That is, in step 312, the controller 200 causes the frame rate converter to increase the frame rate of the input video signal from about 24 Hz to about 72 Hz. This method avoids the usual 3: 2 pull-up glitches when converting a video signal at 24 frames per second to a video signal at, for example, a 30Hz or 60Hz frame rate. [0051]

The embodiments of the present invention described so far present methods and devices for avoiding defects in displayed moving images due to 3: 2 conversion of 24Hz video source video. There are other format-related features that can be used to optimize this behavior, such as multiple video format DTV receivers. For example, a US patent application filed on the same day as the present application for a multi-format video signal processing system that works with a display device timing system that produces synchronized video and timing signals suitable for use in fixed horizontal scanning frequency display devices. It is explained in more detail in Book 09/001952 (Attorney Reference No. 12713), which is included in the present application as a reference. Another example is a video processing system that automatically adjusts video processor behavior such as horizontal peaking, vertical peaking, and colorimetric quantitative parameters according to the format of the received video signal, on the same day as this application. It is explained in more detail in US Patent Application No. 09/001620 (Patent Attorney Reference No. 12669) to be filed, which is included in the present application as a reference. [0052]

Although various embodiments incorporating the contents of the present invention have been described and described here, those skilled in the art can easily devise many other various embodiments incorporating the contents of the present invention.

[Simple explanation of drawings]

[Figure 1]

FIG. 1 is a high level block diagram of a DTV receiver according to the present invention. [Figure 2]

FIG. 2 is a high level block diagram of a DTV receiver including a light valve display according to the present invention. [Fig. 3]

FIG. 3 is a flowchart of a video signal processing method according to the present invention.