Reconfigurable input galois field linear transformer system

The present invention relates to a reconfigurable input Galois field linear transformer system.

The Galois extension field linear transformer has recently been improved to be able to historically perform multi-cycle operations in one cycle using predictive logic (filed on January 18, 2002). Patent Document 1) for Stein et al. Titled GALOIS FIELD LINEAR TRANSFORMER. In this approach, each cell of the Galois field linear transformer (GFLT) contains a AND gate, an exclusive OR gate, and a storage device. Input data, such as bit arrays, cyclic redundancy check (CRC), scrambling / descrambling, and patterns of enabled / disabled cells that define specific features that apply to convolutional coding. To perform, the storage device is used to enable or disable the associated cell. Typically, the entire matrix of cells that make up the GFLT is set in a pattern to perform a particular function, even when only part of the matrix is required. This is not economical in terms of output or die size.<patcit num="1"><text>U.S. Patent Application No. 10 / 051,533</text></patcit>

<p> Therefore, it is an object of the present invention to provide an improved reconfigurable input Galois extension field linear converter device.</p><p> A further object of the present invention is to provide such an improved reconfigurable input Galois extension linear converter device that is more economical in terms of output and die size.</p><p> A further object of the present invention is to provide such an improved reconfigurable input Galois extension field linear converter device in which the same arrangement plane can be shared by different functions.</p><p> A further object of the present invention is such an improved reconfigurable input galois extension that allows the converter to perform both memory bit manipulation and memory-less bit manipulation separately or simultaneously. The purpose is to provide a field linear converter device.</p><p> A further object of the present invention is to provide such an improved reconfigurable input Galois extension linear converter device capable of selecting and combining any byte combination of current data and previous state inputs. There is.</p>

<p> The present invention allows an improved Galois extension field linear converter (GFLT) device with multiple storage surfaces to store control patterns representing many different bit manipulation functions to be easily reconfigured and one in terms of placement To reconfigure the input circuit that can perform more functions and send the input data to the enabled cells to enable the cells of the GFLT matrix and to give the functions to the input data. In addition, it is realized that it can be achieved by selecting a storage surface representing the selected function.</p><p> The present invention features a reconfigurable input Galois extension field linear converter apparatus comprising a Galois extension field linear converter having a matrix of cells and a plurality of storage surfaces for storing control patterns representing many different functions. The storage surface selection circuit selects a storage surface that represents a function in order to enable cells in a matrix that defines the function. A reconfigurable input circuit sends input data to a cell that has been enabled to provide functionality to the input data.</p><p> In a preferred embodiment, each cell can include an exclusive OR logic circuit, a AND logic circuit having an output connected to the exclusive OR logic circuit, and an input receiving input data bits. Each storage surface can include a storage device associated with each cell. Each storage device can include a plurality of storage units arranged with related cells, one storage unit corresponding to each storage surface. Each storage device can include a multi-stage register arranged with associated cells, one stage corresponding to each storage surface. The storage surface selection circuit can include a surface selection register. The reconfigurable input circuit can include at least a first input register and a switching device that transmits input data from the first input register to the available cells. The switching device can include a plurality of switching circuits, one of which is associated with each byte of input data in the first input register. It can have a second input register and the switching device can selectively transmit input data from the first and second input registers to the available cells. The storage device can be programmable.</p><p> Other objectives, features, and advantages will be found to those skilled in the art from the description of the following preferred embodiments and the accompanying drawings.</p>

FIG. 1 includes a Galois extension field linear transducer 12, a reconfigurable input circuit 14, an output circuit 16, and a plurality of storage surfaces 18, 18 , 18 that can be separately selected by the storage surface selection circuit 20. A reconfigurable input Galois extension field linear transducer device 10 is shown. The control patterns contained in each of the storage surfaces 18, 18 , 18 can use all or only a part of the complete Galois extension field linear converter. For example, function f₁The function f that the control pattern is contained in the storage surface 18'while the storage surface 18 representing₂Requires only 19 out of 12 total (GFLT). Similarly, the function f represented by the control pattern on the storage surface 18 ₃Requests only a quarter of the entire array of cells in (GFLT) 12. These small parts 19 and 21 are shown neatly placed at the corners of (GFLT) 12, but the necessary restrictions as the cell can be programmed to use any part of the cell's (GFLT) 12 matrix. is not it.

The Galois extension field linear converter (GFLT) 12 consists of 32-bit matrix cells (1024 cell matrix), 64-bit matrix cells (4096 cell matrix), or any other desired size, smaller or larger. be able to. Continuing with this invention, each cell is associated with storage surfaces 18, 18 , 18 , and each of the storage surfaces has a specific function f to be performed by (GFLT) 12.₁, f₂, f₃Stores the pattern of individual cell settings that represent. For example, the storage surface 18 can include a control pattern that performs reordering of inputs to outputs. Function of memory surface 18'2, f₂Can include control patterns that exchange the order of inputs to outputs. By alternately selecting one of the storage surfaces 18, 18 , 18 , the function f₁, Function f₂, Function f₃, Or (GFLT) 12 can be used to perform any other function in which the control pattern is stored on the storage surface. For example, when the storage surface selection circuit 20 selects the storage surface 18, the function f₁Can be executed as shown in FIG. 2, where cell 12 of the 32-bit matrix represents a usable cell, namely cell 22, as a shaded circle. The input register 24, which represents bits 1 to 32 of the ordered form, has bits sorted according to the cell enablement pattern depicted in FIG. 2, as sorted by the output register 26. For example, the data at bit position 1 in the input register 24 is given to bit position 16 in the output register 26. The data at bit position 2 of the input register 24 is given to bit position 29 of the output register 26, and so on. Excludes storage surface 18 and functions f₂By selecting the storage surface 18'representing the control pattern for, the pattern of cell enablement depicted in FIG. 3 is generated. Here smaller subsection 19, that contains a 256-bit 16-bit portion of the non-matrix is operated by a portion 28 of the input register 24, interchanging the order of the bits located in bit positions 0-7, the output register 26 The order of the bits in bit positions 8 to 15 as given to the corresponding part 30 of is swapped separately. In this way, for example, the bits at the input register bit positions 0 to 7 appear at the bit positions 7 to 0 of the part 30 of the output register 26, and the bit position data at the bit positions 8 to 15 of the part 28 of the input register 24 is It appears at positions 15 to 8 of part 30 of the output register 26.

In one embodiment, the reconfigurable input circuit 14a of FIG. 4 contains more than one input register, ie, register 40 and input register 42, each with 4 bytes in byte sections 44-50 and 52-58, respectively. Can be held. The reconfigurable input circuit 14a also includes multiplexers 60, 62, 64, and 66, one of which is associated with each byte section of input registers 40 and 42. There is one multiplexer 60-66 for each byte section, and each of these multiplexers is connected to the byte section in each of the two registers as shown. (GFLT) 12a is again shown as 32 by the cells of the 32-bit array, and the column length has been shortened for convenience of explanation. Each of the multiplexers 60, 62, 64, and 66 can provide 8-bit bytes from one multiplexer, and two related registers can be used for an 8-column cell. For example, the multiplexer 60 can send either the bits from byte section 44 or the bits from byte section 52 to any of the cells in the eight associated cell columns 68. Multiplexers 62,64, and 66 are associated with columns 70,72, The same can be done for and 74, and multiplexers 60-66 can be operated in any combination. For example, the multiplexer 62 and 64 can select byte sections 46 and 48 from register 40, while the multiplexer 60 can select byte section 52 from register 42, and the multiplexer 66 can select byte section 58 from register 42, for example. You can choose. In this way, the data in registers 40 and 42 can be assigned to cells in any given pattern. By transmitting selective data to a cell in the (GFLT) transducer 12a in combination with the ability to select a specific storage surface that represents a specific function in this way, the storage surface is selected and stored in the storage surface. The same Galois extension field linear transducer 12a can perform many different functions, depending on its function and the selective transmission of data from the reconfigurable input circuit 14a. This not only saves the die size of the equipment, but is also economical in terms of output. Moreover, with two or more input registers, such as input registers 40 and 42, both memory bit operations and memoryless bit operations, and predictive Galois extension fields can be achieved separately or simultaneously. Can be done. Thus, it is no longer necessary to transfer data from register to register, and the data in registers 40 and 42 are simultaneously selected, combined, and loaded into (GFLT) 12a via multiplexers 60-66 in one cycle. Can be done. This makes it possible to select the linear converter output (previous state) as one of the inputs in the multi-cycle Galois extension field predictive conversion, as shown in FIG. Function of (GFLT) 12a in part 21a f With force registers, such as input registers 40 and 42, both memory bit and memoryless bit operations and predictive Galois extension can be achieved separately or simultaneously. Thus, it is no longer necessary to transfer data from register to register, and the data in registers 40 and 42 are simultaneously selected, combined, and loaded into (GFLT) 12a via multiplexers 60-66 in one cycle. Can be done. This makes it possible to select the linear converter output (previous state) as one of the inputs in the multi-cycle Galois extension field predictive conversion, as shown in FIG. Function of (GFLT) 12a in part 21a f With force registers, such as input registers 40 and 42, both memory bit and memoryless bit operations and predictive Galois extension can be achieved separately or simultaneously. Thus, it is no longer necessary to transfer data from register to register, and the data in registers 40 and 42 are simultaneously selected, combined, and loaded into (GFLT) 12a via multiplexers 60-66 in one cycle. Can be done. This makes it possible to select the linear converter output (previous state) as one of the inputs in the multi-cycle Galois extension field predictive conversion, as shown in FIG. Function of (GFLT) 12a in part 21a f₃Is taught in US Patent Application 10 / 051,533 (AD-239J)) to Stein et al., Titled GALOIS FIELD LINEAR TRANSFORMER, filed January 18, 2002, which is incorporated herein by reference in its entirety. Perform a predictive multicycle Galois extension field transformation. U.S. Patent Application No. 10 / 060,699 against Stein et al., Titled GALOIS FIELD MULTIPLIER SYSTEM, filed January 30, 2002, is also incorporated herein by reference in its entirety. The state before the conversion performed in part 21a is passed from the corresponding part of output register 16a and loaded into byte section 50 of register 40 so that both inputs are sent to part 21a of GFLT12a at the same time. Loaded into byte section 56 of register 42. Part 21a is, for example, functional f, as described in US Patent Application 10 / 051,533 to Stein et al., Titled GALOIS FIELD LINEAR TRANSFORMER, filed January 18, 2002.₃Has a control pattern of storage surface 18 that is utilized to perform.

Each cell 100 in (GFLT) 12a of FIG. 6 contains a AND gate 102 whose output is connected to the exclusive OR gate 104, which is the output from the previous cell on line 106. And provide the output to the next cell on line 108. The AND gate 102 is configured to enable or disable the exclusive OR gate 104 by input on line 110 from storage device 112, which is a simple flip-flop in this case. In some situations, storage 112 enables the AND gate 102 to enable the exclusive OR gate 104 and therefore cell 100. In other conditions, it is not enabled and cell 100 is not enabled. The state of the storage device 112 is controlled by a signal on line 114. The storage device 112 does not need to be executed by a flip-flop, and any other storage device can be used. In FIGS. 8 and 9, cells 100a and 100b each require the AND function and the exclusive OR function, which are Boolean meanings such as the exclusive OR gate and the OR gate. As long as the logic circuit works with sense), it can be executed in many different ways without requiring a specific exclusive OR gate or AND gate. For example, the AND function can be achieved without a specific AND gate with the 2: 1 input multiplexer 120 of FIG. 8A. The storage device 112 is imagined as part of the storage surface, eg, function f.₁Set to control line 114 according to the control pattern of the enabled cell required to perform, or function f if storage 112 is associated with storage surface 18'.₂It is set according to.

The storage surface selection circuit 20 and the reconfigurable input circuit 14 of FIG. 1 have the configuration register 120 of FIG. 7, that is, the storage surface selection circuit 20, 16 bits for operating the surface portion 122, and the reconfigurable input circuit 14, the input. It is controlled by a 32-bit register, which allocates 16 bits to operate part 124. For example, 124 16-bit inputs labeled 0-15 require only four bits to operate the four multiplexers 60-66, and one bit / multiplexer is shown in this example. It is "0" to select bytes from register 40 and "1" to select from register 42. However, if 8 of the bits are used, 8 multiplexers can be used to help the 64 bit matrix. If 16 bits are used, 16 multiplexers can be used for a 128-bit matrix. Similarly, the 16 bits available from positions 16-31 of face 122 of configuration register 120 are used to select so many different storage surfaces that contain control patterns that represent so many different functions. Can be done. The control bits loaded into configuration register 120 select the storage surface and enter so that the input data is sent to the enabled cells to apply the functionality represented by the enabled cells to the input data. Reconfigure the circuit appropriately. This information comes from configuration command 126 from the microprocessor or any suitable hierarchical controller. Storage device 112'contains many individual storage units 112a, 112b, 112c, 112d, 112 ..., as shown in FIG. Here, each of these storage units can be a simple flip-flop, and each flip-flop constitutes a different part of the storage surface. Alternatively, the storage device 112 of FIG. 9 has 2 at many stages 112a , 112b , 112c , 112d , 112e , 112f , 112g , 112h .ⁿCan include a multi-stage register 116 containing a selector 118 that receives the data bits of. Here each stage executes a storage unit and is associated with a different storage surface.

Specific features of the present invention have been described in some drawings and not elsewhere, but for convenience as each feature can be combined with some or all of the other features according to the invention. Only. The terms "include," "have," and "provide," as used herein, should be broadly and comprehensively interpreted and are not limited to any physical interconnection. Moreover, all examples disclosed in this application should not be construed as merely possible examples.

Other examples have been found by those skilled in the art and are within the scope of the claims.

This application claims the priority of US provisional application 60 / 341,737 to Stein et al., Titled PROGRAMMABLE GF2-ALU LINEAR FEEDBACK SHIFT REGISTER-INCOMING DATA SELECTION, filed December 18, 2001.

<figref num="1">FIG. 6 is a simplified schematic block diagram of a reconfigurable input Galois extension field linear converter (GFLT) device according to the present invention.</figref><figref num="2">Function represented by the storage surface in Fig. 1 f₁It is a simplified schematic showing the pattern of available cells in the GFLT to perform.</figref><figref num="3">Function represented by the storage surface in Fig. 1 f₂It is a simplified schematic showing the pattern of available cells in the GFLT to perform.</figref><figref num="4">It is a more detailed schematic diagram of the GFLT apparatus of FIG. 1 which shows the reconfigurable input circuit which concerns on this invention.</figref><figref num="5">One is a predictive multi-cycle Galois extension field conversion, and the second is a memoryless bit operation. It is a functional diagram of a GFLT device that performs many functions.</figref><figref num="6">It is a more detailed figure which shows one cell of GFLT.</figref><figref num="7">It is a schematic diagram which shows the arrangement command and composition register which selects a storage surface and reconfigures an input circuit.</figref><figref num="8">It is a more detailed figure of the cell which shows one structure of the storage device using a plurality of storage units.</figref><figref num="8A">It is a schematic diagram which shows the alternative storage device which performs the function of a logical product without using a specific logical product gate.</figref><figref num="9">It is a more detailed view of the cell which shows the other structure of the storage device using a multi-stage register.</figref>

Code description

10 Reconfigurable Input Galois Extension Linear Converter 12 Galois Extension Linear Converter 14 Reconfigurable Input Circuit 16 Output Circuit 18,18 , 18 Storage Surface 20 Storage Surface Selection Circuit 112 Storage Device 112a, 112b, 112c, 112d Storage unit 116 Multistage register