Nova Patents
EP1550046B1

Compact galois field multiplier engine

Abstract

A compact Galois field parallel multiplier engine includes a multiplier circuit for multiplying together two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit has a multiply input from the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; first and second polynomial inputs; the Galois field linear transformer circuit may include a plurality of cells configured in a matrix section and a unity matrix section wherein the unity matrix section cells represent the prediction of the remainder when the output of the multiplier circuit is a polynomial with a power less than the power of the irreducible polynomial.

EP1550046B1, drawing sheet 1
Sheet 1 of 90

Term

Term ended

Expired 9 October 2023, 3 years ago.

  1. Priority
  2. Filed
  3. Granted
  4. Expired
  5. Today

4 claims: 2 independent, 2 dependent

  1. 1
    A Galois field multiplier engine (10) comprising:a multiplier circuit (18b, 18g) for multiplying two polynomials with coefficients over a Galois field to obtain their product, a first polynomial input (12b) to said multiplier circuit;a second polynomial input (14b) to said multiplier circuit;an add input (26b);an adder input selection circuit (64);and a multiplier input selection circuit (62);characterised by further comprising: a reconfigurable Galois field linear transformer circuit (20b) including a matrix of cells, each of which can be selectively enabled such that the Galois field linear transformer circuit (20b) can be adapted to perform a Galois field reduction of the polynomial product plus an add input for any irreducible polynomial, and wherein the cells (24b) of each row of the matrix co-operate to determine one bit of the modulo remainder, the Galois field linear transformer circuit having a multiply input (40b) from said multiplier circuit, an output (31b) and an add input (42b) for implementing an addition of the add input with the polynomial product output by the multiplier circuit;wherein the multiplier input selection circuit is arranged to provide to said second polynomial input of the multiplier circuit, a second polynomial in a multiply mode, said output of said Galois filed linear transformer circuit in a multiply-add mode, and a second polynomial in a multiply-accumulate mode;and the adder input selection circuit (64) is arranged to provide to said add input of said Galois field linear transformer an additive identity in the multiply mode, a second polynomial in the multiply-add mode, and said output of said Galois field linear transformer circuit in the multiply accumulate mode to obtain Galois field multiply, multiply add and multiply-accumulate functions of the input polynomials.
  2. 4
    The Galois field multiplier engine of as claimed in any of the preceding claims in which said additive identity is a null level.