CPU with cache memory

[Technical field to which the invention belongs] The present invention relates to the field of a central processing unit (hereinafter referred to as a CPU), and particularly to a CPU support cache.

[0002] [Convention] As the demand for high-performance computer systems increases, the design of CPUs incorporated in such computer systems is becoming more sophisticated. For high performance, the CPU utilizes an internal cache (L1) or an external cache (L2) that is configured to be closer to the CPU than system memory. A cache is a high-speed storage device located between the CPU and system memory. Usually, data or instructions are first accessed from main memory and a copy is cached. If this data or instruction is accessed again, the cache is faster than the main memory, so it can be searched quickly. However, the storage capacity of the cache is usually much smaller than the storage capacity of the memory represented by the main memory. Therefore, cache unification techniques exist to determine how data and instructions are maintained in the cache. These techniques rely on maintaining a "high interruption rate" (obtaining instructions and data from the cache as often as possible).

[0003] A cache composed of a high-speed device, which is a static constant-speed calling memory (hereinafter referred to as SRAM), improves the performance of the CPU by storing the data used last time by the CPU. The proximity to the CPU and its high speed allow the cache to access the required data fairly quickly without invoking long memory cycles to get the data from system memory. To do.

[0004] The cache is limited in size due to the cost of incorporating the SRAM device. Today, the size of a typical L1 cache ranges from 8K bytes to 64K bytes, and the size of the L2 cache ranges from 128K bytes to 1M bytes. In general, computer systems and CPUs are designed to kill, or expel, old cached data when the transfer of new cached data exceeds the cache capacity limit. One of the commonly used CPU platforms is the Intel X86 group of processors, some of which provide CPUs with L1 cache. For example, the Intel 486 processor contains an 8K byte internal cache L1. However, the Intel Pentium Processor has a 16K byte L1 cache and a 512K byte L2 cache.

[0005] [Problems to be Solved by the Invention] However, most of the software effective for the processors of the X86 group uses a specific instruction type such as an iterative (REP) instruction, and unnecessary data is a useful cache. Data will be expelled. This expulsion of useful CPU data reduces CPU performance because such data must be refilled by the long system memory cycles created by the CPU. The REP instruction is used to manipulate data blocks. The purpose of this operation is to move data from one area of memory to another and compare one data block to another in order to search for data blocks that have a particular pattern or similar operation. Is to let. The advantage of the REP instruction is that the data block can be manipulated with a single instruction, but the REP instruction tends to expel the cache. That is, if an iterative operation moves a data block, that data block also goes into that cache and removes the data block that is already in that cache. Often the data is in the cache, but the CPU no longer needs it. However, the data needed by the CPU is removed, and that data must be accessed from memory with the associated low functionality. Therefore, the iterative string search instruction fills the L1 cache with unnecessary string data at the expense of loss of useful cache data. Therefore, it is necessary to improve the CPU performance when a certain instruction is executed by the CPU.

[Means for Solving the Problems] The central processing unit (CPU) according to the present invention is connected to a cache device via a data bus having a predetermined width. This CPU has an instruction processing unit for processing CPU instructions that have an instruction type field. This instruction processing unit has an instruction type detection device that detects a cache-storable instruction type or a cache-unstorable instruction type. The CPU also has an execution unit to execute the instruction. The execution unit provides a CPU output signal indicating whether the data associated with the detected instruction type can be cache-stored according to the instruction type detected by the instruction type detection device.

[Embodiments of the Invention] FIG. 1 shows a block diagram showing an example of a computer system incorporating the CPU of the present invention. The computer system 100 consists of a personal computer system such as IBM PC or a system compatible with it. The computer system 100 can operate as a stand-alone desktop workstation or as part of a large computer network that operates as either a client station or a server station.

[0008] The computer system 100 has two processing lines, one of which is the host processing system 110, which performs high-level processing functions as specified by the operating system or application, and the other is local. The processing system 120 executes peripheral functions such as providing a storage medium interface and a communication interface for the computer system 100. The host processing system 110 and the local processing system 120 are connected to each other via an input / output (I / O) expansion bus 130. The I / O expansion bus 130 follows one of many suitable I / O expansion bus protocols and is local to perform specific functions such as forwarding data blocks through the I / O expansion bus 130. -Allows the interface control device to control the bus.

[0009] The host processing system 110 has a single central processing unit 103 to control the overall function of the computer system 100, or a plurality of central processing units in a multiprocessing system. The central processing unit 103 is one of many commercially available products, such as Intel's Pentium Processor and IBM's PowerPC . As is well known, the central processing unit 103 operates only by executing the firmware instruction stored in the read-only storage device (ROM) 101. Firmware instructions are Basic I / O System (basic I / O routine) or Also known as the BIOS, it contains instructions for detecting ancillary devices and power-on self-test (POST) instructions. Generally, upon completion of the firmware instruction, the central processing unit 103 executes the operating system instruction by loading the operating system from the storage device 114 of the local processing system into the system memory 107. Data transfer between the central processing unit 103, ROM 101 and system memory 107 is controlled by memory controller 109. However, the transfer of data between the host processing system 110 and the I / O expansion bus 130 is controlled by the I / O bridge interface 111. To improve processor performance, central processing unit 103 has an internal cache (L1 cache) 104 and an optional external cache (L2 cache) 105 to store last-minute data and instructions, and long system memory. It is possible to avoid having to start the access cycle of. The cache generally consists of high-speed static constant-speed invocation memory (SRAM) and is located close to the central processing unit 103. Data transfer from the L1 and L2 caches and data transfer to the L1 and L2 caches are controlled by a known cache controller 106. The cache controller stores and fetches data at multiple data bus widths called cache lines. The I / O bridge interface 111 is designed to interface between the memory controller 109 and the central processing unit 103 via the external cache controller 106 and the I / O expansion bus 130. The central processing unit 103 interfaces with the I / O expansion bus 130 and then the local processing system 120 via the appropriate bus bridge I / O bridge interface 111.

[0010] As will be described in detail later, the storage device 114 interfaces with the I / O expansion bus 130 via the local interface control device 113. The illustrated host processing system 110 is merely an example, and various system configurations (single processing or multiple processing) can be designed by an application to fulfill the functional requirements of the host processing system 110. ..

[0011] In the local processing system 120, the computer system 100 has a plurality of local interface control devices 113. The control device 113 is, for example, a SCSI interface (small computer system interface) and is connected to various peripheral devices 115. In this way, a storage device, a communication device, a printing device, a network connection device, an image reading device, and the like are added to execute the functions and features of the system. For example, the computer system 100 can be used as a server station with a high-speed wide SCSI local interface controller with a redundant array (RAID) of inexpensive drivers as a storage device.

[0012] FIG. 2 shows a block diagram of an example of a central processing unit (CPU) 200. The CPU 200 includes an instruction processing device 201 that receives an instruction from the internal L1 instruction cache device 205. The L1 instruction cache device 205 stores a plurality of instructions. The instruction is fetched by the instruction fetch controller 203 for processing.

[0013] As is known, the L1 instruction cache device 205 receives and stores instructions through the CPU bus 230 including the data bus 235, the address bus 237, and the control bus 239. The CPU local bus is connected to and interfaces with the CPU interface device 223 for interfacing the CPU with external components such as the L2 external cache and system memory shown in Figure 1. The data bus 235 and the address bus 237 have a predetermined width consisting of a predetermined number of bits. The width of the data and address bus characterizes the data transfer capacity and the size of the area of system memory that can be addressed by the CPU. Thus, for example, the data bus 235 has a data width of 16 bits, 32 bits, or 64 bits, and the address bus has a width of 16 to 64 bits. In particular, the instruction processor determines the type of instruction and sends it appropriately to one or more execution units 221. As is known, a super-scalar CPU has a plurality of execution units for executing a plurality of tasks at the same time. The execution unit performs mathematical or logical operations on the operand data provided by the instruction, for example. This execution unit receives the required data from the L1 data cache 207, which is similar to the L1 instruction cache that stores the data received through the CPU bus or the data received from the execution unit 217. The CPU also has a set of general purpose registers identified by AX to EX for storing instruction operands, temporary data, and indexes instructed by instruction 300 in a known manner. When the instruction 300 is received, the instruction processing device processes the instruction and determines the instruction type by decoding. The instruction is decoded by the instruction decoding device 209. When executing the instruction, the execution unit outputs a signal to the data bus 235, the address bus 237, and / or the control bus 239 through the CPU interface device 223.

FIG. 3 illustrates an example of instruction 300. The illustrated instruction 300 is an instruction having a CISC format compatible with the complex instruction set command (CISC) instruction format used in the X86 processor platform provided by Intel. Instruction 300 has a prefix section 301, an OP code section 303 that defines a logical or mathematical command to be executed by the execution unit 221, an addressing mode specific field 305, an address substitution field 307, and an immediate data field 309. As is known, CISC instructions have variable lengths, and some OP codes may not utilize all of the instruction fields. Intel's CISC instruction format and programming are well known in the industry.

[0015] According to the present invention, the instruction processing device 201 has an instruction type detection device 211 for determining whether or not the type of instruction prior to the OP code is a repeatable type. For example, if the prefix section 301 indicates an iterative operation, the instruction type detector 211 detects the iterative instruction type. The execution unit 217 generates a signal indicating that the data combined with the detected instruction cannot be cached in response to the detection of the repeatable instruction type of the instruction type detection device 211. Does Not Cache (DNC) (cache not activated) The instruction signal 215 is output from the CPU via the bus interface device 223. CPU 103 also has a set of buffers 219, which are used as temporary storage to perform operations on the data associated with the detected iterative instructions. In a preferred embodiment, a set of buffers 219 consists of two buffers, each with two cache line widths. That is, the width of each buffer in this buffer set 219 is equal to twice the size of the cache line. The size of this buffer ensures that all data from the iterative move instruction is properly stored.

DNC signals are used in conjunction with cacheable (memory-unmapped I / O, etc.) data or instruction fetch or storage operations, and simply indicate all caches for handling data in the manner shown below. ing.

(The English text in the program list is a symbol representing a command or the like and cannot be translated.) The IF data should be loaded into the processor. The THEN IF data in which the AND DNC signal is set is stored in the THEN processor currently in the cache. Give the cache line containing the data ELSE The data is not currently in the cache The cache line of the DO data is stored in the fetch processor The cache line containing the data is stored in the give cache The cache line is not stored in the give cache Store the data from the ENDIF processor The AND DNC signal to be set is set. THENIF data is currently in the cache. Update the cache with the data from the THEN processor. ELSE data is not currently in the cache. Store the cache line in the output cache. ENDIF without, and without updating the cache memory THEN data with no DNC signal set is not associated with the REP instruction. [0018] The repeat (REP) instruction is a class of instructions, and the instruction is automatically repeated a predetermined number of times. The number of times an instruction is re-executed is determined when the instruction is executed by the contents of a particular general-purpose register (GPR) in the CPU. This general purpose register is called the counting register (CREG).

The repeatable instructions are shown below.

Comparison String (CMPS) Compares a string that starts at the memory address pointed to by the source register with a string that starts at the memory address pointed out by the destination register. Depending on the particular OP code of the instruction, the comparison can be based on bytes, words, or double words. For REP operations, the source and destination addresses are incremented and subsequent bytes, words, or double words are compared. This operation repeats the number of times specified by CREG.

[0021] Compare the contents of the scan string (SCAS) source register with the string starting at the memory address pointed to by the destination register. Depending on the particular OP code of the instruction, the comparison can be based on bytes, words, or double words. For REP operations, the destination address is incremented and the following bytes, words, or double words are compared. This operation repeats the number of times specified by CREG.

Load String (LODS) Loads the destination register with a string that starts at the memory address pointed to by the source register. Depending on the particular OP code of the instruction, the load can be based on bytes, words, or double words. For REP operations, the source address is incremented and the following bytes, words, or double words are loaded. This operation repeats the number of times specified by CREG.

Storage String (STDS) Stores the contents of the source register at the memory address pointed to by the destination register. Depending on the particular OP code of the instruction, storage can be based on bytes, words, or double words. For REP operations, the destination address is incremented and the contents of the source register are stored in the byte, word, or doubleword address that follows memory. This operation repeats the number of times specified by CREG.

[0024] The I / O port address pointed out by the OUT string (OUTS) destination register stores the contents of the memory position pointed out by the source register. Depending on the particular OP code of the instruction, storage can be based on bytes, words, or double words. For REP operations, the source address is incremented and the bytes, words, or double words that follow memory are stored at the I / O port address pointed out by the destination register. This operation repeats the number of times specified by CREG.

The data from the I / O port address pointed out by the IN string (INS) source register is loaded into the memory location pointed out by the destination register. Depending on the particular OP code of the instruction, the load can be based on bytes, words, or double words. The destination address is incremented for the REP operation. This operation repeats the number of times specified by CREG.

[0026] Move the data at the memory location pointed out by the contents of the moving string (MOVS) source to the memory location pointed out by the destination position. Depending on the particular OP code of the instruction, storage can be based on bytes, words, or double words. For REP operations, the source and destination addresses are incremented and the bytes, words, or double words that follow memory are moved. This operation repeats the number of times specified by CREG.

[0027] The execution of the pseudo code of the present invention for each of the REP instructions defined above will be described. First of all, for all of the following operations, let CREG load the number of iterative operations to be executed before executing the instruction to be iterated. For all of the following operations, the two buffers 219 are referred to as the A and B buffers.

[0028] CHECK the buffer of the REP CMPS execution unit. IF No need to access THEN cache where required data is currently in these buffers. ISSUE data read request by ELSEDO execution unit. The DNC signal is set. The amount of cached lines of data is loaded into the A buffer. WHEN Load is complete, the DNC signal is reset. The second data read request is ISSUE by the execution unit. The DNC signal is set. The amount of cached lines of data is loaded into the B buffer. The WHEN load is complete and the DNC signal is RESETd. END The comparison operation is EXECUTE. DECREMENT CREG and REPEAT operations that are not IF zero.

[0029] CHECK the buffer of the REP SCAS execution unit. The data in the IF request does not need to access the THEN cache, which is currently in the buffer. The ELSEDO data read request is ISSUE by the execution unit. The DNC signal is set. The amount of cached lines of data is loaded into the A buffer. When the WHEN load is complete, the THEN DNC signal is reset. The END scan operation is EXECUTE. DECREMENT CREG and REPEAT operations that are not IF zero.

[0030] Check the A buffer of the REP LODS execution unit. IF No need to access THEN cache where required data is currently in this buffer. The ELSEDO data read request is ISSUE by the execution unit. The DNC signal is set. The amount of cached lines of data is loaded into the A buffer. The DNC signal that completes the WHEN load is reset. The END load operation is EXECUTE. DECREMENT CREG and REPEAT operations that are not IF zero.

REP STDS data storage is ISSUE by the execution unit. The DNC signal is set. WHEN storage is complete, the DNC signal is RESETd. DECREMENT CREG and REPEAT operations that are not IF zero.

[0032] The THENDO data read request for which the data of the REP OUTSIF request is not currently in the A buffer is ISSUE by the execution unit. The DNC signal is set. The DNC signal that completes WHEN storage is reset. DECREMENT data to the END port, SENDCREG, and REPEAT an operation that is not IF zero.

[0033] REP INSIF For the first time in a REP operation, the THENDO execution unit sets the DNC signal for which a data request has been ISSUE. RECEIVEWHEN load completed with data cache line amount into A buffer RESETENDELSE This is not the first time in a REP operation THENDOIF request data position is not currently in A buffer THENDOA buffer data storage ISSUEDNC signal SETWHEN data A data request is ISSUE by the RESET execution unit for the DNC signal that has been stored. The DNC signal is set. RECEIVEWHEN load completed with data cache line amount into A buffer RESET END NC signal from A buffer to B buffer MOVEEND CREG DECREMENT and IF non-zero, REPEATWHEN CREG equal to zero, REP The data storage of the A buffer to which IN is COMPLETE at that time is ISSUE by the execution unit. At the same time, the DNC signal is set. WHEN The memory is completed, the DNC signal is reset. Load that data from the port into the A buffer.

[0034] CHECK the A buffer of the REP MOVS execution unit. The IF request data does not need to access the THEN cache currently in that buffer. The ELSEDO data request is ISSUE by the execution unit. The DNC signal is set. RECEIVE WHEN load is completed with the amount of data cache line in the A buffer, and the DNC signal is checked in the B buffer of the RESET execution unit. It is not necessary to access the THENDO cache where the ENDIF request storage location is currently in the B buffer. MOVEENDELSEIF data from A buffer to B buffer This is the first time in a REP operation that a THENDO data request is ISSUE by the execution unit. The DNC signal is set. RECEIVE WHEN loading of data cache line amount into A buffer completed THEN RESET ENDELSE DNC signal This is not the first time in a REP operation ISSUEDNC signal is set to store data in the DOB buffer. WHEN Data storage completed DNC signal RESET Execution unit ISSUE data request. The DNC signal is set. RECEIVE WHEN load completed with cache line amount of data into B buffer THENDODNC signal from RESET A buffer to B buffer MOVE ENDEND CREG is not DECREMENTIF zero, operation REPEAT WHEN CREG is equal to zero REP MOVS is COMPLETE at that point. The data storage in the B buffer is ISSUE by the execution unit. At the same time, the DNC signal is set. WHEN The memory is completed, the DNC signal is reset.

[0035] It can be seen that the present invention eliminates the problem of expulsion of a cache at the time of repeated instructions by protecting the iterative instruction from the influence on the cache (or the cache for a system having a multi-level CPU cache). DNC signals are unique when data should be processed so that it can be cached as it is transferred. Data is transferred on one cache line at a time. However, when the DNC signal is set, the cache will consistently no longer load or store data in the cache to maintain the consistency of the data in the system.

[0036] As mentioned above, the present invention achieves this by using a new signal called DNC (cache inactive). The DNC is an indicator for the cache and this criterion should be treated as normal cache access except when the data associated with this request does not need to be cached. This is different from non-cacheable requests. Non-cacheable data is data that cannot be cached. Memory-mapped I / O is an example of such data. Non-cacheable data is usually handled separately by this system. Normally, when non-cacheable data is fetched, it is not fetched as a cache line. Also, non-cacheable data is usually treated separately from those related to cache retrieval. According to the present invention, all types of repetitive instructions are shown as non-cacheable. That is, the data associated with this instruction type is non-cacheable. This instruction was created to throw away valuable cached data generated in repetitive move instructions and avoid replacing it with unused data. Instead, use a set of buffers 219 as temporary storage space to store data related to the type of iterative command. Thus, each buffer is considered to have a width equal to a multiple of the data width of the CPU bus.

[0037] As a summary, the following matters will be disclosed with respect to the configuration of the present invention.

(1) To determine the instruction type in a central processing unit (CPU) of a computer system having a cache device connected to the central processing unit via a data bus having a predetermined data bus width. An instruction processing device that has an instruction decoding device that decodes the instruction and processes a CPU instruction, an instruction type detection device that detects a cacheable instruction type or a non-cacheable instruction type, and an execution unit that executes the instruction. The central processing unit responds to the instruction type detection device and outputs a cache capability indicator signal indicating whether or not the data related to the detected instruction type can be cached. (2) The instruction type detection device detects an iterative type instruction, and the execution unit responds to the detection of the iterative type instruction and outputs the cache capability indicator signal indicating data related to the non-cacheable iterative type instruction. The central processing unit according to (1) above, which is characterized by outputting. (3) The central processing unit according to (2) above, further comprising a storage buffer for storing data related to the iterative instruction type. (4) The central processing unit according to (3) above, wherein the storage buffer has two registers. (5) The central processing unit according to (4) above, wherein the register has a register width substantially equal to an integral multiple of the data bus width. (6) The central processing unit according to (5) above, wherein the register width is substantially equal to twice the data bus width. (7) Further, the internal cache control device is provided, and the control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to the instruction type to the internal cache. Central processing unit according to 1). (8) A. A system memory, B. an optional external cache, C. a memory control device for controlling the system memory, and D. a central processing unit for processing instructions. Is a. An instruction decoding device that decodes the instruction that determines the instruction type, b. an instruction type detection device that detects a cacheable instruction type or a non-cacheable instruction type, and c. a reaction and detection of the instruction type detection device. A computer system comprising an execution unit that executes an instruction that outputs a cache capability indicator signal indicating whether the data associated with the instruction type can be cached. (9) The instruction type detection device detects an iterative type instruction, the execution unit responds to the detection of the iterative type instruction, and outputs the cache capability indicator signal indicating data related to the non-cacheable iterative type instruction. The computer system according to (8) above. (10) The computer system according to (9) above, further comprising a storage buffer for storing data associated with the iterative instruction type. (11) The computer system according to (10) above, wherein the storage buffer has two registers. (12) The computer system according to (11) above, wherein the register has a register width substantially equal to an integral multiple of the data bus width. (13) The computer system according to (12) above, wherein the register width is approximately equal to twice the data bus width. (14) Further, the internal cache control device is provided, and the control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to the instruction type to the internal cache. The computer system described in 8). (15) The computer system according to (8) above, wherein the memory control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to an instruction type to the internal cache. .. A computer characterized by having an execution unit that executes the instruction in response to the instruction type detection device and outputs a cache capability indicator signal indicating whether or not the data related to the detected instruction type can be cached. system. (9) The instruction type detection device detects an iterative type instruction, the execution unit responds to the detection of the iterative type instruction, and outputs the cache capability indicator signal indicating data related to the non-cacheable iterative type instruction. The computer system according to (8) above. (10) The computer system according to (9) above, further comprising a storage buffer for storing data associated with the iterative instruction type. (11) The computer system according to (10) above, wherein the storage buffer has two registers. (12) The computer system according to (11) above, wherein the register has a register width substantially equal to an integral multiple of the data bus width. (13) The computer system according to (12) above, wherein the register width is approximately equal to twice the data bus width. (14) Further, the internal cache control device is provided, and the control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to the instruction type to the internal cache. The computer system described in 8). (15) The computer system according to (8) above, wherein the memory control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to an instruction type to the internal cache. .. A computer characterized by having an execution unit that executes the instruction in response to the instruction type detection device and outputs a cache capability indicator signal indicating whether or not the data related to the detected instruction type can be cached. system. (9) The instruction type detection device detects an iterative type instruction, the execution unit responds to the detection of the iterative type instruction, and outputs the cache capability indicator signal indicating data related to the non-cacheable iterative type instruction. The computer system according to (8) above. (10) The computer system according to (9) above, further comprising a storage buffer for storing data associated with the iterative instruction type. (11) The computer system according to (10) above, wherein the storage buffer has two registers. (12) The computer system according to (11) above, wherein the register has a register width substantially equal to an integral multiple of the data bus width. (13) The computer system according to (12) above, wherein the register width is approximately equal to twice the data bus width. (14) Further, the internal cache control device is provided, and the control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to the instruction type to the internal cache. The computer system described in 8). (15) The computer system according to (8) above, wherein the memory control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to an instruction type to the internal cache. .. The computer system according to (8) above, wherein the knit responds to the detection of the iterative type instruction and outputs the cache capability indicator signal indicating data associated with the non-cacheable iterative type instruction. (10) The computer system according to (9) above, further comprising a storage buffer for storing data associated with the iterative instruction type. (11) The computer system according to (10) above, wherein the storage buffer has two registers. (12) The computer system according to (11) above, wherein the register has a register width substantially equal to an integral multiple of the data bus width. (13) The computer system according to (12) above, wherein the register width is approximately equal to twice the data bus width. (14) Further, the internal cache control device is provided, and the control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to the instruction type to the internal cache. The computer system described in 8). (15) The computer system according to (8) above, wherein the memory control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to an instruction type to the internal cache. .. The computer system according to (8) above, wherein the knit responds to the detection of the iterative type instruction and outputs the cache capability indicator signal indicating data associated with the non-cacheable iterative type instruction. (10) The computer system according to (9) above, further comprising a storage buffer for storing data associated with the iterative instruction type. (11) The computer system according to (10) above, wherein the storage buffer has two registers. (12) The computer system according to (11) above, wherein the register has a register width substantially equal to an integral multiple of the data bus width. (13) The computer system according to (12) above, wherein the register width is approximately equal to twice the data bus width. (14) Further, the internal cache control device is provided, and the control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to the instruction type to the internal cache. The computer system described in 8). (15) The computer system according to (8) above, wherein the memory control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to an instruction type to the internal cache. .. Computer system. (13) The computer system according to (12) above, wherein the register width is approximately equal to twice the data bus width. (14) Further, the internal cache control device is provided, and the control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to the instruction type to the internal cache. The computer system described in 8). (15) The computer system according to (8) above, wherein the memory control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to an instruction type to the internal cache. .. Computer system. (13) The computer system according to (12) above, wherein the register width is approximately equal to twice the data bus width. (14) Further, the internal cache control device is provided, and the control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to the instruction type to the internal cache. The computer system described in 8). (15) The computer system according to (8) above, wherein the memory control device reacts to the cache capacity indicator signal to determine the cache capacity of data related to an instruction type to the internal cache. ..

[Effect of the Invention] The present invention can eliminate the problem of expulsion of stored data required at the time of repetitive instruction of the cache by protecting the repetitive instruction from the influence on the cache.

BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1] Fig. 1 is a block diagram showing an example of a computer system incorporating the CPU of the present invention.

FIG. 2 is a block diagram of a CPU according to the present invention.

FIG. 3 is a diagram of an instruction format executed by the CPU of FIG.

[Code description] 100 Computer system 101 Read-only storage device (ROM) 103 Central processing device 104 L1 cache 105 L2 cache 106 Cache control device 107 System memory (host memory) 109 Memory control device 110 Host processing system 111 I / O bridge interface 113 local interface controller 114 storage 115 local device 120 local processing system 130 input / output (I / O) expansion bus 200 central processing device 201 instruction processing device 203 instruction fetch 205 L1 instruction cache device 207 L1 Data cache 209 Instruction decoder 211 Instruction type detector 217 Execution unit 219 Buffer 223 CPU bus Interface device 230 CPU bus 235 Data bus 237 Address bus 239 Control bus 300 Instruction 301 Prefix field 303 OP code field 305 Address Specified mode Specific field 307 Address replacement field 309 Immediate data field