Multiprocessor system with vector pipelines.

Description: TECHNICAL FIELD [Detailed description of the invention]

[Industrial Application Field] The present invention relates to a multiprocessor system.

[Conventional technology]

Since the shipment of a computer system named Cray-1 from the US company Cray in 1978, the demand for scientific calculations has increased rapidly, and various improvements have been made to realize high-speed calculations. As such an improvement, for example, a method of providing a plurality of vector calculation units for performing vector operations, a method in which the instruction control unit controls these vector calculation units to process a large-scale vector at high speed, and a plurality of processors are provided. There are methods such as performing multiprocessing to improve throughput.

[Problems to be solved by the invention]

By the way, when a vector calculation unit is provided with a plurality of vector calculation units, it is difficult to handle a large number of jobs, and when a plurality of processors are provided to perform a calculation, the vector calculation unit is generally used alone. Since it is one, there is a problem that the response time in the processing of a large-scale vector becomes slow. In other words, the conventional calculation system has insufficient computing power to satisfy the demand for processing a large amount of vector data at high speed and processing a large number of jobs.

An object of the present invention is to provide a multiprocessor system capable of processing a large amount of vector data at high speed and a large number of jobs.

[Means to solve problems]

The multi-processor system of the present invention is provided with a plurality of processors, a shared memory shared by the plurality of processors, and at least one of each of the plurality of processors, and the number of installations is independently set for each of the processors. A vector calculation unit, a configuration information holding means provided corresponding to each of the plurality of processors and holding configuration information indicating the configuration of the vector calculation unit installed in the processor, the shared memory, and the plurality of. When data is transferred to and from the vector calculation unit provided in the processor, the vector calculation unit shown in the configuration information held in the configuration information means of one of the plurality of processors to which the data transfer is performed and the vector calculation unit. It includes a control means for controlling data transfer to and from the shared memory.

[Example]

Next, the present invention will be described by way of examples.

With reference to FIG. 1, the multiprocessor system according to the present invention includes processors 1 and 2, a memory access control device (MAC) 3 and a main storage device (MM) 4.

Request information is supplied from the processor 1 to the MAC 3 via the connection 101, store data is supplied via the connection 102, and load data is supplied from the MAC 3 to the processor 1 via the connection 103. Similarly, request information is supplied from the processor 2 to the MAC3 via the connection 111, store data is supplied via the connection 112, and load data is supplied from the MAC3 to the processor 2 via the connection 113. In MAC3 and MM4, request information and address are supplied from MAC3 to MM4 via connection 121, store data is supplied from MAC3 to MM4 via connection 122, and load data is supplied from MM4 to MAC3 via connection 123, respectively. MAC3 and MM4 are connected by three ports, and request information, store data, and load data are transferred to each.

As shown in FIG. 2, the processors 1 and 2 include an instruction control unit 11 and a vector operation unit 21 to 24. The instruction control unit 11 controls the decoding and issuance of instructions, and when the vector operation instruction is decoded, the instruction control unit 11 issues an operation instruction to the operation units 21 to 24 via the connection 200. When the instruction control unit 11 decodes the memory reference instruction, it sends request information such as a request, a command, an address, and a distance between elements of vector data to MAC3 via the connection 101-1.

When data is transmitted due to the end of memory access, a reply signal is supplied from MAC3 to the instruction control unit 11 via the connection 101-2, and when the instruction control unit 11 receives the reply signal, a vector operation is performed via the connection 200. Instruct units 21 to 24 to import load data. Vector operation units 21 to 24 operate in parallel in the vector operation pipeline, and each vector operation unit has a set of vector registers holding multiple elements and a set of addition / subtraction, multiplication / division, logical operation, and shift operation pipelines. There is. Then, the element numbers are given in the order of configuration of the vector operation units 21 to 24, and the same vector operation unit is assigned to process the element numbers divided by the number of vector operation units and having the same remainder. In addition, if any of the vector operation units 21 to 24 fails, the instruction control unit determines which vector operation unit that can operate in a degenerate manner is configured or equipped. It is indicated by the vector operation unit configuration register 12 provided in 11. The register 12 consists of 4 bits, and each bit corresponds to the vector operation units 21 to 24, respectively. That is, when all vector operation units are configured, the value held in register 12 is "1111". Further, for example, when only the vector operation unit 21 is configured, the value held in the register 12 is 1000. Register 12 is set only by a scan path (not shown), and the values that register 12 can take are "1111", "1100", "0011", "1000", "0100", "for ease of control by MAC3. It is limited to 7 ways, 0010 "and" 0001 ". Load data from MM4, The store data to MM4 has a path between each vector operation unit 21 to 24 and MAC3, and the store data is transferred from vector operation units 21 to 24 to MAC3 via paths 102-1 to 102-4, respectively. It is sent, and load data is sent from MAC3 to vector operation units 21 to 24 via paths 103-1 to 103-4, respectively. If any of the vector operation units 21 to 24 is not configured (equipped), MAC3 selects to send only the data from the vector operation unit configured as store data to MM4, and the load data is configured. It controls so that all the data read from MM4 is supplied to the vector calculation unit.

As shown in FIG. 3, the MAC 3 includes a request control unit 51, an address generation unit 52, a switching circuit 53, an align control unit 54 and 57, an align circuit 55 and 58, and a delay circuit 55. The request control unit 51 controls the request to the MM4 based on the request information supplied from the processors 1 and 2 via the connections 101-1 and 111-1, respectively. In addition to the request signal, the request information includes the start address of the vector data, the spacing between the elements of the vector data, the number of elements of the vector data, the command indicating the access type, and the vector operation unit configuration information held in the register 12. include. The request control unit 51 arbitrates the request from the processor 1 and the request from the processor 2, and determines the maximum number of elements to be accessed at the same time based on the request information. The maximum number of simultaneous access elements is determined by the number of configuration vector operation units included in the request information. That is, when four vector operation units are configured, the maximum number of simultaneous access elements is 4, two, and in the case of one, the maximum number of simultaneous access elements is 2 and 1, respectively. Since the request information is sent for each processor, the maximum number of simultaneous access elements can be correctly obtained for each request even if the number of vector operation units differs for each processor.

The maximum number of these simultaneous access elements is sent to the address generation unit 52 via the connection 300 together with the start address and the interval between the elements, and the address of each element is calculated here. Then, these calculated addresses are sent to the corresponding ports together with the request via the connections 121-1 to 121-4.

The store data from the vector operation units 21 to 24 is supplied from the processor 1 and the processor 2 to the switching circuit 53 via the paths 102-1 to 102-4 and the paths 112-1 to 112-4, respectively. In the switching circuit 53, the store data from the processor on the processing side is arbitrated by the request control unit 51, and the store data is supplied from the request control unit 51 via the connection 301 via the connection 302-1 to 302-4, respectively. Is supplied to the align circuit 55. The align circuit 55 receives the store data from the vector calculation units 21 to 24 as inputs via the connections 302-1 to 302-4, and the memory ports 122-1 to the addresses where the respective store data are stored are stored. It is a circuit that aligns to output to 122-4, and is controlled by the control signal generated by the align control unit 54. The align control unit 54 generates a control signal for the align circuit 55 based on the start address, the inter-element spacing, and the vector calculation unit configuration information supplied by the connection 303. The configurations of the align control unit 54 and the align circuit 55 are described in, for example, Japanese Patent Application No. 61-12258.

Here, since the vector calculation unit configuration information is independently supplied as request information from each processor (in the case of this embodiment, the processor 1 and the processor 2), even if the configuration of the vector calculation unit is different for each processor, each processor The align circuit 55 can be controlled by the configuration of the vector calculation unit corresponding to the processor of. For example, when the content of the register 12 of the processor 1 is "1111" and the content of the register 12 of the processor 2 is "0011", the address of the first element is the port corresponding to the memory port 122-1 and the address of the next element is. Assuming that it belongs to the port corresponding to the memory port 122-2, when accessing from the processor 1, the data supplied from the connection 302-1 to the align circuit 55 is connected to the MM4 via the memory port 122-1 and the connection 302-. The data supplied from 2 to the align circuit 55 is sent to the MM4 via the memory ports 122-2.

On the other hand, in the access from the processor 2, even if the address of the first element and the interval between the elements are the same as those of the processor 1, the processor 2 only constitutes the vector calculation units 23 and 24, so the data is sent from the vector calculation unit 23. The data that has been received, that is, the data that is supplied to the align circuit 55 via the connection 302-3, is sent to the MM4 via the memory port 122-1 from the vector calculation unit 24, that is, the connection 302-4. The data supplied to the align circuit 55 via the memory port 122-2 is sent to the MM4 via the memory port 122-2.

Information about the request sent from the request control unit 51 to the MM4 is sent to the delay circuit 6 via the connection 303, and this request information is delayed by the access time to the MM4, and the reply to the processor 1 is connected to the connection 101-. The reply to the processor 2 is sent to the processors 1 and 2 via the connection 111-2 via 2. Further, in order to supply the data read from the MM4 to the vector calculation unit of each processor, control information is supplied from the delay circuit 56 to the align control unit 57 via the connection 305. The data read from the MM4 via the memory ports 123-1 to 123-4 is input to the align control unit 57, and the read data is connected to the corresponding vector calculation units 21 to 24 103-1 to 103-4, or Align to supply via connections 113-1 to 113-4. The align control unit 57 and the align circuit 58 are the same as the align circuit 55 and the align control unit 54 used when storing data in the MM4, except that the vector calculation unit side is the output side. That is, the align circuit 58 is controlled so as to return the data read from the start address to the corresponding vector operation unit based on the vector operation unit configuration information. Therefore, even if the configuration of the vector operation unit is different for each processor, the load data can be correctly supplied to the vector operation unit.

[Effect of the invention]

As described above, in the present invention, each processor includes at least one vector operation unit, and the number of vector operation units in each processor is determined without depending on the number of vector operation units in other processors. That is, the number of constituents of the vector arithmetic unit is determined independently for each processor, and at the time of main memory access, each processor includes the configuration information indicating the configuration of the vector arithmetic unit in the request information and is stored in the memory. Since it is given to the access control device, the main memory access control can be performed even if the configuration of the vector calculation unit is different for each processor. That is, the processor can be operated. This enables a flexible system configuration and minimizes the degeneracy of the vector operation unit.

Therefore, a large amount of vector data can be processed at high speed and a large number of jobs can be processed.

[Simple explanation of drawings]

FIG. 1 is a block diagram showing a multiprocessor system according to the present invention, FIG. 2 is a block diagram showing an embodiment of a processor configuration, and FIG. 3 is an embodiment of a memory access control device configuration of FIG. It is a block diagram which shows. 1,2 ...... Processor, 3 ...... Memory access control unit (MAC), 4 ...... Main storage unit (MM), 11 ...... Instruction control unit, 12 ...... Pipeline arithmetic unit configuration register, 21-24 ...... Vector calculation unit, 51 ...... Request control unit, 52 ...... Address generator, 53 ...... Switching circuit, 54, 57 ...... Align control unit, 55, 58 ...... Align circuit, 56 ...... Delay circuit.