Multilayer printed circuit board containing semiconductor elements

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention also relates to a build-up multilayer printed wiring board, and particularly to a multilayer printed wiring board incorporating electronic components such as IC chips.

【0002】

[Conventional technology]

The IC chip was electrically connected to the printed wiring board by mounting methods such as wire bonding, TAB, and flip chip. Wire bonding is to protect the IC chip and the wire after die-bonding the IC chip to the printed wiring board with an adhesive and connecting the pad of the printed wiring board and the pad of the IC chip with a wire such as a gold wire. Was coated with a sealing resin such as a thermosetting resin or a thermoplastic resin. In TAB, the bumps of the IC chip and the pads of the printed wiring board were connected together with wires called leads by soldering, etc., and then sealed with resin. The flip chip was performed by connecting the IC chip and the pad portion of the printed wiring board via bumps and filling the gap between the bumps with resin.

【0003】

[Problems to be Solved by the Invention]

However, in each mounting method, electrical connection is made between the IC chip and the printed wiring board via lead components (wires, leads, bumps) for connection. Each of these lead components is easily cut and corroded, which may cause a loss of connection with the IC chip or a malfunction. Further, in each mounting method, sealing is performed with a thermoplastic resin such as epoxy resin in order to protect the IC chip, but if air bubbles are contained when filling the resin, the air bubbles become the starting point. It causes destruction of lead parts, corrosion of IC pads, and deterioration of reliability. For sealing with thermoplastic resin, it is necessary to create a resin loading plunger and mold according to each part, and even if it is a thermosetting resin, consider the materials such as lead parts and solder resist. Since it is necessary to select the selected resin, it also causes a high cost in each case.

【0004】

Therefore, various techniques for embedding a semiconductor element in a substrate have been proposed. As a technique for establishing an electrical connection by embedding a semiconductor element in a substrate and forming a build-up layer on the substrate, JP-A-9-321408 (USP5875100), JP-A-10-256429, and JP-A-11-126978 No., etc. have been proposed.

【0005】

In Japanese Patent Application Laid-Open No. 9-321408 (USP5875100), a semiconductor element having stud bumps formed on a die pad is built in a printed wiring board, and wiring is formed on the stud bumps to make an electrical connection. However, since the height of the stud bumps varies widely, there is a problem in connectivity. In addition, these stud bumps are planted one by one by bonding, and there is a problem in productivity.

【0006】

In Japanese Patent Application Laid-Open No. 10-256429, a semiconductor element was built in a ceramic substrate and electrically connected in the form of a flip chip. However, ceramics have poor outer shape workability, and semiconductor elements do not fit well. Further, since the height of the bump varies widely, there is a problem in connectivity.

【0007】

In Japanese Patent Application Laid-Open No. 11-126978, a semiconductor element is built in a gap accommodating portion of a multilayer printed wiring board stored via a via hole to connect with a conductor circuit. However, since the accommodating portion is a gap, misalignment is likely to occur, and there is a problem in connectivity. Further, since the die pad and the conductor circuit are directly connected, there is a problem that an oxide film is easily formed on the die pad and the insulation resistance increases.

【0008】

In addition, when using a multi-layer printed wiring board composed of a board in which a semiconductor element is embedded, housed, and housed as a package board, chipset, etc., it should be electrically connected to an external board (so-called motherboard, daughter board). Can exert its function. Therefore, it is necessary to dispose a BGA or a conductive connection pin (PGA) on the multilayer printed wiring board. The BGA and PGA are formed by disposing a solder pad on the solder resist layer on the surface of the multilayer printed wiring board.

【0009】

However, when solder bumps are arranged on the surface layer of a substrate in which a semiconductor element is embedded and electrically connected to an external substrate to perform a functional test or a reliability test, an interlayer insulating layer, a solder resist layer, and an interlayer resin insulating layer are performed. Cracks and peeling occurred around the solder resist, solder bumps, and solder bumps (intended to be a solder layer or corrosion-resistant metal), and it was confirmed that the solder bumps fell off or were misaligned. In particular, it was confirmed that cracks were generated in the pads of the semiconductor element through the interlayer insulating layer. Therefore, in the multilayer printed wiring board containing the semiconductor element, it has been clarified that the electrical connectivity and reliability between the solder bump and the conductor circuit are deteriorated.

【0010】

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is a multilayer printed wiring board having high electrical connectivity and reliability, particularly a multilayer printed wiring board having a built-in semiconductor element. The purpose is to propose.

【0011】

[Means for solving problems]

In order to achieve the above object, in the multilayer printed wiring board according to claim 1, an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate in which a semiconductor element is embedded, accommodated or housed, and the interlayer insulating layer is formed. In the multilayer printed wiring board in which a via hole is formed and electrically connected via the via hole, an external connection terminal (BGA / PGA) is formed only in a region other than directly above the semiconductor element in the substrate. Is a technical feature.

【0012】

In the invention of claim 1, the region on the substrate in which the semiconductor element of the multilayer printed wiring board is built is distinguished from the region on the substrate in which the semiconductor element is not built. Then, an external connection terminal (BGA / PGA) is arranged in a region on the substrate in which the semiconductor element is not built. The peeling and cracking that occur around the external connection terminal (BGA / PGA) described above are caused by the difference in the coefficient of thermal expansion of the semiconductor element, the external substrate, the interlayer insulating layer, and the solder resist layer. That is, the semiconductor element and the outer substrate made of ceramic have a small coefficient of thermal expansion and a small elongation due to thermal expansion. On the other hand, since the interlayer insulating layer and the solder resist layer made of resin have a large coefficient of thermal expansion as compared with the semiconductor element and the external substrate, the elongation due to thermal expansion is large. Due to this difference in the coefficient of thermal expansion, stress is concentrated around the external connection terminals (BGA / PGA), causing peeling and cracking. In other words, by arranging the external connection terminal (BGA / PGA) in the area on the substrate where the semiconductor element is not built in, the influence of thermal expansion can be reduced, so that it can be placed around the external connection terminal (BGA / PGA). It is possible to prevent peeling and cracking that occur. Therefore, it is possible to prevent the external connection terminal (BGA / PGA) from falling off or being displaced, and to improve the electrical connectivity and reliability.

【0013】

Here, the external connection terminal means a terminal for connecting to an external board, a so-called motherboard, or a daughter board in a board on which an IC chip is mounted. The terminals of concern are BGA, PGA and solder bumps.

【0014】

In the invention of claim 2, in the multilayer printed wiring board according to claim 1, a transition layer for connecting to the via hole formed in the interlayer insulating layer of the lowermost layer is provided on the pad portion of the semiconductor element. The technical feature is that it is formed.

【0015】

In the invention of claim 2, the transition layer is formed so as to cover the pad of the semiconductor element. The reason for providing the transition layer on the die pad of the IC chip is as follows. IC chip die pads are generally made of aluminum or the like. When the via holes of the interlayer insulating layer were formed by photoetching with the die pad on which the transition layer was not formed, the resin tended to remain on the surface layer of the die pad after exposure and development if the die pad remained. In addition, the adhesion of the developer caused discoloration of the die pad. On the other hand, in the case of a laser, when the via diameter is larger than the die pad diameter, the die pad and passivation (protective film of the IC) are destroyed by the laser. In addition, discoloration and dissolution of the die pad of the IC chip occurred when the IC chip was immersed in an acid, an oxidizing agent, or an etching solution in a subsequent step, or was subjected to various annealing steps. Furthermore, the die pad of the IC chip is made with a diameter of about 20 to 60 μm, and the via hole is larger than that, so that the die pad is likely to be unconnected when the position is displaced.

【0016】

On the other hand, by providing a transition layer made of copper or the like on the die pad, a solvent can be used and resin residue on the die pad can be prevented. Further, discoloration and dissolution of the die pad do not occur even if the die pad is immersed in an acid, an oxidizing agent or an etching solution in a subsequent step, or is subjected to various annealing steps. The formation of an oxide film on the die pad can be prevented. This improves the connectivity and reliability between the die pad and the via hole. Further, by interposing a transition layer having a diameter larger than 20 μm on the die pad of the IC chip, the via hole can be reliably connected. Desirably, the transition layer should be equal to or larger than the diameter of the via hole.

【0017】

Further, by forming a transition layer larger than the pad, the inspection probe pin can be easily contacted, and the inspection can be easily performed. That is, since the inspection can be performed before or after the semiconductor element is built in the substrate, it is possible to determine in advance whether or not the product is acceptable. Therefore, it is possible to improve productivity and reduce costs. That is, it can be said that the semiconductor element provided with the transition layer is a semiconductor element for embedding, accommodating, and accommodating the printed wiring board.

【0018】

The transition layer defined in the present invention will be described. The transition layer means an intermediate intermediate layer provided for directly connecting the IC chip, which is a semiconductor element, and the printed wiring board. As its feature, it is formed of at least two or more metal layers in which a thin film layer is formed on a die pad and a thickening layer is formed on the thin film layer. Then, it is made larger than the die pad of the IC chip which is a semiconductor element. This improves electrical connection and alignment, and enables via-hole processing by laser or photo-etching without damaging the die pad. Therefore, the IC chip can be embedded in the printed wiring board, accommodated, stored, and connected reliably. Further, it is possible to directly form a metal which is a conductor circuit of a printed wiring board on the transition layer. Examples of the conductor circuit include via holes in the interlayer insulating layer and through holes on the substrate.

【0019】

The transition layer is formed as follows. A conductive metal film (first thin film layer) is formed on the entire surface by vapor deposition, sputtering, etc. on the entire surface of the IC chip. As the metal, tin, chromium, titanium, nickel, zinc, cobalt, gold, copper and the like are preferable. The thickness is preferably formed between 0.001 and 2.0 μm. If it is less than 0.001 μm, it cannot be uniformly laminated on the entire surface. It was difficult to form anything larger than 2.0 μm, and the effect was not enhanced. In the case of chromium, a thickness of 0.1 μm is desirable. In particular, 0.01 to 1.0 μm is desirable. In particular, it is preferably formed of nickel, chromium and titanium. This is because there is no intrusion of moisture from the interface and the metal adhesion is excellent.

【0020】

The first thin film layer can coat the die pad and improve the adhesion between the transition layer and the IC chip at the interface between the die pad and the IC chip. Further, by coating the die pad with these metals, it is possible to prevent the invasion of moisture into the interface, prevent the die pad from melting and corroding, and improve the reliability. In addition, this first thin film layer enables connection with an IC chip by a leadless mounting method. Here, it is desirable to use chromium and titanium in order to prevent the intrusion of moisture into the interface.

【0021】

A second thin film layer is formed on the first thin film layer by sputtering, vapor deposition, or electroless plating. The metals include nickel, copper, gold and silver. Copper should be used because of its electrical properties, economy, and the thickening layer that will be formed later is mainly copper.

【0022】

The reason why the second thin film layer is provided here is that the lead for electrolytic plating for forming the thickening layer described later cannot be taken in the first thin film layer. The second thin film layer 36 is used as a thickening lead. The thickness should be in the range of 0.01 to 5 μm. If it is less than 0.01 μm, it cannot serve as a lead, and if it exceeds 5 μm, more of the first thin film layer underneath is scraped off to create gaps, which makes it easier for moisture to penetrate and reliability. Is reduced.

【0023】

The second thin film layer is thickened by electroless or electroplating. The types of metals formed include copper, nickel, gold, silver, zinc and iron. Since the electrical characteristics, economy, strength and structural resistance as a transition layer, and the conductor layer that is the build-up to be formed later are mainly copper, it is desirable to form it by electroplating using copper. .. The thickness should be in the range of 1 to 20 μm. If it is thinner than 1 μm, the connection reliability with the upper via hole will decrease, and if it is thicker than 20 μm, undercut will occur during etching, and a gap will be created between the transition layer and the via hole to be formed. Because. Further, depending on the case, the first thin film layer may be directly thickly plated, or may be further laminated in multiple layers.

【0024】

After that, an etching resist is formed, exposed and developed to expose the metal other than the transition layer, and etching is performed. The die pad of the IC chip is composed of a first thin film layer, a second thin film layer, and a thickening layer. Form a transition layer.

【0025】

In addition to the above method for manufacturing a transition layer, a metal film formed on an IC chip is thickened by electroplating, and then a dry film resist is formed to remove a portion other than the transition layer. A transition layer can also be formed on the die pad. Further, after the IC chip is attached to the core substrate, a transition layer can be formed on the die pad of the IC chip in the same manner.

【0026】

In the invention of claim 3, in the multilayer printed wiring board according to claim 1, a resin filling material is filled between the recess or through hole of the substrate into which the semiconductor element is embedded, accommodated or accommodated, and the semiconductor element. The technical feature is what was done.

【0027】

In the invention of claim 3, the adhesiveness between the substrate and the semiconductor element is improved by filling the recess or through hole of the substrate with the resin filling material between the semiconductor element. Further, since this resin-filled material relaxes the stress generated by thermal expansion, it is possible to prevent cracks in the core substrate and waviness of the interlayer resin insulating layer and the solder resist layer. Therefore, it is possible to prevent peeling and cracking that occur around the solder bumps. Therefore, it is possible to prevent the solder pump from falling off and misalignment, so that it is possible to improve electrical connectivity and reliability. As the resin filling material, a thermosetting resin, a thermoplastic resin, or a composite thereof can be used.

【0028】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment] First, the configuration of the multilayer printed wiring board according to the first embodiment of the present invention will be described with reference to FIG. 14 showing a cross section of the multilayer printed wiring board 10.

【0029】

As shown in FIG. 14, the multilayer printed wiring board 10 includes a core substrate 30 for accommodating an IC chip 20, an interlayer resin insulating layer 50, an interlayer resin insulating layer 150, and an interlayer resin insulating layer 250. A via hole 60 and a conductor circuit 58 are formed in the interlayer resin insulating layer 50, a via hole 160 and a conductor circuit 158 are formed in the interlayer resin insulating layer 150, and a via hole 260 and a conductor circuit 58 are formed in the interlayer resin insulating layer 250. A conductor circuit 258 is formed.

【0030】

A solder resist layer 70 is disposed on the interlayer resin insulating layer 250. The conductor circuit 258 under the opening 71 of the solder resist layer 70 is provided with a BGA 76 for connecting to an external board such as a daughter board or a motherboard (not shown). The BGA76 is arranged in an area R2 other than the area R1 directly above the IC chip 20.

【0031】

The IC chip 20 is covered with a passivation film 24 that protects the IC chip 20, and a die pad 22 that constitutes an input / output terminal is arranged in the opening of the passivation film 24. A transition layer 38 mainly made of copper is formed on the pad 22.

【0032】

An adhesive material 34, which is a resin material, is filled between the IC chip 20 and the inside of the recess 32 of the substrate 30. The IC chip 20 is fixed in the recess of the substrate 30 by the adhesive material 34. Since the resin filling material 34 relaxes the stress generated by thermal expansion, it is possible to prevent cracks in the core substrate 30 and waviness of the interlayer resin insulating layers 50, 150, 250 and the solder resist layer 70. Therefore, it is possible to prevent peeling and cracking that occur around the BGA76. Therefore, since the solder pump 76 can be prevented from falling off or being displaced, it is possible to improve the electrical connectivity and reliability.

【0033】

The EE cross section of the multilayer printed wiring board 10 in FIG. 14 is shown in FIG. The inner area shown by the dotted line in FIG. 16 is the area R1 in which the IC chip 20 is built. The area from the outside of the dotted line to the inside of the solid line in FIG. 16 is the area R2 in which the IC chip 20 is not built. The conductor circuit 258 is formed so as to radially extend from the region R1 to the region R2. The solder pads 75 for connecting to the BGA76 are arranged in a grid in the area R2.

【0034】

FIG. 17A shows a plan view of the multilayer printed wiring board 10 in FIG. The BGA76 is arranged in a grid pattern in the area R2 and is connected to an external board such as a daughter board or a motherboard (not shown). The BGA76 may be formed in a staggered pattern in the region R2 as shown in FIG. 17 (B).

【0035】

In the multilayer printed wiring board of the present embodiment, the BGA76 is arranged in the region R2 on the substrate on which the IC chip 20 is not built. That is, by disposing the BGA76 in the region R2 directly above and outside the IC chip 20, the IC chip 20 made of ceramic and having a small coefficient of thermal expansion and the interlayer insulating layers 50, 150, 250 made of resin and having a large coefficient of thermal expansion and Since the influence of thermal expansion with the solder resist layer 70 can be reduced, peeling and cracks that occur around the BGA76 can be prevented. Therefore, it is possible to prevent the solder pump 76 from falling off or misaligning, and to improve electrical connectivity and reliability.

【0036】

Further, in the multilayer printed wiring board 10 of the present embodiment, the IC chip 20 is built in the core substrate 30, and the transition layer 38 is arranged on the pad 22 of the IC chip 20. Therefore, it is possible to establish an electrical connection between the IC chip and the multilayer printed wiring board (package substrate) without using lead parts or sealing resin. Further, since the transition layer 38 is formed on the IC chip portion, the IC chip portion is flattened, so that the interlayer insulating layer 50 of the upper layer is also flattened and the film thickness becomes uniform. Further, the transition layer can maintain the stability of the shape even when the via hole 60 of the upper layer is formed.

【0037】

Further, by providing the transition layer 38 made of copper on the die pad 22, it is possible to prevent the resin remaining on the pad 22, and in the post-process, it is immersed in an acid, an oxidizing agent or an etching solution, and various annealings are performed. No discoloration or dissolution of the pad 22 occurs even after the process. This improves the connectivity and reliability between the pad of the IC chip and the via hole. Further, by interposing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, a via hole having a diameter of 60 μm can be reliably connected.

【0038】

A. Semiconductor device First, with reference to FIG. 18, regarding the configuration of the semiconductor element (IC chip) housed, stored or embedded in the multilayer printed wiring board 10 described above, FIG. 3 (B) showing a cross section of the semiconductor element 20 and a plan view are shown. This will be described with reference to FIG. 4 (B).

【0039】

As shown in FIG. 3B, a die pad 22 and wiring (not shown) are arranged on the upper surface of the semiconductor element 20, and a passivation film 24 is coated on the die pad 22 and the wiring. The die pad 22 is formed with an opening of the passivation film 24. A transition layer 38 mainly made of copper is formed on the die pad 22. The transition layer 38 is composed of a thin film layer 33 and an electrolytic plating film (thick film) 37. In other words, it is made up of two or more layers of metal film.

【0040】

[First Manufacturing Method] Subsequently, the first manufacturing method of the semiconductor device described above with reference to FIG. 3 (B) will be described with reference to FIGS. 1 to 4.

【0041】

(1) First, the wiring 21 and the die pad 22 are formed on the silicon wafer 20A shown in FIG. 1 (A) by a conventional method (see FIG. 4 (A) showing the plan views of FIGS. 1 (B) and 1 (B). Note that FIG. 1 (B) shows the BB cross section of FIG. 4 (A)). (2) Next, a passivation film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided on the die pad 22 (FIG. 1 (C)).

【0042】

(3) Physical vapor deposition such as thin film deposition and sputtering is performed on the silicon wafer 20A to form a conductive metal film (thin film layer) 33 on the entire surface (Fig. 2 (A)). The thickness should be formed in the range of 0.001 to 2 μm. If it is below that range, the thin film layer cannot be formed on the entire surface. If it is above that range, the thickness of the formed film will vary. The optimum range is 0.01 to 1.0 μm. As the metal to be formed, it is preferable to use a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold and copper. These metals serve as a protective film for the die pad and do not deteriorate the electrical characteristics. In the first manufacturing method, the thin film layer 33 is formed of chromium using sputtering. Further, a copper thin film layer may be formed on the chromium thin film layer 33 by sputtering. Two layers of chromium and copper can also be formed continuously in a vacuum chamber. At this time, the thickness is about 0.05 μm to 0.1 μm for chromium and 0.5 μm for copper.

【0043】

(4) After that, a resist layer of any of a liquid resist, a photosensitive resist, and a dry film is formed on the thin film layer 33. A mask (not shown) on which the portion forming the transition layer 38 is drawn is placed on the resist layer, and the plating resist 35 is formed with the non-forming portion 35a through exposure and development. Electroplating is applied to provide a thick layer (electroplating film) 37 on the non-formed portion 35a of the resist layer (Fig. 2 (B)). The types of plating formed include copper, nickel, gold, silver, zinc, and iron. Copper is often used because of its electrical properties, economy, and the build-up conductor layer that will be formed later is mainly copper, and copper is used in the first manufacturing method. The thickness should be in the range of 1 to 20 μm.

【0044】

(5) After removing the plating resist 35 with an alkaline solution or the like, the metal film 33 under the plating resist 35 is coated with sulfuric acid-hydrogenated water, ferric chloride, cupric chloride, cupric acid complex-organic acid salt, etc. The transition layer 38 is formed on the pad 22 of the IC chip by removing it with the etching solution of (Fig. 2 (C)).

【0045】

(6) Next, an etching solution is sprayed onto the substrate by spraying, and the surface of the transition layer 38 is etched to form a roughened surface 38α (see FIG. 3 (A)). A roughened surface can also be formed by electroless plating or redox treatment.

【0046】

(7) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like to form the semiconductor element 20 (plan views of FIGS. 3B and 3B). See Figure 4 (B)). After that, if necessary, the operation of the divided semiconductor element 20 may be confirmed or an electrical inspection may be performed. Since the semiconductor element 20 has a transition layer 38 formed larger than the die pad 22, the probe pin can be easily applied to the semiconductor element 20, and the inspection accuracy is high.

【0047】

[Second Manufacturing Method] The manufacturing method of the semiconductor element 20 according to the second manufacturing method will be described with reference to FIGS. 5 and 6. (1) As described above with reference to FIG. 2 (B) in the first manufacturing method, physical vapor deposition such as thin film deposition and sputtering is performed on the silicon wafer 20A, and a conductive metal film (first thin film) is formed on the entire surface. Layer) 33 is formed (Fig. 5 (A)). Its thickness is preferably in the range of 0.001 to 2 μm. If it is below that range, the thin film layer cannot be formed on the entire surface. If it is above that range, the thickness of the formed film will vary. The optimum range should be formed in 0.01 to 1.0 μm. As the metal to be formed, it is preferable to use a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold and copper. These metals serve as a protective film for the die pad and do not deteriorate the electrical characteristics. In the second manufacturing method, the thin film layer 33 is formed of chromium.

【0048】

(2) The second thin film layer 36 is laminated on the first thin film layer 33 by sputtering, vapor deposition, and electroless plating (FIG. 5 (B)). In that case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it may be formed of either copper or nickel. This is because copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to thin films and is unlikely to cause peeling or cracking. In the second manufacturing method, the second thin film layer 36 is formed by electroless copper plating. The thickness is preferably 0.01 to 5 μm, and particularly preferably 0.1 to 3 μm. The desirable combination of the first thin film layer and the second thin film layer is chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of bondability with metal and electrical conductivity.

【0049】

(3) After that, a resist layer is formed on the thickened layer. A mask (not shown) on which the portion forming the transition layer 38 is drawn is placed on the resist layer, and the plating resist 35 is formed with the non-forming portion 35a through exposure and development. Electroplating is applied and a thick layer (electroplating film) 37 is provided on the non-formed portion 35a of the resist layer (Fig. 5 (C)). The types of plating formed include copper, nickel, gold, silver, zinc, and iron. Copper is preferred because of its electrical properties, economy, and the build-up conductor layer that will be formed later is mainly copper, and copper is used in the second manufacturing method. The thickness should be in the range of 1 to 20 μm.

【0050】

(4) After removing the plating resist 35 with an alkaline solution or the like, the metal film 33 and the metal film 36 under the plating resist 35 are subjected to sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, and cupric complex-. The transition layer 38 is formed on the pad 22 of the IC chip by removing it with an etching solution such as an organic acid salt (Fig. 6).

【0051】

(5) Next, an etching solution is sprayed onto the substrate by spraying, and the surface of the transition layer 38 is etched to form a roughened surface. Since the subsequent steps are the same as those of the first manufacturing method, the description thereof will be omitted.

【0052】

[Third Manufacturing Method] The manufacturing method of the semiconductor element 20 according to the third manufacturing method will be described with reference to FIGS. 7 and 8. The configuration of the semiconductor element of the third manufacturing method is almost the same as that of the first manufacturing method described above with reference to FIG. 3 (B). However, in the first manufacturing method, the transition layer 38 was formed by forming the thick layer 37 in the non-resist forming portion by using the semi-adapted step. On the other hand, in the third manufacturing method, the transition layer 38 is formed by uniformly forming the thickening layer 37 using a full-adaptation step, providing a resist, and removing the non-resist-forming portion by etching.

【0053】

The manufacturing method of this third manufacturing method will be described with reference to. (1) As described above with reference to FIG. 2 (B) in the first manufacturing method, physical vapor deposition such as thin film deposition or sputtering is performed on the silicon wafer 20A to form a conductive metal film 33 on the entire surface. (Fig. 7 (A)). The thickness is preferably in the range of 0.001 to 2.0 μm. If it is below that range, the thin film layer cannot be formed on the entire surface. If it is above that range, the thickness of the formed film will vary. The optimum range should be formed in 0.01 to 1.0 μm. As the metal to be formed, it is preferable to use a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold and copper. These metals serve as a protective film for the die pad and do not deteriorate the electrical characteristics. In the third manufacturing method, the thin film layer 33 is formed of chromium. Further, a thin film layer may be laminated on the thin film layer. In that case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it is preferable to form it with either copper or nickel. This is because copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to thin films and is unlikely to cause peeling or cracking. The desirable combination with the second thin film layer is chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of bondability with metal and electrical conductivity. Further, the thin film can be formed by sputtering, vapor deposition, or electroless plating.

【0054】

Physical vapor deposition such as thin film deposition and sputtering is performed on the entire surface of the IC chip 20A to form a conductive metal film 36 on the entire surface (Fig. 7 (B)). As the metal, one in which one or more layers of metals such as tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper are formed is preferable. The thickness is preferably formed between 0.001 and 2.0 μm.

【0055】

A metal film may be further provided on the metal film 36 by electroless plating or the like. The upper metal film is preferably one in which one or more layers of metals such as nickel, copper, gold, and silver are formed.

【0056】

A plating film 37 is formed on the metal film 36 by electroless or electrolytic plating (FIG. 7 (C)). The types of plating formed include nickel, copper, gold, silver, zinc, and iron. Copper should be used because of its electrical properties, economy, and the build-up conductor layer that will be formed later is mainly copper. The thickness should be in the range of 1 to 20 μm. If it is thicker than that, undercut may occur during etching, and a gap may be generated at the interface between the transition layer and the via hole to be formed. After that, an etching resist is formed, exposed and developed to expose the metal other than the transition layer, and etching is performed to form a transition layer on the pad of the IC chip.

【0057】

(3) After that, the resist layer 35 is formed on the thickening layer 37 (Fig. 8 (A)).

【0058】

(4) The metal film 33 and the thickening layer 37 of the non-formed portion of the plating resist 35 are etched with sulfuric acid-hydrogenated water, ferric chloride, cupric chloride, cupric oxide complex-organic acid salt, etc. After removal, the plating resist 35 is peeled off to form a transition layer 38 on the pad 22 of the IC chip (FIG. 8 (B)). Since the subsequent steps are the same as those of the first manufacturing method, the description thereof will be omitted.

【0059】

Subsequently, the manufacturing method of the multilayer printed wiring board described above with reference to FIG. 14 will be described with reference to FIGS. 9 to 13.

【0060】

(1) First, an insulating resin substrate (core substrate) 30 in which a prepreg impregnated with a resin such as epoxy is laminated on a core material such as glass cloth is prepared as a starting material (see FIG. 9 (A)). Next, a recess 32 for accommodating the IC chip is formed on one side of the core substrate 30 by counterbore processing (see FIG. 9B). Here, the recess is provided by counterbore processing, but a core substrate having an accommodating portion can be formed by laminating an insulating resin substrate having an opening and a resin insulating substrate having no opening.

【0061】

As a resin substrate for incorporating electronic parts such as IC chips, a resin impregnated with a reinforcing material such as glass epoxy resin or a core material or a prepreg impregnated with epoxy resin is laminated on epoxy resin, BT resin, phenol resin, etc. Epoxy is used, but the one generally used for printed wiring boards can be used. In addition, double-sided copper-clad laminates, single-sided plates, resin plates without a metal film, and resin sheets can be used. However, if a temperature of 350 ° C or higher is applied, the resin will melt and carbonize.

【0062】

(2) After that, the adhesive material 34 is applied to the recess 32 using a printing machine. At this time, in addition to coating, potting or the like may be performed. Next, the IC chip 20 according to the manufacturing method described above is placed on the adhesive material 34 with reference to FIGS. 1 to 8 (see FIG. 9 (C)). The adhesive material 34 uses a resin having a coefficient of thermal expansion larger than that of the core substrate 30. As a result, the difference in thermal expansion between the IC chip 20 and the core substrate 30 is absorbed.

【0063】

(3) Then, push or tap the upper surface of the IC chip 20 to completely accommodate it in the recess 32 (see FIG. 9 (D)). As a result, the core substrate 30 can be smoothed. At this time, the adhesive material 34 may be applied to the upper surface of the IC chip 20, but as will be described later, since the resin layer on the upper surface of the IC chip 20 is provided and then the opening for the via hole is provided by the laser, the transition layer and the transition layer are provided. It does not affect the connection with the via hole.

【0064】

(4) On the substrate 30 that has undergone the above steps, a thermosetting resin sheet having a thickness of 50 μm is heated to a temperature of 50 to 150 ° C and a pressure of 5 kg / cm.²Vacuum pressure-bonded laminate with, and provide an interlayer resin insulating layer 50 (see FIG. 10 (A)). The degree of vacuum during vacuum crimping is 10 mmHg.

【0065】

As the interlayer resin insulating layer, a thermosetting resin, a thermoplastic resin, a photosensitive resin, a resin in which a part of the thermosetting resin is replaced with a photosensitive group, a resin composite of a thermosetting resin and a thermoplastic resin, and a photosensitive resin are used. A composite of a sex resin and a thermoplastic resin or the like can be used. Examples of the thermosetting resin include epoxy resin, phenol resin, polyimide resin, polyolefin resin, fluororesin and the like. As the thermoplastic resin, polyether sulfone (PES), polyetherimide, phenoxy resin and the like can be used. Further, even when used as a resin composite thereof, one or more kinds of resins may be mixed and used. For example, there are combinations such as epoxy resin, phenol resin, and phenoxy resin.

【0066】

Further, as described above, the interlayer resin insulating layer 50 is coated with a resin composition whose viscosity has been adjusted in advance by a roll coater, a curtain coater, or the like, instead of forming a semi-cured resin into a sheet and heat-pressing it. It can also be formed by.

【0067】

(5) Next, CO with a wavelength of 10.4 μm₂With a gas laser, a via hole opening 48 with a diameter of 60 μm is provided in the interlayer resin insulating layer 50 under the conditions of a beam diameter of 5 mm, a top hat mode, a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and one shot (Fig. 10). See (B)). Remove the resin residue in the opening 48 with 60 ° C permanganate. By providing the copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented, thereby improving the connectivity and reliability between the pad 22 and the via hole 60 described later. Further, by interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, the opening 48 for the via hole having a diameter of 60 μm can be reliably connected. Here, although the resin residue was removed using permanganate, it is also possible to perform desmear treatment using oxygen plasma.

【0068】

(6) Next, the roughened surface 50α of the interlayer resin insulating layer 50 is provided by immersing it in an oxidizing agent such as dichromic acid or permanganate (see FIG. 10 (C)). The roughened surface 50α is preferably formed in the range of 0.05 to 5 μm. As an example, a roughened surface 50α of 2 to 3 μm is provided by immersing in a sodium permanganate solution of 50 g / l and a temperature of 60 ° C. for 5 to 25 minutes. In addition to the above, it is also possible to perform plasma treatment using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. to form a roughened surface 50α on the surface of the interlayer resin insulating layer 50. At this time, argon gas is used as the inert gas, and plasma treatment is carried out for 2 minutes under the conditions of electric power 200 W, gas pressure 0.6 Pa, and temperature 70 ° C.

【0069】

(7) A metal layer 52 is provided on the interlayer resin insulating layer 50 on which the roughened surface 50α is formed (see FIG. 11 (A)). The metal layer 52 is formed by electroless plating. A catalyst such as palladium is applied to the surface layer of the interlayer resin insulating layer 50 in advance, and the metal layer 52 which is a plating film is provided in the range of 0.1 to 5 μm by immersing it in an electroless plating solution for 5 to 60 minutes. As an example, [Electroless plating solution] NiSO₄ 0.003 mol / l Tartaric acid 0.200 mol / l Copper sulphate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyrzil 100 mg / l Polyethylene glycol (PEG) 0.10 g / l It was immersed for 40 minutes at a liquid temperature of 34 ° C. Other than the above, using the same equipment as the plasma treatment described above, after exchanging the argon gas inside, sputtering targeting Ni and Cu was performed under the conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C, power 200 W, and time 5 minutes. The Ni / Cu metal layer 52 can be formed on the surface of the interlayer resin insulating layer 50. At this time, the thickness of the Ni / Cu metal layer 52 formed is 0.2 μm. Further, instead of sputtering, a metal film can be formed by vapor deposition, electrodeposition, or the like. Further, it is also possible to perform electroless plating after forming the thin layer by a physical method such as sputtering, vapor deposition, or electrodeposition.

【0070】

(8) A commercially available photosensitive dry film is attached to the substrate 30 after the above treatment, and a photomask film is placed on the substrate 30 to 100 mJ / cm.²After exposure with, it is developed with 0.8% sodium carbonate, and a plating resist 54 having a thickness of 15 μm is provided (see FIG. 11 (B)). Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 56 having a thickness of 15 μm (see FIG. 11 (C)). The additive in the electrolytic plating aqueous solution is Capalacid HL manufactured by Atotech Japan.

【0071】

[Electroplating aqueous solution] Sulfuric acid 2.24 mol / l Copper sulphate 0.26 mol / l Additive (Atotech Japan, Capallaside HL) 19.5 ml / l [Electroplating conditions] Current density 1A / dm² Time 65 minutes Temperature 22 ± 2 ° C [0072]

(9) After peeling and removing the plating resist 54 with 5% NaOH, the metal layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitrate, sulfuric acid and hydrogen peroxide, and the metal layer 52 and electrolytic plating are performed. A 16 μm-thick conductor circuit 58 and a via hole 60 made of a film 56 are formed (see FIG. 12 (A)). As the etching solution, cupric chloride, ferric chloride, peroxides, hydrogen peroxide / sulfuric acid, alkaline chants and the like can be used. Subsequently, the roughened surfaces 58α and 60α are formed by the etching solution containing the cupric cupric complex and the organic acid (see FIG. 12 (B)).

【0073】

(10) Next, by repeating the steps (7) to (12) above, the interlayer resin insulating layer 150 and the conductor circuit 158 (including the via hole 160) are further laminated on the upper layer of the interlayer resin insulating layer 50. A resin insulating layer 250 and a conductor circuit 258 (including a via hole 260) are formed (see FIG. 12 (C)).

【0074】

(11) Next, 50% of the epoxy group of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight is acrylicized to impart photosensitivity. 46.67 parts by weight of oligomer (molecular weight 4000), 80% by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell Co., Ltd., trade name: Epicoat 1001) 15 parts by weight, imidazole hardener (manufactured by Shikoku Kasei Co., Ltd., product) Name: 2E4MZ-CN) 1.6 parts by weight, photosensitive monomer, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product name: R604) 3 parts by weight, also polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product name: DPE6A) Take 1.5 parts by weight and 0.71 parts by weight of a dispersion-based foaming agent (manufactured by Sannopco, trade name: S-65) in a container, stir and mix to prepare a mixed composition, and start light weight for this mixed composition. A solder resist composition prepared by adding 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Ltd.) and 0.2 parts by weight of Michler ketone (manufactured by Kanto Chemical Co., Ltd.) as a photosensitizer to adjust the viscosity to 2.0 Pa · s at 25 ° C. (Organic resin insulating material) is obtained. The viscosity was measured with a B-type viscometer (manufactured by Tokyo Keiki Co., Ltd., DVL-B type) using rotor No. 4 at 60 rpm and rotor No. 3 at 6 rpm. A commercially available solder resist can also be used as the solder resist.

【0075】

(12) Next, the above solder resist composition was applied to the substrate 30 to a thickness of 20 μm, dried at 70 ° C for 20 minutes and at 70 ° C for 30 minutes, and then the solder resist resist was applied. A photomask with a thickness of 5 mm on which the pattern of the opening is drawn is brought into close contact with the solder resist layer 70 and is 1000 mJ / cm.²It is exposed to ultraviolet rays and developed with a DMTG solution to form an opening 71 having a diameter of 200 μm (see FIG. 13 (A)).

【0076】

(13) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 was formed was subjected to nickel chloride (2.3 × 10).^-1mol / l), sodium phosphate (2.8 × 10)^-1mol / l), sodium citrate (1.6 × 10)^-1Immerse in an electroless nickel plating solution containing mol / l) at pH = 4.5 for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. Furthermore, the substrate is made of potassium gold cyanide (7.6 × 10).^-3mol / l), ammonium chloride (1.9 × 10)^-1mol / l), sodium citrate (1.2 × 10)^-1mol / l), sodium hypophosphite (1.7 × 10)^-1By immersing in an electroless plating solution containing mol / l) for 7.5 minutes at 80 ° C to form a gold plating layer 74 with a thickness of 0.03 μm on the nickel plating layer 72, a solder pad is formed on the conductor circuit 258. Form 75 (see Figure 13 (B)).

【0077】

(14) After that, the solder paste is printed on the opening 71 of the solder resist layer 70. Sn / Pb, Sn / Sb, Sn / Ag, Sn / Ag / Cu and the like can be used for this solder paste. Further, a low α ray type solder paste may be used. Subsequently, by reflowing at 200 ° C, the BGA76 is arranged in a grid shape (or staggered shape) in the region R2 in which the IC chip 20 is not built (FIGS. 14 and 17 (A), See (B)). As a result, a multilayer printed wiring board 10 having a built-in IC chip 20 and a BGA76 can be obtained (see FIG. 14). The IC chip 20 may be arranged at an unbalanced position instead of the central portion of the substrate 30. In FIG. 14, the BGA is arranged as an external connection terminal, but as shown in FIG. 15, even when the PGA96 is attached as an external connection terminal, it can be arranged in the area R2 in which the IC chip 20 is not built. desirable.

【0078】

[Modified Example of First Embodiment] A multilayer printed wiring board according to a modified example of the first embodiment will be described. In the first embodiment described above, a laser was used to form a via hole in the interlayer resin insulating layer. On the other hand, in the modified example, a via hole is formed by exposure. A method for manufacturing a multilayer printed wiring board according to this modification will be described with reference to FIG.

【0079】

(4) Similar to the first embodiment, the thermosetting epoxy resin 51 having a thickness of 50 μm is applied to the substrate 30 that has undergone the steps (1) to (3) above (see FIG. 18 (A)).

【0080】

(5) Next, a photomask film (not shown) on which a black circle corresponding to the via hole formation position is drawn is placed on the interlayer resin insulating layer 50 and exposed. Subsequently, spray development is performed with a DMTG solution and heat treatment is performed to provide a via hole opening 48 having a diameter of 85 μm (see FIG. 18 (B)).

【0081】

(6) The surface of the interlayer resin insulating layer 50 is roughened with permanganate or chromic acid to form a roughened surface 50α (see FIG. 18 (C)). The roughened surface 50α is preferably formed in the range of 0.05 to 5 μm. Since the subsequent steps are the same steps as (7) to (14) of the first embodiment described above, the description thereof will be omitted.

【0082】

In the above-described embodiment, thermosetting resin sheets are used for the interlayer resin insulating layers 50, 150, and 250. This thermosetting resin sheet resin contains a sparingly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.

【0083】

The thermosetting resin sheet used in the production method of the first embodiment is a resin in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are poorly soluble in an acid or an oxidizing agent (hereinafter referred to as a sparingly soluble resin). It is dispersed inside. The terms "poorly soluble" and "soluble" used in the first embodiment refer to those having a relatively high dissolution rate when immersed in a solution consisting of the same acid or oxidizing agent for the same time as "soluble" for convenience. The one with a relatively slow dissolution rate is called "poorly soluble" for convenience.

【0084】

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Particles (hereinafter, soluble metal particles) and the like can be mentioned. These soluble particles may be used alone or in combination of two or more.

【0085】

The shape of the soluble particles is not particularly limited, and examples thereof include spherical particles and crushed particles. Further, it is desirable that the shape of the soluble particles is a uniform shape. This is because it is possible to form a roughened surface having irregularities with uniform roughness.

【0086】

The average particle size of the soluble particles is preferably 0.1 to 10 μm. Within this range of particle size, two or more different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm. As a result, a more complicated roughened surface can be formed, and the adhesion to the conductor circuit is also excellent. In the first embodiment, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

【0087】

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as they have a faster dissolution rate than the poorly soluble resin when immersed in a solution consisting of an acid or an oxidizing agent. There is no particular limitation. Specific examples of the soluble resin particles include those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin and the like, and may be one of these resins. However, it may consist of a mixture of two or more kinds of resins.

【0088】

Further, as the soluble resin particles, resin particles made of rubber can also be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, and (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in the acid or the oxidizing agent. That is, when dissolving soluble resin particles with an acid, it can also be dissolved with an acid other than a strong acid, and when dissolving soluble resin particles with an oxidizing agent, permanganate, which has a relatively weak oxidizing power, can be dissolved. It can also be dissolved with acid salts. Moreover, even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid and the oxidizing agent do not remain on the resin surface, and as will be described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is no such thing.

【0089】

Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

【0090】

Examples of the aluminum compound include alumina, aluminum hydroxide and the like, examples of the calcium compound include calcium carbonate, calcium hydroxide and the like, and examples of the potassium compound include potassium carbonate and the like. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.

【0091】

Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure the insulating property.

【0092】

When two or more of the above soluble particles are mixed and used, a combination of resin particles and inorganic particles is desirable as a combination of the two types of soluble particles to be mixed. Since both have low conductivity, the insulation of the resin sheet can be ensured, thermal expansion can be easily adjusted with the sparingly soluble resin, and cracks do not occur in the interlayer resin insulating layer made of the resin sheet. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

【0093】

The sparingly soluble resin is not particularly limited as long as it can retain the shape of the roughened surface when the roughened surface is formed by using an acid or an oxidizing agent in the interlayer resin insulating layer, and is, for example, thermosetting. Examples thereof include resins, thermoplastic resins, and composites thereof. Further, it may be a photosensitive resin obtained by imparting photosensitivity to these resins. By using the photosensitive resin, an opening for a via hole can be formed in the interlayer resin insulating layer by exposure and development treatment. Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

【0094】

Specific examples of the poorly soluble resin include epoxy resin, phenol resin, phenoxy resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin and the like. These resins may be used alone or in combination of two or more. Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-mentioned roughened surface be formed, but it is also excellent in heat resistance, etc., so stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.

【0095】

Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, and di. Examples thereof include a cyclopentadiene type epoxy resin, an epoxidized product of a condensate of phenols and an aromatic aldehyde having a phenolic hydroxyl group, triglycidyl isocyanurate, and an alicyclic epoxy resin. These may be used alone or in combination of two or more. As a result, the heat resistance and the like are excellent.

【0096】

In the resin sheet used in the first embodiment, it is desirable that the soluble particles are substantially uniformly dispersed in the poorly soluble resin. A roughened surface having unevenness with uniform roughness can be formed, and even if a via hole or a through hole is formed in the resin sheet, the adhesion of the metal layer of the conductor circuit formed on the via hole or the through hole can be ensured. Because it can be done. Further, a resin sheet containing soluble particles may be used only in the surface layer portion forming the roughened surface. As a result, only the surface layer portion of the resin sheet is exposed to the acid or the oxidizing agent, so that the insulating property between the conductor circuits via the interlayer resin insulating layer is surely maintained.

【0097】

In the above resin sheet, the blending amount of the soluble particles dispersed in the poorly soluble resin is preferably 3 to 40% by weight with respect to the resin sheet. If the blending amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities, and if it exceeds 40% by weight, when the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin sheet is melted deeply, and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin sheet cannot be maintained, which may cause a short circuit.

【0098】

It is desirable that the resin sheet contains a curing agent, other components, and the like in addition to the soluble particles and the sparingly soluble resin. Examples of the curing agent include imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents, microencapsulations of these curing agents, triphenylphosphine, and tetraphenylphospho. Examples thereof include organic phosphine compounds such as nium / tetraphenylborate.

【0099】

The content of the curing agent is preferably 0.05 to 10% by weight with respect to the resin sheet. If it is less than 0.05% by weight, the resin sheet is not sufficiently cured, so that the degree of acid or oxidizing agent invading the resin sheet increases, and the insulating property of the resin sheet may be impaired. On the other hand, if it exceeds 10% by weight, the excess curing agent component may modify the composition of the resin, which may lead to a decrease in reliability.

【0100】

Examples of the other components include fillers such as inorganic compounds and resins that do not affect the formation of roughened surfaces. Examples of the inorganic compound include silica, alumina, and dolomite, and examples of the resin include polyimide resin, polyacrylic resin, polyamide-imide resin, polyphenylene resin, melanin resin, and olefin resin. By containing these fillers, it is possible to improve the performance of the multilayer printed wiring board by matching the coefficient of thermal expansion, improving heat resistance and chemical resistance.

【0101】

Further, the resin sheet may contain a solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene and xylene. These may be used alone or in combination of two or more. However, these interlayer resin insulating layers are melted and carbonized when a temperature of 350 ° C. or higher is applied.

【0102】

[Second Embodiment] Subsequently, the manufacturing method of the multilayer printed wiring board of the second embodiment will be described with reference to FIGS. 19 to 21. In the first embodiment described above, the transition layer 38 is formed on the IC chip 20 and then mounted on the core substrate 30. On the other hand, in the second embodiment, the transition layer is formed after the IC chip is mounted on the core substrate.

【0103】

(1) First, an insulating resin substrate (core substrate) 30 in which a prepreg impregnated with a resin such as epoxy is laminated on a core material such as glass cloth is prepared as a starting material (see FIG. 19 (A)). Next, a recess 32 for accommodating the IC chip is formed on one side of the core substrate 30 by counterbore processing (see FIG. 19 (B)).

【0104】

(2) After that, the adhesive material 34 is applied to the recess 32 using a printing machine. At this time, in addition to coating, potting or the like may be performed. Next, the IC chip 20 is placed on the adhesive material 34 (see FIG. 19 (C)).

【0105】

(3) Then, push or tap the upper surface of the IC chip 20 to completely accommodate it in the recess 32 (see FIG. 20 (A)). As a result, the core substrate 30 can be smoothed.

【0106】

(4) After that, physical vapor deposition such as vapor deposition and sputtering is performed on the entire surface of the core substrate 30 containing the IC chip 20 to form a conductive metal film 33 on the entire surface (FIG. 20 (B)). As the metal, one in which one or more layers of metals such as tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper are formed is preferable. The thickness is preferably formed between 0.001 and 2.0 μm. In particular, 0.01 to 1.0 μm is desirable.

【0107】

A plating film 36 may be formed on the metal film 33 by electroless plating (FIG. 20 (C)). The types of plating formed include copper, nickel, gold, silver, zinc, and iron. Copper should be used because of its electrical properties, economy, and the build-up conductor layer that will be formed later is mainly copper. The thickness should be in the range of 1 to 20 μm.

【0108】

(5) After that, a resist is applied, exposed, and developed to provide a plating resist 35 so as to provide an opening at the upper part of the pad 22 of the IC chip 20, and electroless plating is performed to provide an electroless plating film 37 (Fig.). 21 (A)). After removing the plating resist 35, the transition layer 38 is formed on the pad 22 of the IC chip by removing the electroless plating film 36 and the metal film 33 under the plating resist 35 (FIG. 21 (B)). Here, the transition layer was formed by the plating resist, but after the electrolytic plating film was uniformly formed on the electroless plating film 36, the etching resist was formed, exposed and developed, and the portion other than the transition layer 38 was formed. It is also possible to expose the metal and perform etching to form a transition layer 38 on the pad 22 of the IC chip 20. In this case, the thickness of the electrolytic plating film is preferably in the range of 1 to 20 μm. If it is thicker than that, undercut may occur during etching, and a gap may be generated at the interface between the transition layer and the via hole to be formed.

【0109】

(6) Next, an etching solution is sprayed onto the substrate 30 with a spray, and the surface of the transition layer 38 is etched to form a roughened surface 38α (see FIG. 21 (C)). Since the subsequent steps are the same as those in the first embodiment, the description thereof will be omitted.

【0110】

[Comparative Example] A multilayer printed wiring board according to a comparative example will be described. In the first embodiment described above, the BGA76 is arranged in the region R2 just above the IC chip. On the other hand, in the comparative example, BGA76 is uniformly arranged on the solder resist layer as shown in FIG. 17 (C). That is, BGA76 is formed in a grid shape (full grid shape) on the entire surface of the solder resist layer without distinguishing between the region R1 and the region R2.

【0111】

After each of the multilayer printed wiring board according to the first embodiment and the multilayer printed wiring board of the comparative example were connected to an external board, they were electrically connected to evaluate the following items. Presence or absence of cracks or peeling after mounting with an external board Presence or absence of BGA malfunction Presence or absence of cracks or peeling after mounting with an external board after reliability test Presence or absence of BGA defects after reliability test Measurement of contact resistance Good results were obtained with the multilayer printed wiring board according to the first embodiment, but in the comparative example, cracks and peeling around the BGA were found. In addition, an increase in contact resistance was also confirmed. As shown in FIG. 15, similar results were obtained when PGA was used instead of BGA.

【0112】

[Effect of the invention]

As described above, in the invention, the region on the substrate in which the semiconductor element of the multilayer printed wiring board is built is distinguished from the region on the substrate in which the semiconductor element is not built. Then, an external connection terminal (BGA / PGA) is arranged in a region on the substrate in which the semiconductor element is not built. In other words, by arranging the external connection terminal (BGA / PGA) in the area on the substrate where the semiconductor element is not built in, the influence of thermal expansion can be reduced, so that it can be placed around the external connection terminal (BGA / PGA). It is possible to prevent peeling and cracking that occur. Therefore, it is possible to prevent the external connection terminal (BGA / PGA) from falling off or being displaced, and to improve the electrical connectivity and reliability.

[Simple explanation of drawings]

[Figure 1]

(A), (B), and (C) are process charts of the first manufacturing method of the IC chip according to the first embodiment of the present invention.

[Figure 2]

(A), (B), and (C) are process charts of the first manufacturing method of the IC chip according to the first embodiment.

[Fig. 3]

(A) and (B) are process charts of the first manufacturing method of the IC chip according to the first embodiment.

[Fig. 4]

(A) is a plan view of the silicon wafer according to the first embodiment, and (B) is a plan view of an individualized IC chip.

[Fig. 5]

(A), (B), and (C) are process charts of the second manufacturing method of the IC chip according to the first embodiment.

[Fig. 6]

It is a process drawing of the 2nd manufacturing method of the IC chip which concerns on 1st Embodiment.

[Fig. 7]

(A), (B), and (C) are process charts of the third manufacturing method of the IC chip according to the first embodiment.

[Fig. 8]

(A) and (B) are process charts of the third manufacturing method of the IC chip according to the first embodiment.

[Fig. 9]

(A), (B), (C), and (D) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

[Fig. 10]

(A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

[Fig. 11]

(A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

[Fig. 12]

(A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

[Fig. 13]

(A) and (B) are manufacturing process diagrams of the multilayer printed wiring board which concerns on 1st Embodiment of this invention.

[Fig. 14]

It is sectional drawing of the multilayer printed wiring board which concerns on 1st Embodiment.

[Fig. 15]

It is sectional drawing of the multilayer printed wiring board which concerns on 1st Embodiment.

[Fig. 16]

It is EE sectional view of FIG.

[Fig. 17]

(A) is a plan view of the multilayer printed wiring board according to the first embodiment of the present invention, (B) is a plan view of the multilayer printed wiring board in which bumps are arranged in a staggered pattern, and (C). Is a plan view of a multilayer printed wiring board according to a comparative example.

[Fig. 18]

(A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the modified example of the first embodiment.

[Fig. 19]

(A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment of the present invention.

[Fig. 20]

(A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment.

[Fig. 21]

(A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment.

[Explanation of symbols]

20 IC chip 22 pad 24 Passivation membrane 30 core board 32 recess 33 Metal film 34 Adhesive material 36 Plating film 37 Electroless plating film 38 Transition layer 38α roughened surface 50 Interlayer resin insulation layer 50α roughened surface 52 Metal layer 54 Plating resist 56 Electroplating film 58 Conductor circuit 58α roughened surface 60 via hole 60α roughened surface 70 Solder resist layer 71 opening 72 nickel plating 74 gold plating 75 solder pad 76 Solder bump 150 interlayer resin insulation layer 158 Conductor circuit 160 Via Hall 250 interlayer resin insulation layer 258 Conductor circuit 260 Via Hall