Improved integrated circuit storage device having interleave-read and program-capability, and its operating method

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to an improved integrated storage circuit having the capability of continuously reading or programming pages of data without gaps, and a method of operating the same.

【0002】

[Conventional technology]

Semiconductor integrated storage circuits for storing data are generally volatile, such that data is lost once the power is turned off, or non-volatile, such that the data is retained even after the power is turned off. It is classified as one of them.

【0003】

Non-volatile memory, which comprises an array of non-volatile memory cells arranged in multiple rows and columns (or bit lines), is a method in which the non-volatile memory cells are arranged in an array. Can be classified as either NAND or NOR type with reference to. In addition, non-volatile memory cells are pages such that pages of data (typically 512 bytes) are stored in multiple latches (or multiple page buffers) that are integrated with the memory circuit. It can be arranged to operate in a modal manner. The reading of the integrated storage circuit device causes the data from the page of the memory cell to be read and stored in a plurality of latches. The contents of the latch to be restored are then generally read serially from the integrated storage circuit device. In the programming of the integrated storage circuit device, data from the outside is stored in a plurality of latches. The contents of the plurality of latches are then stored on the page of the non-volatile memory cell. Generally, pages in non-volatile memory cells reside on the same row or word line.

【0004】

In normal page mode read operation, whenever a word line is addressed, it is turned on to sense (sense out) the data stored in the memory cells of the selected word line. A standby state is required for the chip control circuit. After being sensed, the data is latched into multiple page buffers before they are clocked out to the I / O pads. This wait state, typically about a few microseconds, accounts for a significant portion of the average page mode read access time. Quite contiguous word lines are often contiguously addressed, especially in applications that read large amounts of data. One wait state for each addressed word line degrades overall read performance. Therefore, a non-volatile memory with a minimum number of standby states will need to provide high performance page-mode read operation.

【0005】

In U.S. Pat. No. 5,768,215, the proposed solution to the above problem in the standby state provides two groups of page buffers, such that each group's page buffer is half the size of a page memory cell. It is to be. First of all, the data from the first page of the memory cell is read into the page buffers of the two groups. After that, the page buffer of the first group is read and the content is output to the outside. However, as soon as a read of the contents of the second group's page buffer is performed, the second page read of the memory cell is a memory cell stored in the first group's page buffer. Executed with the data read from half of the second page of. After the contents of the page buffer of the second group are output to the outside, half of the second page of the memory cell is also read and stored in the page buffer of the first group. The second half of the second page of memory cells is read and stored in the second group's page buffer, just as the first group's page buffer reads are performed. This alternation of reading half of the pages in a memory cell and storing data in one of the groups of page buffers continues while the contents of the page buffers of the other group are read.

【0006】

[Problems to be Solved by the Invention]

In normal page-mode program operation, the data is first loaded into multiple page buffers in sequence. All data loaded into multiple page buffers, regardless of the number of bits programmed (or aggregate bytes), are simultaneously programmed into the memory cells of the selected page. Programming because the on-chip can carry only a limited amount of current, such as a charge pump (because general programming requires a voltage source higher than the voltage supplied from the outside). Efficiency deteriorates as the number of bits increases. Due to the limitation on the amount of current that can be supplied by the on-board charge pump, one solution is that it takes a lot of time to program the pages of data. Therefore, there is a need for new technologies that provide highly efficient programming.

【0007】

And the non-volatile memory cells used in the NADN architecture are of the stack gate type, as generally disclosed in US Pat. No. 5,768,215. In addition, the non-volatile memory cells used in the NOR architecture are of the split gate type as disclosed in U.S. Pat. No. 5,668,757, which incorporates the disclosure of the stack gate type or in its entirety here as a reference. It can be both.

【0008】

[Means for solving problems]

In the present invention, the integrated circuit storage device has pages of memory cells arranged in a plurality of subpages of the memory cells. Memory cells are electrically connected to multiple word lines and multiple bit lines. The plurality of subpage buffers are electrically connected to the plurality of bit lines to store the data read from the memory cells connected to the plurality of bit lines. The device further has an I / O data buffer. Each subpage has multiple non-adjacent bitlines with memory cells connected to it, such that each bitline of the subpage interleaves with the bitline of another subpage. .. The read controller circuit simultaneously reads data from the second subpage buffer into the I / O data buffer while the associated first subpage buffer from the first subpage of the memory cell. Connected to multiple subpage buffers to initiate a read operation to read data into.

【0009】

The present invention also relates to an integrated circuit storage device having a NOR architecture that emulates read and programming operations of a NAND integrated circuit storage device. And the present invention relates to a read-modify-write circuit.

【0010】

BEST MODE FOR CARRYING OUT THE INVENTION

The integrated circuit storage device of the present invention includes a page of a memory cell composed of a plurality of corresponding word lines and a plurality of subpages of a memory cell electrically connected to a plurality of bit lines; A plurality of subpage buffers electrically connected to the plurality of bit lines and an I / O data buffer for storing data read from the memory cell connected to the plurality of bit lines. And; with each subpage, each subpage has multiple non-adjacent bitlines with memory cells connected to it, each of which subpages interleaves with another subpage bitline; And while reading data from the second subpage buffer into the I / O data buffer at the same time, read from the first subpage of the memory cell to the associated first subpage buffer to read the data. -It includes a read controller circuit connected to the plurality of subpage buffers for invoking an operation.

【0011】

In the integrated circuit storage device of the present invention, each subpage may further include a plurality of non-adjacent, evenly spaced bit lines having memory cells connected to it.

【0012】

In the integrated circuit storage device of the present invention, each subpage buffer becomes a column selection circuit for selecting a subpage buffer for a plurality of adjacent bit lines; and one of the plurality of adjacent bit lines. It may be configured to be associated.

【0013】

In the integrated circuit storage device of the present invention, each subpage buffer may be configured to be associated with two bit lines. In the integrated circuit storage device of the present invention, each subpage buffer may further include a latch; a reset circuit connected to the latch; and a switch for connecting the latch to the callan selection circuit. .. In the integrated circuit storage device of the present invention, the memory cell may be a non-volatile memory cell. In the integrated circuit storage device of the present invention, the page of the non-volatile memory cell may be configured in NOR architecture.

【0014】

The method of the present invention comprises a page of a memory cell composed of a plurality of corresponding word lines in an integrated circuit storage device and a plurality of subpages of the memory cell electrically connected to the plurality of bit lines. A method of reading: the stage of reading the first subpage of a memory cell, where the first subpage has a memory cell connected to multiple first non-adjacent bitlines; The subpage buffer stores data from the first subpage of the memory cell; and the second subpage is connected to a second plurality of non-adjacent bitlines, said first plurality. A second subpage of a memory cell that has a non-adjacent bitline and an interleaved memory cell and stores data from it in a second subpage buffer that is different from the first subpage buffer. While simultaneously reading, it comprises a step of reading data from the first subpage buffer to the outside of the integrated circuit storage device.

【0015】

In the method of the present invention, the first plurality of non-adjacent bit lines may be evenly separated from each other. In the method of the present invention, the second plurality of non-adjacent bit lines may be evenly separated from each other. In the method of the present invention, the first subpage buffer may include a plurality of latches, each latch being associated with a plurality of bit lines. In the method of the invention, each latch may be associated with two bit lines. In the method of the present invention, the second subpage buffer may include a plurality of latches so that each latch is associated with a plurality of bit lines.

【0016】

The integrated circuit storage device of the present invention is an integrated circuit storage device that emulates the reading operation of a NAND storage device: it is composed of a NOR configuration and is electrically connected to a plurality of corresponding word lines and a plurality of bit lines. An array of split-gate type floating gate memory cells connected to the array, which consists of multiple subpages of the memory cells; the memory cells connected to the plurality of bitlines. With multiple subpage buffers electrically connected to the plurality of bitlines to store the data read from; and data from the second subpage to the second subpage buffer of the memory cell. At the same time that the read operation is activated to read, the read operation is activated to read data from the first subpage of the memory cell to the first subpage buffer, and the integrated circuit is activated from the first subpage buffer. It includes a read control circuit connected to the plurality of subpage buffers in order to activate a read operation to read data to the outside of the storage device.

【0017】

In the integrated circuit storage device of the present invention, each of the plurality of subpages of the memory cell comprises a non-adjacent, evenly spaced bitline having a memory cell connected to the memory cell. Subpages of may be configured to interleave with each other. In the integrated circuit storage device of the present invention, each subpage buffer becomes a column selection circuit for selecting a subpage buffer for a plurality of adjacent bit lines; and one of the plurality of adjacent bit lines. It may be configured to be associated. In the integrated circuit storage device of the present invention, each subpage buffer may be configured to be associated with two bit lines. In the integrated circuit storage device of the present invention, each subpage buffer may further include a latch; a reset circuit connected to the latch; and a switch connecting the latch to the column selection circuit.

【0018】

The integrated circuit storage device of the present invention stores a plurality of non-volatile memory cells electrically connected to a plurality of corresponding word lines and a plurality of bit lines; data to be programmed in a selected memory cell. Latch electrically connected to the plurality of bit lines to perform; sense electrically connected to the plurality of bit lines to sense data stored in the selected memory cell. Amplifier; Bits that receive the data sensed by the sense amplifier and are connected to the selected memory cell only if the sensed data is from a memory cell in the programmed state. It includes a modification circuit for storing the data in the latch associated with the line; and a programming circuit for storing the data from the latch to the selected memory cell.

【0019】

The method of the present invention is a method of programming selected non-volatile memory cells in a plurality of arrays of non-volatile memory cells connected to a plurality of word lines and a plurality of bit lines: said above. The data to be programmed in the selected memory cell is stored in the latch connected to the selected memory cell; the stage of reading the data from the selected memory cell; and the stage of reading the read data. Based on this, the latch is provided with a step of changing the latch.

【0020】

The integrated circuit storage device of the present invention is an integrated circuit storage device that emulates the reading operation of a NAND storage device: it is composed of a NOR configuration and is electrically connected to a plurality of corresponding word lines and a plurality of bit lines. An array of split gate type floating gate memory cells connected to the array, which consists of multiple subpages of the memory cells; externally supplied to the device and the plurality of bits. With a plurality of subpage buffers electrically connected to the plurality of bit lines to store data to be programmed in the memory cell connected to the line; and from the plurality of subpage buffers. The plurality of subpages to initiate a programming operation to sequentially program data from one subpage buffer to the relevant subpages of the memory cell until the data is programmed into the plurality of subpage memory cells. -Has a programming control circuit connected to the buffer.

【0021】

In the integrated circuit storage device of the present invention, each of the memory cells may be configured to be programmed by hot electron channel injection. The integrated circuit storage device of the present invention is an array of floating gate memory cells electrically connected to a plurality of corresponding word lines and a plurality of bit lines, and is composed of a plurality of subpages of the memory cells. With the array; electrical to the plurality of bit lines for storing data to be programmed into the memory cells externally supplied to the device and connected to the plurality of bit lines. With multiple subpage buffers connected to the memory cell; with a start subpage address buffer for storing the start address of the data to be programmed in the memory cell; and the data to be programmed in the memory cell. From the address stored in the start subpage address buffer to the end subpage address buffer in the end subpage address buffer for storing the end address of; and the associated subpage of the memory cell. It includes a programming control circuit connected to the plurality of subpage buffers in order to activate a programming operation to sequentially program data.

【0022】

The integrated circuit non-volatile storage device of the present invention includes an array of floating gate memory cells electrically connected to a plurality of corresponding word lines and a plurality of bit lines; A plurality of subpage buffers electrically connected to the plurality of bit lines for storing data to be programmed in the memory cells connected to the plurality of bit lines; each sub The page buffer is a latch with a first I / O node and a second I / O node, with the second I / O node being the reverse of the first I / O node, and the first and second nodes. And the first node is connected to the first voltage, and the first I / O node is connected to the associated bit line; and along the first and second I / O nodes. The first voltage is supplied to the second node when data is supplied to or from the latch from the outside, and the data is read from the bit line to the latch. The two nodes are provided with a control circuit that supplies a second voltage different from the first voltage.

【0023】

The integrated circuit non-volatile storage device of the present invention may further include a reset circuit connected to the second input / output node that resets the state of the latch. The integrated circuit non-volatile storage device of the present invention includes an array of floating gate memory cells electrically connected to a plurality of corresponding word lines and a plurality of bit lines; A plurality of subpage buffers electrically connected to the plurality of bit lines for storing data to be programmed in the memory cells connected to the plurality of bit lines; each sub The page buffer is a first I / O node and a second I / O node where the second I / O node is the reverse of the first I / O node and the first I / O node is connected to the associated bit line. It has I / O nodes and has latches that store information for memory cells connected to the associated bit line; it has a first and second comparer, the first comparer of which: It has two inputs for receiving a signal from a latch supplied along the first I / O node and a signal along the second I / O node, and compares them and said the latch. Generates a first output signal indicating the state stored in, and the second comparer has two inputs for receiving a signal from the bit line and a reference signal, and compares them. A sense amplifier; and a multiplexer that outputs the first or second output signal, which generates a second output signal indicating information stored in a memory cell connected to the bit line. ing.

【0024】

In the integrated circuit non-volatile storage device of the present invention, the sense amplifier may further include a feedback connection that connects the output of the second comparator to the two inputs of the first comparator. Good.

【0025】

[Example]

With reference to FIG. 1, a schematic layout of the floor plan for the integrated storage circuit device 10 of the present invention is shown. As is well known, the device 10 is made of silicon and is an integrated circuit device or chip 10. In a preferred embodiment, the device or chip 10 is a split gate type non-volatile memory cell arranged in a NOR array 12 as disclosed in US Pat. No. 5,668,757, the disclosure of which is incorporated as a reference. 8M x 8M bit flash EEPROM using. Memory cell programming is caused by the hot channel electron tunneling effect, as disclosed in US Pat. No. 5,668,757. Further, in a preferred embodiment, device 10 has its non-volatile memory cells arranged in a NOR array 12, which emulates the operation of a NAND type page mode device. However, it should be noted that the present invention is not limited to this particular density or mode of configuration or operation.

【0026】

The memory cell array 12 is located in the center of the device 10. A control gate decoder 14 is arranged on the left side of the array 12. A word line decoder 16 is arranged on the right side of the array 12. A plurality of page buffers 18 are arranged on the upper side of the array 12. In a preferred embodiment, there is a 512x8 page buffer corresponding to pages in 1024x8 memory cells. The peripheral circuit 24 is arranged on the upper side of the device 10. A charge pump 22 is located on the left side of the device 10. A current pump 20 is arranged on the right side of the device 10. Pads (such as I / O, power and control) are placed near the corners of device 10.

【0027】

Since the memory cell array is configured as 8M x 8M, the entire memory cell array 12 is divided into eight identical subarrays (subarray 12-0, subarray 12-1, ... subarray 12-7). To. Each subarray has a corresponding I / O. Therefore, the sub-array 12-0 corresponds to I / O-0, and ... the sub-array 12-7 corresponds to I / O-7. The memory cell array 12 is divided into eight identical subarrays 12-n, but each word line from the word line decoder 16 and each control gate line from the control gate decoder 14 is 8 It runs "horizontally" between all of the two identical subarrays 12-n. In a preferred embodiment, the word line and control line Chris (cross) 1024x8 cells so that each cell has its own associated bit line. Therefore, there are 1024 cells in each subarray 12-n. Within each subarray 12-n, there are 512 page buffers 18. Therefore, there are two memory cells associated with each page buffer 18. For simplicity, one of the eight subarrays 12-n and its corresponding page buffer 18-n will be described and shown in the drawings below.

【0028】

Referring to FIG. 2A, a plurality of adjacent signal lines PBL0 to PBL511 are connected to the page buffer 18. Each signal line PBL is connected to one page buffer 18. Therefore, there are 512 page buffers 18. Each signal line PBL is further connected to a pair of directly adjacent bit lines BLj and BL (j + 1) through a bit line switch 44 (see FIG. 3). Therefore, the 512PBL line connects 512 page buffers to 1024 bit lines. Each bit line is then connected to a column in a non-volatile memory cell. There are 1024 memory cells associated with 512 PBL lines when a particular row of memory cells is selected. The 512 (# 1 to # 511) page buffers 18 connected to the signal lines PBL0 to PBL511 are further grouped into 16 interleaved subpages 18-n. Therefore, each subpage 18-n has 32 page buffers 18. The grouping (gubooping) of each subpage 18-n and its members is as follows: subpage n comprises PBL [16k + n]; where n = 0,1, ... 15 k = 0,1, ··· 31; therefore, subpage 18-0 connects to PBL [0], [16], [32], [48], ···, [496]. It has a page buffer 18 that has been created. Subpage 18-1 includes a page buffer 18 connected to PBL [1], [17], [33], [49], ..., [497]. Subpage 18-2 includes a page buffer 18 connected to PBL [2], [18], [34], [50], ..., [498]. ... and subpages 18-15 include page buffer 18 connected to PBL [15], [31], [47], [63], ..., [511]. There is.

【0029】

As can be seen from the above, each subpage 18-n has a page buffer 18 that is not located directly adjacent to each other. Instead, the page buffers 18 of the same subpage 18-n are connected to and form subpages on the signal line PBL, which are equidistant from each other (specifically, depending on the size of the 15 page buffers 18). Grouped together as much as possible. Therefore, the 16 subpages 18-0 to 18-15 are interleaved with each other. With this configuration, the current drawn by the selected memory cells during subpage pre-fetch is more memory cell subarray 12 than packed over a narrow area such as the pitch of 32 adjacent PBL signal lines. -n Can be evenly distributed throughout. The distance between two adjacent PBLs is carefully selected based on the sheet resistance of the source diffusion region of the memory cell.

【0030】

Referring to Figure 2A, the source lines of each memory cell are connected to each other by a local spread path. Metal strapping runs horizontally through the cell array. Periodic VSS taps are formed to connect the local spread path to VSS. If the subpage distance L is long enough to accommodate one VSS tap for each selected bit line as shown, the VSS bounce (or ground bounce) is minimized to lcell × Rdiff. Here, lcell is the cell current and Rdiff is the diffusion resistance. If the subpage distance is reduced to L / 4, one VSS tap is shared between the four select bit lines and the VSS bounce is for those four bit lines as shown in Figure 2B. Increase differently. Therefore, the optimum value of L can be the result of a trade-off between the VSS tap layout area penalty and the VSS bounce.

【0031】

FIG. 3 is a schematic diagram showing a page buffer 18, a first column decoder 46, a second column decoder 38/40/42, a sense amplifier and an output buffer 48. In this figure, the data latch and sensing circuit 34 constitute the page buffer 18. The data latch and sensing circuit 34 are connected to the corresponding PBL lines, respectively, and the PBL line is connected to the MBL line through the first column decoder 46. Each MBL line is connected to a pair of bit lines through a 2-bit-line switch 44BSW0 / BSW1. Also, each data latch and sensing circuit 34x is a data line Dx through a second column decoder 38/40/42 (as shown and explained below, the data line Dx is a pair of data lines. Is equipped with a line).

【0032】

FIG. 3A is a schematic circuit diagram showing a bit line pre-charge circuit 44P and a bit line switch 44. The 44P pre-charge transistor is used to pre-charge the selected bit line to a given voltage level BIASP before initiating the page-mode read operation. The pre-charge transistor is activated (started) by the signal YLPBx at x = 0, ···, 15. The signal YLPBx is a decoded signal that represents the selection of a particular subpage 18-n. When a particular YLPBx is activated, it activates 32 pairs of bit line BLs to precharge those 64 bit lines. For example, if YLPB0 is started, the bit lines BL0,1, BL16,17,BL32, 33, BL48,49, ..., BL496,497 are all connected to the voltage source BIASP.

【0033】

Each page buffer 18 is connected to the output line Dx (as mentioned above, the output line Dx is actually a pair of output lines). Since there are 512 page buffers 18, there are 512 output lines Dx. The 16 adjacent page buffers 18 and their associated output lines D (x, x + 15) are grouped together to form group 36. There are a total of 32 groups of output lines D. The output line D of the 32 groups is supplied to the second column decoder 38 as shown in FIG. 3B. The second column decoder 38 selects one of the output lines D from each group 36 based on the selection signals YL0 ... YL15. Therefore, the second column decoder 38 selects one, 32 outputs from each group 36 to represent all of the output of page buffer 18 from the same selection subpages 18-n.

【0034】

The 32 outputs of the second column decoder 38 are supplied to the pre-charge circuit 38P, which outputs 32 signals at the nodes DLU0 ... DLU15, DLU0 ... DLU15. (Again, each line represents a pair of output lines.) The pre-charge transistor in the pre-charge circuit 38P pre-charges the intermediate node DLUx before switching (switching) the second column decoder 38. Used to do.

【0035】

From the output of the pre-charge circuit 38P, the signals DLU0 ... DLU15, DLU0 ... DLU15 are supplied to the second column decoder 40. The second column decoder 40 is based on the selection signals YU0 ... YU15 and is one of the output lines from the 16 DLU signals of the first group and one of the output lines from the 16 DLU signals of the second group. Select one. Therefore, the second column decoder 40 selects two outputs, each of which is a pair of lines.

【0036】

The two outputs from the second column decorator 40 are supplied to the pre-charge circuit 40P, which outputs two signals at nodes DLL0 and DLL1. The pre-charge transistor of the pre-charge circuit 40P is used to pre-charge the intermediate node DLLx before switching (switching) the second column decoder 40.

【0037】

From the pre-charge circuit 40P, the signals DLL0 and DLL1 go to the second column decoder 42, which selects one of the signals as the output DL (a pair of output lines: DL and DLB) based on the selection signals Z0 and Z1. Be supplied. The selection signals DL (DL and DLB) from the second column decoder 42 are supplied to the output buffer 48.

【0038】

Therefore, one signal (both the signal and its complement) stored in the page buffer 18 from the selected subpages 18-n through the action of the second column decoder 38/40/42 is output from device 10. Will be done. The pre-charge circuit 38P / 40P serves only to pre-charge certain nodes before the second column decoder 38/40/42 is activated. Since all of these intermediate nodes DLUx / DLLx are loaded with large parasitic capacitance, any switching of the second column decoder 38/40/42 interferes with the data latch 34C shown in Figure 4. ) Brings. To prevent this interference (failure), all DLUx / DLLx nodes must be precharged to VCC-VTN before switching.

【0039】

FIG. 3C is a schematic circuit diagram showing the output buffer 48 in detail. A pair of output signals DL and DLB representing the data from the output of the latch from the selection page buffer 18 and the data inversion signal are fed to the differential amplifier (differential amplifier) 48SA. The output DOUT of the differential amplifier 48SA is fed to a series of latches and then to the multiplexer 48M. In the page mode of operation, this can be the path of the signal. However, device 10 can also operate in non-page mode such that the signal from the non-volatile memory cell is read directly but not stored in page buffer 18. In that case, the signal from the non-volatile memory cell along with the signal from the reference cell is fed to the sense amplifier 48NA. The output of the sense amplifier 48NA is fed to a series of latches and another input to the multiplexer 48M. The output of the multiplexer 48M is supplied as the output of device 10.

【0040】

Also, the latch signal CSAOUT from the sense amplifier 48NA is connected to the output lines DL and DLB and is used in read-change-write mode during programming operation, a feedback circuit whose details are detailed below. It is supplied to the 48R by the feedback method.

【0041】

FIG. 4 is a circuit diagram showing one of the page buffers 18 in detail. The second column decoder 38 is shown to have three transistors l26 / l10 / l9 for each data latch and sensing circuit 34; however, for illustration purposes only. The second column decoder 38 shown in 3 is shown to have only one transistor for each data latch and sensing circuit 34. The first column decoder 46 has two transistors l24 / l42 for each data latch and sensing circuit 34, but only for the purpose of re-explanation, only one transistor is shown in FIG. It is shown. In this schematic, each data latch and sensing circuit 34 includes a data latch 34C, a latch reset circuit 34D, a program / sensing selection circuit 34B and a program driving circuit 34A. The programming / sensing behavior of this page buffer 18 is described in detail below.

【0042】

To perform the page-mode read operation, the data latch 34C is first reset by the latch reset circuit 34D and the selected bit line is the voltage level of BIASP by the bit line pre-charge circuit 44P in Figure 3A. Is pre-charged. Depending on the data stored in the selected memory cell, the PBL (or bit line or column line) will be either one of two binary voltage levels: high or low after bit line pre-charging. Driven. The data stored in the memory cell can be one of two states: ON or OFF. Each state represents one of binary data: 1 or 0. If the selected memory cell is in the ON state, this cell draws current to discharge the PBL from the BIASP pre-charge level to 0V (low level). If the selected memory cell is in the OFF state, this cell draws no current and the PBL stays at BIASP's pre-charge level (high level). After the pre-charge bit line reaches an electrically stable state, the data stored in the selected memory cells is converted to the corresponding voltage level of the PBL.

【0043】

The signal BIASL of the program / sensing selection circuit 34B and the selection YLS of the first column decoder 46 turn on the sensing path between the PBL and the data latch 34C (at the node indicated by D in latch 34C). .. The data latch 34C stores the state according to the voltage level of the PBL. In this operation, the signal BIASR is held at about 1.5v. Therefore, the data in the selected memory cells is transferred and latched in the data latch 34C after this read operation. Data latched at 34C can be clocked out using a state-of-the-art SRAM sense amplifier 48SA, as symbolically shown in Figure 3C. The data (DLU) and data bar (DLUB) signals shown in FIG. 4 are fed to the input DLs and DLBs shown in FIG. 3C. The output of the sense amplifier 48SA is further buffered by two latches connected in a master-slave configuration to extend the data retention time for the output buffer.

【0044】

As can be seen from the above, the data latch 34C is merely SRAM, but can operate under two different conditions. When the data latch 34C supplies data to the outside or serves to store the data supplied from the outside, the data is supplied to the signal lines D and DB, which are the DLUs and DLUBs, respectively. In this state, the node BIASR is connected to ground and the data latch 34C acts as a normal symmetrical SRAM latch. However, if the data latch 34C serves to sense and store the state of the memory cell during the pre-fetch and sense operations, then the memory cell is single-ended. Connected to a single bit line. In that state BIASR is connected to 1.5v. The latch 34C is first set high at the D output by the latch reset circuit 34D, which pulls (pulls) the node DB to ground. The ratio of the conductance of the P-type transistor l34 to the conductance of the memory cell at the data latch 34C determines the D output of the data latch 34C.

【0045】

In addition to the page-mode read operation, the page buffer 34 of the present invention can perform a random-access read operation with one additional path-gate transistor 38A. Along with the second column decoder 38, the transistor 38A connects the PBL to the data line CDLU and eventually to the CDLLx and then to the CDL as shown in Figure 4B. FIG. 4B is a schematic circuit diagram showing a further portion of the second column decoder 38/40/42. During the random-access read operation, the data stored in the selected memory cells passes through the second column decoder 38/40/42 to the CDL without passing through the first column decoder 46 and the data latch 34. Is transferred from the corresponding PBL. The CDL signal can be read using any state-of-the-art non-volatile semiconductor storage sense amplifier 48NA, as symbolically shown in Figure 3C. The output of the sense amplifier 48NA is further buffered by two latches connected in a master-slave configuration to extend the data retention time for the output buffer.

【0046】

FIG. 4A shows a detailed timing diagram for the read operation. A specific page x group is selected during the period shown as Sense YLS <0>. If the signal YLPB <0> goes low, the selected bit line is precharged. If the signal YLS <0> goes high first, the reset of latch 34 is caused by circuit 34D which is on (Rstpgb is also high) and the transistor of the first column decoder 46 , Turned on. However, since BIASL is low, the signal from the PBL can be prevented from passing to latch 34 by a 34B transistor that is not turned on. If BIASL initially goes high, a PBL memory cell discharge will occur. If BIASL is high and YLS <0> is high, the path from PBL to latch 34C is on. During this period Rstpgb is low and prevents latch 34 from resetting. The value of the bit line PBL is then stored in latch 34C.

【0047】

The programming operation for the page buffer 34 is as follows. Page-The data latch 34C is first set by the latch reset circuit 34D before the mode program operation begins. The input data (DLU and DLUB) from the IO pad must then be loaded into the data latch 34C through the second column decoder 38/40/42. After the programming circuit reaches the electrical steady state, the data loaded into the data latch 34C is programmed into the selected memory cell as follows: The signal pgmd of the program / sense selection circuit 34B and the selection YLS of the first column decoder 46 turn on the program path between the PBL and the program drive circuit 34A. With the data stored in the data latch 34C, the PBL is driven by the program drive circuit 34A to one of two binary voltage levels: high (high) or low (low). If node D = VCC (this is called the program suppression (prohibition) state), turn on transistor l17. It connects one of the nodes of the path transistor l16 of circuit 34B to VCC. Turning on transistor l16 connects PBL to VCC-VTN. The action of connecting the PBL to VCC-VTN results in no programming action. If node D is low, i.e. D = 0V (this is called the program state), then DB is high. This turns on the transistor l18, which connects the PBL to the ground PGND.

【0048】

With reference to FIG. 4C, a detailed timing diagram for the above programming operation is shown. FIG. 5 is a schematic circuit block diagram showing various circuits for executing the program and read operation according to the present invention.

【0049】

FIG. 6 is a timing chart for performing a page-mode read operation. The page-mode read operation of the present invention starts in the initial standby state [t0-t2] in which the data of two subpages is continuously pre-fetched into the corresponding page buffer in the meantime. These two subpages include a first subpage selected by external address input and a second subpage that locally follows the first subpage. For purposes of explanation, the data on subpage [0] (S0 [0:31]) and the data on subpage [1] (S1 [0:31]) are pre-fetched during the initial wait state. To. After this initial standby state, the control signal RE_ is toggled to sequentially clock out the data S0 [0:31] stored in the page buffer of subpage [0] during [t3-t4]. be able to. Once the time crosses t4, the data S1 [0:31] on subpage [1] starts to clock out and the data on subpage [2] (S2 [0:31]) is [ It starts to be pre-fetched at the same time during t4-t5]. Then, within any time interval t [N] -t [N + 1], at the same time, by toggle RE_, the data on subpage [M] (S (M) [0:31]) will be clocked. The out and subpage [M + 1] data (S (M + 1) [0:31]) is pre-fetched. Here, M = 0-15 and N> 3. No wait state is required after the time frame (time period) t3 because the data clocking out always precedes the data pre-fetch. Therefore, except for the initial wait state, the wait state is eliminated for the entire remaining interval.

【0050】

FIG. 7 is a flowchart for performing the page-mode gapless reading operation of the present invention shown in FIG. This flowchart has three main sections. In sections 1 and 2, subpages are continuously pre-fetched during the initial wait state. The second and third sections are parallel processing. In section 2, the page buffer data is clocked out. Once the address is clocked across the subpage boundary, the third section is sent out in parallel with the second section to pre-fetch new subpages.

【0051】

FIG. 8 is a flowchart for executing the page-mode program operation described above. This flowchart has four main loops. Before starting program operation, all page buffers must be reset to the "program-suppressed (prohibited)" state and the start address must be entered into the on-chip address counter. The starting address for programming is latched by the first set of on-chip address registers. In loop 1, the bytes of data are sequentially loaded into the page buffer. As the address counter increments, the second set of address registers stores the latest address as the end address for programming. In loop 2, the read-modify-write routine is executed. In the routine, each memory cell on the selected page is read and checked through the PBL-CDL path shown in Figure 4B. If the memory cell is already in the program state, the data latch 34C in the corresponding page buffer is set to the program state regardless of its original content.

【0052】

In the NAND specification, the user can program the selection page with less than 10 program command sequences, and it is legal to load "1" into the selection subpage programmed in the previous programming sequence. ). This results in a validation contradiction between memory and latch data during a later validation phase. (The memory cell is 0 but the latch data is 1.) One way to solve the problem is to bypass the validation error if the latch data is 1. It is to be. However, it does not catch (do not catch) program failure (jamming) errors when the memory cell of a non-selected subpage of a selected page changes (changes) from "1" to "0" during programming. In the present invention, read-modify-write is implemented to avoid the above error during verification if the cell was previously programmed and to further program the cell on the selected subpage. All cases of read-modify-write are shown below: a) If memory is on the selection subpage of the selection page: read-modify if the latch data is either "1" or "0" and the original memory cell data is "0" -Writing changes the latch data to "0" and this memory is reprogrammed. During the verification, the memory cell data is compared with the latch data 0.

【0053】

If the new data is "0" and the original memory cell data is "1", then this memory is programmed. During validation, memory cell data is compared to latch data 0 If the latch data is "1" and the original memory cell data is "1", then this memory is not programmed. During the verification, the memory cell data is compared with the latch data 1.

【0054】

b) If the memory is on a non-selected subpage of the selected page: Latch data is 1. If the original memory cell data is "0", read-modify-write changes the latch data to "0" and this memory is not reprogrammed. During the verification, the memory cell data is compared with the latch data 0.

【0055】

The latch data is "1". If the original memory cell data is "1", read-modify-write does not change the latch data and this memory is not reprogrammed. During the verification, the memory cell data is compared with the latch data 1.

【0056】

Due to the nature of flash memory, all memory cells can be erased only during the erase operation. In the present case, the erase cell holds binary data 1. During program operation, memory cells can only be programmed from 1 to 0. If the cell was first erased to 1, it can be programmed to 0. If a cell is already programmed to 0, it cannot be programmed to return to 1 by the program action (only the erase action can return the data from 0 to 1). If the control circuit attempts to program the cell from 0 to 1, nothing happens to the cell. The cell should retain its original data. Therefore, in the read-modify-write procedure, the original cell data is read first. If the cell is already programmed, regardless of what the latch indicates, the latch must be flipped back to the programmed state to ensure that the programmed cell is still a programmed cell. If the cell is erased, what the latch indicates is stored in the cell.

【0057】

In FIG. 3C, circuit 48R shows a preferred embodiment for executing this read-modify-write routine. As shown in Figure 3C, CSAOUT is 0V if the selected memory cell is already in the programmed state. Path gates N0 / N1 are turned on when DlatWbk is high. Therefore, DL is pulled down to 0V. The corresponding page buffer data is also set to 0V (program state). In loop 3, continuous subpages are programmed continuously. There are three register sets: Start address register set (SAR) End address register set (EAR) Address counter (ADC) Throughout loop 1, bytes of data are loaded into the page buffer, and the address from which programming should start is also loaded into the address counter (ADC). The SAR address register set stores this address as the starting address. When the data loading procedure stops, the address counter holds the last address that programming should stop. The EAR address register set stores this address as the end address. Throughout loop 3, the starting address is reloaded into the address counter. Then, subpage programming starts from this address. When programming proceeds to the end address, programming stops. Figure 5 shows the SAR, EAR and ADC registers. Therefore, in this loop, only the subpages previously loaded with data in loop 1 are programmed. In loop 4, each memory cell on the selected page is read through the PBL-CDL path shown in Figure 4B. Each data latch 34C is also read through the path shown in FIG. 3B. The data in each memory cell is compared with the data in its corresponding data latch 34C. If the data from both the memory cell and the data latch 34C match each other, then this memory is successfully programmed. Otherwise, this memory cell has failed.

[Simple explanation of drawings]

[Figure 1]

It is a figure which shows the schematic layout of the floor plan of the integrated storage circuit apparatus of this invention.

[Fig. 2A]

It is a schematic diagram which shows the connection of a bit line to a page buffer and grouping (grouping) of a page buffer to a subpage in the apparatus of this invention.

[Fig. 2B]

It is a schematic diagram which shows the connection of the metal strapping to VSS.

[Fig. 3]

It is a detailed schematic circuit diagram which shows the connection between a page buffer and a bit line, and the connection from a page buffer to the output buffer of the apparatus of this invention.

[Fig. 3A]

It is a detailed circuit diagram which shows the bit line precharge circuit of the apparatus of this invention.

[Fig. 3B]

It is a detailed circuit diagram which shows the data line precharge circuit of the apparatus of this invention.

[Fig. 3C]

It is a circuit diagram which shows the read-change-write circuit associated with each page buffer of a sense amplifier and the apparatus of this invention.

[Fig. 4]

It is a detailed circuit diagram which shows the connection of the page buffer to the 1st and 2nd column decoder circuits.

[Fig. 4A]

It is a timing diagram for the page mode reading operation for the apparatus of this invention.

[Fig. 4B]

It is a detailed circuit diagram which shows the connection between a bit line and an output buffer.

[Fig. 4C]

It is a timing diagram for the page mode program operation for the apparatus of this invention.

[Fig. 4D]

It is a circuit diagram which shows the generation of the signal BIASR used in the circuit shown in FIG.

[Fig. 5]

It is a schematic block diagram of the apparatus of this invention.

[Fig. 6]

It is a timing diagram for the page mode reading operation for the apparatus of this invention.

[Fig. 7]

It is a flowchart which shows the subpage prefetch operation in the page mode reading method of this invention.

[Fig. 8]

It is a flowchart which shows the subpage programming operation in the page mode programming method of this invention.

[Explanation of symbols]

10 Integrated storage circuit device (chip) 12 Memory cell array (NOR array) 12-0 ~ 12-7 Subarray 14 Control Gate Decoder 16 word line decoder 18-page buffer 20 current pump 22 Charge pump 24 Peripheral circuit