Pipeline protection

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a pipeline processor structure, and more particularly to protecting the processor pipeline from conflict.

【0002】

[Conventional technology]

In general, modern processing engines, such as those found in digital signal processors (DSPs) or microprocessors, use pipeline architectures to improve processing performance. Pipeline architecture means performing different stages of instruction processing so that two or more instructions are in different stages of processing within the pipeline at one stage.

【0003】

PROBLEM TO BE SOLVED: To solve a problem

The pipeline architecture allows for higher processing speeds than completing the processing of another instruction before starting one operation, but this architecture adds complexity, which in turn leads to potential conflicts during operation. Will increase. Conflicts are, for example, an attempt by a second instruction to access that register or part of that register before the first instruction completes operation on the register, thus the second instruction receives invalid data. As you can see, such conflicts can occur between resource accesses.

【0004】

Such potential competition is often referred to as a "data hazard." Examples of possible data hazards include:

【0005】

-read after write (for example: after ARx = ARy)^*ARx = k16 follows) -write after read (for example: ARx = ARy followed by mar (ARy = P16)) -write after write (for example: ARx = ARy followed by mar (ARx = P16)) [0006]

Various techniques for hardware pipeline protection are known in the art. One example is called "scoreboarding". By using scoreboarding, each register or field can have a write and read during pending that has passed by the phase of execution using the table or scoreboard. However, such a method is complicated to handle and is costly in terms of logic overhead and thus power consumption. Such a method is not desirable, especially for processing engines designed for portable applications or applications that are powered by methods other than pull-in commercial power (eg, batteries or other methods of power supply). In addition, scoreboarding methods can be cumbersome if the processing engine has a large instruction set and / or parallel processing architecture.

【0007】

Other methods can use read / write queuing. However, if you have a wide variety of pipeline field and / or resource access sources, such a method is inappropriate. In addition, such methods can be rapidly complicated to handle and costly in terms of logic overhead and power consumption.

【0008】

Alternatively, you can use the method of attaching the resource encoding to the instruction in the pipeline. However, such a method may have drawbacks similar to those described above.

【0009】

Many different types of processors are known, one of which is the microprocessor. Digital signal processors (DSPs) are widely used for specific applications, such as mobile processing applications. DSPs are generally configured (architecture) to optimize and achieve the performance of related applications, and these DSPs use a more specialized execution unit and instruction set. In particular, for applications such as, but not limited to, mobile communications applications, it is desirable to gradually increase DSP performance while keeping power consumption as low as possible.

【0010】

Therefore, there is a need for a different method for resource contention management within the pipeline to avoid data hazards without the drawbacks of the conventional method.

【0011】

[Means for solving problems]

The attached independent and dependent claims describe certain preferred features of the invention. The features from the dependent claim and the features of the independent claim can be combined appropriately and as not explicitly stated in the claim.

【0012】

According to the features of the present invention, a processing engine including a processor pipeline having a plurality of pipeline stages, a plurality of resources, and a pipeline protection mechanism is provided. The pipeline protection mechanism includes an interlock circuit for anticipating access conflicts for each protected resource among multiple resources between pipeline stages. The output of this interlock detection circuit is controllably connected to a set of shadow registers. Respond to expected access conflicts by the interlock circuit and direct data items from the first pipeline stage to selected shadow registers so that resource access conflicts can be resolved without disrupting the processor pipeline. A set of shadow registers is interconnected to the processor pipeline so that it can be fixed.

【0013】

The resource may be, for example, a register or a part of a register (eg, a field).

【0014】

The interlock circuit includes an interlock detection circuit, which can operate to anticipate access contention for all protected resources and to form a stop vector signal. A hold and filter circuit is connected to receive this stop vector signal, which can act to respond to the stop vector signal and select an available shadow register from a set of shadow registers. A shadow management circuit is connected to this hold and filter circuit, which has an output signal that is controllably sent to a set of shadow registers.

【0015】

The arbitration logic for each of the resources is preferably derived from the comprehensive arbitration logic determined for the pipeline. The inclusive function itself can be embodied in an integrated circuit as an inclusive arbitration logic that can handle the concurrency of all possible conflicts. Each of these arbitration logic blocks can embody a completely inclusive arbitration function, but generally only embodies a different special form of inclusive arbitration function. This comprehensive arbitration function logically defines all possible potential or theoretical conflicts between each pipeline stage. Since the resource is not accessible at all of the pipeline stages that are actually being monitored, it is unlikely that all of the theoretical conflicts will physically occur for each of the resources. However, when constructing each arbitration logic block from one block, the comprehensive function simplifies the logical design for individual resources and provides consistent performance and testability.

【0016】

The processing engine will generally include pipeline control logic to control the stages of the pipeline. This pipeline control logic can be connected to receive stop control signals that are guided or output from the arbitration logic, stop control to control selective stop of the pipeline and prevent resource access conflicts. An output merging logic for merging the outputs of each arbitration logic can be provided to form the signal.

【0017】

Access information can be associated with pending access. This access information can also be associated with the current access. Of course, the currently access decoding stage can be connected and protected resources to receive the current access information from the pipeline and direct the current access information for each protected resource. The arbitration logic for is connected to receive not only the current access information for this protected resource, but also the pending access information.

【0018】

The processing engine can be in the form of a digital signal processor. Alternatively, it could be a microprocessor-like or other form of processing engine that uses a pipeline architecture. This processing engine can be realized in the form of an integrated circuit.

【0019】

Specific applications for processing engines according to the present invention are in the form of wireless communication devices, especially portable communication devices such as mobile phones that require low power consumption and high processing performance.

【0020】

Another feature of the invention provides a method of protecting a pipeline within a processing engine, which processing engine comprises a processor pipeline with multiple pipeline stages and multiple resources. This method anticipates access conflicts between pipeline stages for each resource, with separate arbitration for each protected resource and resource access conflicts without disrupting the processor pipeline. In response to expected access conflicts, it involves redirecting data items from the first pipeline stage to selected shadow registers.

【0021】

Next, a specific embodiment according to the present invention will be described as a mere example with reference to the accompanying drawings. In the accompanying drawings, similar numbers indicate similar parts unless otherwise stated.

【0022】

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention is particularly used in digital signal processors (DSPs) implemented, for example, in application specific integrated circuits (ASICs), but is also used in other types of processors. The basic configuration of an example of the processor according to the present invention will be described below. Processor 100 is a programmable fixed-point DSP core with variable instruction length (8 to 48 bits), which has high code density and is easy to program. The configuration and instruction set are optimized to reduce power consumption and increase the efficiency of executing DSP algorithms such as for radiotelephones and dedicated control tasks. Processor 100 includes embroidery and code debugging capabilities.

【0023】

FIG. 1 is a schematic view of a digital device 10 according to an embodiment of the present invention. The digital device includes a processor 100 and a processor backplane 20. In a particular example of the invention, the digital device is a digital signal processor device 10 implemented in an application specific integrated circuit (ASIC). For simplicity, FIG. 1 shows only those parts of the microprocessor 100 that are needed to understand embodiments of the present invention. The details of the general structure of the DSP are well known, so please refer to another document. For example, US Pat. No. 5,072,418 issued by Frederick Boutaud et al. Describes DSP in detail and is incorporated herein by reference. U.S. Pat. No. 5,329,471 issued by Gary Swoboda et al. Describes in detail how to test and emulate a DSP, which is incorporated herein by reference. Some details of the microprocessor 100 with respect to one embodiment of the present invention will be described below so that those skilled in the art of microprocessor technology can make and use the present invention.

【0024】

Some exemplary devices that may benefit from aspects of the invention are described herein with reference to US Pat. No. 5,072,418, particularly US Pat. No. 5,072,418, FIGS. 2-18. .. Microprocessors incorporating aspects of the invention that improve performance and reduce costs can be used to further improve the equipment described in US Pat. No. 5,072,418. Such devices are, but are not limited to, industrial process control, automotive systems, motor control, robot control devices, satellite communication systems, echo erasing devices, modems, videovisual devices, voice recognition devices, encrypted devices. Includes voice recorders, modem devices, etc. A description of the features of the various structures of the microprocessor in Figure 1 and a description of the complete set of instructions are given in Application No. 09 / 410,977 (TI-28433) assigned to Applicant. Is used here.

【0025】

As shown in FIG. 1, the processor 100 is a central processing unit (CPU) having a processor core 102 and a memory interface unit 104 that interfaces the processor core 102 with a memory unit outside the processor core 102. ) Is formed. The processor backplane 20 includes a backplane bus 22 to which the memory management unit 104 of the processor is connected. An instruction memory 24, a peripheral device 26, and an external interface 28 are also connected to the backplane bus 22. As will be appreciated, in other examples, different configurations and / or different techniques can be used to achieve the present invention. For example, the processor 100 may separate the processor backplane 20 from it to form a first integrated circuit. For example, the processor 100 may be a DSP mounted on the backplane 20 that supports the backplane bus 22 and peripheral and external interfaces. For example, the processor 100 may be a microprocessor instead of a DSP, or may be realized by a technology other than the ASIC technology. This processor or a processor including this processor may be implemented in one or more integrated circuits.

【0026】

FIG. 2 shows the basic structure of an embodiment of the processor core 102. As shown, this embodiment of processor core 102 includes four elements: an instruction buffer unit (I unit) 106 and three execution units. The execution unit executes the instructions decoded from the program flow unit (P unit) 108, the address data flow unit (A unit) 110, and the instruction buffer unit (I unit) 106, and also programs. It is a data calculation unit (D unit) 112 that controls and monitors the flow.

【0027】

FIG. 3 shows the P unit 108, A unit 110, and D unit 112 of the processor core 102 in more detail, and also shows a bus structure connecting various elements of the processor core 102. The P-unit 108 includes, for example, a loop control circuit, a GoTo / branch control circuit, and various registers that control and monitor the program flow, such as repeat counter registers, interrupt masks, flags or vector registers. The P unit 108 is coupled to a general-purpose data write bus (EB, FB) 130, 132, a data read bus (CB, DB) 134, 136, and an address constant bus (KAB) 142. P unit 108 is also coupled to subunits within A unit 110 and D unit 112 via various buses labeled CSR, ACB and RGD.

【0028】

As shown in FIG. 3, in this embodiment, the A unit 110 includes a register file 30, a data address generation subunit (DAGEN) 32, and an arithmetic and logical operation unit (ALU) 34. The A unit register file 30 contains various registers. For example, 16-bit pointer registers (AR0 to AR7) and data registers (DR0 to DR3) that are also used for data flow and address generation. The register file also contains a 16-bit circular buffer register and a 7-bit data page register. In addition to the general-purpose buses (EB, FB, CB, DB) 130,132,134,136, the data constant bus 140 and the address constant bus 142 are also coupled to the A unit register file 30. The A unit register file 30 is coupled to the A unit DAGEN unit 32 via unidirectional buses 144 and 146, which operate in opposite directions, respectively. The DAGEN unit 32 includes, for example, a 16-bit X / Y register and a coefficient / stack pointer register that control and monitor address generation in the processing engine 100.

【0029】

A unit 110 also includes ALU34, which includes shifter functions as well as functions generally related to ALUs such as addition, subtraction and AND, OR, XOR logical operators. ALU34 is also coupled to the general purpose bus (EB, DB) 130,136 and the instruction constant data bus (KDB) 140. The A unit ALU is coupled to the P unit 108 via the PDA bus and receives register constants from the P unit 108 register file. The ALU34 is also coupled to the A unit register file 30 via the bus RGA, RGB to receive the contents of the address and data registers, and the address and data register of the register file 30 via the bus RGD. Transfer the content.

【0030】

According to an exemplary embodiment of the invention, the D unit 112 comprises a D unit register file 36, a D unit ALU38, a D unit shifter 40, and two multiplication and accumulation units (MAC1, MAC2). Including 42,44. The D unit register file 36, the D unit ALU38, and the D unit shifter 40 are connected to the bus (EB, FB, CB, DB, KDB) 130,132,134,136,140, and the MAC units 42,44 are connected to the bus (CB, DB, It is combined with KDB) 134,136,140 and Data Read Bus (BB) 144. The D unit register file 36 contains a 40-bit accumulator (AC0 to AC3) and a 16-bit transition register. In addition to the 40-bit accumulator, the D unit 112 also uses the 16-bit pointer and data registers of the A unit 110 as source or destination registers. The D unit register file 36 is located on the D unit ALU38, MAC1 42 and MAC2 via the accumulator write bus (ACW0, ACW1) 146,148. Data is received from 44 and from D unit shifter 40 via the accumulator write bus (ACW1) 148. Data is read from the D-unit register file accumulator to the D-unit ALU38, D-unit shifter 40, MAC1 42 and MAC2 44 via the accumulator read bus (ACR0, ACR1) 150,152. The D-unit ALU38 and D-unit shifter 40 are also coupled to the subunits of A-unit 108 via various buses labeled EFC, DRB, DR2 and ACB.

【0031】

Referring to FIG. 4, an instruction buffer unit 106 according to the invention is shown, which includes an instruction buffer queue (IBQ) 502 of 32 words. The IBQ502 contains a 32-x16-bit register 504 that is logically divided into 8-bit bytes 506. Instructions arrive at IBQ502 via the 32-bit program bus (PB) 122. Instructions are retrieved in 32-bit cycles at the position pointed to by the local write program counter (LWPC) 532. The LWPC532 is contained in a register on the P unit 108. The P unit 108 also includes a local read program counter (LRPC) 536 register, a write program counter (WPC) 530 register, and a read program counter (RPC) 534 register. The LRPC536 points to the position in the IBQ502 of the next instruction to be loaded into the instruction decoders 512,514. That is, the LRPC536 points to the position in the IBQ502 of the instruction currently dispatched to the decoders 512,514. The WPC points to the starting address of the next 4-byte instruction code for the pipeline in program memory. Each time it is fetched to IBQ, the next 4 bytes from program memory are fetched regardless of instruction boundaries. RPC534 points to the address of the program memory of the instruction currently dispatched to decoder 512/514.

【0032】

In this embodiment, the instructions are formed in 48-bit words and are loaded into the instruction decoder 512,514 by the 48-bit bus 516 via multiplexers 520,521. As will be apparent to those skilled in the art, instructions may be formed in terms other than 48 bits, and the invention is not limited to the particular embodiments described above.

【0033】

For the currently preferred 48-bit word size, bus 516 can load up to two instructions (one instruction per decoder) during any one instruction cycle running in parallel. The instruction combination may be any combination of formats (8,16,24,32,40 and 48 bits) that fits the 48-bit bus. When loading only one instruction in one cycle, the decoder 15 12 is given priority over the decoder 2 514. Each instruction is then sent to each functional unit to execute them and access the data on which the instruction or operation should be executed. Instructions are aligned on a byte boundary before being passed to the instruction decoder. The alignment is based on the format obtained for the previous instruction during its decryption. Multiplexing related to instruction alignment with byte boundaries is done in multiplexers 520,521.

【0034】

If one of the two instructions has a parallel enable bit, the two instructions can be put in parallel. The hardware that supports this type of parallel method is called a parallel enable mechanism. Similarly, if both instructions perform single data memory access (Smem or dbl (lmem)) in indirect mode, then the two instructions can be placed in parallel. The hardware that supports this type of parallel system is called a soft dual mechanism.

【0035】

Processor core 102 executes instructions through a seven-step pipeline. Each step is described below with reference to Table 1 and Figure 5. It executes processor instructions in a 7-step pipeline regardless of where it is executed (A unit or D unit). According to one aspect of the invention, in order to reduce the program code size, the C compiler dispatches as many instructions as possible for execution in the A unit, so that the D unit saves power. The power may be turned off. For this reason, A unit needs to support the basic operations performed by the memory operands.

【0036】

[table 1]

<img file="JP2000276352A_D0001.tif" />【0037】

The first stage of the pipeline is the pre-extract (P0) stage 202, during which the next program memory location is expressed by asserting the address on the address bus (PAB) 118 of memory interface 104. Is addressed. In the next stage retrieval (P1) stage 204, the program memory is read and the I unit 106 is filled from the memory interface unit 104 via the PB bus 122. The pre-fetch and fetch stages are separated from the other pipeline stages, interrupting the pipeline during the pre-fetch and fetch stages, interrupting the continuous program flow, and another instruction in program memory ( For example, a branch instruction) can be pointed to.

【0038】

Next, in the third stage decoding (P2) stage 206, the next instruction in the instruction buffer is dispatched to the decoder 512/514, and the execution unit that executes the instruction as the instruction is decoded (for example, P unit 108). , A unit 110 or D unit 112). Decoding step 206 decodes at least part of an instruction, including a first part indicating the type of instruction, a second part indicating the format of the instruction, and a third part indicating the addressing mode for the instruction. Including. The next step is address (P3) step 208, where the address of the data to be used in the instruction is calculated, or a new program address is calculated if the instruction requires a branch or jump in the program. To. Each calculation is performed on A unit 110 or P unit 108, respectively.

【0039】

In access (P4) stage 210, the address of the read operand is generated, and the memory operand whose address is generated by the DAGEN Y operator in Ymem indirect addressing mode is indirectly addressed to the Y memory (Ymem). ) Is read from. The next stage in the pipeline is read (P5) stage 212, where the memory operands whose addresses are generated in DAGEN X in Xmem indirect addressing mode or by the DAGEN C operator in coefficient address mode are read. The address of the memory location where the result of the instruction should be written is generated.

【0040】

The last is execution (P6) step 214, in which the instruction is executed in either A unit 110 or D unit 112. The result is then stored in a data register or accumulator or written to memory for read / modify / write instructions. In addition, a shift operation is performed on the data in the accumulator during the execution phase. The processor 100 pipeline is protected. This greatly improves C compiler performance because NOP instructions do not have to be inserted to meet latency requirements. This also greatly facilitates code conversion from the previous generation processor to the later generation processor.

【0041】

The basic rules for pipeline protection used in Processor 100 are as follows: If a write access is initiated before the running read access ends and both accesses share the same resource, then an additional cycle is inserted to complete the write and the updated operand is next: Allows the instruction to be executed, but for emulation, single-step code execution must be done exactly like free-running code execution.

【0042】

The basic principles of operation of a pipeline processor are described below with reference to Figure 5. As can be seen from FIG. 5, in the first instruction 302, the continuous pipeline steps are time T.₁~ T₇Is executed during. Each time is one clock cycle of the processor machine clock. The second instruction 304 is the time T₂Can enter the pipeline. Because the previous instruction has already moved to the next pipeline stage. In order 3 (306), the pre-extraction stage 202 is time T₃Happens to. As can be seen from Figure 5, the 7th stage pipeline can process all 7 instructions at the same time. For all seven instructions 302 to 314, Figure 5 shows the time T.₇Shows all of them being processed in. Such a structure adds a parallel form to the processing of instructions.

【0043】

As shown in FIG. 6, this embodiment of the invention is a memory interface coupled to an external program storage unit 150 via a 24-bit address bus 118 and a 32-bit bidirectional data bus 120. Includes unit 104. The memory interface unit 104 is also coupled to the data storage unit 151 via a 24-bit address bus 114 and a bidirectional 16-bit data bus 116. The memory interface unit 104 is also coupled to the I unit 106 of the machine processor core 102 via a 32-bit program read bus (PB) 122. The P unit 108, the A unit 110, and the D unit 112 are coupled to the memory interface unit 104 via a data read / write bus and a corresponding address bus. The P unit 108 is further coupled to the program address bus 128.

【0044】

More specifically, the P unit 108 includes a 24-bit program address bus 128, two 16-bit data write buses (EB, FB) 130,132 and two 16-bit data read buses (CB, DB) 134,136. It is coupled to the memory interface unit 104 via. Unit 110 has two 24-bit data write address buses (EAB, FAB) 160,162, two 16-bit data write address buses (EB, FB) 130, 132 and three data read address buses (BAB, CAB, DAB). ) 164,166,168 and two 16-bit data read buses (CB, DB) 134,136 are coupled to the memory interface unit 104. The D unit 112 is coupled to the memory interface unit 104 via two data write buses (EB, FB) 130,132 and three data read buses (BB, CB, DB) 144,134,136.

【0045】

FIG. 6 shows the passing of an instruction from the I unit 106 to the P unit 108 at 124, for example, sending a branch instruction. Also, FIG. 6 shows the transfer of data from I unit 106 to A unit 110 and D unit 112 at 126 and 128.

【0046】

As shown in Figure 7, the processor 100 is organized around a unified program / data space. The program pointer is internally 24-bit and has a byte addressing function, but since the program is always fetched on a 32-bit boundary, only the 22-bit address is sent to the memory. However, for example, during emulation for software development, all 24-bit addresses are given to achieve the hardware break point. The data pointer is a 16-bit extension of the 7-bit main data page and has a word addressing function.

【0047】

The software defines up to three main data pages as follows: MDP direct access indirect access CDP MDP05 --Indirect access AR [0 ~ 5] MDP67 --Indirect access AR [6 ~ 7] The stack is maintained and resides on primary data page 0. CPU memory map registers are visible on all pages. Table 2 summarizes various aspects of processor 100.

【0048】

[Table 2]

<img file="JP2000276352A_D0002.tif" />【0049】

The problem with the pipeline working is that different instructions must access one and the same resource. Very often the first instruction acts to change a resource, eg, some register, eg a field in a register, and then the second instruction must access that resource. If these instructions are processed separately so that the processing of the second instruction starts only when the processing of the first instruction is completed, this does not cause a conflict. However, if no action is taken in the pipeline architecture, the second instruction may access this resource before the first instruction terminates access to the resource.

【0050】

Such potential conflicts are often referred to as "data hazards," and examples of possible data hazards include, for example:

【0051】

-Read after Write (for example: after ARx = ARy)^*ARx = k16 follows) -Write after Read (for example: ARx = ARy followed by mar (ARy = P16)) -Write after Write (for example: ARx = ARy followed by mar (ARy = P16)) [0052]

Figure 8A shows an example of a pipeline protection operation for ReadAfterWrite (RAW). Step 600 shows the write performed by the first instruction in the execution stage (EXE) on register AR1 (eg AR1 = AR0 + K16), and step 602 is the read performed in the address stage (ADR) on AR1. (For example, AC0 = * AR1) is shown. Pipeline protection operation (604) is for reading at 610 until a new AR1 value is available after writing to AR1 at 612 and the stop for the address stage is relaxed (removed) at 614. Includes setting a stop 606 for the address stage so that no address is generated (reading AR1 is not valid).

【0053】

Figure 8B shows another example of pipeline protection behavior for ReadAfterWrite (RAW). Step 620 indicates the write (eg AR0 = AC0 + K16) performed by the first instruction in the execution stage (EXE) on register AR0. Step 622 shows the reads performed in the read phase (RA) on AR0 (eg, Read Condition Read / Memory Mapped Register (MMR)). Pipeline protection operation (624) includes setting a stop 626 for the expected access phase (ACC), thus keeping addresses and requests active at 628, writing on AC0 at 630, and access phase. The outage has been relaxed (removed) and new values for Condition / MMR are available at 632. Unlike this, a stop can be inserted during the read phase at 630 instead of the access phase.

【0054】

Figure 9 shows an example of pipeline protection operation for Write After Write (WAW). Step 640 shows the write performed by the first instruction at the execution stage (EXE) in register AR1 (eg AR1 = AR0 + K16), and step 642 shows the write performed at the address stage (ADR) on AR1 (eg AR1). AC0 = * AR1 +) is shown. Pipeline protection action (644) includes setting a stop 646 for the address stage, so a new AR1 value is available after the first write to AR1 is done at 650 and for the address stage at 652. The 648 does not generate an address for a second write on AR1 (writes to AR1 are not allowed) until the outage is relaxed (removed).

【0055】

Figure 10A shows an example of pipeline protection behavior for Write After Read (WAR). Step 660 shows the read (eg AC2 = AR3 + K8) performed by the first instruction in the execution stage (EX) at register AR3. Step 662 shows the writes (eg * AR3 + DR0) performed at the address stage (ADR) on AR3. Pipeline protection action (664) includes setting a stop 666 for the address stage, so AR3 reads are performed at 670, and AR3 goes to AR3 at 668 until AR3 writes are allowed during the same stage at 670. No address is generated for writing to AR3 (writing to AR3 is not allowed). Reads capture the old values of AR3, so AR3 reads and writes can be performed at the same stage in the 670. The outage for the address stage is mitigated (removed) at 672.

【0056】

Figure 10B shows another example of pipeline protection behavior for WriteAfterRead (WAR). Step 680 indicates the read (eg Condition or MMR) performed by the first instruction in the read stage (RD) at register AR3. Step 682 shows the writes (eg * AR3 + DR0) performed at the address stage (ADR) on AR3. Pipeline protection action (684) includes setting a stop 686 for the address stage, so the 690 performs an AR3 read, allows AR3 writes, and relaxes (removes) the stop for the address stage. Until, 688 does not generate an address for writing to AR3 (writing to AR3 is not allowed).

【0057】

Figure 11 is a schematic representation of the method adopted to determine the definition of all comprehensive arbitration functions for potential resource access conflicts in the pipeline. This inclusive arbitration function is an abstract concept that supports and simplifies the design of each arbitration logic, and all of this design can be realized as a special form of the inclusive function. The processing engine can also include logic in which comprehensive arbitration functions are embedded . This comprehensive arbitration function can also assist in circuit inspection at the end of circuit design. Although not described in the content of this embodiment, this method can be used for other processor architectures.

【0058】

Referring to FIG. 11, in the initial step (1), the entire processing engine organization (700) is divided into groups of registers, i.e. register files (eg, 702, 704, 706). In this example, there are three register files for the program unit, namely control flow (CF), data unit (DU) and address unit (AU). Each of these register files contains a number of registers N (i) (eg, 708, 710, 712). These registers can form resources to protect and not only protect the entire register, or instead of protecting the entire register, some of the registers (eg, 714, 716, 718) (or fields within these registers). It is desirable to protect. Figure 11 shows such a definition of resource granularity. Thus, the protected resource may be, for example, a register or a field within the register.

【0059】

For each protected resource, step 2 guides an analysis of the worst possible resource utilization. Different instructions provide different ways of reading and writing to and from resources, for example. For register field 714, the pipeline stages shown in 720 that can perform read / write operations on that resource are stages P3, P5 and P6, as shown in FIG. In other words, the worst-case resource utilization for this resource is relevant to pipeline stages P3, P5 and P6. The above access can be classified in terms of execution stage.

【0060】

For the five instructions I1, I2, I3, I4 and I5, in step 3 the pipeline depth (eg pipeline steps P2, P3, here, to consider the instruction execution overlap, as shown in 722. P4, P5 and P6) must be considered.

【0061】

Consider all potential data hazards, as indicated by the arrows in Figure 12. This figure is a schematic showing potential contention at different stages of the pipeline, showing the five stages P2 through P6 of FIG. 5 for each of the four instructions I0, I1, I2, I3 and I4.

【0062】

By examining the data hazards that can be found, a comprehensive arbitration function can be derived, as shown in Figure 13. This comprehensive arbitration function defines the relationship between current access and pending access. This comprehensive arbitration function can be used to control the selective outage of the pipeline and avoid data hazards. Comprehensive logic shows all potential resource access contention to the pipeline, and analyzes the potential contention problem graphically shown in Figure 12 to give the following conflict-prone signals: Can be identified.

【0063】

a: current read stage P3 b: pending (stage P4) read stage P6 c: pending (stage P4) read stage P5 d: current read stage P5 e: pending (stage P5) read stage P6 f: current read stage P6 1: current write stage P3 2: pending (stage P4) write stage P6 3: pending (stage P4) write stage P5 4: pending (stage P5) write stage P6 5: current write stage P5 6: current write stage P6 [0064]

The logic for decoding these signals and forming the signal stol-stage 4 for stopping the ADR (P3) stage and the signal stol-stage 5 for stopping the ACC (P4) stage is shown in FIG. .. It can be seen that the signals "d" and "f" are not shown in Figure 13. However, these signals are not needed, as anticipating the use of the pending signals "b" and "e" can eliminate all potential conflicts associated with the 7-step read. Therefore, it is not necessary to display these signals in FIG. 13 as the conflicts associated with them are already predictable.

【0065】

Therefore, in general, an inclusive function has a large number of variable operands, and each arbitration logic has a lower degree of regression, that is, a special feature of an inclusive function that has a large number of operands that are variables within a fixed inclusive function. It can be understood that it is a form or a subset.

【0066】

Once the inclusive arbitration function has been determined, this inclusive arbitration function can be used to implement the circuit design of each arbitration logic block that can be defined as a special form of the inclusive arbitration function. The arbitration logic of individual resources does not require a complete inclusive form. The reason is that it is not possible for each of the resources to have some of the conflicts that are generally considered by the comprehensive arbitration function.

【0067】

If you want complete protection from the concurrency of all possible conflicts, the processing engine only needs to have a comprehensive arbitration logic that embodies a comprehensive arbitration function.

【0068】

Another feature of the present invention will be described with reference to FIGS. 9, 10A and 10B. Using dynamic reordering methods for write cycles such as scoreboarding or queuing is difficult with the microprocessors of this embodiment. The reason is that to be able to change the order of instruction execution, one must know how to use the full resources of the instructions that occur. In this embodiment, any register can be accessed by instruction through an indirect address. This address can be known (can be used) by hardware only from stage 5. Therefore, most instructions with addressing mode cannot be reordered. However, it has been found that other techniques can be used to minimize the interlock stop penalty. According to one feature of the invention, the techniques disclosed herein dynamically redirect competing write destinations to a set of shadow registers when free, thus preventing conflicts. , Delay the actual destination write from stage 4 to the next stage.

【0069】

In one embodiment, this method is dedicated to write-to-write (WAR) contention as shown in FIGS. 10A and 10B and write-to-write (WAW) contention as shown in FIG. This technique can be used to reduce the stop penalty for a subset of register files or for all sets of registers in a microprocessor. If you select only a subset of registers, you can determine the number of shadow registers in the stack by analyzing the application code that runs on the microprocessor. Similarly, a subset of the registers that favorably form this stack can be obtained by studying application code that determines where and how often conflicts occur.

【0070】

FIG. 14 is a block diagram showing a shadow register 1400 and a control circuit for performing delayed writing according to the features of the present invention. Basically, this logic consists of three subsets: the interlock detection unit 1402, the storage and filtering unit 1404, and the shadow management unit 1406.

【0071】

The interlock detection unit 1402 includes an arbitration circuit similar to FIG. 13 with improvements for identifying outages that can be resolved by performing a delayed write. Each arbitration logic generates a stop signal and a predicted length (cycle) of the stop signal (worst signal). Consider write delayed through the transfer signal from the SM-unit. According to another feature of the present invention, the read reinstruction mechanism does not add read (RAW) dependency after writing by this logic.

【0072】

The hold and filtering unit 1404 selects a free shadow register from the shadow register stack 1400 to receive the conflict write signal. This unit contains K cascaded fast filters (using a carry-look ahead adder (CLA) type architecture) and a destination / stop-length encoding circuit (where K is the number of shadow registers). ) Consists of.

【0073】

Shadow management unit 1406 receives and saves destination and stop length information. This unit reinstructs write 1410, swaps shadow content to destination 1410, and generates a control signal for register file 832 to reinstruct read 1412. A stop signal 1430 is received from the pipeline and control circuit 820 to identify all stops from stages 4-7 to keep it in sync with the pace of the pipeline.

【0074】

Register file 832 contains a set of shadow registers 1400 with a multiplexed data bus. The merge circuit 1440 receives the direct stop signal 1441 and the filtered stop signal 1442 and forms a stop signal 1443 sent to the pipeline control circuit 830 to stop the pipeline. The direct stop signal 1441 indicates a stop that cannot be resolved by delayed writing, and the filtered stop signal 1442 indicates a stop that could have been resolved except that an empty shadow register is not available.

【0075】

FIG. 15 is a schematic representation of the arbitration circuit for delayed writing in FIG. The arbitration circuit function is basically the same as the function shown in Figure 13, but it is divided to distinguish WAW and WAR from RAW conflicts and to differentiate the stop lengths of 1, 2 or 3 cycles. The point is different. RAW conflicts are resolved with a simple stop and are sent directly to the second level merge logic. The direct stop signals 1441a and 1441b are asserted for RAW contention. A stop vector 1450 and a length-encoded signal 1451 are sent to the filter unit 1404 to indicate that a WAW or WAR conflict has been detected. Another signal is sent to the stop arbitration circuit:

【0076】

7: pending stage 3 for stage 6 8: pending stage 3 for stage 5 9: pending stage 5 for stage 6 10: current write from shadow register Additional signals 7-9 can stop the stop resulting from reinstruction reading. It is possible to detect WAW contention resulting from writes delayed by signal 10.

【0077】

FIG. 16 is a block schematic of a structural example for the interlock control mechanism 1402 that uses the arbitration circuit of FIG. 15 for the pipeline 820 of FIG. 14, for example. It can be seen that it may have the same structure for other pipelines, eg the pipeline 850 of FIG. Furthermore, since the instruction pipeline itself is used for stop management, it can be understood that a memory element (read / write queue) is provided for stop management. For example, a post-write write conflict in the pipeline between stages P3 to P6 between two consecutive instructions should result in a three-cycle outage (at stage P3). In fact, the interlock logic produces 3 × 1 cycles of continuous outages (at stage P3).

【0078】

FIG. 16 shows a constant parallel structure for hazard detection, including the following levels:

【0079】

The first level includes the basic decoder 882 (from pending access or current access). These decoders are identical to the decoder 880 in the register file, except that they are used for pending signals. This decoder logic responds to access information from at least the selected pipeline stage in order to derive access information for each protected resource. The decoder 882 acts to decode the pending access information, and the decoder 880 can act to decode the current access.

【0080】

The second level involves merging the equivalent signals (in the sense of an arbitration function) for each protection register 884. Such a merge is achieved by ORing these signals at an OR gate using, for example, the logic shown in FIG. The output of the decoder 880 for current access is merged in merge logic 883 and then fed to merge logic 884, where it is merged with the output of decoder 882 for pending access.

【0081】

The third level consists of the same number of sets of arbitration logic 886 as the protection registers. This arbitration logic is extracted from the arbitration function shown in FIG. 15 according to the input signal to this function (ie, this function forms a subset of the arbitration logic in FIG. 15) and applied (reduced) to each register access trace. To. Register access traces are formed from incoming signals that specify access / phase. Each arbitration circuit 1600a outputs a stall_stage4 signal 1650a and a length-encoded signal 1651a. Therefore, a stop vector with a number of bits T equal to the number of target registers being detected is formed.

【0082】

The fourth level is simply a merge of all arbitration results using, for example, an OR gate, 1440 (Figure 14). Each set of arbitration logic causes up to two outages (at stages 3 and / or 4). All stops at the same stage are merged together. These merged output signals are fed as stop control signal 1443 to the relevant pipeline control logic to control the selective stop of the pipeline.

【0083】

The stop control signal 1444 is currently supplied to the register access control logic 890 for access control. Advantageously, since the reduction of the stop penalty is performed in this embodiment, only the conflicts that are not resolved by the delayed write cause a proper pipeline stop, i.e. a lower stage freeze and a bubble insertion in the next stage. ..

【0084】

Arbitration logic is relatively simple in hardware as a result of logical reuse. Logical reuse means that the arbitration logic uses tapping from the queues of the existing main pipelines 822-828 (rather than forming a new queue for the previously proposed arbitration purpose) and merges in the examples. It means to use the result from the decoder 880 through logic 883 as well. Therefore, the additional amount of hardware required for the arbitration logic block is significantly reduced. When implementing the example as a DSP integrated circuit on specific hardware, all arbitration logic covers less than 2% of the total CPU area. In contrast, without logical reuse, the chip area required for logic required to provide comparable levels of pipeline protection would be at least several times greater, perhaps larger than magnitude.

【0085】

At the stage of software inspection of the hardware design of the processing engine, the concept of comprehensive arbitration function can be further utilized. In general, due to the complexity of the CPU, its instruction set and architecture, generating all the test patterns for pipeline processing engine hardware can be a great undertaking. The test pattern needs to be defined with reference to the criteria specified in advance. The use of this standard can be extremely labor intensive. By using this design, a function test pattern generator can be created by using an inclusive function as a criterion related to the latency table of a conventional instruction set. This simplifies the creation of test pattern generators because the scope of the test can be limited to the possible conflicts that can be considered by the inclusive function. Since the test pattern generator directly follows an inclusive function, the process of hardware design testing is not only faster, but also more systematic and guarantees good coverage.

【0086】

FIG. 17 is a block diagram of the hold and filter circuit 1404 for the three shadow registers of FIG. This unit receives a stop (WAR-WAW) via the stop vector signal 1750, of which K (K can be 0 to 3 to be resolved by reinstructing the write into the free shadow register). select. This shadow register resolves the conflict (known by the length information), and the shadow register maintains this value until it is then written to the correct destination register. If the stop register is selected, the corresponding destination code 1462 and stop length cy () are encoded and sent to SMU1406. This selected stop signal is unwound from the stop vector 1450 before being sent to the next filter stage. After all filters 1700 (n) (as many as shadows), the filtered stop vectors are sent to the second level merge 1440 and the shadow registers are busy or more than four at a time. If there is a conflict, a stop operation occurs. Other embodiments can have more or less shadow registers, so K is selected in this case.

【0087】

Each encoder 1710a to 17c generates a destination code (actual target write instruction) from the R [N: 0] vector. Table 3 below is the truth table.

【0088】

[Table 3]

<img file="JP2000276352A_D0003.tif" />Table 3: Shadow address code coding table [0089]

In this embodiment, this method targets a shrink bench of registers, such as auxiliary and data registers, to minimize the number of shadow registers. In FIG. 16, eight arbitration circuits 1600 are provided for eight target registers so that an 8-bit stop vector is formed. Since the filtering is serialized, it is advantageous to use a high speed device.

【0090】

as follows, S [i]: i-th bit of input stop vector C [i]: Filter coefficient coeff (n) propagating to the i-th bit, (C [0] = 1 when shadow is free) SF [i]: Filtered value of S [i] R [i]: Bit selection flag [0091]

When referred to, equations (1), (2) and (3) define how to determine SF {I} and C {I + 1}. Table 4 is a truth table showing these relationships for the four target registers. Contain different numbers of target registers with similar coding.

【0092】

[Table 4]

<img file="JP2000276352A_D0004.tif" />Table 4: Selection filter truth table [0093]

[Number 1]

<img file="JP2000276352A_D0005.tif" />【0094】

Here, C [0] = 1 when the shadow is free. FIG. 18 is a schematic for a look-ahead structure for the filter circuit of FIG. This structure is contained within each of the filters 1700a-c. Another embodiment can use a look-ahead structure with different devices for improving its speed, such as a fast carry CLA. However, for adders, for example, any parallel prefix architecture (such as CLA, fast CLA) can be used, depending on the timing constraints of the design. FIG. 18 shows an example for four target registers provided with a 4-bit stop vector S [3 ~ 0].

【0095】

FIG. 19 is a schematic representation of the multiplexer circuit 1720 for stop length selection for the filter circuit of FIG. The multiplexer circuit 1720 is controlled by the signal R [i] and selects one stop length L () 1451 from the K input signals. Signal Cy [x] 1721 sends the selected stop length to SMU1406.

【0096】

FIG. 20 is a block diagram of the shadow management circuit 1406 for the shadow register of FIG. FIG. 21 is a block diagram of the shadow management circuit of FIG. 20 showing the state machine control circuit 2100.

【0097】

This unit receives the destination signal 1462 and stop length signal 1721 from RF unit 1404, as well as the stop and write enable signal 2000 (for conditional instructions). The destination register 2010 stores the destination code. The length register 2012 stores the stop length and the increment register 2014 is incremented to form a pending write signal. From these signals, the shadow management unit 1406 generates the following signals.

【0098】

--Reg2Sh [i] signal 2010: Transfer write instruction from register in stage 3 to shadow [i]. This makes it impossible to write to the conflicting stage 3 registers. --Sh [i] 2Reg signal 2012: Write instruction from shadow [i] to the conflicting register first. --Coeff [i] signal 2014: Free shadow [i] signal used as a factor in the RF unit. --Pending write signal 2016: A signal sent to ID unit 1402 to manage conflicts that may occur within stages 4 and 5 as a result of delayed writes from the shadow register. --Redirect read signal 2110: Instructions for steps 3, 5 and 6 to the register file. These redirect signals become active at the start of any operational read cycle. In this embodiment, these signals are expected and latched for up to one cycle.

【0099】

The write in stage 6 is not considered because it causes a conflict (stop) with the subsequent read. In the case of a 3-cycle delayed write by an instruction that executes a step 6 write, the write in stage 6 is given overwrite priority and a pending, current write and redirect read signal is generated as shown below. These signals are sent to the interlock detection unit 1402 and the register file 832.

【0100】

FIG. 22 is a schematic diagram of a circuit for routing data from the shadow register to the target register in the register file of FIG. Within this register file, a multiplexed data path is realized between the targeted register and the shadow register. When a conflict is detected, the data item is loaded into the shadow register [i] 2200 via the step 3 write path 2202 in response to the control signal reg2shadow [i] 2012 from SMU1406. In the same cycle, the reg2shadow [i] signal 2010a prohibits writing data to target register 2210 so that the detected conflicts are offset. In response to the control signal shadow2reg [i] as a delayed write cycle, this data item is transferred and written to target register 2210 in a later cycle. The multiplexer 2206 is controlled to select a data item from the shadow register 2200 selected from a set of shadow registers, and the multiplexer 2210 is to select from one of the write paths of stages 3 to 6 or from the shadow register. Is controlled by.

【0101】

Multiplexers 2220, 2222, 2224 and 2226 are provided to allow redirected reads from the shadow register to the stage 3, stage 5 or stage 6 read path if the data item has not yet been written to the target register. ..

【0102】

FIG. 23 is a state diagram showing the operation of the state machine 2100 of FIG. Each shadow register has a separate state machine 2100 associated with it, either during a reset or when the shadow register associated with the state machine 2300 is not selected as indicated by the signal Cout = 0, or the signal Stall (3). ), Loop 2302 holds state machine 2100 in load state 2300 when stage 3 is stopped. When the associated shadow register is selected (Cout = 1), Arc2304 changes state machine 2100 to count state 2310. The destination register 2010 and the length register 2012 are loaded with data related to the selected conflict, and the increment register 2014 is loaded with 0.

【0103】

In count state 2310, the length register 2012 is decremented for each clock cycle and the increment register 2014 is incremented for each clock cycle. If the length register 2012 is greater than 0 or a stop is asserted beyond step 3 by a value equal to the increment register, loop 2312 holds the state machine in count state 2310. For example, if the increment register holds a value of 2, the count state 2310 is maintained if stage 5 is stopped. However, in this case, the length register and the increment register do not change. During the count state 2310, the pending write signal 2016 is asserted. A pending write signal is generated during the count state using the destination code and increment output (Ino) and sent to the interlock detection logic to track another conflict.

【0104】

Once the length register reaches a value of 0, arc2314 returns the state machine to load state 2300. The signal shadow2reg [i] 2012 is asserted to complete the delayed write of the target register using the contents of the shadow register. The transfer write signal Shadow2Reg [i] is generated using the destination code input and length output (Lo).

【0105】

Delaying writes eliminates WAR and / or WAW conflicts, but also has side effects that need to be considered. In this example, three types of side effects are detected and managed as described in the next chapter.

【0106】

Read redirection is performed so that delay logic does not cause RAW contention. The next read from an instruction that uses the delay mechanism MUST uses the register value as if the write was done consistently with non-conflicting behavior. This is achieved by providing the data stored in the associated shadow register via a redirection multiplexer described with reference to FIG.

【0107】

RAW locking that can occur when removing a WAW / WAR stop can also be stopped by using a read redirect. WAW conflicts caused by the delayed write mechanism must be detected. .. These induced WAW conflicts can also be resolved by a delayed write mechanism when the shadow is free.

【0108】

The following figure shows the three contents of the delayed write in this embodiment, and this write can be from 1 cycle to 3 cycles. FIG. 24A is a timing diagram showing one cycle of write delay and the resulting read redirect from the shadow register. Write 2400 is detected as a WAR conflict and is delayed by one cycle to 2402 due to the features of the invention. Due to this delay, Read 2404 requires a RAW stop. Preferably this stop can be stopped by a read redirect from shadow [i].

【0109】

FIG. 24B is a timing diagram showing the write delay of Loop Nine 1 which requires only one shadow register. The WAR conflict between write 2410 and read 2411 is resolved by the delayed write 2412. However, this induces WAW contention with write 2414. Preferably, this induced WAW conflict can also be resolved by delayed write 2416. Since this delay is only one cycle, only one shadow register is needed to resolve the conflict between the two.

【0110】

FIG. 25A is a timing diagram showing a read redirect resulting from a two-cycle write delay and a delay from the shadow register that stopped the potential conflict. The WAR conflict for write 2500 is resolved by write 2502, which is delayed by two cycles. This induces RAW contention for read 2502. This induced conflict is preferably resolved by a read redirected from shadow [i]. It is preferred to resolve it by a read redirected from the shadow [i] of the RAW conflict between the write 2510 and the read 2512.

【0111】

FIG. 25B is a timing diagram showing a two-cycle write delay in a loop that requires two shadow registers. The WAR conflict between write 2520 and read 2521 is resolved by write 2522, which is delayed by two cycles. However, this induces WAR contention with write 2524. This induced WAR conflict is also preferably resolved by the delayed write 2526. Since the delay time is 2 cycles, 2 shadow registers are needed to resolve the conflict between the two. Conflicts between write 2524 and write 2530 and conflicts between read 2521 and read 2532 are also preferably resolved by the delayed write 2526. Reads 2522 and 2526 are also performed without interruption by the reads redirected from shadow [i] and shadow [j], respectively. Read 2534 is also executed without stopping by the read redirected from shadow [i].

【0112】

FIG. 26A is a timing diagram showing the resulting read redirection from a shadow register with three cycles of write delay and potential contention stopped. The WAR conflict for write 2600 is resolved by write 2602, which is delayed by 3 cycles. This induces RAW contention for the read 2602. This induced conflict is preferably resolved by a read redirected from shadow [i]. A delayed write 2602 for read 2604 also induces one conflict. This induced conflict is preferably resolved by a read redirected from shadow [i]. It is also preferable that the RAW conflict between the write 2610 and 2611 and the read 2612 be resolved by the read redirected from the shadow [i]. Induced RAW conflicts for reads 2614 and 2616 are also preferably resolved by reads redirected from shadow [i].

【0113】

FIG. 26B is a timing diagram showing that a write delay of 3 cycles is performed in the loop so that 3 shadow registers are required. The WAR conflict between write 2620 and write 2640 is resolved by write 2622, which is delayed by 3 cycles. However, this induces WAW contention with write 2624 and write 2626. Preferably, these induced WAW conflicts can also be resolved by delayed writes 2622. Since the delay time is 3 cycles, 3 shadow registers are needed to resolve the 3 conflicts. The conflict between write 2640 and read 2623 is also favorably stopped by the delayed write 2622. Reads 2622, 2628 and 2630 are also performed without interruption by read redirected from shadow [i], shadow [j] and shadow [k], respectively.

【0114】

FIG. 27 shows the architecture of a dual pipeline arithmetic logic unit of a processing engine incorporating an embodiment of the present invention. As shown in FIG. 27, a first pipeline 820 and a second pipeline 850 are provided to receive instructions from the control flow 800. In the terminology of FIG. 2, the first pipeline can be the D unit and the second pipeline can be the A unit.

【0115】

The control flow includes an instruction buffer 810 and first and second decoders 812 and 814 for decoding the first and second instruction streams. A parallel coding enablement check is performed within the parallel proof logic 816 to ensure that the parallel contents are valid. Instructions from decoders 812 and 814 are dispatched from dispatch logic 818 under the control of dispatch controller 808.

【0116】

In the first pipeline 820, the continuous pipeline stages 822, 824, 826 and 828 are under the control of the local pipeline controller 830. The first local interlock / filter / shadow logic 838 that forms the first local interlock controller is associated with the first pipeline 820, and the interlock / filter / shadow logic 838 is similar to IDU1402, RFU1404 and SMU1406. Includes circuit. This pipeline controller responds to control signals from the associated interlock control logic, resulting in a selective outage of the pipeline stage. This controller responds to output from pipeline 820 as well as output from register file 832 for pipeline 820. The register file 832 contains a register file control logic 834 and individual registers 836, and a part of the register 836 is a shadow register. Control logic 834 responds to interlock / filter / shadow logic 838 by sending a delayed write signal to the selected target register so that the occurrence of pipeline outages can be beneficially reduced. One or more operators 840 and 842 can be accessed in relation to the current access behavior.

【0117】

In the second pipeline 850, the continuous pipeline stages 852, 854, 856 and 858 are under the control of the local pipeline controller 860. The second local interlock / filter / shadow logic 868 that forms the second local interlock controller is associated with the second pipeline 850. This pipeline controller responds to control signals from the associated interlock control logic, resulting in a selective outage of the pipeline stage. This controller responds to output from pipeline 850 as well as output from register file 862 for pipeline 850. The register file 862 contains a register file control logic 864 and individual registers 866, and a part of the register 866 is a shadow register. Control logic 864 responds to interlock / filter / shadow logic 868 by sending a delayed write signal to the selected target register so that the occurrence of pipeline outages can be beneficially reduced. One or more operators 870 and 872 can be accessed in relation to the current access behavior.

【0118】

It is understood that each of the local pipeline controllers 830 and 860 can respond to the output from each of the local interlock controllers 838 and 868 with a signal 875 that spreads the outages generated by the interlock controller to other pipeline controllers. Let's do it. This general principle is extensible. Therefore, if there are three or more pipelines, the local pipeline controller for each pipeline can respond to the output from all of the local interlock controllers.

【0119】

Therefore, in FIG. 27, the natural division of the interlock control is the same for the register file. However, this does not have to be the case, moving individual interlock controls (eg 838 or 868) from the original register file to another register file depending on the arbitration function information position (pending vs. current access). Is desirable.

【0120】

As described above, in this embodiment, for example, three register files are provided for the control flow (CF), the D unit (DU), and the A unit (AU). Therefore, three sets of local interlock control logic are provided. However, the physical locations of the control logic are distributed so that the pending and / or current access information is primarily located at their respective locations (AU, CF). For the D unit, the interlock logic is moved to the control flow unit, which has a significant percentage of control signals pending in the instruction pipeline. Logical overhead can be minimized by reusing as many current accesses as possible in the register file. The outages that occur are spread within the pipeline and all CPU subunits that have associated local pipeline control logic. Preferably, according to the features of the present invention, the conflict resolved by the delayed write via the shadow register does not generate a stopped state.

【0121】

Pipeline protection mechanisms that have been implemented and tested straight forward as a result of regularity and generality have been described above. The queuing of read / write pending operations is handled by the pipeline itself. Therefore, the interlock detection logic is a pure combination and does not require a read / write queue as part of the interlock mechanism.

【0122】

FIG. 28 is a spectral diagram showing a stopped state in a typical application using the circuit of FIG. The application used for this benchmark is vocoder code applied in a set of 4 frames (45K cycles). Figure 28 shows the stop frequency of stage 4 while the code is running.

【0123】

FIG. 29 is a distribution diagram showing a stopped state that can be removed from the application of FIG. 28 using the circuit of FIG. Figure 29 shows the same stop state distributed between the internal registers, distinguishing between RAW and WAW / WAR race conditions. From this, it can be determined that up to 50% of these conflicts can be eliminated without using bubble insertion using the circuit according to the feature of the present invention.

【0124】

FIG. 30 is a schematic diagram of an integrated circuit 40 incorporating the processor 10 of FIG. This integrated circuit can be implemented using application specific integrated circuit (ASIC) technology. As shown, this integrated circuit includes multiple contacts 42 for surface mounting. However, this integrated circuit can include other configurations, such as multiple pins provided on the lower surface of the circuit for mounting with zero insertion force sockets or any other suitable configuration.

【0125】

Applications of a processing engine, eg, a processor 10 such as those incorporated in an integrated circuit as shown in FIG. 32, are provided in a communication device, eg, a mobile wireless communication device. FIG. 17 shows an example of such a communication device. In the particular example shown in FIG. 17, the communication device is an integrated user input device, such as a mobile phone 11 with a keypad or keyboard 12 and a display 14. The display can be realized using a suitable technique, for example a liquid crystal display or a TFT display. Processor 10 is connected to the keypad 12 via a keyboard adapter (not shown) where appropriate and to display 14 via a display adapter (not shown) where appropriate and is a communication interface or transceiver. 16, for example connected to a radio communication interface that includes a radio frequency (RF) circuit. This radio frequency circuit may be incorporated into an integrated circuit 40 including the processor 10 or may be separate. This RF circuit 16 is connected to the antenna 18.

【0126】

Manufacture of the data processing device 100 requires a number of steps to implant various amounts of impurities into the semiconductor substrate and diffuse the impurities to a selected depth within the substrate to form a transistor device. A mask is formed to control the placement of impurities. A large number of films of conductive and insulating materials are deposited and these films are etched to interconnect the various devices. These steps are performed in a clean room environment.

【0127】

Most of the cost of manufacturing data processing devices is related to inspection. In the form of a wafer, the individual devices are biased into working conditions and probed for basic working functions. The wafers are then separated into bare dies or individual dies for sale in a packaged state. After packaging, the finished parts are biased to working condition and undergo an inspection for working function.

【0128】

Another embodiment of the novel features of the invention can include other circuits combined with the circuits disclosed herein to reduce the total gate count of the combined functions. Those skilled in the art will know the techniques for minimizing gates and will not provide details of such embodiments herein.

【0129】

Therefore, a processor that is a programmable digital signal processor (DSP) that increases the code density and facilitates programming has been described. Architecture and instruction sets have been optimized to reduce power consumption and increase the efficiency of executing DSP algorithms, such as algorithms for pure control work as well as radiotelephones. This processor includes an instruction buffer unit and a data calculation unit for executing instructions decrypted by the instruction buffer unit. Instructions can be executed in parallel in response to implied parallelism or in response to user-defined parallelism.

【0130】

Pipeline conflicts are detected when they occur, and many of the detected conflicts are resolved by using a set of shadow registers to give a delayed write signal to the conflicting target registers. Reads to the selected shadow register can be redirected to the resolved conflicts induced by the delayed write.

【0131】

Another embodiment may have three or more pipelines interlocked by the detection of a stop state. Another embodiment may have more or fewer target registers protected by a set of shadow registers. Another embodiment may use another technique for detecting pipeline conflicts. However, a feature of the present invention allows pipeline conflicts to be detected and shadow registers to be used to eliminate conflicts.

【0132】

In another embodiment, read redirection can be omitted. The terms "applied," "connected," and "connected" used in the present invention mean an electrical connection, including the case where another element is present in the electrical connection path.

【0133】

Although the present invention has been described above with reference to the illustrated examples, this description should not be construed in a limited sense. Various other embodiments of the present invention will become apparent to those skilled in the art with reference to this description. Accordingly, the claims cover all such variations of the examples that fall within the true scope and gist of the invention.

【0134】

With respect to the above description, the following sections will be further disclosed. (1) A digital system having a processor pipeline having a plurality of pipeline stages, a plurality of resources, and a processor having a pipeline protection mechanism, wherein the pipeline protection mechanism is a set of shadow registers. And an interlock circuit for predicting access conflicts for each protected resource of the plurality of resources during the pipeline stage, and the output of the interlock detection circuit can be controlled by a set of shadow registers. Connected to, data items from the first pipeline stage can be redirected to selected shadow registers in response to expected access conflicts by the interlock circuit, thus stopping the processor pipeline. A digital system in which the set of shadow registers is interconnected with the processor pipeline so as to resolve resource access conflicts without the need for.

【0135】

(2) The interlock circuit is connected to an interlock detection circuit capable of anticipating access conflicts for all of the protected resources and operating to form a stop vector signal to receive the stop vector signal. A hold and stop vector filtering circuit that is capable of responding to the stop vector signal and operating to select an available shadow register from the shadow register set, and a controllably connected output to the shadow register set. The processing engine according to paragraph 1, comprising a shadow management circuit having a signal and connected to a hold and stop vector filtering circuit.

【0136】

(3) The processing engine according to paragraph 1, wherein the interlock circuit includes an arbitration circuit for each protected resource so that each arbitration circuit can be defined as a particular form of a single comprehensive arbitration function. ..

【0137】

(4) The first paragraph, wherein the pipeline control logic for controlling the stage of the pipeline is provided, and the pipeline control logic is connected so as to receive a stop control signal output from the interlock circuit. Processing engine.

【0138】

(5) The processing engine according to paragraph 1, wherein at least one resource is selected from a group of registers, one register, a field of registers, and a subfield of registers.

【0139】

(6) The interlock circuit comprises a stop vector filter, the stop vector filter having a plurality of selection filter stages serially connected so that each of the selection filter stages is associated with a corresponding protected resource. The processing engine described in item 1.

【0140】

(7) The set of shadow registers interconnected to a processor pipeline having a multiplexing circuit capable of redirecting reads from protected resources to selected shadow registers, item 1. Processing engine.

【0141】

(8) The process of paragraph 2, further comprising an arbitration circuit for each protected resource so that the interlock circuit can define each arbitration circuit as a particular form of a single comprehensive arbitration function. engine.

【0142】

(9) The processing engine according to paragraph 8, wherein the stop vector filter has a plurality of selection filter stages in which the stop vector filters are serially connected so that each of the selection filter stages is associated with a corresponding protected resource.

【0143】

(10) Further comprising a pipeline control logic for controlling the stages of the pipeline, wherein the pipeline control logic is connected to receive a stop control signal output from the interlock circuit, item 9. Described processing engine.

【0144】

(11) The set of shadow registers interconnected to a processor pipeline having a multiplexing circuit capable of redirecting reads from protected resources to selected shadow registers, item 10. Processing engine.

【0145】

(12) The processing engine according to paragraph 11, wherein at least one resource is selected from a group of registers, one register, a field of registers, and a subfield of registers.

【0146】

(13) An integrated keyboard connected to the processor via a keyboard adapter, a display connected to the processor via a display adapter, a radio frequency (RF) circuit connected to the processor, and the RF. The digital system according to paragraph 1, which is a cellular telephone further equipped with an antenna connected to a circuit.

【0147】

(14) A method in which the processor protects a pipeline within a processor engine, including a processor pipeline with multiple pipeline stages and multiple resources, with access conflicts between the pipeline stages for each resource. As expected, the process of arbitrating separately for each protected resource and the expected access conflict to resolve the resource access conflict without disrupting the processor pipeline. A method of protecting a pipeline, including the process of redirecting data items from the first pipeline stage to a selected shadow register in response to.

【0148】

(15) If shadow registers are not available to resolve expected access contention, select pipeline stages depending on the outcome of the arbitration for each resource to prevent resource access contention. 14. The method of protecting a pipeline, which further comprises a step of stopping the pipeline.

【0149】

(16) A processing engine having a processor pipeline 820 with a large number of pipeline stages, a large number of resources, and a pipeline protection mechanism. The pipeline protection mechanism includes an interlock detection circuit 1402 for each protection resource to anticipate and / or detect access conflicts for protection resources during the pipeline phase. The output end of the interlock detection circuit is connected to the hold and filtering circuit 1404 to select a shadow register. When shadow registers are available, the shadow management circuit 1406 generates control signals 1410, 1412 corresponding to a set of shadow registers 1400. Resolve pipeline conflicts by writing to the selected registers. In a later cycle, the pipeline is restored by lazy writing to the corresponding target register. The merge circuit 1440 merges the unresolvable conflicts to form a stop control signal to control the selective stop of the pipeline to prevent resource access conflicts. The resource may be, for example, a register in the register file 832 or a part (field) in the register. By providing an arbitration logic within the interlock detection circuit for each resource, the embodiments of the present invention can distribute the control logic required to anticipate potential resource access contention, making the pipeline selective. Can be stopped to prevent the actual conflict from occurring.

【0150】

This application is filed in Europe on March 8, 1999, European Patent Application No. SN99400551.0 (TI-28234EU), and filed in Europe on October 6, 1998, European Patent Application No. SN98402466.1 (TI). -27681EU), claiming priority under European Patent Application No. SN98402455.4 (TI-28433EU) filed in Europe on October 6, 1998.

[Simple explanation of drawings]

[Figure 1]

It is block schematic of the processor which concerns on one Embodiment of this invention.

[Figure 2]

It is a schematic diagram of the core of the processor of FIG.

[Fig. 3]

FIG. 1 is a more detailed block schematic of the various execution units of the processor core of FIG.

[Fig. 4]

It is a schematic diagram of the instruction buffer queue and the instruction decoder controller of the processor of FIG.

[Fig. 5]

FIG. 6 is a schematic representation of a processor core to illustrate the operation of a processor pipeline.

[Fig. 6]

It is a block diagram of a processor which shows the memory interconnected to a memory management unit.

[Fig. 7]

Shows a unified structure of processor programs and data memory space.

[Fig. 8]

An example of a read hazard after writing is shown, of which FIG. 8A shows one example and FIG. 8B shows another example.

[Fig. 9]

An example of the writing hazard after writing is shown.

[Fig. 10]

An example of a write hazard after reading is shown, of which FIG. 10A shows one example and FIG. 10B shows another example.

[Fig. 11]

Shows possible conflicts at various pipeline stages.

[Fig. 12]

The process guidance for defining a comprehensive arbitrary function is shown.

[Fig. 13]

It is a schematic diagram of comprehensive arbitration logic.

[Fig. 14]

It is a block diagram which shows the shadow register and the control circuit for delayed writing which concerns on one Embodiment of this invention.

[Fig. 15]

FIG. 4 is a schematic diagram of an arbitration circuit for delayed writing in FIG.

[Fig. 16]

It is a block schematic of the structural example for the interlock control mechanism using the arbitration circuit of FIG.

[Fig. 17]

FIG. 4 is a block diagram of a hold and filter circuit for the shadow register of FIG.

[Fig. 18]

FIG. 6 is a schematic for a look-ahead structure for the filter circuit of FIG.

[Fig. 19]

FIG. 5 is a schematic representation of a multiplexer circuit for selecting a stop length for the filter circuit of FIG.

[Fig. 20]

It is a block diagram of the shadow management circuit for the shadow register of FIG.

[Fig. 21]

It is a block diagram of the shadow management circuit of FIG. 20 which shows the state machine control circuit.

[Fig. 22]

It is a schematic diagram of the circuit for routing data from a shadow register to a target register in the register file of FIG.

[Fig. 23]

It is a state diagram which shows the operation of the state machine of FIG.

[Fig. 24]

It is a timing diagram showing one cycle of write delay, of which FIG. 24A is a timing diagram showing one cycle of write delay and the redirection of the resulting read from the shadow register, and FIG. 24B requires only one shadow register. It is a timing diagram which shows the write delay of one cycle in the loop which does not.

[Fig. 25]

A timing diagram showing a two-cycle write delay, of which FIG. 25A is a timing diagram showing a two-cycle write delay and the resulting read redirection from a shadow register that eliminates potential conflicts, FIG. 25B. Is a timing diagram showing two cycles of write delay in a loop that requires only two shadow registers.

[Fig. 26]

A timing diagram showing a three-cycle write delay, of which FIG. 26A is a timing diagram showing a three-cycle write delay and the resulting read redirection from a shadow register that eliminates potential conflicts, FIG. 26B. Is a timing diagram showing a write delay of 3 cycles in a loop that requires only 3 shadow registers.

[Fig. 27]

The architecture of the dual pipe arithmetic logic unit of the processing engine which carried out one Example of this invention is shown.

[Fig. 28]

It is a spectrum diagram which shows the stop state in the typical application which uses the circuit of FIG.

[Fig. 29]

It is a distribution diagram which shows the stop state which can be removed from the circuit of FIG. 28 using the circuit of FIG.

[Fig. 30]

This is an integrated circuit containing the processor shown in Fig. 1.

[Fig. 31]

This is an example of a mobile communication device having a built-in processor shown in FIG.

[Explanation of symbols]

820 processor pipeline 832 register file 1400 shadow register 1402 Interlock detection circuit 1404 Hold and filtering circuit 1406 Shadow management circuit 1410, 1412 control signal 1440 merge circuit