Circular buffer management

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a patrol buffer, a patrol buffer management, and a processing engine that manages the patrol buffer.

【0002】

[Conventional technology]

Circular addressing of memory is useful in processor design to implement many different types of processes, such as processes involving Viterbi, backtracking, deinterleaving and vocabulary computation.

【0003】

It has been proposed to implement a cyclic buffer in random access memory, which is defined with a defined buffer size (BK) aligned to a given memory boundary. For example, it has been proposed to align cycle buffers of size R at the memory boundary represented by the least significant N bits of an address that is 0. The cyclic buffer is then started with an index of 0 relative to the boundary. Where N is 2^NThe minimum value such that> R. For example, the cyclic buffer can be aligned on a 64-word boundary. The patrol buffer manager uses pointers to physical memory space to control access to the patrol buffer. The requirement to align cyclic buffers on memory boundaries can mean inefficient use of space. For example, if a 38-word buffer must be aligned on a 64-word boundary and multiple cyclic buffers are kept in memory, the memory is rapidly fragmented and 26 words are between adjacent circular buffers. Not used in. Also, any alignment constraints are not preferred for efficient control of the cyclic buffer under a programming language.

【0004】

[Problems to be Solved by the Invention]

Therefore, an object of the present invention is to provide a cyclic buffer management without the drawbacks of the prior art.

【0005】

[Means for solving problems]

According to the first aspect of the present invention, a data processing device that supports a cyclic buffer is provided. This device includes an address storage device that holds a virtual buffer index, an offset storage device that holds an offset address, and a buffer size storage device that holds a buffer size. The cyclic buffer management logic applies a modifier to the virtual buffer index held in the address storage to retrieve the changed virtual buffer index and the changed buffer offset held in the offset storage. It is configured to apply to the buffer index and act to pull out the physical address that addresses the cyclic buffer.

【0006】

By utilizing virtual addressing to the buffer index for cyclic buffer management, one of the more cyclic buffers can be placed adjacent to each other or to other data in memory, avoiding memory fragmentation. Memory resources can be used efficiently. The buffer index forms a pointer for the cyclic buffer. Modifiers can be user-defined or automatically generated in response to parameters such as buffer size.

【0007】

The use of virtual addressing also provides compatibility with existing software designed for devices that align the cyclic buffer to memory boundaries. Virtual address changes are transparent to pre-existing software.

【0008】

The use of virtual addressing also facilitates the implementation of cyclic buffers that use programming languages that do not support memory alignment constraints, such as the "C" programming language.

【0009】

The buffer offset can define the buffer start address that can be held in the offset register. You can then add this to the modified virtual buffer index to retrieve the physical cyclic buffer address. Original and modified virtual buffer addresses can be kept in the address register.

【0010】

The address storage device can be formed by a predetermined number of low-order bits of the address register. The modified virtual buffer index can also be held in a predetermined number of low-order bits of the address register. The high-order bits in the address register (typically the rest of the address register) can define the buffer start address, so the combination of the high-order and low-order bits in the address register defines the physical address.

【0011】

A physical address that addresses the cyclic buffer can be defined by adding the buffer offset that can be held in the offset register to the physical address in the address register. The device can include random access memory holding a patrol buffer.

【0012】

Instead of implementing a cyclic buffer in memory, one embodiment of the invention can provide bit array operation, which can be held in memory or in one or more processor registers.

【0013】

A pointer configuration register can be provided to selectively set the cyclic buffer mode for the address register. An exception mode qualifier can be provided to dynamically overwrite the cyclic buffer mode settings. The qualifiers can be used dynamically to define whether the address storage can operate in cyclic or linear addressing mode.

【0014】

In the cyclic buffer address calculation mechanism, the carry signal from the first and second addition / subtraction calculations is used to calculate the sign value that determines the selection of one result of the addition / subtraction operation for calculating the cyclic buffer address. Will be done. By using the carry signal in this way, the need for an initial masking step is avoided and, as a result, the speed path of the device is improved.

【0015】

This device can be in the form of a digital signal processing device that provides a digital signal processor (DSP) and can be implemented in one or more integrated circuits. The random access memory can be inside or outside the integrated circuit.

【0016】

An embodiment of the present invention is applied to telecommunications equipment, where the cyclic buffer function is particularly utilized in processes including, for example, Viterbi, backtracking, deinterleaving and vocoder calculations.

【0017】

According to another aspect of the present invention, there is provided a method of managing cyclic buffer addressing within a data processing apparatus. This method includes a step to pull out the virtual buffer index, a step to change the virtual buffer index to pull out the changed virtual buffer index, and a step to add the buffer offset to the changed virtual buffer index to pull out the cyclic buffer address. , Including.

【0018】

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention is particularly applied to digital signal processors (DSPs) implemented in application specific integrated circuits (ASICs), for example, but is also applied to other types of processing engines.

【0019】

FIG. 1 is a block diagram of a microprocessor 10 having an embodiment of the present invention. The microprocessor 10 is a digital signal processor (DSP). For clarity, FIG. 1 shows only the parts of the microprocessor 10 that are relevant to understanding an embodiment of the present invention. The details of the general structure of the DSP are well known and can be easily found elsewhere. For example, US Pat. No. 5,072,418 of Frederick Bootud et al. Describes the DSP in detail and is incorporated herein by reference. U.S. Pat. No. 5,329,471 of Gary Suoboda et al. Describes DSP testing and emulation methods in detail and is incorporated herein by reference. Details of a portion of the microprocessor 10 relating to an embodiment of the present invention will be described in sufficient detail below so that those skilled in the art of microprocessors can manufacture and use the present invention.

【0020】

Examples of several systems that can benefit from aspects of the invention are in US Pat. No. 5,072,418, which is incorporated herein by reference in reference herein, in particular US Pat. No. 5,072,418, FIGS. 2-18. Are listed. A microprocessor incorporating an aspect of the invention that improves performance or reduces cost can be used to further improve the system described in US Pat. No. 5,072,418. Such systems include, but are not limited to, industrial process control, automotive systems, motor controls, robot control systems, satellite telecommunications systems, echo canceling systems, modems, video imaging systems, voice recognition systems and encrypted vocabulary-modems. Including system etc.

【0021】

A description of the various architectural features and complete instruction set of the microprocessor in Figure 1 is set forth in Patent Application No. 98402455.4 (TI-28433) by the same assignee, which is incorporated herein by reference. To do.

【0022】

Next, the basic architecture of an example of the processor according to the present invention will be described. FIG. 1 is an overall schematic representation of a processor 10 forming one typical embodiment of the present invention. Processor 10 includes a processing engine 100 and a processor backplane 20. In this embodiment, the processor is a digital signal processor 10 realized in an application specific integrated circuit (ASIC).

【0023】

As shown in FIG. 1, the processing engine 100 forms a central processing unit (CPU) having a processing core 102 and a memory interface, that is, a management unit 104, that interfaces the processing core 102 with a memory unit outside the processing core 102.

【0024】

The processor backplane 20 includes a backplane bus 22, to which the memory management unit 104 of the processing engine is connected. An instruction cache memory 24, a peripheral device 26, and an external interface 28 are also connected to the backplane bus 22.

【0025】

In other embodiments, it will be found that different configurations and / or different techniques can be used to achieve the present invention. For example, the processing engine 100 can form the processor 10, and the processor backplane 20 is separated from it. The processing engine 100 can be, for example, a DSP mounted on the backplane bus 22, independent of the backplane 20 supporting the peripherals and external interfaces. The processing engine 100 can be, for example, a microprocessor instead of a DSP, and can be realized by a technology other than the ASIC technology. A processing engine or a processor including a processing engine can be implemented in one or more integrated circuits.

【0026】

FIG. 2 shows the basic structure of an embodiment of the processing core 102. As can be seen from the figure, the processing core 102 contains four elements: an instruction buffer unit (I unit) 106 and three execution units. The execution unit is a data calculation that controls and monitors the program flow by executing the instructions decoded from the program flow unit (P unit) 108, the address data flow unit (A unit) 110, and the instruction buffer unit (I unit) 106. It is a unit (D unit) 112.

【0027】

FIG. 3 shows in detail the P unit 108, A unit 110 and D unit 112 of the processing core 102, and shows the bus structure connecting various elements of the processing core 102. The P unit 108 includes, for example, a loop control circuit, a GoTo / branch control circuit, and various registers that control and monitor the program flow, such as repeat counter registers and interrupt masks, flags or vector registers. The P unit 108 is coupled to a general-purpose data write bus (EB, FB) 130, 132, a data read bus (CB, DB) 134, 136, and an address constant bus (KAB) 142. In addition, P unit 108 is coupled to subunits within A unit 110 and D unit 112 via various buses labeled CSR, ACB and RGD.

【0028】

As shown in FIG. 3, in this embodiment, the A unit 110 includes a register file 30, a data address generation subunit (DAGEN) 32, and an arithmetic and logical arithmetic unit (ALU) 34. The A unit register file 30 contains various registers, including 16-bit pointer registers (AR0, ..., AR7) and data registers (DR0, ...) that can be used not only for address generation but also for data flow. , DR3). In addition, the register file contains a 16-bit cyclic buffer register and a 7-bit data page register. In addition to the general-purpose buses (EB, FB, CB, DB) 130,132,134,136, the data constant bus 140 and the address constant bus 142 are combined in the A unit register file 30. The A unit register file 30 is coupled to the A unit DAGEN unit 32 by unidirectional buses 144 and 146, which operate in opposite directions, respectively. The DAGEN unit 32 includes 16-bit X / Y registers and, for example, coefficients and stack pointer registers that control and monitor address generation within the processing engine 100.

【0029】

A unit 110 includes ALU34, which includes shifter functions as well as functions typically associated with ALUs such as addition, subtraction and AND, OR and XOR logical operators. ALU34 is also coupled to the general purpose bus (EB, DB) 130,136 and the instruction constant data bus (KDB) 140. The A unit ALU is coupled to the P unit 108 by the PDA bus that receives the register contents from the P unit 108 register file. The ALU34 is also coupled to the A unit register file 30 by the bus RGA, RGB that receives the address and data register contents and the bus RGD that transfers to the address and data register of the register file 30.

【0030】

As can be seen from the figure, the D unit 112 contains a D unit register file 36, a D unit ALU38, a D unit shifter 40, and two multiplication and accumulation units (MAC1, MAC2) 42,44. The D unit register file 36, the D unit ALU38, and the D unit shifter 40 are connected to the bus (EB, FB, CB, DB, KDB) 130,132,134,136,140, and the MAC units 42,44 are connected to the bus (CB, DB, KDB). ) 134,136,140 and the data read bus (BB) 144. The D unit register file 36 contains a 40-bit accumulator (AC0, ..., AC3) and a 16-bit transition register. In addition, the D unit 112 can use the 16-bit pointer and data register of the A unit 110 as a source, and can use a destination register in addition to the 40-bit accumulator. The D unit register file 36 is the D unit ALU38 and MAC1 & 2 via the accumulator write bus (ACW0, ACW1) 146,148. Data is received from 42,44 and from the D unit shifter 40 via the accumulator light bus (ACW1) 148. Data is read from the D unit register file accumulator to the D unit ALU38, D unit shifter 40 and MAC1 & 2 42,44 via the accumulator read bus (ACR0, ACR1) 150,152. The D-unit ALU38 and D-unit shifter 40 are also coupled to the subunits of A-unit 108 via various buses labeled EFC, DRB, DR2 and ACB.

【0031】

Referring to FIG. 4, an instruction buffer unit 106 containing a 32-word instruction buffer queue (IBQ) 502 is shown. The IBQ502 contains a 32 × 16-bit register 504 that is logically divided into 8-bit bytes 506. Instructions arrive at the IBQ 502 via the 32-bit program bus (PB) 122. The instruction is fetched in a 32-bit cycle at the position indicated by the local write program counter (LWPC) 532. The LWPC532 is contained in a register located in P unit 108. The P unit 108 also includes a local read program counter (LRPC) 536 register, a write program counter (WPC) 530 register, and a read program counter (RPC) 534 register. The LRPC536 indicates the position of the next one or more instructions loaded in the instruction decoders 512,514 within the IBQ502. That is, the LRPC534 indicates the position of the instruction currently dispatched to the decoders 512,514 within the IBQ502. The WPC points to the address in program memory at the beginning of the next 4 bytes of the instruction code for the pipeline. For each fetch into the IBQ, the next 4 bytes from program memory are fetched regardless of instruction boundaries. The RPC534 indicates the address in the program memory of the instruction currently dispatched to the decoders 512,514.

【0032】

Instructions are formed into 48-bit words and loaded into the instruction decoder 512,514 by the 48-bit bus 516 via multiplexers 520,521. Those skilled in the art will appreciate that instructions can be formed in words other than 48 bits, and that the invention is not limited to the particular embodiment described above.

【0033】

Bus 516 can load up to two instructions, one per decoder, during any one instruction cycle. The instruction combination can be any combination of 8,16,24,32,40 and 48-bit formats that fit across both ends of the 48-bit bus. If only one instruction can be loaded in one cycle, decoders 1,512 are loaded in preference to decoders 2,514. Each instruction is then transferred to each functional unit to execute them and to access the data on which the instruction or operation should be performed. Instructions are aligned on a byte boundary before being passed through the instruction decoder. Alignment is based on the format extracted for the previous instruction during its decoding. The multiplexing associated with the alignment of instructions with byte boundaries is performed by multiplexers 520,521.

【0034】

Processor core 102 executes instructions through a 7-stage pipeline, each stage of which is described with reference to FIG.

【0035】

The first stage of the pipeline is PRE-FETCH (P0) stage 202, during which the next program memory is expressed by asserting an address on the memory interface or address bus (PAB) 118 of the memory management unit 104. The position is addressed.

【0036】

In the next stage, FETCH (P1) stage 204, the program memory is read and the I unit 106 is filled from the memory management unit 104 via the PB bus 122.

【0037】

The PRE-FETCH and FETCH stages remain in that the pipeline can be interrupted during the PRE-FETCH and FETCH stages to interrupt the sequential program flow and direct other instructions in program memory, such as branch instructions. Independent of the pipeline stage.

【0038】

The next instruction in the instruction buffer is then dispatched to decoder 512 or multiple decoders 514 in third stage DECODE (P2) 206, where the instruction is decoded and the execution unit executing that instruction, eg Dispatched to P unit 108, A unit 110 or D unit 112. Decryption stage 206 includes decoding at least a portion of an instruction that includes a first part indicating the class of the instruction, a second part indicating the format of the instruction, and a third part indicating the addressing mode for the instruction. I'm out.

【0039】

The next stage is ADDRESS (P3) stage 208, where the address of the data used in the instruction is calculated, or a new program address is calculated if the instruction requires a program branch or jump. To. Each calculation is performed on A unit 110 or P unit 108, respectively.

【0040】

In ACCESS (P4) stage 210, after the address of the read operand is output, the memory operand whose address is generated by the DAGEN X operator that has the Xmem indirect address specification mode is the indirect address specified X memory (Xmem). Read from.

【0041】

The next stage in the pipeline is READ (P5) stage 212, where the memory where the address is generated is within the DAGEN Y operator with Ymem indirect addressing mode or within the DAGEN C operator with coefficient address mode. The operand is read. The address of the memory location where the instruction result is written is output.

【0042】

In the case of dual access, the read operand can be generated in the Y path and the write operand can be generated in the X path.

【0043】

Finally, there is an execution EXEC (P6) stage 214 in which the instruction is executed within A unit 110 or D unit 112. The result is then stored in a data register or accumulator or written to memory for read / modify / write or store instructions. In addition, shift operations are performed on the data in the accumulator during the EXEC stage.

【0044】

Next, the basic principle of operation of the pipeline processor will be described with reference to FIG. As can be seen from FIG. 6, for the first instruction 302, the continuous pipeline stage has a period T.₁~ T₇It is done over. Each period is a clock cycle with respect to the processor machine clock. The second instruction 304 has a period T because the previous instruction has moved to the next pipeline stage.₂You can enter the pipeline with. In response to the third instruction 306, the PRE-FETCH stage 202 has a period T.₃It is done in. As can be seen from Figure 6, a total of 7 instructions can be processed simultaneously for a 7-stage pipeline. For all seven instructions 302 to 314, Figure 6 shows the period T.₇Indicates that all of them are being processed. Such a structure adds a form of parallelism to the processing of instructions.

【0045】

As shown in FIG. 7, this embodiment of the present invention includes a memory management unit 104 coupled to an external memory unit (not shown) via a 24-bit address bus 114 and a bidirectional 16-bit data bus 116. .. Further, the memory management unit 104 is coupled to the program storage memory (not shown) via the 24-bit address bus 118 and the 32-bit bidirectional data bus 120. The memory management unit 104 is also coupled to the I unit 106 of the machine processor core 102 via a 32-bit program read bus (PB) 122. The P unit 108, A unit 110 and D unit 112 are coupled to the memory management unit 104 via the data read and data write buses and the corresponding address buses. The P unit 108 is further coupled to the program address bus 128.

【0046】

More specifically, the P unit 108 is connected to the memory management unit 104 by a 24-bit program address bus 128 and two 16-bit data write buses (EB, FB) 130,132 and two 16-bit data read buses (CB, DB) 134,136. It is combined. Unit 110 has two 24-bit data write address buses (EAB, FAB) 160,162, two 16-bit data write address buses (EB, FB) 130,132 and three data read address buses (BAB, CAB, DAB) 164,166,168 and 2. It is coupled to the memory management unit 104 via two 16-bit data read buses (CB, DB) 134,136. The D unit 112 is coupled to the memory management unit 104 via two data write buses (EB, FB) 130, 132 and three data read buses (BB, CB, DB) 144, 134, 136.

【0047】

FIG. 7 shows, for example, the passage of an instruction from I unit 106 to P unit 108, which transfers a branch instruction, with reference to reference numeral 124. Further, FIG. 7 shows the passage of data from the I unit 106 to the A unit 110 and the D unit 112 with reference numerals 126 and 128, respectively.

【0048】

In this embodiment of the invention, the processing engine 100 responds to machine instructions in several formats. Examples of such instructions in various formats are shown below.

【0049】

8-bit instruction: It represents an 8-bit instruction, such as a memory-mapped qualifier (MMAP ()) or a readport qualifier (readport ()). Such modifiers simply include 8-bit manipulation codes (). In such cases, parallelism is implied.

【0050】

16-bit instructions: E FSSS FDDD This is a 16-bit instruction, for example, an instruction in which the contents of a destination register (for example, dst) are the sum of the contents before that register (dst) and the contents of the source register (src). [Number 1]

<img file="JP2000200212A_D0001.tif" />An example is shown.

【0051】

Such an instruction is a 7-bit operation code () having a 1-bit parallel enable field (E), a 4-bit source register identifier (FSSS), and a 4-bit destination register identifier (FDDD). is there.

【0052】

16-bit instructions: FDDD PPPM MMMI This means that, for example, the contents of the destination register (eg, dst) become the contents of the memory location (Smem), that is, [Number 2]

<img file="JP2000200212A_D0002.tif" />Another example of a 16-bit instruction.

【0053】

Such instructions include a 4-bit manipulation code (), a 4-bit destination register identifier (FDDD), a 3-bit pointer address (PPP), a 4-bit address modifier (MMM), and a direct / indirect address indicator. (I) and are included.

【0054】

24-bit instructions: E LLLL LLLL oCCC CCCC This represents a 24-bit instruction, such as a conditional branch instruction and the offset (L8) when the condition is met, i.e. [Number 3]

<img file="JP2000200212A_D0003.tif" />An example is shown.

【0055】

Such an instruction is a 7-bit manipulation code () with a 1-bit parallel enable field (E), an 8-bit branch offset (LLLL LLLL), a 1-bit operation sign extension (o), and a 7-bit condition field (CCC CCCC). ) is included.

【0056】

24-bit instruction: PPPM MMMI SSDD ooU% This is another example of a 24-bit instruction, for example the contents of a accumulator (AC)._y) Is the contents of another accumulator (AC_x) And the sum of the squares of the contents of the memory position (with voluntary rounding), and the contents of the data register (DR3) are the contents of the voluntary memory position. [Number 4]

<img file="JP2000200212A_D0004.tif" />Is another example of.

【0057】

Such instructions include an 8-bit manipulation code (), a 3-bit pointer address (PPP), a 4-bit address modifier (MMM), and a 1-bit direct / indirect address indicator field (I). And 2-bit source accumulator identifier (SS), 2-bit destination accumulator identifier (DD), 2-bit operation code extension (oo), update condition field (u), and 1-bit rounding option field (%). Includes.

【0058】

32-bit instructions: PPPM MMMI KKKK KKKKKKKK KKKK This is a 32-bit instruction, for example, an instruction in which the contents of the test register (TC1) are set to 1 or 0 depending on the sign comparison with a fixed value (K16) of the memory position (Smem), that is, [Number 5]

<img file="JP2000200212A_D0005.tif" />This is an example.

【0059】

Such instructions include an 8-bit manipulation code (), a 3-bit pointer address (PPP), a 4-bit address modifier (MMM), and a 1-bit direct / indirect address indicator field (I). And a 16-bit constant field (KKKK KKKK KKKK KKKK).

【0060】

In the following description, the cyclic buffer management will be specifically described. The cyclic buffer is applied, for example, to Viterbi, backtracking, deinterleaving and vocoder calculations. Such calculations are required, for example, in telecommunications systems .

【0061】

In the conventional system, the cyclic buffer is realized by aligning the buffers on a fixed memory boundary. For example, it has been proposed to align the size R cyclic buffer with a memory boundary represented by the least significant N bits of an address of 0. The cyclic buffer then starts with an index of 0 relative to the boundary. Where N is 2^N&gt; R is the minimum value. For example, the cyclic buffer can be aligned on a 64-word boundary. As a result, the cyclic buffer does not completely occupy memory space, resulting in rapid fragmentation and / or inefficient use of system memory. This is shown in FIG. 8, in which the first, second, and third cyclic buffers CB1, CB2, and CB3, each containing N words, are arranged on the K word memory boundary. Where K&gt; N. It will be easy to see that the unused memory UM is left between the patrol buffers. The present invention attempts to solve this inefficient use of memory.

【0062】

FIG. 9 is a schematic block diagram of the aspect of the processor of FIG. 1 suitable for understanding the present invention. Embodiments of the processor of FIG. 1, which are not suitable for understanding the present invention, can be realized by those skilled in the art by conventional methods and are not shown in FIG. 9 for clarity.

【0063】

In one embodiment of the invention, the cyclic buffer does not need to be aligned to any particular fixed memory boundary and can be offset from the memory boundary. In one embodiment of the invention, this can be achieved while maintaining compatibility with conventional devices that require the cyclic buffer to be located on a fixed memory boundary. This means that cyclic buffer management must be transparent to traditional software applications. Therefore, hardware support for cyclic buffer realignment is provided.

【0064】

FIG. 9 shows the cyclic buffer management unit 802, which can form part of the DAGEN unit described above. The various registers used for cyclic buffer management are also illustrated. These include a pointer configuration register (ST2), an address register ARx (AR0 to AR7), a coefficient data pointer (CDP), an index / offset register DR0, DR1, a buffer offset register BOFxx, and a buffer size register BKxx. Is included. The patrol buffer management unit 802 manages the patrol buffer addressing in response to the values stored in various registers. The various data items utilized by the patrol buffer management unit are stored in registers in this example, but it can be seen that at least some or perhaps all of these data items can be stored in registers configured in random access memory. Will.

【0065】

The pointer configuration register ST2 contains a qualifier that indicates whether the associated address register can operate in cyclic addressing mode or linear addressing mode. The provision of registers avoids the need to specify for each instruction whether a cyclic buffer or linear operation is currently in use. The appropriate bits in the pointer configuration register ST2 can be set when entering the cyclic addressing mode and can be reset when the cyclic addressing mode ends. However, in order to avoid the need to redefine the qualifier for the pointer configuration register ST2 for the linear buffer that is already set for the cyclic buffer, an exception can be provided that ignores the state of the pointer configuration register. Therefore, an exception mode qualifier can be provided to dynamically override the cyclic buffer mode setting. The qualifier can also be used dynamically to define whether the address storage can operate in cyclic or linear addressing mode.

【0066】

The index / offset registers DR0 and DR1 give indexes to the eight address registers ARx. This is likened to a traditional processing engine given only one address register (AR0). The index can also be given in the form of a user-defined constant or ± 1 for 1-word access or ± 2 for 2-word access.

【0067】

The buffer offset register acts as a qualifier for the address register, so that the address register can be accessed by conventional software without knowledge of the offset provided in one embodiment of the invention. As can be seen from Table 1 below, the buffer offset register BOFxx and the buffer size register BKx are shared between the address registers. For example, as shown in Table 1, the buffer offset register BOF0 is shared between the address registers AR0 and AR1, the BOF23 is shared between the address registers AR2 and AR3, and so on. The buffer size register defines the size of the cyclic buffer. As you can see from Table 1, the buffer size register is shared. For example, the buffer size register BK03 is shared among the address registers AR0, AR1, AR2, and AR3.

【0068】

[table 1]

<img file="JP2000200212A_D0006.tif" />【0069】

The cyclic buffer size is defined by the buffer size register associated with the address register pointer. In the example above, three buffer sizes are supported (in another example, different buffer sizes can be supported). Therefore, the buffer size register can provide cyclic addressing parameters for the first group of address registers, the second group of address registers, and the coefficient data pointer register, respectively. Two consecutive address registers can share the same buffer offset register. However, each pointer has its own cyclic / linear configuration bits in the pointer configuration register (ST2). The cyclic addressing is specified only when the associated ST2 configuration bit is set or the memory instruction is executed in parallel with the cyclic byte qualifier. There are two basic operation modes.

【0070】

In the first mode, the address register points to a virtual buffer with a start address that matches the K-bit boundary. The virtual buffer start address is defined by ARx highfield (field width is defined by buffer size) and ARx lowfield clear. Address calculation is performed on the virtual address according to the modifier. Address conversion from virtual to physical is performed by adding the buffer address offset stored in the associated buffer offset register BOFxx to the virtual address. Offsets are only added if cyclic changes are selected.

【0071】

In the second mode, the buffer start address is stored in the BOFxx register. The index is stored in the ARx register and calculated according to the modifier. Address translation from virtual to physical is performed by adding an index to the buffer start address stored in the associated BOFxx register. The buffer start address is only added if cyclic change is selected.

【0072】

FIG. 10 is a schematic diagram of the generation of the cyclic buffer address. This is done within A unit DAGEN32. Here, the signed calculation 702 is performed based on the buffer size from the BKxx register and, for example, the index value from the DR0 / DR1 register. All carry outputs from the first and second add / subtract operations 704,706 are fed to sign calculation 702. This allows the sign calculation to determine whether to capture the output from the first or second addition / subtraction operations 704,706, as described below. By using the carry output, the initial masking step (which would otherwise be required before the stage shown in FIG. 10) can be omitted.

【0073】

The first addition / subtraction operation 704 is performed based on the pointer from the ARx register and the index value from, for example, the DR0 / DR1 register. A second addition / subtraction operation 706 is performed based on the output of the first increment / decrement operation 704 and the buffer size from the BKxx register. The output of sign calculation 702 is used to control the modulo selection of the output of the first and second addition / subtraction operations 704,706. Therefore, the carry signals from the first and second addition / subtraction calculations are used to calculate the sign value to determine the choice of one result of the addition / subtraction operation for the cyclic buffer address calculation.

【0074】

The masking operation 710 is then performed under the control of the signed calculation 702, based on the output from the modulo selection 708 and the pointer from the ARx register. The back and forth changes from the mask operation are returned to the register file. The output of the mask operation is also used by the selection operation 712. There, the selection is made directly from the memory access offset (dma) value. The selection is also made between the stack pointer / data page pointer (SP / DP) value and the buffer offset from the BOFxx register 714. The outputs of select operations 712,714 are ANDed at 716 to feed the signal to the memory address bus interface.

【0075】

Patrol addressing is an indirect dual data memory that includes indirect single data memory access (Smem, dbl (Lmem)), indirect register bit access (Baddr), or software indirect dual data memory access and coefficient data memory addressing (coeff). Can be used for access (Xmem, Ymem).

【0076】

The ARx and CDP address registers are used as pointers in the cyclic buffer. The cyclic memory buffer start address is not bound by any alignment constraints. As described with reference to FIG. 11, compatibility with conventional cyclic buffer management mechanisms with alignment constraints is guaranteed.

【0077】

In the example of FIG. 11, address register AR0 and offset register BOF01 are used to address the cyclic buffer. Another register, BK03, is used to hold the buffer size. One bit in the pointer configuration register ST2 is set to 1 to set the cyclic address specification change mode for the address register AR0.

【0078】

The DAGEN unit uses the main data page pointer register to assemble a 23-bit word address pointer for data memory addressing. When the register bit address is specified, the connection with the main data page pointer does not occur.

【0079】

Each of the eight address registers ARx and the coefficient data pointer CDP can be configured independently so that they are linearly or cyclically modified via indirect addressing made in these pointer registers. This configuration is achieved by setting the ST2 state bit register. Table 1 shows the various states of the ST2, BOFxx, and BKxx registers that make up the cyclic changes in the ARx and CDP registers.

【0080】

As mentioned above, the cyclic buffer size is defined by the buffer size register. The examples shown in Table 1 support 16-bit buffer size registers (BK0, BK7 and BKC). The cyclic buffer start address is defined by a buffer offset register in combination with the corresponding ARx address register or CDP coefficient data pointer register. In the example shown in Table 1, five 16-bit buffer offset registers (BOF01, BOF23, BOF45, BOF67 and BOFC) are supported. Table 1 also shows which buffer offset registers are used when the cyclic addressing is done.

【0081】

By providing the three buffer size registers BKx and three address generators shown in Table 1, three operand instructions can be supported.

【0082】

Next, with reference to FIG. 11, the address specification applied by the logic of the cyclic buffer address specification unit will be described.

【0083】

The address boundary of the virtual buffer is defined by the buffer size value in the buffer size register BKxx810 (register BK03 in FIG. 11). The cyclic buffer management unit maintains the buffer index within the virtual buffer address boundaries represented by the buffer size value 812.

【0084】

The top of the virtual buffer address is address 0H, and the bottom of the virtual buffer address is defined by the contents of the buffer size register BKxx810. The position of the first 1 (eg bit N) in the BKxx register allows the virtual buffer index to be constructed in the virtual buffer from the ARx register (register AR0 in Figure 11). The virtual buffer index is then defined by the least significant bit of the ARx register up to bit N, and the remaining high-order bits are fetched as zero (ie, bits N + 1-15 are zero, as shown in 816 in Figure 11). Taken out as).

【0085】

The cyclic buffer management unit 800 performs arithmetic operation 818 on this index, from which the BKxx register contents are added or subtracted according to the values of the virtual buffer index vs. the top and bottom of this virtual buffer and modified (ie). , New) Virtual buffer index 820 is formed.

【0086】

The modified (ie, new) ARx820 register value is then constructed from the old contents of the high (15-N) bits of the modified virtual buffer index 820 and ARx register 814.

【0087】

According to the selected indirect addressing mode, the address 830 output by DAGEN is a 23-bit word address resulting from any of the following: New contents of ARx register 822 for addressing mode that requires 16-bit addition 826 of BOFxx register 824 and pre-modification of pointer register, or address specification that requires 16-bit addition of BOFxx register 824 and post-modification of pointer register The old contents of the ARx register 814 for the mode, in each case, are followed by the concatenation of the corresponding 7-bit main data page pointer register MDPxx828 (MDP05 in Figure 11). Note that this concatenation does not occur when register bit addressing is done.

【0088】

In the cyclic address specification made by the cyclic buffer management unit, the ARx register may be changed by the step value due to the previous change of the pointer register (for example,).^*+ ARx (# K16) addressing mode), which is further represented by the algorithm described in Table 2.

【0089】

[Table 2]

<img file="JP2000200212A_D0007.tif" />【0090】

The realization of patrol buffer management is further shown in Fig. 12 with a flow diagram.

【0091】

In step S1, the appropriate bits of the ST2 pointer configuration register are initialized and the patrol activity for the selected pointer is set.

【0092】

In step S2, the appropriate MDPxx main data page pointer is initialized to select the 64K page where the cyclic buffer is realized.

【0093】

In step S3, the appropriate BOFxx buffer offset register is initialized to the start address of the cyclic buffer.

【0094】

In step S4, the appropriate ARx register is initialized as an index in the cyclic buffer.

【0095】

Initialization of the MDPxx, BOFxx and ARx registers is done so that the 23-bit address MDPxx &amp; (BOFx + ARx) points in the cyclic buffer before any pointer changes occur on the selected pointer register.

【0096】

In step S5, the DR0 and DR1 step registers are initialized to be less than or equal to the buffer size BKxx. Table 3 shows the code strings for achieving this.

【0097】

[Table 3]

<img file="JP2000200212A_D0008.tif" />【0098】

In another mode, which provides compatibility with addressing based on memory boundaries with the state bit set to 1, the cyclic buffer size register BK03 is associated with bits AR [0-7] and BK47 register access is disabled. Will be done. In this case, the steps are as shown in FIG.

【0099】

In step S11, the appropriate bits of the ST2 pointer configuration register are initialized and the patrol activity for the selected pointer is set.

【0100】

In step S12, the appropriate MDPxx main data page pointer is initialized to select the 64K page where the cyclic buffer is realized. The address translator output code estimates that the main data page is 0.

【0101】

In step S13, the appropriate BOFxx buffer offset register is initialized to some value (eg 0 or a user-provided value). The address translator output code presumes that all BOFxx registers are set to 0.

【0102】

In step S14, the appropriate ARx registers are initialized before using any cyclic addressing. The selected register must point in the cyclic buffer.

【0103】

In step S15, the address register and the DR1 step register are initialized so that the buffer size is BKxx or less. Table 4 shows an example of a code string to achieve this.

【0104】

[Table 4]

<img file="JP2000200212A_D0009.tif" />【0105】

You will find that the BOF01 register is initialized with the offset provided by the user. This eliminates the alignment between the cyclic buffer and the memory boundaries. Therefore, flexible positioning of the cyclic buffer is possible.

【0106】

In the above description, it has been described that the circulation buffer is provided by addressing a word in the memory, particularly in a situation where the necessity of arranging the circulation buffer at a specific memory boundary is avoided. However, the present invention is not limited to addressing the cyclic buffer in memory. An embodiment of the present invention can also be used to address a bit array, whether in memory or in one or more processor registers. In this case, the bit array is effectively managed as a cyclic buffer. For example, a bit manipulation instruction can access the address register ARx that indicates a bit in a register, and the indicated address can be changed to step around the register for each X bit.

【0107】

FIG. 14 is a schematic diagram of an integrated circuit 40 incorporating the processor 10 of FIG. Integrated circuits can be implemented using application specific integrated circuit (ASIC) technology. As can be seen from the figure, the integrated circuit contains multiple surface mount contacts 42. However, the integrated circuit can include other configurations, such as multiple pins on the underside of the circuit for mounting in a zero insertion force socket or any other suitable configuration.

【0108】

One application of a processing engine, such as the processor 10 built into the integrated circuit of FIG. 15, is a telecommunications device, such as a mobile wireless telecommunications device. FIG. 16 shows an example of such a telecommunications device. In the particular example shown in FIG. 16, the telecommunications device is a mobile telephone 11 having an integrated user input device such as a keypad or keyboard 12 and a display 14. The display can be implemented using suitable techniques such as liquid crystal displays and TFT displays. The processor 10 is connected to the keypad 12, where it is connected to the display 14 via the appropriate keyboard adapter (not shown), where the telecommunications equipment interface or transceiver is connected via the appropriate display adapter (not shown). 16, for example connected to a wireless telecommunications equipment interface that includes a radio frequency (RF) circuit. The radio frequency circuit may be built in or separated from the integrated circuit 40 including the processor 10. The RF circuit 16 is connected to the antenna 18.

【0109】

A data processing device that supports a cyclic buffer including an address storage device that holds a virtual buffer index and an offset storage device that holds an offset address has been described. The cyclic buffer management logic applies modifiers to the virtual buffer index held in the address storage to retrieve the changed virtual buffer index and the buff offset held in the offset storage to be the modified virtual buffer. It is configured to be applied to an index and act to retrieve the physical address for addressing the cycle buffer, which can be in memory or in one or more processor registers and is a word address, byte address or Can be related to bit addresses.

【0110】

The terms "applied," "connected," and "connected" used herein mean that they are electrically connected, even if there are additional elements in the electrical connection path.

【0111】

Although the present invention has been described with reference to examples, the present specification has no restrictive meaning. Various other examples of the present invention will be obvious to those skilled in the art upon reading this specification. Therefore, all such modifications of the embodiments that fall within the true spirit and scope of the invention shall fall within the appended claims.

【0112】

This application claims priority to SN98402464.6 (TI-27691EU) filed in Europe on October 6, 1998 and SN98402455.4 (TI-28433EU) filed in Europe on October 6, 1998. It is a thing.

[Simple explanation of drawings]

[Figure 1]

It is a schematic block diagram of the processor according to the Example of this invention.

[Figure 2]

It is a schematic diagram of the core of the processor of FIG.

[Fig. 3]

FIG. 1 is a more detailed schematic block diagram of the various execution units of the processor core.

[Fig. 4]

It is a schematic diagram of the instruction buffer queue and the instruction decoder controller of the processor of FIG.

[Fig. 5]

It is a representation of the pipeline phase of the processor in Figure 1.

[Fig. 6]

It is a diagram of the operation example of the pipeline in the processor of FIG.

[Fig. 7]

It is an abbreviation of the core of the processor for explaining the operation of the pipeline of the processor of FIG.

[Fig. 8]

It is a figure which shows the patrol buffer memory alignment by the prior art.

[Fig. 9]

It is a figure which shows the aspect of the processor which concerns on the cyclic buffer management by the Example of this invention.

[Fig. 10]

It is a figure which shows the patrol buffer address designation by the Example of this invention.

[Fig. 11]

It is a figure which shows the cyclic buffer memory alignment by the Example of this invention.

[Fig. 12]

It is a flow figure which shows the step of the circulation buffer management by an Example of this invention.

[Fig. 13]

It is another flow diagram which shows the step of the circulation buffer management by the Example of this invention.

[Fig. 14]

It is a schematic diagram of the integrated circuit which incorporates the processor of FIG.

[Fig. 15]

It is a schematic diagram of the telecommunications equipment with built-in processor of FIG.

[Explanation of symbols]

10 microprocessor 20 processor backplane 22 backplane bus 24 instruction cache memory 26 Peripherals 28 External interface 30 register file 32 Data address generation subunit 34,970 ALU 36 D unit register file 38 D unit ALU 40 D unit shifter 42,44 Accumulation unit 100 processing engine 102 Processing core 104 interface unit 106 Instruction buffer unit 108 Program flow unit 110 Address data flow unit 112 Data communication unit 118 Address Bus 120 data bus 122 Program lead bus 128 Program address bus 130,132 data light bus 134,136,144 Data lead bus 140 instruction constant data bus 142 Address constant bus 146,148 Accumulator Light Bus 150,152 Accumulator lead bus 160,162 Data write address bus 502 Instruction buffer queue 504 register 512,514 instruction decoder 520,521 multiplexer 530 Light Program Counter 532 Local write program counter 534 Read program counter 536 Local read program counter 800,802 Patrol buffer management unit 810 buffer size register 814,822 address register 820 Modified address register 824 buffer offset register 828 Main data page register