Dual mode horizontal deflection circuit

Horizontal deflection circuit

The present invention relates to a horizontal deflection circuit for use in a television, comprising: a horizontal deflection section for producing an output signal during normal operation; an automatic frequency and phase correction section sensitive to a source of external synchronization signals, which produces control signals for the deflection section at a predetermined frequency and phase ratio with respect to said synchronization pulses and in response to horizontal trigger pulses derived from the deflection section output signal.

In addition to performing a line deflection of an electron beam or beams across a picture tube on a television screen, the horizontal deflection circuit also produces many source voltages by rectifying and filtering high energy horizontal return pulses. The source voltages for the horizontal deflection circuit itself are often derived from the return pulses. Obviously, when the receiver is initially turned on, no return pulses occur. This requires special technology and circuits to temporarily supply power to critical circuits from alternate sources such as an ac line until the receiver begins to produce usable return pulses. A start-up circuit of this type is described in U.S. Patent Application No. DW Luz, Serial No. 186,789, Horizontal Circuit with a Start-Up Power Supply.

Some receivers also include a horizontal deflection circuit with an automatic frequency and phase control (AFPC) circuit that maintains the synchronization of the horizontal return signal to the incoming external horizontal synchronization signals. A typical AFPC circuit is described in U.S. Patent Application Serial No. 192,332, RE Fernsler and DH Willis, Serial No. 192,332, Two Loop Horizontal AFPC System. Täs2

3 In the 5 6 0 AFPC circuit, the first loop is synchronized 16 times at horizontal frequency (16 f_B) to the incoming horizontal pacing frequency of the operating oscillator. The second loop maintains the correct timing of the horizontal control pulses to compensate for the phase shift of the return pulses due to the load applied to the horizontal deflection circuit by the power supply or beam. A failure to maintain the correct timing of the control signal may result in a distorted display and / or a focus on the image area of ​​the picture tube screen.

The second loop of this AFPC system includes a phase detector that uses horizontal return pulses at its output. It is obvious that when the display is initially switched on, the absence of return pulses prevents

AFPC system operation. Therefore, some method is needed to initially supply power to the horizontal control circuit to allow the generation of return pulses that can then maintain the operation of the AFPC system.

According to the present invention, a starting device for a horizontal deflection circuit is used. The horizontal deflection circuit according to the invention is characterized by a deflection section starting part operating in the absence of a deflection section output signal and including a source of horizontal frequency pulses occurring during a given horizontal deflection period later than said trigger pulses. .

In the accompanying drawings, Fig. 1 is a partially blocked circuit diagram of a television receiver having a display having a horizontal deflection circuit including an automatic frequency and phase control circuit; and Figures 2a-2i show waveforms that help to understand the operation of the present invention.

The television receiver of Figure 1 includes an antenna 10 that supplies radio frequency signals to a tuner and intermediate frequency (IF) circuits 11. The IF signals are fed to a video detector 12 which produces a combined video signal. The video information of the combined video signal is processed by luminance and chrominance processing circuits 13 which supply a video control signal to the picture tube 14.

The combined video signal is also fed to a sync Separator 15 which separates the horizontal and vertical sync signals from the video information. This combined synchronization signal is applied to a vertical deflection circuit 16 via an integrator 17 which includes a series resistor 20 and a parallel capacitor 21. The integrator 17 supplies the integrated vertical synchronization pulses to the vertical deflection circuit to implement the timing of the vertical deflection waveforms which are applied to the vertical deflection coils 22 of the picture tube.

The differentiator 23 separates the horizontal synchronization information from the combined synchronization signal and produces horizontal synchronization signals for the first AFPC loop of the horizontal AFPC system. The differentiator 23 includes a series capacitor 25, a parallel resistor 26 and a cutting diode 27 connected in parallel with the resistor 26. The horizontal synchronization signals are applied to one input of the first phase detector 30. The first phase detector 30 also receives a signal from the divider at its horizontal input frequency at its horizontal deflection frequency. The output signal resulting from the phase comparison of the two signals is filtered as a filter and fed as a control signal to a 16f „oscillator 33, the characteristic frequency of which is sixteen times the desired horizontal scanning frequency. Oscillator 33 produces an output signal which is applied to divider 31.

Divider 31 includes a counter that produces various signals. One function of the divider 31 is to divide the output signal of the oscillator by sixteen and thus produce an output signal at a horizontal fundamental frequency to the first phase detector 30.

The second output of the divider 31 is connected to the input of a ramp generator 34, the output of the ramp generator 4

3 The 5 6 0 input is connected to the input of the comparator or comparator circuit 35. The third output of the splitter is connected to one input of the second phase detector 36 of the second AFPC loop 37.

The output of the second phase detector 36 is filtered as a filter 40. The filtered output signal is applied to the second input of the comparator circuit 35. The output of the comparator circuit 35 is connected to a pulse generator 41, the output of which produces a horizontal deflection control signal of a certain duration for the horizontal deflection circuit 42. The horizontal deflection circuit 12 produces horizontal deflection waveforms for the horizontal deflection coils 43 of the picture tube and generates return pulses for the second phase pulses 36.

The pulse generator 41 produces a constant width pulse for the horizontal deflection circuit 42 through the output transistor 44. The pulse generator 41 includes a monostable multivibrator consisting of transistors 45 and 46, gates 47, 50 and 51, latch 52 and comparator 53. Transistors 45 and 46 act as switches to alternately charge and discharge capacitor 54 through source + V- and ground, respectively. The signals that turn the transistors 45 and 46 on and off are generated by the remaining components of the pulse generator 41 in the following manner.

During normal operation of the receiver, the comparator 35 compares the repetitive ramp voltage of the ramp generator 34, as shown in Figure 2a, with the dc voltage from the filter 40 (shown in Figure 2b). The comparator 35 reverses the polarity of its output when it indicates the intersection of the ramp dc voltage. The time of the intersection may vary from line to line because the voltage dc from the filter 40 varies according to the phase changes of the return pulses. The output of comparator 35, shown in Figure 2c, is fed to the second input of AND gate 51 via OR gate 47.

The output of divider 31 produces a plurality of repetitive pulses of 8 μs during each horizontal scan line. This series of pulses is processed by gate circuit 55, which removes all but one of the 8-microsecond pulses from each line by opening gate circuit 55 at a specified location on each horizontal line. This residual pulse, shown in Figure 2d, is applied to transistor 45 via inverter 56. Transistor 45 turns on for the duration of this pulse period, which is the time between t 1 and t 2, and causes capacitor 54 to charge from the + V 2 source through the impedance described by resistor 60, as shown in Figure 2e. This pulse is also applied to the input of the inverter 50 to close the ANDport 51 during the charging cycle so that the circuit does not flicker until the capacitor 54 is charged.

Capacitor 54 maintains its charge at the end of the charge pulse (during time t?) Until the trigger signal generated by the output of comparator 35 appears. The occurrence of this trigger pulse during t1 causes the gate 51 to generate an output by connecting transistors 46 and 44 and discharging capacitor 54. Comparator 53 provides an output that resets latch 52 when capacitor 54 discharges to the reference plane. The output of the latch 52, which is inverted by the inverter 49, closes the gate 51, thus switching off the transistors 46 and 44. This realizes that the output transistor 44 switches off at a suitable time.

During normal operation, the appearance of a trigger pulse at the input of gate 51 causes gate 51 to generate output. The output of gate 51, shown in Figure 2f, connects output transistor 44 and thus controls the horizontal deflection circuit 42. The output of gate 51 also connects transistor 46, causing capacitor 54 to discharge through resistor 60. The capacitor 54 is discharged until its terminal voltage reaches the reference level determined by the voltage source V f connected to the input of the comparator 53. When the terminal voltage of the capacitor 54 drops to this V ^ ^^ ^ level during t ^, the comparator 53 does not produce an output which closes the gate 51 through the latch 52 and the inverter 49, thus switching off the transistors 44 and 46. The horizontal deflection circuit also switches off, which makes ai6

3 5 6 No return pulses are generated and return is initiated.

When the transistor 46 turns off, the discharge of the capacitor 54 stops, which can be seen in Fig. 2a at time t1. Capacitor 54 remains at voltage level V._re£ seu5 to a constant 8 microsecond charge pulse at time t ^.

The length of the discharge period of the capacitor 54 is known, which guarantees a certain operating time of the horizontal sweep. The moment of occurrence of the discharge cycle is variable due to the operation of the phase detector 36. This maintains the correct centering of the image area despite the load changes in the circuit.

When the display is turned on, the horizontal deflection circuits are not operating and no return pulses are generated, with the result that the second phase detector 36 does not receive a return pulse at its input and the comparator 35 does not produce a trigger pulse at its output. Since there is no trigger pulse at the input of gate 51, the output transistor 44 does not turn on. If the external switching signal is not used, the receiver will never start operation. According to the present invention, this external switching signal is produced through port 47 and splitter 31.

The divider 31 produces switching pulses at the input of the gate 47, which occur during t £ after the occurrence of normal trigger pulses from the comparator 35. The switching pulses shown in Figure 2g have a sufficient duration to effectively initiate the operation of the deflection circuit 42. These external switching pulses occur after normal trigger pulses to minimize interference during normal receiver operation. The switching pulses supplied to the gate 47 from the divider 31 can continue after the end of the normal trigger pulses (time t ^) to a later time t ^. The gate 47 therefore ensures that the output transistor 44 is switched on for a sufficient time on each horizontal line for the horizontal deflection circuit 42 to operate. Fig. 2h illustrates the voltage of the capacitor 54 during the switching period during the start-up of the receiver, when no horizontal return pulses are produced, but the external switching pulses described in Fig. 2g are used. Figure 2i shows the output pulse produced during the start-up operation. Although the duration of the output pulse and thus of the horizontal sweep may be the same during both normal and start operation, the start output pulse is delayed compared to the output pulse of the nor5 target operation shown in Fig. 2f. This means that the return pulse generated at the end of the output pulse is also delayed. The second loop of the AFPC circuit operates in the presence of horizontal return pulses and synchronizes these pulses to an external pacing signal when normal operation begins, at which point signals from comparator 35 that occur earlier than start switching pulses from divider 31 effectively deactivate the latter pulses.

The delayed timing of the start pulses relative to the normal switching pulses therefore allows the receiver to operate efficiently during both start-up and normal operation. The logic shown in Figure 1 illustrates only one implementation that provides this required timing relationship.