Dual mode horizontal deflection circuit

(42) Date of commencement of the patent: 15. 9.1988 (45) Date of issue: 25. 4.1989 (30) Priority:

11th 2.1981 US 233480 claimed. (56) Documents:

(73) Patent owner:

RCA CORPORATION 10020 NEW YORK (US).

CQ

AT 388 068

US-PS3891892 US-PS 3898525 US-PS 3936115 US-PS4127875 US-PS4188568 US-PS4188641 US-PS4292654 DE-OS 2940461 DE-0S2853927 (54) HORIZONTAL SHIFT SWITCHING (57) A horizontal deflection start-up circuit operates in the absence of trigger pulses normally provided by an AFPC Loop (37) are derived. In normal operation, the AFPC loop generates trigger pulses due to a synchronized phase relationship with sampled flyback pulses. During start-up of the receiver, there are still no return pulses and no trigger pulses are generated. The start-up circuit supplies auxiliary pulses which occur later than the normal trigger pulses. There is provided a gate circuit (47) for supplying these Hifsimpulse to the Horizontalablenkschaltung only in the absence of the normal trigger pulses.

<img file="AT388068B_D0001.tif" />

OIR 0078018

Nr.388068

The invention relates to a horizontal deflection circuit for a television display device having a horizontal deflection output circuit, an automatic frequency and phase locked loop which is coupled to an external synchronizing signal source and to the input and the output of the horizontal deflection output circuit, a source for horizontal frequency trigger pulses, which is coupled to an input to the output of the horizontal deflection output circuit and to an output to the input of the horizontal deflection output circuit.

In the television display, the horizontal deflection circuit not only provides the line deflection of the electron beam (s) across the screen, but also provides supply voltages by rectification and filtering of high-energy horizontal retrace pulses. The supply voltages for the horizontal deflection circuit itself are often derived from the flyback pulses. If the device is initially switched on, then understandably there are no return pulses. Therefore, special techniques and circuits are required to temporarily supply critical circuits from other sources, such as the AC power line, until the receiver begins to generate useful flyback pulses.

In some receivers, horizontal sweep circuits with automatic frequency and phase control are also used to maintain the synchronism of the horizontal flyback pulses with the incoming external horizontal sync pulses. In a typical such AFPC circuit, a first loop synchronizes an oscillator oscillating at about 16 times the horizontal frequency (16 fpj) with the incoming horizontal synchronizing frequency. The second loop maintains the proper time relationship of the horizontal drive pulses to compensate for phase shifts in the flyback pulses due to loads on the horizontal deflection circuits by the power supply or beam current. Failure to maintain the proper timing relationship with the driver signals can result in playback distortion and / or incorrect screen centering on the screen.

The second loop of this AFPC system includes a phase detector which uses the horizontal retrace pulses as input. It will be appreciated that when the unit is initially powered up, the AFPC system will not operate due to the lack of flyback pulses.

The object of the invention is to provide a Horizontalablenkschaltung in which the horizontal drive circuit is initially fed so that return pulses are generated, which then keep the AFPC system in operation.

This object is achieved in that in a start circuit, an oscillator is connected via its output to a source for the generation of horizontal frequency pulses which are delayed with respect to the trigger pulses, and wherein an output of the source for horizontal frequency pulses with an input of an electronic controlled switch whose output is coupled to the Horizontalablenkausgangsschaltung connected.

In the drawings, Fig. 1 is a partially block diagram of a television receiver having a reproducing apparatus whose horizontal deflection circuit comprises an automatic frequency and phase locked loop, and Figs. 2a to 2i are waveforms for understanding the operation of the circuit of the present invention.

In the television receiver of Fig. 1, an antenna -10- provides high frequency signals to a tuner and IF circuit -11- of the receiver. The IF signals are applied to a video demodulator 12-12, which provides a composite video signal. The video information of the composite video signal is processed by a luminance and color signal processing circuit -13- into drive signals for a picture tube -14-.

The composite video signal is further applied to a synchronizing signal separating circuit 15-15, which separates the horizontal and vertical synchronizing signals of the video information. This composite synchronizing signal is fed to a vertical deflection circuit -16- via an integrator -17- having a series resistance -20 and a transverse capacitance -12-. Integrator -17- provides integrated vertical synchronizing pulses to the vertical deflection circuit to establish the proper temporal relationship of the vertical deflection oscillations applied to a vertical deflection winding -22- of the picture tube.

A differential circuit -23- separates the horizontal synchronization information from the composite sync signal and provides horizontal sync signals to the first AFPC loop -24--

- 3 Nr.388068

Horizontal AFPC system. The differentiating circuit -23- includes a series capacitance -25-, a shunt resistor -26- and a limiter diode -27- connected in parallel therewith. The horizontal sync signals are applied to one input of a first phase detector -30-, whose second input is supplied with a horizontal-frequency output signal from a divider -31-. The output signal resulting from the phase comparison of these two signals is filtered by a filter 32 and fed as input to a 16 f.sub.O oscillator 33 whose nominal frequency is 16 times the desired horizontal deflection frequency. The output of the oscillator -33- is supplied to the divider -31-.

The divider contains a counter which provides the various signals. One of the divider functions is to divide the oscillator signal by 16 to provide an output of the fundamental horizontal frequency for the first phase detector -30-.

Another output of divider -31- is coupled to the input of a ramp generator -34- whose output is again coupled to the input of a comparison circuit -35-. A third output of the divider is coupled to an input of a second phase detector of the second AFPC loop -37-.

The output of the second phase detector -37- is filtered by means of a filter -40-, and this filtered output signal is applied to a second input of the comparison circuit -35-. The output of this comparison circuit -35- is coupled to a pulse generator -41- which provides at its output a horizontal variable drive signal of fixed duration to a Horizontalablenkausgangsschaltung -42-. The horizontal deflection output circuit -42- provides horizontal frequency deflection to a horizontal deflection winding -43- on the picture tube, and generates flyback pulses for the second phase detector -36-.

The pulse generator -41- supplies a constant width pulse to the horizontal deflection output circuit -42- via an output transistor -44-. The pulse generator -41- contains a monostable multivibrator with transistors -44 and 46-, gates -47, 50 and

51-, a latch circuit -52- and a comparator circuit -53-. Transistors -45 and 46- operate as switches, alternating a capacitor -54- via a voltage source + V_} or load and unload mass. The signals turning on and off the transistors -45 and 46- are generated by the remaining components of the pulse generator -41- in the following manner.

During normal operation of the receiver, the comparison circuit -35- compares a recurring ramp voltage from the generator -34- (see Fig. 2a) with a DC voltage shown in Fig. 2b from a filter -40-. The comparison circuit -35- reverses the polarity of its output signal when it detects an intersection of the ramp voltage with the DC voltage. The time of this intersection can vary from line to line because the DC voltage from the filter changes with phase changes of the flyback pulses. The output signal of the comparison circuit -35- shown in FIG. 2c is fed to an input of an AND gate -51- via an OR gate 47.

At an output of divider -31-, there are several recurring pulses of 8 gs duration during each horizontal line. This pulse train passes to a gate circuit -55- which blocks all but one of the 8 gs pulses in each line by selectively activating the gate circuit -55- at a particular location on each line. This remaining pulse, which is shown in Fig. 2d, passes through an inverter -56- to the transistor -45-. This switches between t during the pulse interval_ß and t_? on so that the capacitor -54- is charged from the voltage source + Vj via an impedance illustrated as resistor -60-, as illustrated in Fig. 2e. This pulse is also applied to an input of inverter -50- to disable the AND gate -51- during the charge interval so that the circuit will not be triggered until capacitor -54- is charged. The capacitor -54- retains its charge at the end of the charge pulse (t_?) until the trigger signal generated at the output of comparator -35- occurs. This is the case at time tj and results in an output of gate -51- which turns on transistors -46 and 44- so that capacitor -54- is discharged. The comparison circuit -53- provides an output signal for resetting the latch circuit -52- when the capacitor -54- on

- 4 No.388068 is discharged to the reference level. The output of the latch circuit is determined by the

Inverter -59- reversed and disables the gate -51-, so that the 'transistors -46 and 44- are locked in turn. This allows the output transistor -4- to be disabled at the right time.

During normal operation, the occurrence of a trigger pulse at an input of the gate -51- causes the generation of an output signal at gate -51-. This output signal of the gate -51- shown in Fig. 2f causes the output transistor -44- to become conductive, thereby driving the horizontal deflection circuit -42-. The output of gate -51- also causes transistor -46- to conduct, causing capacitor -54- to discharge across resistor -60-. The capacitor 54- discharges until the voltage in it reaches a reference level which is represented by a voltage source V_pef is determined, which is connected to an input of the comparison circuit -53-. When the voltage across capacitor -54- at time t₃ to this level V_pef The comparison circuit -53- does not produce an output signal, and the gate -51- is disabled via the latch circuit -52- and the inverter -59-, so that also the transistors -44 and 46- are disabled. The Horizontalablenkschaltung is also disabled, with a flyback pulse is generated and the return is initiated. When the transistor -46- is turned off, the discharge of the capacitor -54- ceases, as in Fig. 2e at time t₃is illustrated. Capacitor -54- is energized until the next 8 gs load pulse at time t₅ at the voltage level V_pe); held.

The discharge interval of the capacitor -54- is of known duration, and thus a fixed operating interval of the horizontal deflection is ensured. However, the occurrence of the discharge interval varies because of the operation of the phase detector -36-. This maintains the correct grid centering independent of changes in circuit loading.

When the player is turned on, the horizontal deflection circuit does not yet operate and, accordingly, no flyback pulses are generated so that no flyback pulses appear at the input of the second phase detector -36- and comparator -35- does not provide output trigger pulses. If there are no trigger pulses at the input of gate -51-, then output transistor -44- will not turn on. If an auxiliary power-on signal is not supplied then the receiver will never go into service. According to one aspect of the invention described herein, this auxiliary turn-on signal is supplied through gate -47 and divider -31-. The divider -31- supplies turn-on pulses to an input of the gate -47-, which at time t₂ appear after the occurrence of the normal trigger pulses from the comparison circuit -35-. The turn-on pulses shown in Figure 2g are sufficiently long to initiate the operation of the deflection circuit. These auxiliary switch-on pulses occur after the normal trigger pulses so as not to disturb normal receiver operation as far as possible. The switch-on pulses applied to the gate -47- by the divider -31- can also be switched off after the normal trigger pulses have ended (time t₄ ) until a later time t_G take.

The gate -47- thus ensures that the output transistor -44- conducts during each horizontal line for a sufficient interval to operate the horizontal deflection circuit -42-. Fig. 2h shows the voltage across the capacitor -54- during the start-up interval, when no horizontal flyback pulses are generated, but the auxiliary starting pulses are used in accordance with Figure 2. Fig. 2i shows the output pulse generated during startup. Although the output pulse, and hence the horizontal deflection, can be of equal length in both normal and start-up operation, the start-up output pulse is delayed from the normal-mode output pulse shown in FIG. This means that the flyback pulse generated at the end of the output pulse is also delayed. The second loop of the AFPC circuit operates in the presence of the horizontal retrace pulses and synchronizes these pulses with external synchronizing signals until normal operation begins, at which time the signals from comparator -35-, which are earlier in time than the start-up pulses from the splitter, inhibit -31- occur, these latter pulses.

Nr.388068

- 5 Due to the delay of the starting pulses compared to the normal switch-on pulses, the receiver works both during start-up and during normal operation. The logic circuit shown in Fig.l represents only one possible embodiment to give this required temporal relationship.