Method for doppler-replica harmonic avoidance in a gps receiver

ES 2 196 353 T3

DESCRIPTION

Procedure to avoid Doppler replica harmonics in a GPS receiver.

Background of the Invention Field of the Invention

The present invention relates generally to spread spectrum communication systems and more particularly to a low power signal processing architecture and method for spread spectrum receivers. Description of the background

Spread spectrum communication has advantages in communication applications that require high reliability in a noisy environment. Often the dominant noise is man-made interference, either intentional or accidental. In a specific application the communications environment may include many potential reflectors, which increase severe multipath interference. Such multipath interference typically hints at deep nulls in the form of frequency selective fading. Spread spectrum communications are an excellent countermeasure to these difficulties.

There are several types of spread spectrum systems including direct sequence spread spectrum systems, frequency hopping systems, pulse (or chirp) modulated frequency systems, and various hebrids. Of these, direct sequence spread spectrum (DSSS) systems and frequency hopping systems are perhaps the most widely implemented. The following discussion focuses on binary DSSS systems.

In binary DSSS communication, a broadband carrier signal is modulated by means of a narrowband message signal. The broadband carrier is typically generated in two phases by modulating a single carrier frequency using a pseudo-random binary noise code (P / N) sequence. The P / N code is often generated using one or more high-speed shift registers, each having feedback modulus two according to a primitive polynomial. The generated high speed P / N code is then applied to a balanced modulator (multiplier) whose other input signal is the narrowband carrier. The balanced modulator output signal is a broadband signal often referred to as a "broadband carrier." To communicate data, the broadband carrier is modulated in two phases by a binary stream of message data. The message data rate is generally much slower than the P / N code symbol rate or "chip" rate, and the data and code chip edges are generally synchronized. The ability of the DSSS technique to suppress interference is directly proportional to the ratio of code chip rate to data rate. In many applications, there are thousands of code chips per message bit.

A DSSS signal can be received by first shifting the signal down to the baseband by multiplying it by a locally generated replica of the original narrowband carrier (eg, a properly tuned local oscillator). If the frequency (and phase) of the carrier replica is the same as that of the original received narrowband carrier, the output signal of the multiplier will then be a bipolar stream of "broadband data" that is the product of the code. bipolar P / N and message data streams. The P / N code is then removed by multiplying the broadband data stream by a locally generated replica of the P / N code that is time aligned with the received P / N code. AND^and This is the data de-dispersion process and produces the original message data stream at the output of the multiplier.

In the process of data de-dispersion, the broadband data power spectrum is refocused on the original narrower data bandwidth, raising the data power level well above the background noise in that bandwidth. The amount by which the power level is raised is called the processing gain and is directly proportional to the ratio of the code rate to the data rate. Furthermore, any received narrow band interference is spread by means of code replica modulation, and this greatly reduces the interference power level in the data band.

An often difficult task associated with DSSS signal reception is to generate the carrier replica with both the appropriate carrier frequency and phase and to generate the P / N code replica at the proper rate and in line alignment. appropriate time (displacement). In many DSSS communication systems, the necessary carrier frequency, necessary carrier phase, and necessary P / N code shift are not known a priori at the receiver and these parameters must be determined by testing different values ​​until a large signal is observed at the same time. data filter output. This is known as the search or acquisition procedure, and a DSSS signal is said to be acquired when the proper frequency, phase, and code shift are determined.

In many DSSS applications, DSSS signal levels are well below ambient noise and / or interference levels and are not detectable until after proper de-dispersion and proper low-pass filtering. When the received signal-to-noise ratio (SNR) is very low, the filter must be very narrow to achieve the necessary processing gain for the detection and acquisition of the signal. As a narrow filter requires a long integration period, the result of multiplying many received P / N code samples by the corresponding replica P / N code samples must be accumulated before the detection decision can be made. This multiplication and accumulation is a cross-correlation between the received replica and P / N code sequences, and the sequences may have to be long for low SNR signals.

Using the DSSS procedure enables multiple users to share seamlessly.

ES 2 196 353 T3 fines the same broadband channel using code division multiple access (CDMA) technique. With this technique, each transmitter uses a different P / N code so that the cross-correlation between different codes is substantially zero. A receiver selects and detects a particular transmitted signal by choosing the appropriate P / N code and performing the acquisition search. In some cases, it is not known which transmitter may be transmitting and the acquisition search must include examining different P / N codes from a known list. When many different codes, code offsets, and carrier frequencies have to be examined and the SNR ratio is low, the acquisition task can consume both time and energy. An important aspect of the present invention is the reduction of time and energy consumed in the acquisition process of the DSSS signal.

A description of direct sequence and other types of spread spectrum communications systems can be found, for example, in Spread Spectrum Systems, 3^to edition, by Robert C. Dixon, John Wiley & Sons (1994), and Spread Spectrum Communications, Vol. II, by MK Simon et al., Computer Science Press (1985). A description of CDMA techniques can be found, for example, in CDMA Principles of Spread Spectrum Communication, by Andrew J. Viterbi, Addison-Wesley (1995).

The popular and ubiquitous Global Positioning System signals are an important application of DSSS communications. In recent years, Navstar Global Positioning System (GPS) satellites have been launched into medium altitude Earth orbits in six orbital planes, each inclined 55 ° from the equator. The complete constellation of GPS satellites comprises twenty-one satellites and several spare satellites. The signals transmitted from these satellites allow a receiver close to the earth to accurately determine the time and its own position. Each satellite transmits data that provides accurate knowledge of the satellite's position and allows the measurement of the distance from that satellite to the user's receiver antenna. With this information from at least four GPS satellites, the user can calculate his own position, speed, and time parameters through triangulation techniques (ie, the navigation solution). Typically, seven, but a mononym of four, satellites are observable by a user anywhere on or near the earth's surface if the user's receiver has an unobstructed view of the sky, toward near the horizon. Each satellite transmits signals on two frequencies known as L1 (1575.42 MHz) and L2 (1227.6 MHz), and all satellites share these frequencies using the DSSS CDMA techniques described above.

More particularly, each satellite transmits a single high resolution DSSS signal on the L2 frequency and the same signal plus another low resolution DSSS signal on the L1 frequency. The low resolution DSSS signal comprises a P / N code with a chipping rate of

1.023 MHz and a repetition period of 1.0 ms, and a sequence of message data (the NAV data) with a rate of 50 bits per second. The high resolution DSSS signal uses a P / N code with a chipping rate of 10.23 MHz and a repetition period longer than one week. The same NAV data stream is used on all DSSS signals for a given satellite. The NAV message for a given satellite contains the GPS signal transmission time, ephemeris data (position) for that satellite, almanac data (an ephemoeris of reduced precision) for all satellites in the constellation, and a handover word. used in conjunction with code tracking transition from low resolution to high resolution. The low and high resolution codes are known as the course / acquisition (C / A) and precise (P) codes, respectively.

After the acquisition, the displacement of each code, together with the signal transmission time of the NAV data, enables the receiver to determine the margin between the corresponding satellite and the user. By including both the P code and the repeating C / A code in the transmitted signal, a faster hierarchical acquisition of the P code would be possible and two tiered levels of global navigation service could be provided. The P code can provide positions that are accurate to approximately 3 meters, while the C / A code produces accuracies on the order of 30 meters. Typically, the low resolution service is not restricted, while the high resolution service is restricted to the military by encryption or otherwise controlling the knowledge of the high resolution P / N code.

In a topical military receiver, the C / A code is acquired first. Then the handover word is read from the NAV data stream. The handover word specifies the approximate offset of the P-code relative to the GPS time (as transmitted at the time setpoint), and its use will greatly reduce the number of different code offsets that must be sought during data acquisition. code P. Acquisition of the C / A code is substantially easier than direct acquisition of the P code since the C / A code repeats every 1.0 ms. and there are therefore only 1023 different code offsets to search (twice this if the search is done in normal half-chip stages).

Received GPS signals are generally shifted in frequency from the nominal carrier frequencies L1 and L2 as GPS satellites move in orbits at several kilometers per second, producing a substantial Doppler shift. Satellite tracks are generally known a priori and the shifted Doppler carrier frequencies are therefore predictable if the location of the GPS receiver is known. Unfortunately, the location of the receiver is not known a priori, and there is often substantial local oscillator error with cheap receivers. The resulting uncertainty in the received carrier frequency (i.e. the necessary replica carrier frequency) can be large (e.g. ± 7.5 kHz),

ES 2 196 353 T3 and this frequency range may have to be searched during the GPS signal acquisition process. The frequency or Doppler search is generally done by repeating the cross-correlation of the received sample and the local replica P / N sequences for different local oscillator (carrier replica) frequencies. The spacing between frequency stages is made small enough to avoid signal loss when using long cross-correlation integration times (narrow filter bandwidths). Long integration times improve detection of low SNR signals. With typical civil GPS applications, 1.0 millisecond cross-correlation integrations are used (a single C / A code cycle), yielding an equivalent Doppler filter bandwidth of approximately 500 Hz. ± 7.5 kHz with thirty 500 Hz steps. The GPS acquisition then involves a search on the satellite code, code shift and Doppler frequency.

The control part of the GPS system is comprised of a master control station (MCS) and several supervisory stations. Monitoring stations passively follow all GPS satellites in view, collecting range data and satellite clock data from each satellite. This information is passed to the MCS where future satellite ephemeris and clock drifts are predicted. Updated ephemeris and clock data are downloaded to each satellite for retransmission in each satellite NAV message.

During operation, a typical GPS receiver does the following for each of at least four satellite signals:

1) acquire the DSSS signal,

2) syncs with the NAV data stream and reads the satellite time setpoint, clock correction, ionospheric delay and ephemeris data,

3) calculate the position of the satellite from the ephemeris data,

4) reads its own receiver clock to determine the receiver time associated with receiving the time set epoch, ^Y

5) estimates the travel time of the signal by subtracting the time setpoint from the time of the associated receiver.

This time difference is multiplied by the speed of light to obtain an estimated satellite interval. If the GPS receiver had a clock that was perfectly synchronized with the satellite clocks (or the error is known), only three of those interval estimates would be required to accurately locate the receiver. There is, however, a clock drift (slow changing error) due to the fact that GPS receivers typically use cheap glass clocks, while satellites are equipped with athemic clocks. This clock drift is learned and its effect is eliminated by measuring the interval (travel time) from four GPS satellites and using these measurements in a system of four equations with four unknowns (receiver x, y, z, and time). For general information on GPS, the reader is referred to Tom Logsdon's book "The Navstar Global Positioning System" by Van Nostrand Reinhold (1992).

A preferred embodiment of the present invention is locating and tracking assets such as automobiles, ships or cargo containers, trucks, trucks and the like, using GPS. In this application, GPS receivers are generally powered by batteries since a separate power source is generally not available. It is advantageous to increase the operational life of the batteries by reducing the energy consumed by the GPS receiver.

In a typical spread spectrum receiver, the receiver's input stage, (ie, RF and IF electronics) consumes a large amount of power while turning on. This results in high power consumption if signal acquisition and signal synchronization take a long time. Most first art GPS receivers do not have signal storage (memory) and must process the received signals in real time. In addition, they use either a sequential search or search for a small number of code / satellite Doppler shift containers simultaneously to achieve signal acquisition. These receivers must continuously receive and process each satellite signal until its SCD container is identified and the necessary NAV data is decoded. With a sequential search, power consumption is high as a substantial amount of time elapses before identifying the SCD container associated with each GPS signal. Alternatively, multiple SCD containers can be searched for in parallel to reduce elapsed time, but power consumption is still high as existing processing procedures are not very low-power procedures. Furthermore, the degree of parallelism is very limited with existing processing procedures due to the large amount of circuitry involved.

In one embodiment of the invention, a central facility or central station must track multiple assets (eg automotive). Each tracked object carries a GPS receiver that processes data from several of the visible GPS satellites; however, no precise position determination is made on the receiver. Instead, only partial processing is done at the receiver and intermediate results are transmitted from the asset to the central station. These intermediate results do not require decoding of navigation data or other data from the GPS signals. This system allows the GPS receiver and signal processor to be powered only long enough to acquire satellite signals (determine SCD containers). With this system, the

ES 2 196 353 T3 dominant power consumer is the acquisition process, and the GPS receiver power used in each tracked asset will be greatly reduced if the signal acquisition time and power are greatly reduced.

US Patent No. 5,420,593 to Niles uses a memory to store an interval of the received signal containing multiple GPS satellite signals. The received signal is sampled and written to memory at one speed and then read from memory at another faster speed. Upon reading it, the signal is digitally processed to acquire and synchronize with the received GPS satellite signals. This allows a short period of time to pass for the acquisition of the GPS signals. However, the receiver is not turned off immediately after signal storage, and low-power signal acquisition is not used. Furthermore, substantially reduced energy consumption is not achieved.

US Patent No. 5,225,842 to Brown describes a centralized GPS-based asset tracking system that reduces the cost of GPS receivers on each tracked asset by avoiding the calculation of the navigation solution on the asset. Each asset carries a GPS receiver that processes the signal from various visible GPS satellites and forwards the processed result to the central station where the precise asset navigation solutions are calculated. This system does not substantially reduce the energy consumed by the GPS receiver in the asset and does not substantially extend the life of the asset's batteries or reduce the time between services to replace the batteries. Also, low power parallel correlation is not used. Summary of the invention

An object of the present invention is to provide a Direct Sequence Spread Spectrum (DSSS) signal processing architecture that allows the receiver to be switched off during most of the reception acquisition phase, thus allowing to significantly reduce the time of reception. switching on the input stage of the associated receiver.

Another object of the invention is to provide a signal processing architecture that allows low power consumption during the acquisition phase of DSSS signal reception.

A further object of the invention is to provide a low power parallel correlation method that is easily manufactured with available integrated circuit processes and uses low energy to acquire DSSS signals.

Another object of the invention is to provide a GPS signal processing architecture that allows P / N code searches and Doppler searches (associated with the acquisition process) to be performed with a standard sequential processor (i.e. relatively slow and with a small processing resource) without the need for the receiver input stage to be turned on during the search process.

Yet another object of the invention is to provide a GPS signal processing architecture that requires little power for tracking an asset using GPS.

Another object of my invention is to provide a signal processing architecture that can dynamically interchange coherent and non-coherent integration times as needed for a particular received signal-to-noise ratio (SNR).

Another object of the invention is to employ a low receiver output sampling rate in obtaining a precise DSSS subchip signal acquisition timing.

Another further objective of the invention is to provide a GPS signal processing architecture that displays rapid acquisition of GPS satellite signals.

Yet another object of the invention is to provide a GPS signal acquisition method that allows rapid low-energy signal acquisition even when the GPS receiver uses a cheap local oscillator that can be inaccurate.

In one embodiment of the invention, a high speed, low power parallel correlator is used during DSSS signal acquisition to reduce acquisition power consumption. The power consumption of the receiver is further reduced because the time the receiver must be in the on state is reduced due to the speed of the parallel correlator.

In another embodiment of the invention, a time interval of the receiver's output data is sampled and stored in a memory and then the receiver is turned off. The time interval is long enough to allow acquisition of any of the received CDMA DSSS signals contained in the receiver's output stored data. The stored data output from the receiver is played back from memory as many times as necessary to acquire each desired CDMA signal. To keep the processing power consumption low, a low-power parallel correlator (partially analog) can be used in the acquisition process. This approach uses much less energy than existing digital cross-correlators.

The existing centralized GPS tracking system according to the invention allows the tracked assets to consume very little power and to use a receiver with a cheap local oscillator. The use of a parallel correlator allows the local oscillator to be imprecise, since many frequencies are searched quickly during the acquisition process using low power. Furthermore, the use of the parallel correlator makes it possible to avoid the reception and demodulation of the GPS NAV data, also reducing the average receiver start-up time. The almanac is no longer needed to support a reduced satellite search time since the parallel correlator can quickly search over all satellite codes. As the navigation solution is not necessary in the tracking units, only limited processing is necessary which consumes very low power, the navigation solution being generated at the central station.

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Brief description of the drawings

Features of the invention which are thought to be novel are set forth in the appended claims. The invention, however, together with additional objects and advantages thereof, may be better understood by referring to the following description taken in conjunction with the accompanying drawings, in which:

Figure 1 is a block diagram of a remote monitoring system in accordance with the present invention;

Figure 2 is a block diagram of a tracking unit on an object to be tracked according to the invention;

Figure 3 is a block diagram of a conventional sequential acquisition architecture;

Figure 4 is a block diagram of the sequential signal processing architecture in accordance with one embodiment of the invention;

Figure 5 is a block diagram of the parallel signal processing architecture according to another embodiment of the invention;

Figure 6 is an illustration of the parallel correlation procedure between stored data and sliding replica waveforms.

Fig. 7 is a block diagram showing a structure for generating a replica sequence;

Figure 8 is a block diagram showing a short segment of one embodiment of the data memory, mirror register and parallel correlator using the mirror generation procedure of Figure 7;

FIG. 9 is a block diagram showing a one-stage embodiment of the two-sequence parallel correlator of FIG. 8;

Fig. 10 is a block diagram showing a procedure for generating separate replica code and Doppler sequences;

FIG. 11 is a block diagram showing one embodiment of the data memory, code replica record, Doppler replica record, and parallel correlator using the replica generation procedure of FIG. 10;

Fig. 12 is a block diagram showing a one-stage embodiment of the three-sequence parallel correlator of Fig.

11;

Figure 13 is a schematic diagram illustrating the principles of the digital-to-analog differential converter and summation in accordance with one aspect of the invention;

Fig. 14 is a graph showing the noisy and noisy autocorrelation waveform for a short section of the 1.0 ms C / A code P / N sequence near the correlation peak;

Figure 15 is a block diagram showing an acquisition system based on a low power parallel correlator with full I / Q processing in which the RF / IF section generates two quadrature outputs;

Figure 16 is a block diagram of one embodiment of a quadratic A / D converter;

Figure 17 is a block diagram of a combined data memory organization, replica generation, parallel correlator that reduces the number of code register offsets by code / Doppler combination.

Figure 18 is a schematic diagram of a three sequence multiplier digital-to-analog converter cell;

Figure 19 is a schematic diagram of a data ping-pong memory organization;

Figure 20 is a schematic diagram of a parallel correlator with data Doppler pre-multiplication;

Figure 21 is a block diagram of a complete IQ processor with data Doppler pre-multiplication; Y

Figure 22 is a block diagram of a complete IQ processor with complex pre-multiplication data Doppler.

Fig. 23 is a block diagram of the low energy register write procedure using a scanner shift register.

Detailed description of the preferred embodiments of the invention

Figure 1 illustrates a plurality of GPS satellites 12, an (active) object that is tracked, such as a car carrying a tracking unit 14, and a central station 16. As described above, each satellite 12 transmits a signal that a GPS receiver in tracking unit 14 uses to measure propagation delay (and delay rate, if asset speed is desired) from that satellite to the receiver antenna. The satellite signals also include the periodically repetitive NAV data that is needed to determine a navigation solution from the measured time delays. Due to the low speed (50 bits per second) of the NAV data in the GPS signal, a receiver must be active for a substantial period of time (from one to several minutes) if the NAV data is to be collected. In addition, the NAV data of a particular satellite changes over time and the MCS GPS monitors these changes and provides updates almost every hour for the NAV data. To ensure accurate navigation solutions, any GPS-based navigation system must use NAV data that is no older than four hours. If asset positions are to be monitored more frequently than every four hours, then new NAV data will have to be collected at least every four hours. Maintaining NAV data then requires an average of approximately fifteen seconds of receiver operation per hour, and this carries a significant power requirement if done on each tracked asset.

In one embodiment of the present invention, the navigation solution is calculated at the central station rather than at the asset. None of the NAV data is required on the tracked asset. Only the data related to the propagation delay of the GPS signal between each satellite and the asset needs to be measured in the asset, and this data is then sent to the station.

ES 2 196 353 T3 central. NAV data can be determined at central station 16 using a standard GPS receiver therein, or by communicating with an appropriately located standard GPS receiver. If desired, NAV data, or navigation solutions, can be communicated to tracked assets over a high-speed communications link that requires less power to receive at the asset. Without the necessary decoding of NAV data on the asset, GPS signal acquisition becomes the main task of GPS processing on the asset, and the viability of the centralized tracking system is greatly improved through low-power acquisition procedures. of the invention.

As shown in Figure 2, an automotive tracking unit 14 comprises a receiver 2 responsive to the signals received at an antenna 5 from the GPS satellites, a processor 3, and a transmitter 4. The received signals are processed in the processor. 3 to find out and use propagation time differences between signals received from GPS satellites. By using time differences, the need for knowledge of the GPS signal time setpoints in the asset is alleviated, and therefore, data stream decoding in the asset is unnecessary. Without the need for decoding the GPS data stream, the receiver's processing is reduced to acquiring the GPS signals and calculating the relevant time differences (and Doppler frequency differences, if asset speeds are to be determined) from of the acquisition results. The calculated time differences and the identifying data of the satellites associated with the differences are transmitted by means of the transmitter 4 from the antenna 6 to the central station. In GB-A-2,301,725 ​​there is a description of the centralized monitoring system in which the acquisition of the GPS signal is a main part of the asset's GPS power budget.

Figure 3 shows a conventional serial acquisition architecture using a serial correlator. In a conventional GPS receiver, signal acquisition is followed by carrier and P / N code synchronization and NAV data demodulation, but the modules for these processes are not shown in figure 3. The signal acquisition architecture comprises an RF / IF (radio frequency / intermediate frequency) section 21 including an antenna 211, an RF amplifier 212, a mixer 213 and a local oscillator 214, and a low-pass filter 215 that supplies a signal received and converted inferiorly to an analog to digital converter (A / D) 22. The A / D converter 22 typically samples and converts to an integer multiple of the replica C / A code chip rate and supplies a digital sequence to a serial digital correlator 23. The correlator 23 serially computes the inner product of a subsequence of digitized receiver output from A / D converter 22 and a replica C / A code subsequence originating from a code / Doppler (or replica) generator 24. The inner product is made serially by first multiplying the first terms of the two subsequences by a multiplier 231 and storing the result in a coherent accumulator 232, then multiplying the second terms of the two subsequences and adding their product to the coherent accumulator 232, etc. The internal product is made in real time, as the terms of the subsequence are available from the A / D converter 22. As is conventional, subsequences generally span a single period of the repeating C / A code. After an internal product has been calculated, the coherent accumulator contains a sample of the cross-correlation of the received subsequence with a C / A code cycle of the replication signal, for the particular C / A code, code shift, and Doppler frequency generated. by the replica generator. The inner product operation is repeated with several subsequent subsequences from A / D converter 22 while using the same replica C / A code subsequence. The subsequent inner product results are then squared by means of a quadratic exponent 29 and summed in a non-coherent accumulator 30, producing a non-coherent integration of the coherent processing results. The output signal from the non-coherent accumulator 30 is examined by means of a threshold detector 31 and an "acquired signal" command is generated if the signal level in the non-coherent accumulator 30 is high enough. When a signal is acquired, a control 27 monitors the associated C / A code index (satellite index), code shift and Doppler frequency, and commands the code / Doppler generator 24 to switch to a C / A code. (for a different GPS satellite) and start another search, or to stop if enough satellite signals have been acquired. If a signal is not acquired after several subsequences have been processed from the A / D converter 22, control 27 commands the code / Doppler generator 24 to switch to a different C / A code, code shift, or Doppler frequency. When each satellite signal has been acquired, the control 27 supplies the associated code index, code shift, and Doppler frequency for synchronization of the GPS signal and NAV data processing units (not shown).

Provision should be provided for the search of all feasible C / A codes, code offsets, and Doppler frequencies. Control 27 selects the desired C / A code and desired code offset via commands to a satellite code generator 243 and offset generator 244. The offset generator 244 is provided for a time offset of the code replica generated from the satellite code generator 243, relative to the binary stream from the A / D converter 22. A Doppler I / Q generator 242 generates a digital representation of the sinusoid representing the combination of Doppler shift and local oscillator frequency error assumed by the control 27. The replica signal is generated by means of a multiplier 241 as the product of this sinusoid and the C / A code replica. To ensure detection of the

ES 2 196 353 T3 GPS signal, the RF / IF section 21 must generate both an in-phase (I) output signal and a quadrature (Q) output signal (not shown in figure 3), and the two signals they must be processed for signal acquisition. Furthermore, each of the RF / IF output signals, I and Q must be processed with both sinusoidal Doppler components I and Q, as those who are skilled in the GPS technique know.

The conventional approach shown in Figure 3 requires that the receiver output data from the RF / IF section 21 be processed as soon as the motor is available, and the processing is restricted by the code rate in the received signal. The architecture for an improved sequential signal acquisition processor in accordance with one aspect of the invention is shown in Figure 4. The architecture is similar to that of figure 3 except that a signal storage memory 33 is added and the power for the RF / IF section is now controlled by means of the control 35. The GPS signal supplied by the RF / IF section FI 21 is converted to a digital format by means of an A / D converter 22, but now the A / D sampling rate can be set to a low non-integer multiple of the C / A code rate. Memory 33 stores an input signal length sufficient for signal acquisition and allows the RF / IF section to be turned off after storage. The acquisition process then proceeds by reading and possibly rereading the data stored in memory. Power consumption is therefore significantly reduced as the RF / IF section 21 consumes significant power. Furthermore, the acquisition process is not restricted more by the code speed of the received signal, as noted in the first technique. The non-integer input A / D sample rate allows the acquisition processor to determine the precise GPS signal propagation time differences (necessary to determine the location solution) while using a much lower sample rate. Also, when the input SNR is not too low, or when the precision requirements are not too high, the non-integer sampling rate allows the time differences to be determined with sufficient precision to avoid carrier and synchronization processes. conventional P / N code codes normally needed (for example, Costas phase locked loop for carrier tracking, and prepost delay locked loop for carrier tracking).

An advantage of storing the received signal segment in memory and rereading the memory as needed to process different SCD containers is that the correlation process can take place over a period of time without loss of signal acquisition precision due to instability. or inaccuracy of the local oscillator. Furthermore, if the stored signal is also used to derive the time delays necessary for the navigation solution, there is no need to maintain a precise timing between the acquisition and tracking phases of GPS reception. For applications where the navigation solution is not needed immediately after the measurement (for example, asset tracking), a low-power GPS receiver can be built using a very low-power integration process for the sequential correlator (and other circuits) in combination with a low-power data storage memory. Large-scale, very low-power integration processes are being developed in industry (eg, 1.5V, 0.35 micron metal-oxide-complementary semiconductor or CMOS process).

With the GPS system, as in most DSSS systems, the SNR is very low prior to signal processing, and a substantial period of the received signal must be processed to produce the high SNR correlation peak necessary for adequate detection of signal via threshold detector 31. For normal civil GPS applications, approximately 20 ms of signal from RF / IF section 21 must be stored and processed. To keep the memory size small, the signal from the RF / IF section 21 is sampled at a low rate and quantized to only a few levels. For civil applications, conventional GPS receivers topically achieve a location point accuracy of 30 meters. GPS location points with this precision can be calculated from signal cocode offsets that are measured with an error of less than one tenth of a chip in a C / A code. The signal code shift is measured by observing the replica signal code shift associated with the cross-correlation peak. In one embodiment of the invention, a sequence of non-coherent accumulator 30 results is generated in order to increase the replicate code shift while keeping the code onyx and the Doppler frequency constant. If a large correlation result is observed, an interpolation algorithm is applied to the sequence of results and the code shift associated with the correlation peak is estimated. A cocode shift accuracy of one tenth of a cocode chip is achieved while sampling the signal at approximately twice the C / A cocode chip rate. Some conventional GPS receivers do not achieve the desired one-tenth chip accuracy during signal acquisition; instead, some do this during code sync by sampling the signal at twice the C / A code chip rate and tuning the sample phase as part of the pre-post delay locked loop. Alternatively, other conventional GPS receivers achieve one-tenth chip timing by sampling the signal at ten times the C / A code chip rate and observing the code shift, in one-tenth chip increments, that produces the peak. of correlation maós grande. A reduced sample rate requires less memory and slower processing speeds.

The SNR at the output to the A / D converter 22 is well below zero, so that little signal degradation is suffered when the A / D converter uses only three levels of representation.

ES 2 196 353 T3 appropriately chosen. Each sample can be conveniently encoded in sign and magnitude format using only two bits of data. To ensure signal detection, both RF / IF output signals, I and Q, must be generated, stored, and processed (only one RF / IF channel is shown in Figures 3 and 4). The use of three or more levels of representation can provide substantial resistance to interference by non-GPS signals, as is known to those skilled in the GPS technique. However, a small data memory is required if only two levels of representation (one bit) are used for the I and Q signals, and this has a cost advantage in some applications. In one embodiment of the invention, the RF / IF output signals I and Q are digitized and stored simultaneously, and the data memory length is sufficient to store the entire data sequence necessary to achieve acquisition (e.g. , 20 ms). With 1023 C / A code chips per millisecond and sampling both I and Q RF / IF signals at approximately two samples per code chip with two bits per sample, approximately 170,000 bits of storage are required for the 20 signal segment. ms. For convenience, the I and Q data can be considered as stored in separate I and Q memories. When the required data has been sampled, converted and stored, the receiver can be turned off and the recorded data can be processed.

In a sequential procedure, the stored data is reproduced (read) once during the correlation process for each combination of code, code shift, and Doppler shift. In the system of Figure 4, the sequence of stored digital data samples are read from memory 33, one by one. Each sample of the memory sequence 33 is multiplied by the corresponding sample of the code generator / Doppler sequence 24 at multiplier 231, and the result is accumulated in the coherent accumulator 232. The sequence or data segment of the generator code / Doppler or replica generator is packaged for a particular code, code shift and Doppler frequency under test. The length of the memory sequence thus processed is the length of the coherent integration, and is typically chosen as a complete cycle of the C / A code, which is 1.0 milliseconds (ms). Multiple (eg, twenty) 1.0 ms memory data segments are processed in this manner without changing the replica sequence. After each 1.0 ms segment is processed, the value stored in the coherent accumulator 232 represents the cross-correlation between the 1.0 ms replica and the data segments (sequences). This value is squared by the quadratic exponent 29 and added to the non-coherent accumulator 30. Before processing the first 1.0 ms segment for a given replica signal, the non-coherent accumulator 30 is reset to zero so that the final accumulated result represents the total correlation value for the particular code, code shift, and Doppler frequency. specified by the reply signal. Similarly, the coherent accumulator is reset before processing each 1.0 ms segment. The threshold detector 31 monitors the correlation value and produces an "acquired signal" signal if the value is greater than a specified threshold. Upon receiving an “acquired signal” signal, control 35 performs a single peak search and interpolation algorithm (described below) to find the best estimate of the code shift associated with the given code index and the Doppler frequency under examination. . Control 35 then selects another combination of code, code shift, and Doppler frequency and commands the replica generator to alter the replica signal to reflect this change. The signal acquisition process is repeated for multiple replica signals corresponding to the codes, code shifts and Doppler frequencies to be searched, and stops when the desired number of GPS signals (different C / A codes) have been acquired. The control 35 then produces as an output signal the code indices, estimated offsets and Doppler frequencies associated with the acquired signals.

The I and Q memory data can be processed sequentially, (eg, process all the I data, and then process all the Q data) using a digital correlator 23 as shown in Figure 4. Alternatively, the I and Q memory data can be processed simultaneously using separate digital correlators. In any case, to ensure signal acquisition, the I and Q Doppler processing must be performed on both the I memory data and the Q memory data. Thus, there are four IQ combinations and they can be processed sequentially with a single digital correlator, or simultaneously with multiple correlators. In a sequential procedure, the correlation result for the entire memory data stream with a given replica code index, code shift, and Doppler frequency is calculated as follows: first, the coherent and non-coherent accumulators are reset to zero. . The memory data I is then processed with Doppler replica I and the correlation result is accumulated in the coherent accumulator. The memory data Q is then processed with the Doppler replica Q and the correlation result is also accumulated in the coherent accumulator. The total result of the coherent accumulation is squared by means of the quadratic exponent 29 and added to the coherent accumulator 30. The coherent accumulator is then reset. Next, the memory data Q is processed with the Doppler replica I and the correlation result is accumulated in the coherent accumulator, then the memory data I is processed with the Doppler replica Q and the correlation result is inverted (it is multiplied by -1) and also accumulates in the coherent accumulator. The total result of the coherent accumulation is then squared by the quadratic exponent 29 and is added to the non-coherent accumulator 30. This process is repeated for each 1.0 ms memory data segment, without reinitializing the non-coherent accumulator

ES 2 196 353 T3 between segments, and requires two complete read cycles of both I and Q memory data. Acquisition time and energy can be reduced using I and Q Doppler generators 242, multipliers 241 and separate digital correlators 23 to process all four IQ combinations simultaneously.

In a convenient interpretation, the Doppler code generator 24 consists of a Doppler I / Q generator 242, a satellite code generator 243, offset generator 244, and multiplier 241, as shown in Figure 4. The Doppler I / Q generator 242 generates a digital sequence representation of a sine or cosine wave at the desired frequency relative to the sample rate, and can, for example, be implemented with a read-only memory (ROM) controlled by a address counter. The frequency and phase (I or Q) of the sinusoid can be selected by controlling the order in which the stored sinusoidal samples are read (eg, by direction decimals and by starting direction selection, respectively). Those skilled in the art are also familiar with other digital sinusoid generators. For GPS C / A codes, a well known state machine can be used to generate the C / A code bits in the proper order. The Doppler sinusoid and C / A code values ​​are multiplied by multiplier 241 to produce the replica signal. Provision for searching all feasible code offsets is provided by time offset of the stored code replica from satellite code generator 243 using offset generator 244. With the implementation of the satellite code generator state machine 243, a particular code shift is performed by prefixing the state machine to the associated state before starting the mapping process. Initial states, corresponding to different code offsets, can be stored in ROM and can be indexed by means of a simple binary address counter.

In practice, the acquisition search is conveniently performed by first selecting a code and a Doppler frequency, and then indexing through different code offsets. Then the Doppler frequency is changed and the different code shifts are reexamined. Non-coherent accumulator 30 may be implemented as an array of accumulators, one for each candidate code shift in a sequence of adjacent shifts. This arrangement of accumulators allows the values ​​for adjacent offsets to be examined simultaneously so that an interpolation algorithm can be applied to find the subchip offset value associated with the actual value peak. If a sequential interpolation algorithm is used, the peak offset value can be interpolated while using only a single accumulator element.

Total acquisition time can be reduced by processing multiple code shifts simultaneously. For example, multiple digital correlators 23 can be used, each controlled with a differently delayed version of the replica signal. The different delays can be carried out with a derived delay line coupled to the output of the code generator / Doppler 24. The different taps can then each drive an independent serial digital correlator 23, and the results of each correlator can be squared and separately accumulated on associated elements of an array of non-coherent accumulators.

An alternative GPS receiver architecture that is provided for both low power and fast signal acquisition is shown in Figure 5, in accordance with another aspect of the invention. The acquisition architecture is similar to that of Figure 4, except that the digital serial correlator, the serial Doppler and P / N code generators, and the serial reading memory are now replaced by a parallel correlator 36, parallel Doppler generators and code P / N 37, and a parallel read memory 33, respectively. One aspect of the invention is a procedure for analog parallel mass summation in the parallel correlator. The analog sum in combination with the massively parallel organization of memory, the replica generator, and the correlator elements, provides for the massive time and energy reductions in the correlation process. The result of the analog sum is converted into digital format by means of an A / D converter 38 which can be combined with a quadratic exponent 29 as described below. Parallel architecture also has the advantage of complementary low power metal oxide semiconductor (CMOS) integrated circuit technology to achieve low power usage. The use of energy in CMOS circuits is dominated by the charging and discharging of the circuit's node capacities; low energy is used in nodes whose voltages are static (no change) or whose capacities are small. With this invention, the Doppler replica and P / N code generators and recorders, data memory, and parallel correlator are organized to minimize the number of CMOS nodes being loaded and unloaded during the mapping process.

Figure 6 illustrates the concept of parallel correlation and shows the waveforms for the case where the received and replica signals do not have a Doppler shift. Digitized signal data is written sequentially to data memory when it becomes available from RF / FI section 21 and from A / D converter 22. Data memory 33 is organized for mass parallel output so that a long stream of data is available for output simultaneously. Also, a shift register 1004 is loaded with the chosen replica signal and arranged for a parallel bulk output with the same length as that of the data memory. A sample of the cross-correlation (i.e., the inner product) between the parallel data sequence and the parallel replica sequence is generated for a Doppler frequency,

ES 2 196 353 T3 code index and code offset all given at once by parallel correlator 1000. In parallel correlator 1000, each element of the memory data sequence is multiplied by the corresponding element of the replica sequence using a corresponding multiplier in the multiplier matrix. The output signals of the multiplier are summed simultaneously to form the coherent processing result at the output of the correlator. The coherent processing result for an adjacent code shift is generated by shifting the replica register one stage while keeping the memory data stationary. Alternatively, the replica signal can be kept stationary while the memory data is scrolling.

In an attractive embodiment of the invention, the parallel output data and the replica sequences are 1.0 ms long and span a single C / A code cycle. The data stream is generated from the RF / IF output signal by sampling at the rate of approximately two samples per C / A code chip and digitizing at three levels with an A / D converter using a sign and magnitude format. two-bit. This sampling rate and the number of levels avoids overlap, avoids substantial degradation of the SNR if the threshold A / D levels are chosen appropriately, and produces sequence lengths on the order of 2,100 samples. The sign and magnitude format allows a single multiplier to be used in the multiplier matrix described above. Other attractive data representations, sample rates, and parallel output sequence lengths are possible, as will be apparent to those skilled in the art.

Figure 7 shows a procedure for generating the parallel output replica sequence. In a code / Doppler generator 1008, a C / A code generator 1001 generates the desired C / A code sequence and a digitized sinusoid generator 1002 generates the digitized sinusoid sequence with the desired phase and Doppler frequency. A multiplier 1003 sequentially multiplies the code and sinusoid sequences provided by the code / Doppler generator 1008 to generate the replica sequence, and this sequence is shifted in a parallel output code / Doppler (replica) register 1004.

The replica sequence is preferably represented in a three-level (two-bit) sign-and-magnitude format, or a two-level sign format (one bit), since these formats reduce the complexity and power consumption of the parallel correlator with relative to a format that uses more bits. With only three or fewer levels, the Doppler component in the replica sequence will have a high content of harmonics and these harmonics can be falsely correlated with an input signal. This problem can be avoided by choosing the frequency of the RF / IF local oscillator so that the RF / IF output signal is substantially offset from zero frequency. By choosing the shift large enough, the harmonics of all necessary resultant Doppler replica frequencies will be well above the highest Doppler replica frequency. The problem of the Armenians is known to those who are experts in e design of superheterodyne receivers. If desired, the Doppler replica harmonic levels can be reduced by using more bits in the replica and Doppler sequence representation and more bits per sample in the replica register. However, this will increase the power consumption and complexity (size) of the signal acquisition implementation.

Figure 8 shows a short segment of one embodiment of data memory 33, replica shift register 1004, and parallel correlator 1000 using the replica generation procedure of Figure 7. Both the data and replica sequences use a two-bit sign and magnitude representation, and since the rows of elements in both memory 33, shift register 1004 and correlator 1000, are aligned with each other in In the form of columns, the sign (S) and magnitude (M) bits of the corresponding samples of the two sequences can be conveniently fed, in each column, to a corresponding multiplier 1200. With the sign and magnitude input values ​​of, for example, or -1, 0 or 1 of the two input sequences, each 1200 multiplier generates either -1, 0 or 1 as an output signal. A separate 1300 digital to analog converter converts each digital multiplier output signal to analog format. All the output signals from the D / A converter are summed and supplied to a common output that represents the analogue correlation result. Analog summation is conveniently carried out using loaded addition, but alternative analog summation formats are also possible. This summation procedure is spatially efficient, requires very low power, does not need analog memory, and is very fast. Another advantage of this parallel correlator architecture is that the code and Doppler sequences are programmable, allowing a single correlator to quickly search multiple code indices, offsets, and Doppler frequencies in the acquisition process.

Figure 9 shows a one-stage embodiment of the two-sequence parallel correlator of Figure 8. The multiplier 1200 generates sign-and-magnitude output bits that control the switches 1400 and 1500 of the D / A converter 1300. The switches connect a terminal from a charge summing capacitor 1100 or to a positive reference voltage bar or to a negative reference voltage bar, or to an output reference voltage bar (eg to ground). The sum is generated through a two-stage procedure. First, the load reset line is set low, closing a load reset switch 1600 and forcing switch 1400 on each parallel correlator stage to connect the associated capacitor to the output reference bus (ground in figure 9). This discharges all the capacitors. Afterwards, the load reset line is brought up to level

ES 2 196 353 T3 high, opening a load reset switch 1600 and allowing the data and replication values ​​of each parallel correlator stage to control the associated sign and magnitude switches, 1500 and 1400 respectively. This two-stage process ensures that excess charge does not accumulate on the charge sum capacitors over time. It is advantageous that this parallel correlator can be implemented in low cost digital processes using, for example, metal-to-metal "crossover point" capacitors and binary electronic switches. Finally, it is advantageous that the charge sum can be spread across multiple integrated circuits simply by spreading the sum lines.

Figure 10 shows another procedure for generating the replica signal. With this procedure, the code and Doppler replica sequences are stored in separate parallel output registers. The C / A code generator 1001 of the code / Doppler generator 1010 generates the desired C / A code sequence and this sequence is shifted in a 1005 code replica record. Similarly, a digitized sinusoid generator 1002 of the code / Doppler generator 1010 generates the digitized sinusoid sequence with the desired phase and Doppler frequency, and this sequence is shifted in the Doppler replica record 1006.

Figure 11 shows an embodiment of data memory 33, code-replica record 1005, Doppler-replica record 1006, and parallel correlator 1000 using the replica generation procedure of figure 10. An independent code record 1005 and a Doppler record 1006, producing separate memory, code, and Doppler data sequences. The sign (S) and magnitude (M) bits of the corresponding samples of the three sequences are fed to the corresponding multipliers 1201. With the sign and magnitude input values ​​of, for example, -1, 0, or 1 of data and Doppler sequences, and -1 or 1 of the code sequence, each multiplier 1201 generates either -1, 0 or 1 as the output signal. The different multiplier output signals are all summed simultaneously using analog summation as described above for the two-sequence parallel correlator.

Figure 12 shows a one-stage embodiment of the three-sequence parallel correlator of figure 11. The correlator stage shown is similar to that of the two-sequence parallel correlator of figure 9 except that the multiplier has an extra or-exclusive gate. 1205 to allow the separate code register bit to influence the sign of the multiplication result.

The two and three sequence parallel correlators of Figures 8 and 11 can be generalized to plural sequence parallel correlators. With respect to the two-sequence parallel correlator, the three-sequence parallel correlator has had one of the cross-correlated sequences (the replica) decomposed into two separate sequences. This decomposition can be applied to both data and replica sequences in general to provide a parallel plural sequence correlator or inner product machine.

The "differential" analog sum in the parallel correlator may have lower noise susceptibility and other advantages. Figure 13 shows a convenient differential sum configuration. At each stage of the parallel correlator, two D / A converters are controlled in parallel by means of the same sign and magnitude output signals of the associated multiplier. One converter is labeled positive and its capacitor connects to a positive sum line and the other converter is labeled negative and its capacitor connects to the negative sum line. The switches shown in each converter are implemented as electronic switches, as is well known in the art. The two converters work identically except that the sign switch 1500 in the negative converter is connected in reverse of the sign switch of the positive converter. With the differential procedure, the difference between the positive and negative sum results must be taken to determine the final coherent correlation result. This can be done for example by using a high speed linear amplifier or a switched capacitor differential amplifier, as is known to those skilled in the art. Alternatively, the positive and negative sum results can be converted separately from analog to digital and then their digitally calculated reference before squaring and non-coherent accumulation.

The three-sequence parallel correlation procedure of Figure 11 uses less power than the two-sequence procedure of Figure 8 because only the 1-bit deep code register needs to be shifted when developing correlation results for the shifts of posterior code; the sequence on the separate Doppler record can be kept fixed. Shifting a register that is two bits deep consumes approximately twice as much power as shifting a register that is one bit deep. Since register shift is a dominant power consumer with the parallel correlation approach, the three-sequence procedure is advantageous. On the other hand, the two-stream procedure uses fewer shift register elements (bits) and fewer exclusive-or gates in the multipliers and therefore has a smaller implementation. The difference in implementation size decreases as the number of Doppler replica representation bits increases.

The 1300 D / A converters shown in Figures 9 and 12 use series switches to control the charging of the charge sum capacitors. Figure 18 shows an alternative embodiment for the multiplier and the analog converter (D / A) for the case of three sequences in Figure 18. An advantage of this embodiment is that the digital logic functions directly control the sum capacitors loading

ES 2 196 353 T3 and a serial connection of switches is not necessary. This multiplier-D / A combination is quickly implemented in a standard digital CMOS process. Capacitors 1101 and 1102 are of substantially the same value and together provide a three-level D / A conversion, eg, -1, 0, and +1. Level -1 is called bringing both capacitors low (digital ground), level +1 is called bringing both capacitors high (Vdd digital), and level 0 is called bringing one capacitor high. while the other is brought low. In a multiplier 2001, the exclusive NOR gate 1210 and the AND gate 1211 multiply the two-bit data and the Doppler values ​​to form the product of sign and magnitude. The exclusive NOR gate 1212 then converts the two-bit product to signals A and B that control the two capacitors in the same or different directions. Finally, the exclusive NOR gates 1213 multiply the A and B signals by the binary code value, while the NOR gates 1214 provide the grounding of the capacitors to discharge them during the reset phase.

For a given length of stored GPS signal, there is a trade-off between the length of coherent processing and non-coherent processing. As the coherent correlation length increases, the SNR of each coherent processing result increases but the number of coherent processing results available for squared exponentiation and non-coherent accumulation (integration) decreases. Those skilled in the art will know that SNR is improved by 10 dB per decade of increase in coherent processing length, but increases only by 5 dB per decade of non-coherent processing length. Thus, for a given memory data length, the predicted SNR is maximized by performing a long coherent correlation. However, unpredictable receiver movement or local oscillator fluctuation limited the feasible length of coherent processing. Also, as the coherent correlation length increases, the bandwidth of the Doppler containers decreases and this produces more Doppler containers that must be searched. The architectures of Figures 4 and 5 quickly allow coherent and non-coherent processing length dynaamic logging through replication generator control, reinitializing coherent and non-coherent accumulators, and bypassing the quadrotic exponentiation functions.

It is generally true that the predictive SNR necessary for reliable detection is less than the SNR necessary for precise correlation peak localization (ie, interpolation). Thus, acquisition time and energy can be minimized by using shorter or shorter coherent correlations (and searching for even fewer Doppler containers that are as wide as the detection reliability constraints allow) until correlation detection is observed, and then reprocessing. the longest consistent correlation data using code shifts and Doppler shifts close to the values ​​that produced the detection event, to increase SNR and perform higher code shift interpolation. The architectures in Figures 4 and 5 quickly allow for this two-stage process.

Figure 14 shows a section of the non-noisy autocorrelation waveform for a 1.0 ms (unsampled) C / A code P / N waveform. The autocorrelation value is very close to zero for all displacements of magnitude greater than a width of one chip and is a triangular function (of the displacement) for displacements between a chip width of -1 and +1. In another aspect of the invention, accurate subchip correlation peak time estimation is achieved without using sample rates that are substantially greater than twice the C / A chip rate. With an integer number N of samples per C / A code chip, the discrete autocorrelation sample value over time remains substantially constant over a 1 / N time shift variation of the input signal of the C code chip period. / A when the receiver bandwidth is substantially wider than the GPS signal bandwidth. This is a form of quantization and produces a substantial quantization error if N is not large. For example, a displacement measurement precision of one tenth of a C / A code chip would require a sample rate of N = 10 times the C / A code chip rate. With more limited receiver bandwidth, the autocorrelation sample value varies with the time offset of the input signal, but not necessarily linearly with the input offset. If a non-integer multiple sampling rate is used, then the sample times precess or transfer to the relative chip position while sampling a sequence of signal C / A code chips. This precession allows the calculated autocorrelation value to change substantially linearly with time shift of the input signal, and with much smaller time shifts. Although the previous discussion has focused on the correlation of the binary C / A code, the sample precession procedure is generally applicable to multilevel signals.

Using a replicate code ondx and the Doppler frequency matching that of the noisy input signal, the serial or parallel correlator calculated the noisy samples from the displayed autocorrelation function. By choosing the sample rate of the signal so that there is an integer number of samples (for example, 2183) per C / A code period of 1.0 ms, the correlation results of, for example, twenty consecutive memory sequences of 1.0 ms data (using the same replicate code shift) produced twenty noisy samples from the same point on the C / A code autocorrelation waveform. During signal acquisition, the Doppler frequency replicates and the phase rarely matched exactly those of the signal, so quadratic exponentiation

ES 2 196 353 T3 of the consistent correlation result is necessary to ensure a positive correlation result. Figure 14 also shows typical coherent correlation sample points (x) of 1.0 ms squared calculated for various code shifts close to those of the received signal, and with code index and frequency and Doppler phase adjusting to that of the entrance signal. By averaging squared samples of the same code shift, a low noise estimate of the corresponding autocorrelation value is generated. Average autocorrelation samples are also shown in the figure. This averaging is the so-called non-coherent accumulation. The phase of the sample grid, relative to the triangle function, depends on the phase of the received waveform relative to the input A / D sampling clock.

In the waveform of Figure 14, the peak time of the autocorrelation is a parameter of interest, and this peak time is generally not found on the sampling grid. However, using the averaged autocorrelation values ​​surrounding the peak time, the peak time can be estimated by interpolation. Several interpolation procedures are known to those skilled in the art, but one procedure involves ordering the averaged autocorrelation samples according to the increment of the code shift and the search after the two largest adjacent entries. The left entrance (the first) and its left neighbor (points B and A respectively in the figure) together define a line, while the right entrance and its right neighbor (points C and D respectively in the figure) together define another line. These two lines intersect somewhere between the two original endpoints (A and D in the figure) when the SNR is high enough and the time associated with this intersection is the estimated peak correlation time. This procedure requires the solution of two simultaneous equations, it can be used either with the serial or parallel correlator procedures and would be calculated by means of the control 35 shown in figure 4 or in figure

5.

Figure 15 shows an acquisition system based on a low-power parallel correlator with full I / Q processing in which the RF / IF section (not shown) generates two quadrature output signals that are passed to the A / converters. D input 22 and 56. Control 35 applies power to the RF / IF section and input A / D converters 700 and 701. A / D converter 56 generates sampled I data that is stored in data memory I, while A / D converter 22 generates sampled Q data that is stored in data memory Q.

In one embodiment of the system, the input A / D converters sample the I and Q input signals periodically at approximately 2.183 million samples per second, producing 2183 samples per cycle of C / A code and approximately 2.1 samples per chip. code C / A. The samples are quantized at three levels and use the two-bit sign and magnitude representation, as described above. The data storage memories I and Q are each large enough to store the entire segment of data necessary for signal acquisition. For non-military use, this is generally 20 ms. After 20 ms (2183 x 20 samples) of I and Q data that have been stored, power is removed from the RF / IF section and the input A / D converters and acquisition processing begins. The I and Q data memories are each organized as twenty rows of 2,183 two-bit samples, with 2,183 simultaneous outputs (one full row). Four separate parallel correlators of three sequences are used, labeled II, IQ, QI, and QQ. Together, they comprise a complex parallel correlator 70. The parallel correlators each use sequence lengths of 2183 samples. Data memory I controls correlators II and IQ, while data memory Q controls correlators QI and QQ. Also, the Doppler I record controls the II and QI correlators while the Doppler Q record controls the IQ and QQ correlators. The order of data processing is set so that all desired replica code shifts are examined for a given replica code index and Doppler frequency before the code index or Doppler frequency is changed. Also, all desired code offsets are processed for a given row of stored I and Q data before the row is changed. This in all likelihood will minimize the combined memory read and code register shift power usage. Other memory row, code index and Doppler frequency processing orders are also possible, and the order can be chosen to minimize power consumption. The II and QQ coherent processing results are added to form II + QQ by connecting the associated sum lines, and the QI and IQ coherent processing results are summed by connecting their associated sum lines. For proper IQ processing, either the QI result or the IQ result must be inverted, and this can be done, for example, by reversing the direction of all sign switches in all analog converters of the chosen parallel correlator. In this embodiment, IQ-QI is formed.

With GPS signals, the SNR of each II + QQ and IQ-QI signal is typically 0 to 4 dB. These signals are adequately represented with only a few levels (e.g., -1, 0, 1) and are converted to digital format by A / D converters 700 and 701, and then squared separately by means of of quadraitic exponents 702 and 703. The squared signals are added by means of a digital adder 46 and stored in accumulator 44. Accumulator 44 has a separate storage location associated with each candidate code shift, and the correlation results for each code shift with different received data segments are accumulated at the associated storage location.

ES 2 196 353 T3

Figure 16 shows an embodiment of a superfast quadrotic A / D converter that combines the A / D and quadrotic exponentiation functions. Here, two comparators 61 and 62 determine if the analog value was above, below or between the two threshold values ​​associated with the analog representation levels -1, 0, +1. A logic unit 63 then assigns the common output state of the comparators with the appropriate digital value squared. If desired, this superfast quadratic converter is quickly generalized to more than three representation levels by adding more comparators and threshold voltages.

Sample rates, stored sequence lengths, and simultaneous memory output lengths can be chosen to best suit the GPS application. For example, by storing the entire data segment necessary for signal acquisition, the RF / IF section can be turned off after the shortest possible time (which corresponds to the reception of the necessary data segment). The stored data set can be used later for the processing of all SCD containers in the acquisition process. Alternatively, shorter memory can be used at the expense of having to keep the RF / IF section on for a longer time. For example, another attractive embodiment uses a “Ping-Pong” memory organization and is illustrated in Figure 19. Here, the I and Q data storage memories 192 and 194, respectively, are each 2.0 ms in length and are organized as two rows of 1 ms of parallel output (for example, 2183 samples in each row , like before). In both I and Q data channels, one row of data is accessed in parallel, for parallel correlation, while the other row of data is being written with digitized data coming from the RF / FI section. The full lengths of data stream I and Q are each processed in 1.0 ms segments. The full 20 ms data set is then processed for a single SCD container in approximately 20 ms. Since the entire data stream was not stored, the RF / FI section must be powered up and produce another entire stream if another SCD container is to be tested. On average, this increases the time the RF / IF section must be powered during signal acquisition. However, the reduction in memory size can be drastic. In some applications (for example military receivers under severe interference conditions), the GPS SNR is very low and the length of data sequence required for acquisition may be so long that storing the entire sequence is impractical. Under such circumstances, the Ping-Pong acquisition architecture is advantageous.

In some applications, it would be advantageous to further reduce the size of the data storage memories. With the two-segment memory organization (Ping-Pong), a long continuous stream of receiver output data can be processed. At the expense of a long acquisition time, the two-segment I and Q data memories 192 and 194 (Figure 19) can be reduced to single element memories by removing one of the 1.0 ms sections. of each memory. With this reduction, the 1.0 ms receiver output segments adjacent in time are not processed. Instead, only a single segment and a non-1 ms segment are captured in memory, and processed, and this lengthens the elapsed time to process a given number of received signal segments.

To further reduce the memory size and complexity of the parallel mapper, the length of the parallel mapper and associated registers and memory segments can all be made smaller than the desired coherent processing length. The desired coherent processing length can be achieved by processing multiple, shorter data segments and coherently combining their results. For example, a coherent processing length of 1 ms can be achieved by using a single 0.5 ms long parallel correlator on two adjacent 0.5 ms data segments and adding their results digitally, after A / D conversion. . Various combinations of correlator length, coherent processing length, memory segment numbers, and code offset search width are possible.

When the cost, size and power dissipation of a standard serial input, serial output (SISO) memory are sufficiently low, it may be advantageous to store the entire sequences of I and Q data necessary in said memory, turn off the RF receiver section. / FI, and use this memory in conjunction with Ping-Pong or uonic segment memory architectures to examine all desired SCD containers. The entire I and Q data sequences are read from SISO memory once for each SCD container tested, and this reading process will consume energy. However, since the RF / FI section is off, the power usage of the system will be reduced if the power dissipation of a SISO memory is low enough relative to that of the RF / FI receiver section. Other stored sequence lengths, simultaneous memory output lengths, and sample rates are also attractive.

In the two-sequence or three-sequence parallel correlator embodiments of Figures 8 and 11, the product of the associated data and the replicate samples is run in parallel within the correlator. This allows different Doppler containers to be tested for acquisition without having to collect new received data. Figure 20 shows an alternative one-stage embodiment of a parallel correlator and associated parallel memory in which data and Doppler samples are multiplied together by means of multiplier 2001 prior to storage in parallel memory 2002. This is advantageous as the multipliers of the parallel correlator are simplified in this way. Each correlator multiplier now multiplies its associated stored sample only by one uonic associated code bit. The combined multiplier and D / A converter for this realization

ES 2 196 353 T3 correlator is similar to the one shown in figure 18, except that the data-Doppler multiplier and signal converter AB, made up of exclusive NOR gates 1210 and 1212 and the AND gate 1211, is removed from the correlator and is carried in front of the data memory. The disconnected inputs to the exclusive NOR gates 1213 are coupled to the data memory outputs. With this embodiment, new data must be stored if a different Doppler container is to be tested for acquisition, but this is not a disadvantage in some applications.

The combined parallel correlator and parallel memory shown in Figure 20 can be advantageously used to form a simplified full IQ processing GPS acquisition engine. In the complete IQ acquisition engine shown in Figure 19, there are four separate parallel correlators coupled to the I and Q data registers and the I and Q Doppler (parallel memory) register, as well as the parallel code register. Figure 21 shows a complete IQ alternative realization that uses the simplest correlator and the memory organization of the figure.

twenty. In this embodiment, the four parallel Doppler-data memories store the Doppler-data product sequences II, QQ, IQ, and QI, respectively. Each parallel memory can be organized as a Ping-Pong memory or as a single segment memory, as described above. There is no separate storage of data and Doppler. Each parallel memory is connected to an associated parallel correlator, and each parallel correlator is also connected to the single parallel code register. The reduced interconnection between memory sections and correlator sections allows this IQ full processor embodiment to have a simpler (ie, smaller and less expensive) integrated circuit implementation.

The complexity of the embodiment of Fig. 21 can be further reduced by performing the addition II + QQ and the subtraction QI-IQ before data storage. Before storage, the addition and subtraction output signals can often be rounded or truncated to two bits with little SNR degradation. Then, as shown in figure 22, only two data memories are needed - Doppler (one for the II + QQ data and the other for the QI-IQ data), two parallel correlators and a code register. Each data-Doppler memory can be organized as a ping-pong memory or as a uanic segment memory, as described above. Other organizations of parallel correlator, parallel memory and sequence multiplications are also possible and advantageous.

Figure 17 shows a data memory organization, replication generation, combined parallel correlator (for correlation II process only) that reduces the number of code registration offsets to 2183 offsets per code / Doppler combination and eliminates the need for of any non-coherent accumulation RAM. The bottom line is that the input memory must now be segmented to allow simultaneous access to all read data. These data are applied, in 1.0 ms blocks, to separate parallel correlators. These parallel correlators are all controlled by the same code and Doppler replicas, and generate simultaneously (in a complete code cycle) the twenty independent 1.0 ms correlation sequences that were previously accumulated sequentially in time. Separate quadratic exponentiation A / D converters convert the analog correlation sequences to digital format in which an adder tree 80 forms the accumulated correlation sequence. The accumulation RAM can be completely avoided by performing the peak lookup and interpolation process on the accumulated correlation sequence as it is generated. In this arrangement, the code and Doppler logs now control twenty loads where they previously controlled one, which can override the energy reduction.

When using the parallel correlator with data registers and replica registers for the case of two sequences, or with data registers, Doppler and code for the case of three sequences, it is advantageous to minimize the energy used in loading (writing) the different registers. . In another aspect of the present invention, the loading of the various registers is converted into a low energy operation using a scanner shift register to determine which data logging stages, Doppler and code are going to be written at each moment. Figure 23 shows a scanner shift register 304 along with data register 300, Doppler register 301, and code register 302 for the three sequence case. In one operating procedure, the samples arrive sequentially for each of the digital data, Doppler, and code sequences, and the sample rates are the same. As samples arrive for each respective sequence, they are written to the corresponding sequence locations in their respective registers. In synchronization with the arriving samples, a simple lolagic 1 is moved along the binary scanner record, making it possible to write the arriving samples at the corresponding sequential locations of the respective records. The write operation is very low energy as only two adjacent scanner register locations change their stored value at each shift, and neither of the respective registers is shifting during the write operation.

While the invention described is applicable to C / A GPS signal acquisition, it can also be used to dramatically reduce both the time and energy required to directly acquire military P (Y) GPS signals without first acquiring C / A signals. By altering the satellite code generator component of the code / Doppler generator of Figures 4 through 5 to generate the P (Y) code instead of the C / A code, the procedures and architectures described in this document become applicable for the case P (Y).