Low power parallel correlator for measuring correlation between digital signal segments

ES 2 168 656 T3

DESCRIPTION

Low power parallel correlator to measure the correlation between digital signal segments.

Background of the invention

Field of the invention

This invention relates generally to spread spectrum communication systems, and more specifically, to an architecture and a low power signal processing method for spread spectrum receivers.

Background description

Spread spectrum communication is advantageous in communication applications that require high reliability in a noisy environment. Often the dominant noise is man-made interference, either intentional or accidental. In a specific application, the communications environment can include many potential reflectors, leading to significant multipath interference. Such multipath interferences topically allude to deep nulls in the form of frequency selective fading. Spread spectrum communications are an excellent countermeasure to these difficulties.

There are several types of spread spectrum systems, including direct sequence spread spectrum systems, frequency hopping systems, time hopping systems, pulse (or chirp) modulated frequency systems, and various hybrids. Of all these, direct sequence spread spectrum (DSSS) systems and frequency hopping systems are perhaps the most widely implemented. The following discussion focuses on binary DSSS systems.

In binary DSSS communication, a broadband carrier signal is modulated by means of a narrowband message signal. The broadband carrier is topically generated by a biphase modulation of a uonic frequency carrier using a pseudo-random noise (P / N) binary code sequence. The P / N code is often generated using one or more high-speed shift registers, each having module-two feedback according to a primitive polynomial. The generated high-speed P / N code is then applied to a balanced modulator (multiplier) whose other input signal is the narrowband carrier. The balanced modulator output signal is a broadband signal often referred to as a "broadband carrier." To communicate data, the broadband carrier is biphase modulated by a stream of binary message data. The data rate of the message is generally much lower than the "chunk" or symbol rate of the P / N code, and the edges of the data and the code chunk are generally synchronized. The ability of the DSSS technique to suppress interference is directly proportional to the ratio of the code fragment rate to the data rate. In many applications there are thousands of code snippets per message bit.

A DSSS signal can be received first by downshifting the baseband signal by multiplying it by a locally generated replica of the original narrowband carrier (eg, a suitably tuned local oscillator). If the frequency (and phase) of the carrier replica are the same as that of the original received narrowband carrier, then the output signal of the multiplier will be a bipolar "wideband data" stream that will be the product of the code. bipolar P / N and message data streams. The P / N code is eliminated by multiplying the broadband data stream with a locally generated replica of the P / N code that is time aligned with the received P / N code. This is the data de-spreading process that produces the original message data stream at the output of the multiplier.

In the data de-spreading process, the broadband data power spectrum is centered within the original narrower data bandwidth, raising the data power level much more above the background noise in that bandwidth. . The amount by which the power level is increased is called the processing gain and is directly proportional to the ratio of the code rate to the data rate. Furthermore, any received narrowband interference is spread by means of replicate code modulation, and this greatly reduces the interference power level in the data band.

A difficult task often associated with receiving DSSS signals is to generate the carrier replica with both the appropriate frequency and carrier phase and generate the P / N code replica at the proper speed and time alignment. adequate (displacement). In many DSSS communication systems, the necessary carrier frequency, carrier phase, and P / N code shift are not known in advance at the receiver and these parameters must be determined by trying different values ​​until a large signal is observed at the output. of the data filter. This is known as the search or acquisition process, and it is said that a DSSS signal will be acquired when the appropriate frequency, phase, and code shift have been determined.

In many DSSS applications, DSSS signal levels are well below ambient noise and / or interference levels and are not detectable until proper de-expansion and low-pass filtering is done. When the received signal-to-noise ratio (SNR) is very low, the filter must be very narrow to achieve the necessary processing gain for signal detection and acquisition. Because a narrow filter requires a long integration period, the result of multiplying many received P / N code samples by the corresponding replica P / N code samples must accumulate before the detection decision can be made. This multiplication and accumulation is a cross correlation between the

ES 2 received P / N code sequences and replicates P / N code sequences, and the sequences may have to be long for low SNR signals.

The use of the DSSS method enables multiple users to simultaneously share the same broadband channel using the code division multiple access (CDMA) technique. With this technique, each transmitter uses a different P / N code so that the cross-correlation between different codes is substantially zero. A receiver selects and detects a particular transmitted signal by choosing the appropriate P / N code and performing the acquisition search. In some cases, it is unknown which transmitter may be transmitting and the acquisition search must include examining different P / N codes from a known list. When there are many different codes, code offsets and carrier frequencies must be examined and the SNR is low, the acquisition task may be consuming both time and energy. An important aspect of the present invention is the reduction of time and energy consumed in the acquisition process of the DSSS signal.

For example, a description of direct sequence systems and other types of spread spectrum communications systems can be found at Spread Spectrum Systems, 3^toEdited, by Robert C. Dixon, John Wiley & Sons (1994), and Spread Spectrum Communications, Vol. II, by MK Simon et al., Computer Science Press (1985). For example, a description of CDMA techniques can be found in CDMA Principles of Spread Spectrum Communication, by Andrew J. Viterbi, Addison-Wesley (1995).

The popular and ubiquitous Global Positioning System signals are an important application of DSSS communications. In recent years, Navstar Global Positioning System (GPS) satellites have been launched at medium altitude Earth orbits in six orbital planes, each with an inclination of 55^or with respect to the equator. The entire constellation of GPS satellites consists of twenty-one satellites and several spare satellites. The signals transmitted from these satellites allow a receiver close to the ground to accurately determine the time and its own position. Each satellite transmits data that provides accurate knowledge of the satellite's position and allows the distance from that satellite to the user's receiver antenna to be measured. With this information, from at least four GPS satellites, the user can calculate his own position, speed and time parameters through known triangulation techniques (ie, the navigation solution). Typically, seven, but a multiple of four satellites are observable by a user anywhere on or near the earth's surface, if the user's receiver has an unobstructed view of the sky, up to very close to the horizon line. Each satellite transmits signals on two frequencies known as L1 (1575.42 MHz) and L2 (1227.6 MHz) and all satellites share these frequencies using the DSSS CDMA techniques described above 656 T3 4.

More specifically, each satellite transmits a single high resolution DSSS signal on the L2 frequency and the same signal plus another low resolution DSSS signal on the L1 frequency. The low resolution DSSS signal consists of a P / N code with a fragmentation rate of 1023 MHz and a repetition period of 1.0 ms, and a sequence of message data (the NAV data) with a rate of 50 bits. per second. The high resolution DSSS signal uses a P / N code with a fragmentation rate of 10.23 MHz and a repetition period greater than one week. The same NAV data stream is used on all DSSS signals from a given satellite. The NAV message for a given satellite contains the GPS signal transmission time, ephemoerid data (position) for that satellite, almanac data (a reduced precision ephemoerid) for all satellites in the constellation, and the handover word used. in connection with the transition from low resolution to high resolution code tracking. The low and high resolution codes are known as the heading / acquisition (C / A) and precise (P) codes, respectively.

After acquisition, the offset of each code, together with the signal transmission time of the NAV data, enables a receiver to determine the interval between the corresponding satellite and the user. By including both the P code and the repetitive C / A code in the transmitted signal, faster hierarchical acquisition of the P code is made possible, and two layered levels of global navigation service can be provided. The P code can provide positions that have an accuracy of approximately 3 meters, while the C / A code produces accuracies of the order of 30 meters. Typically, the low-resolution service was unrestricted, while the high-resolution service was militarily restricted by encryption, or otherwise, by controlling knowledge of the high-resolution P / N code.

In a topical military receiver, the C / A code is acquired first. After this, the handover word is read from the NAV data stream. The handover word specifies the approximate offset of the P-code relative to GPS time (as transmitted in the time setpoint), and its use will considerably reduce the number of different code offsets that must be searched for during code acquisition. P. Acquisition of the C / A code is substantially easier than direct acquisition of the P code, since the C / A code repeats every 1.0 ms and there are therefore only 1023 different code offsets to search (two times this if the search is done in the usual half-chunk steps).

The received GPS signals are generally shifted in frequency from the nominal carrier frequencies L1 and L2 as GPS satellites move in orbits at several kilometers per second, producing a significant Doppler shift. Satellite trajectories are generally known from before5

ES 2 168 656 T3 hand and shifted Doppler carrier frequencies are therefore predictable if the position of the GPS receiver is known. Unfortunately, the position of the receiver is not known in advance, and there is often substantial local oscillator error using cheap receivers. The resulting uncertainty in the received carrier frequency (i.e. at the necessary replica carrier frequency) can be large (e.g. ± 7.5 kHz), and this frequency range may have to be sought during the data acquisition process. the GPS signal. The frequency search or Doppler search is generally done by repeating the cross-correlation of the received sample and the local P / N replicas sequences for different frequencies of the local oscillator (carrier replica). The spacing between frequency steps is made small enough to avoid signal loss when using long cross-correlation integration times (narrow filter bandwidths). Long integration times improve detection of low SNR signals. With typical civil GPS applications, 1.0 ms cross-correlation integrations are used (a single cycle of C / A code), achieving an equivalent Doppler filter bandwidth of approximately 500 Hz. ± 7.5 kHz with thirty steps of 500 Hz. GPS acquisition brings with it a search on the satellite code, code shift and Doppler frequency.

A master control station (MCS) and several monitoring stations constitute the control part of the GPS system. Monitoring stations passively track all GPS satellites in sight, collecting interval data and satellite clock data from each satellite. This information is passed to the MCS where future satellite ephemoerides and clock drift are predicted. Ephemoeris and updated clock data are uploaded to each satellite for retransmission on each satellite NAV message.

During operation, a typical GPS receiver does the following for each of at least four satellite signals:

1) acquire the DSSS signal,

2) Synchronizes with the NAV data stream and reads satellite time, clock correction, ionosphoric delay and ephemoerid data,

3) calculate the position of the satellite from the ephemoeris data,

4) reads its own receiver clock to determine the receiver time associated with the receipt of the time setpoint generation, and

5) estimates the travel time of the signal by subtracting the value of the hour setpoint from the associated receiver time.

This time difference is multiplied by the speed of light to obtain an estimated interval for the satellite. If the GPS receiver had a clock that was perfectly synchronized with the satellite clocks (or if the error was known), only three of these interval estimates would be needed to precisely locate the receiver. There is, however, a clock handover (slow shift error) due to the fact that the GPS receiver topically uses cheap glass clocks, while satellites are equipped with atomic clocks. This clock handover is known, and its effect is eliminated by measuring the interval (travel time) of four GPS satellites and using these measurements in a system of four equations with four unknowns (receiver x, y, z, and time). For general information on GPS, reference is made to the reader of Tom Logsdon's book The Navstar Global Positioning System, by Van Nostrand Reinhold (1992).

A preferred application of the present invention is the location and tracking of goods such as trains, ship or freighter containers, trucks, trucks and the like, using GPS. In this application, GPS receivers are generally powered by batteries since a separate power source is generally not available. There are advantages in increasing the useful life of the batteries by reducing the energy consumed by the GPS receiver.

In a topical spread spectrum receiver, the front end of the receiver (that is, the RF and IF electronics) consumes a large amount of power while it is on. This results in high power consumption if signal acquisition and timing take a long time. Most GPS receivers of the early art do not have signal storage (memory) and must process the received signals in real time. In addition to this, they use either a sequential search or search a small number of satellite code shift Doppler containers (SCD) simultaneously to achieve signal acquisition. Such receivers must continuously receive and process each satellite signal until its SCD container is identified and the necessary NAV data is decoded. With a sequential search, power consumption is high as a substantial amount of time elapses before the SCD container associated with each GPS signal is identified. Alternatively, multiple SCD containers can be searched in parallel to reduce elapsed time, but power consumption is still high as existing processing methods are not very low power methods. Furthermore, the degree of parallelism was very limited with existing processing methods due to the large amount of circuitry involved.

In a system of the invention, a facility or central station must track multiple assets (eg, trains). Each tracked object carries a GPS receiver that processes data from various visible GPS satellites; however, no precise position determination is made on the receiver. Instead, only partial processing is done at the receiver and the

ES 2 168 656 T3 intermediate results are transmitted from the asset to the central station. These intermediate results do not require decoding of the navigation data or other data from the GPS signals. In this way, this system allows feeding the GPS receiver and the signal processor only the time necessary to acquire the satellite signals (determine the SCD containers). With this system, the dominant power consumer is the acquisition process, and the GPS receiver power used on each tracked asset will be considerably reduced if the signal acquisition time and power are significantly reduced.

US Patent Number 5,420,593 to Niles uses a memory to store an interval of the received signal that contains various GPS satellite signals. The received signal is sampled and stored in memory at one rate and then read from memory at another faster rate. While the reading is taking place, the signal is digitally processed to acquire it and synchronize it with the signals received from the GPS satellite. This allows a shorter elapsed time for the acquisition of GPS signals. However, the receiver is not turned off immediately after signal storage, and low-power signal acquisition is not used. Furthermore, the substantially reduced power consumption is not achieved.

US Patent No. 5,225,842 to Brown describes a GPS-based centralized asset tracking system that reduces the cost of GPS receivers for each asset being tracked by omitting the calculation of the navigation solution on the asset. . Each property carries a GPS receiver that processes the signal from several visible GPS satellites and forwards the processed result to the central station where the precise navigation solutions of the property are calculated. This system does not substantially reduce the energy consumed by the GPS receiver in the property and does not substantially increase the battery life of the property or reduce the time between service to replace the batteries. In addition to this, low power parallel correlation is not used. IEEE Document Transactions On Applied Superconductivity Vol. 5. 1995, March, Num. 1, pages 14 to 18, from Yuh PF et al "256Stage Superconductivity Digital Correlator With Analog Output" describes a parallel correlator consisting of a memory means for storing the incoming encoded signal data, the offset means for retarding or offsetting the code signal data, and the means of multiplication and the means of addition.

Summary of the invention

An object of the present invention is to provide a direct sequence spread spectrum (DSSS) signal processing architecture that allows the receiver to be turned off during most of the reception acquisition phase, thus allowing a significant reduction in time. of the associated receiver's mezzanine processor.

Another object of the invention is to provide a signal processing architecture that allows low power consumption during the acquisition phase of the DSSS signal reception.

A further objective of the invention is to provide a low power parallel correlation method that is rapidly materializable with available integrated circuit processes and uses low energy to acquire DSSS signals.

Another object of the invention is to provide a GPS signal processing architecture that allows to perform P / N code searches and Doppler searches (associated with the acquisition process) with a standard sequential processor (that is, relatively slowly and with a small amount of time). processing resource) without the need for the receiver's mezzanine processor to be turned on during the search process.

A further object of the invention is to provide a GPS signal processing architecture that requires little energy to track a asset using GPS.

Another further object of the invention is to provide a signal processing architecture that can dynamically exchange coherent and non-coherent integration times in the manner necessary for a particular received signal-to-noise ratio (SNR).

A further object of the invention is to employ a low receiver output sample rate to obtain an accurate sub-fragment DSSS signal acquisition timing.

Another further objective of the invention is to provide a GPS signal processing architecture that displays rapid acquisition of GPS satellite signals.

A further objective of the invention is to provide a GPS signal acquisition method that allows fast and low-energy acquisition of the signal even when the GPS receiver uses a cheap local oscillator that may be inaccurate.

In accordance with one aspect of the invention, a low-power, high-speed parallel correlator is used during DSSS signal acquisition to reduce the acquisition power consumption. The power consumption of the receiver is also reduced because the time that the receiver must be in the on state is reduced due to the speed of the parallel correlator.

According to another aspect of the invention, a time interval of the receiver's output data is sampled and stored in a memory and then the receiver is turned off. The time interval is long enough to allow acquisition of any of the received CDMA DSSS signals contained in the stored receiver output data. The stored receiver output data is recalled from memory as many times as necessary to acquire each desired CDMA signal. To keep processing power consumption low, a low-power parallel (partially analog) correlator can be used in the acquisition process. This approach uses much less energy than existing digital cross-correlators.

The centralized GPS tracking system

ES 2 168 656 T3 according to the invention allows the tracked goods to consume very little energy and to use a receiver with a cheap local oscillator. The use of a parallel correlator allows the local oscillator to be imprecise because many frequencies are quickly searched during the acquisition process using low power. In addition, the use of a parallel correlator allows the reception and demodulation of the NAV GPS data that should be avoided, also reducing the average receiver time. The almanac is no longer needed to support a reduced satellite search time because the parallel correlator can quickly search over all satellite codes. Because the navigation solution is not needed in the tracking units, only limited processing is needed which consumes very little power, with the navigation solution being generated at the central station. The invention will be carried out in accordance with the attached independent claim 1.

Brief description of the figures

Features of the invention believed to be novel are set forth in the appended claims. The invention can be better understood, however, together with its objectives and advantages, by referring to the following description, taken together with the accompanying drawings, in which:

Figure 1 is a block diagram of a remote monitoring system in accordance with the present invention;

Figure 2 is a block diagram of a tracking unit on an object to be tracked according to the invention;

Figure 3 is a block diagram of a conventional sequential acquisition architecture;

Figure 4 is a block diagram of the sequential signal processing architecture in accordance with one embodiment of the invention;

Figure 5 is a block diagram of the parallel signal processing architecture according to another embodiment of the invention;

Figure 6 is an illustration of the parallel correlation process between stored data and sliding replica waveforms.

Fig. 7 is a block diagram showing a structure for generating the replica sequence;

Figure 8 is a block diagram showing a short segment of one embodiment of the data memory, mirror register and parallel correlator using the mirror generation method of Figure 7;

FIG. 9 is a block diagram showing a one-stage embodiment of the two-sequence parallel correlator of FIG. 8;

Figure 10 is a block diagram showing a method for generating separate Doppler code and replicate sequences;

Fig. 11 is a block diagram showing one embodiment of the data memory, cocode replicate record, Doppler replicate record, and parallel correlator using the replicate generation method of Fig. 10;

Figure 12 is a block diagram showing an embodiment of one of the stages of the three-sequence parallel correlator of Figure 11;

Figure 13 is a schematic diagram illustrating the principles of differential digital to analog converter and summation in accordance with one aspect of the invention;

Fig. 14 is a graph showing the noisy and noisy autocorrelation waveform for a short section of the 1.0 ms P / NC / A code sequence near the correlation peak;

Figure 15 is a block diagram showing an acquisition system based on a low power parallel correlator with full I / Q processing in which the RF / IF section generates two quadrature outputs;

Figure 16 is a block diagram of one embodiment of a quadrature A / D converter;

FIG. 17 is a block diagram of a combined parallel correlator, data memory, replica generation organization that reduces the number of code register shifts by code / Doppler combination.

Figure 18 is a schematic diagram of a three-sequence multiplier digital-to-analog converter cell;

Figure 19 is a schematic diagram of a ping-pong data memory organization;

Figure 20 is a schematic diagram of a parallel correlator with pre-multiplication of Doppler data;

Figure 21 is a block diagram of a complete IQ processor with Doppler data pre-multiplication; Y

Figure 22 is a block diagram of a complete IQ processor with complex pre-multiplication of Doppler data.

Fig. 23 is a block diagram of the low energy register write method employing a scan shift register.

Detailed description of the preferred embodiments of the invention

Figure 1 illustrates several GPS satellites 12, an object (well) being tracked, such as a railroad carrying a tracking unit 14, and a central station 16. As described above, each satellite 12 transmits a signal that uses a GPS receiver in tracking unit 14 to measure propagation delay (and delay velocity, if the velocity of the asset is desired) from that satellite to the receiver antenna. The satellite signals also include the periodic repetition of the NAV data that are necessary to determine a navigation solution from the measured time delays. Due to the low speed (50 bits per second) of the NAV data in the GPS signal, a receiver must be active for a substantial period of time (from one to several minutes) if the NAV data is to be collected. In addition, the particular satellite NAV data changes over time and MCS GPS monitors these changes and provides near hourly updates to the NAV data. To ensure accurate navigation solutions, a navigation system

GPS-based ES 2 168 656 T3 must use NAV data that is not older than four hours. If asset positions are to be monitored more frequently than four hours, new NAV data should be collected at least every four hours. Maintaining the NAV data then requires an average of approximately fifteen seconds of receiver operation per hour, and this carries with it a significant power requirement if done on each tracked asset.

According to one aspect of the present invention, the navigation solution is calculated at the central station rather than at the asset. None of the NAV data is needed on the tracked asset. Only the data relating to the propagation delay of the GPS signal between each satellite and the property needs to be measured at the well, and this data is then sent to the central station. NAV data can be determined at central station 16 by using a standard GPS receiver there, or by communicating with an appropriately located standard GPS receiver. If desired, NAV data, or navigation solutions can be communicated to tracked assets through a higher speed communications link that requires less power to receive at the asset. Without the need for decoding of NAV data on the property, the acquisition of the GPS signal becomes the main task of GPS processing on the property, and the feasibility of the centralized tracking system is greatly improved by the methods of monitoring. low energy acquisition of the invention.

As shown in figure 2, a train tracking unit 14 consists of a receiver 2 responsive to the signals received at the antenna 5 from the GPS satellites, a processor 3, and a transmitter 4. The received signals are processed in the processor 3 to determine and use the propagation time differences between the signals received from the GPS satellites. Through the use of time differences, the need to know the timekeeping of the GPS signal in the well is alleviated, and the decoding of the data stream is therefore unnecessary in the well. Without the need to decode the GPS data stream, the receiver processing simplifies the acquisition of the GPS signals and the calculation of the important time differences (and the Doppler frequency differences, if the velocities of the well are to be determined). from the acquisition results. The calculated time differences, and the data identifying the satellites associated with the differences, are transmitted by means of a transmitter 4 from an antenna 6 to the central station. A description of a centralized tracking system in which the acquisition of the GPS signal is a major part of the asset's GPS power budget can be found in the co-pending application serial number 08 / 456.229 of Harrison, Pradeep, Brooksby and Hladik, referred to above.

Figure 3 shows a conventional serial acquisition architecture employing a serial correlator. In a conventional GPS receiver, signal acquisition is followed by carrier and P / N code synchronization and NAV data demodulation, but the modes for these processes are not shown in Figure 3. The signal acquisition architecture consists of an RF / IF (radio frequency / intermediate frequency) section 21 that includes an antenna 211, an RF amplifier 212, a mixer 213 and a local oscillator 214, and a low-pass filter 215 that feeds a signal received and converted inferiorly to an analog-to-digital converter (A / D) 22. The A / D converter 22 typically samples and converts to an integer multiple of the replica C / A code chunk rate and supplies a digital sequence to a digital serial correlator 23. The serial correlator 23 computes the inner product of an output subsequence receiver input from the A / D converter 22 and a replica C / A code subsequence originating from a code / Doppler (or replica) generator 24. The inner product is made serially by first multiplying the first terms of the two subsequences in a multiplier 231 and storing the result in a coherent accumulator 232, then multiplying the second terms of the two subsequences and adding their product to the coherent accumulator 232, etc. . The inner product is made in real time, as subsequence terms are available from the A / D converter 22. As is conventional, subsequences generally span a single period of the repeating C / A code. Once an inner product has been calculated, the coherent accumulator contains a sample of the cross-correlation of the received subsequence with a C / A code cycle of the replica signal, for the particular C / A code, code offset and frequency. Doppler generated by the replica generator. The inner product operation is repeated with several subsequent subsequences coming from the A / D converter 22 while using the same replica C / A code subsequence. The subsequent inner product results are then squared by a quadratic exponent 29 and summed in a non-coherent accumulator 30, producing a non-coherent integration of the coherent processing results. The output signal from the non-coherent accumulator 30 is examined by means of a threshold detector 31 and an "acquired signal" command is generated if the signal level in the non-coherent accumulator 30 is sufficiently high. When a signal is acquired, a control 27 monitors the associated C / A code index (satellite index), code shift and Doppler frequency, and commands the code / Doppler generator 24 to change to a C / A code. different (for a different GPS satellite) and start another search, or stop if enough satellite signals have been acquired. If a signal has not been acquired after several subsequences have been processed from the A / D converter 22, then the control 27 commands the code / Doppler generator 24 to change to a different C / A code, code shift, or frequency. Doppler. While each satellite signal is acquired, the control 27

ES 2 168 656 T3 supplies the associated code index, code shift and Doppler frequency to a GPS signal timing and NAV data processing units (not shown).

The searchability of all feasible C / A codes, code offsets and Doppler frequencies should be facilitated. Control 27 selects the desired C / A code and code offset by commands to a satellite code generator 243 and offset generator 244. The offset generator 244 provides for a time offset of the generated code, a replica from the satellite code generator 243, relative to the bit stream from the A / D converter 22. An I / Q Doppler generator 242 generates a digital representation of the sinusoid representing the combination of Doppler shift and local oscillator frequency error assumed by control 27. The replica signal is generated by a multiplier 241 as the product of this sinusoid and the C / A code replica. To ensure the detection of the GPS signal, the RF / FI section 21 must generate both the output signal in phase (I) and the output signal in quadrature (Q) (not shown in figure 3), and the two signals they must be processed for signal acquisition. Furthermore, each of the RF / IF output signals I and Q must be processed with the sinusoidal Doppler components, both I and Q, as is known to those skilled in the GPS art.

The conventional approach shown in Figure 3 requires processing as soon as the receiver output data is available from RF / IF section 21, and processing is restricted by the code rate of the received signal. In figure 4 the architecture for an improved sequential signal acquisition processor according to one of the aspects of the invention is shown. The architecture is similar to that shown in figure 3 except that a signal storage memory 33 has been added and the power for the RF / IF section 21 is now controlled by the control 35. The GPS signal supplied by the RF / FI section 21 is converted to digital format by an A / D converter 22, but now the A / D sampling rate can be set to a low non-integer multiple of the C / A code rate. The memory 33 stores a sufficient length of the input signal for signal acquisition, and allows the RF / IF section to be turned off after storage. The acquisition process then proceeds to the reading and possibly rereading of the data stored in memory. Therefore, the power consumption is significantly reduced as the RF / IF section 21 consumes significant power. In addition to this, the acquisition process is no longer restricted by the code rate of the received signal, as was noted in early technique. The non-integer input A / D sample rate allows the acquisition processor to determine the precise GPS signal propagation time differences (needed to determine the location solution) while using a much lower sample rate. Also, when the SNR input is not too low, or when the precision requirements are not too high, the low non-integer sampling rate allows time differences that are to be determined with sufficient precision than normally to be avoided. require conventional carrier and P / N code synchronization processes (e.g. Costas phase locked loop for carrier tracking, and the hooked lead-lag loop for code tracking).

An advantage of storing the received signal segment in memory and rereading memory as needed to process different SCD containers is that the correlation process can take place over a period of time without loss of precision in signal acquisition due to the instability or inaccuracy of the local oscillator. Furthermore, if the stored signal is also used to calculate from it the time delays necessary for the navigation solution, there is no need to maintain a precise timing between the acquisition and tracking phases of the GPS reception. For applications where the navigation solution is not needed immediately after the measurement (for example, asset tracking), a very low power GPS receiver can be built using a very low power integration process for the sequential correlator ( and other circuits), in combination with a low-power data storage memory. Large-scale, very low-power integration processes are being developed in industry (eg, complementary 0.35 micron 1.5V metal oxide semiconductors, or the CMOS process).

With the GPS system, as in most DSSS systems, the SNR is very low before the signal is processed, and a significant period of the received signal must be processed to produce the high peak of SNR correlation necessary for adequate detection. signal via a threshold detector 31. For normal civil GPS applications, approximately 20 ms of signal from the RF / IF section 21 must be stored and processed. To preserve a small memory, the signal from the RF / IF section 21 is sampled at a low rate and quantized with only a few levels. For civil applications, conventional GPS receivers topically achieve a GPS position (location) accuracy of 30 meters. GPS positions with this precision can be calculated from signal code offsets that are measured with an error of less than one tenth of a C / A code chunk. The signal code shift is measured by recording the replica signal code shift associated with the crossover correlation peak. In one embodiment of the invention, a sequence of results is generated from a non-coherent accumulator 30 in order to increase the replicate code shift while keeping the code onyx and the Doppler frequency constant. If a result of a large correlation is observed, an interpolation algorithm is applied to the sequence of results and is

ES 2 threads the code offset associated with the correlation peak. A code shift precision of one tenth of a code snippet is achieved while the signal is sampled at approximately twice the C / A code snippet rate. Some conventional GPS receivers do not achieve the desired tenth fragment accuracy during signal acquisition; Instead, some do it during code synchronization by sampling the signal at twice the C / A code chunk rate and tuning the sample phase as part of the lead-back delay locked loop. Alternatively, other conventional GPS receivers achieve a fragment timing accuracy of one tenth by sampling the signal at ten times the C / A code fragment rate and recording the code offset, in one tenth fragment increments. , which produce the largest correlation peak. A reduced sample rate requires less memory and slower processing speeds.

The SNR at the input of the A / D converter 22 is well below zero, so that little signal degradation occurs when the A / D converter uses only three appropriately chosen representation levels. Each example can be properly encoded in magnitude and sign format using only two bits of data. To ensure signal detection, both RF / IF I and Q output signals must be generated, stored, and processed (only one RF / IF channel is shown in Figures 3 and 4). The use of three or more levels of representation can provide substantial resistance to interference from signals other than GPS signals, as is well known to those skilled in the GPS technique. However, a smaller data memory is required if only two representation levels (one bit) are used for the I and Q signals, and this has a cost advantage in some applications. In one embodiment of the invention, the RF / IF output signals I and Q are digitized and stored simultaneously, and the length of the data memory is sufficient to preserve the complete data sequence necessary to achieve acquisition (e.g. example, 20 ms). With 1023 C / A code chunks per millisecond and sampling both RF / IF signals, I and Q, at two samples per code chunk with approximately two bits per sample, approximately 170,000 bits of storage are needed for the signal segment of 20 ms. For convenience, the I and Q data can be considered as stored in separate I and Q memories. When the required data has been sampled, converted and stored, the receiver can be turned off and the recorded data can be processed.

In the sequential method of this invention, the stored data is reread (read) once during the correlation process for each combination of code, code shift, and Doppler shift. In the system of Figure 4, the sequence of stored digital data samples are read from memory 33,

656 T3 16 one at a time. Each sample of the memory sequence 33 is multiplied by the corresponding sample of the code generator / Doppler sequence 24 at multiplier 231, and the result is accumulated in the coherent accumulator 232. The sequence or data segment of the code generator / Doppler or replica generator is modeled for a particular code, code shift, or Doppler frequency under test. The length of the memory stream processed in this way is the coherent integration length, and is chosen topically as a full cycle of C / A code, which is 1.0 milliseconds. Several (eg, twenty) 1.0 ms memory data segments are processed in this manner without changing the replica sequence. After each 1.0 ms segment has been processed, the value stored in the coherent accumulator 232 represents the cross-correlation between the 1.0 ms replica and the data segments (sequences). This value is squared by the quadratic exponent 29 and added to the non-coherent accumulator 30. Before the first 1 ms segment is processed for a given replica signal, the non-coherent accumulator 30 is reset to zero so that the final accumulated result represents the degree of total correlation for the particular code, code shift, and Doppler frequency. specified by the replica signal. Similarly, the coherent accumulator is reset before each 1.0 ms segment is processed. The threshold detector 31 monitors the degree of correlation and produces an "acquired signal" signal if the degree is greater than a specified threshold. When reception of the "acquired signal" signal occurs, control 35 performs a simple peak search and interpolation algorithm (described later) to find the best estimate of the code shift associated with the given code ondex and frequency. Doppler under examination. Control 35 selects another combination of code, code shift, and Doppler frequency and commands the replica generator to alter the replica signal to reflect this change. The signal acquisition process is repeated for several replica signals corresponding to the codes, code shifts and Doppler frequencies to be searched, and stops when the desired number of GPS signals (different C / A codes) has been acquired. Control 35 then outputs as an output signal the code indices, estimated offsets, and Doppler frequencies associated with the acquired signals.

Memory data I and Q can be processed sequentially, (eg, process all I data, and then process all Q data) using a digital correlator 23 as shown in Figure 4. Alternatively, the data from I and Q memory can be processed simultaneously using separate digital correlators. In any case, to ensure signal acquisition, I and Q Doppler processing must be performed on both the I memory data and the Q memory data. In this way, there are four IQ combinations and these can be processed sequentially with a single digital processor, or simultaneously with

ES 2 168 656 T3 various correlators. In a sequential method, the correlation result for the entire sequence of memory data with a given replica code index, code shift, and Doppler frequency is calculated as follows: first, the coherent and non-coherent accumulators are reset to zero. . The memory data I is then processed with the Doppler replica I and the result of the correlation is accumulated in the coherent accumulator. The memory data Q is then processed with the Doppler replica Q and the result of the correlation is also accumulated in the coherent accumulator. The total result of the coherent accumulation is then squared by means of the quadrotic exponent 29 and added to the non-coherent accumulator 30. The coherent accumulator is then reset. The next thing that is done is that the memory data Q is processed with the Doppler replica I and the result of the correlation is accumulated in the coherent accumulator, then the memory data I is processed with the Doppler replica Q and the result of the correlation is reversed (multiplied by -1) and also accumulates in the coherent accumulator. The total result of the coherent accumulation is then squared by the quadrotic exponent 29 and added to the non-coherent accumulator 30. This process is repeated for each 1.0 ms memory data segment, without reinitializing the non-coherent accumulator between segments, and requires two complete read cycles of both the I data and the Q data. Acquisition time and energy can be reduced by using separate I and Q Doppler generators 242, multipliers 241, and digital correlators 23 to process all four IQ combinations simultaneously.

In convenient translation, the code / Doppler generator 24 is comprised of an I / Q Doppler generator 242, a satellite code generator 243, an offset generator 244, and a multiplier 241, as shown in Figure 4. The Doppler I / Q generator 242 generates a digital sequence representation of a sine or cosine wave at the desired frequency relative to the sampling rate, and can, for example, be implemented with a read-only memory (ROM) driven by a address counter. The frequency and phase (I or Q) of the sinusoid can be selected by controlling the order in which the stored sinusoidal samples are read (for example, by decimating the address and by selecting the starting address, respectively ). Other digital sinusoidal generators are also known to those skilled in the art. For GPS C / A codes, a well known state machine can be used to generate the C / A code bits in the proper order. The Doppler sinusoid and C / A code values ​​are multiplied by multiplier 241 to produce the replicate signal. Provision for searching all feasible code offsets is facilitated by a time offset of the stored code replica of satellite code generator 243 using offset generator 244. With the satellite code generator 243 implementation of the state machine, a particular code shift is performed by prefixing the state machine to the associated state prior to the beginning of the correlation process. Initial states, which correspond to different code offsets, can be stored in a ROM and can be indexed by means of a simple binary address counter.

In practice, the acquisition search is conveniently performed by first selecting a code and a Doppler frequency, and then indexing through different code offsets. Then the Doppler frequency is changed and the different code shifts are reexamined. Non-coherent accumulator 30 can be implemented as an array of accumulators, one for each candidate code shift in a sequence of adjacent shifts. This accumulator organization allows degrees for adjacent displacements to be examined simultaneously so that an interpolation algorithm can be applied to find the sub-fragment displacement value associated with the actual degree peak. If a sequential interpolation algorithm is used, the peak offset value can be interpolated while using only a single accumulator element.

Total acquisition time can be reduced by processing multiple code offsets simultaneously. For example, multiple digital correlators 23 can be used, each directed with a differently delayed version of the replica signal. Different delays can be implemented with a powered delay line coupled to the output of the code / Doppler generator 24. The different taps can then each control a separate serial digital correlator 23, and the results of each correlator can be squared and separately accumulated into associated elements of a non-coherent accumulator array.

An alternative GPS receiver architecture that is provided for both low power and fast signal acquisition is shown in Figure 5, in accordance with another aspect of the invention. The acquisition architecture is similar to that of Figure 4, except that the serial digital correlator, the serial P / N code and Doppler generators, and the serial read memory are now replaced by a parallel correlator 36, Doppler generators and P / N code number 37, and a parallel read memory 33, respectively. One aspect of the invention is a method for parallel analog bulk summation in the parallel correlator. The analog sum, in combination with the massively parallel organization of memory, replication generator, and correlator elements, is provided for chromic time and energy reductions in the correlation process. The result of the analog sum is converted to digital format by the A / D converter 38 which can be combined with the quadraotic exponent 29, as described later. Parallel architecture

ES 2 168 656 T3 also has the advantage of low power complementary metal oxide semiconductor (CMOS) integrated circuit technology to achieve low power usage. Power use in CMOS circuits is controlled by the charging and discharging of circuit node capacitors; small energy is used in nodes whose voltages are static (no change) or whose capacity is small. With this invention, the P / N and Doppler code replication generators and recorders, data memory and parallel correlator are organized to minimize the number of CMOS nodes that are being loaded and unloaded during the correlation process.

Figure 6 shows the concept of parallel correlation and shows the waveforms for the case where the received and replica signals do not have a Doppler shift. The digitized signal data is sequentially written to the data memory once it is available from the RF / FI section 21 and the A / D converter 22. The data memory 33 is arranged for massive parallel output so that a long stream of data is available at the output simultaneously. Also, a shift register 1004 is loaded with the chosen replica signal and is arranged for massive parallel output with the same length as the data memory. A sample of the cross-correlation ( i.e., inner product) between the parallel data sequence and the parallel replicate sequence is generated for a given Doppler frequency, cocode onyx, and code shift all immediately by means of a parallel correlator 1000 . In parallel correlator 1000, each element of the memory data sequence is multiplied by the corresponding element of the replicate sequence using a corresponding multiplier in an array of multipliers. The output signals of the multiplier are added simultaneously to form the coherent processing result at the output of the correlator. The consistent processing result for an adjacent cocode shift is generated by shifting the replica register one step while holding memory data stationary. Alternatively, the replica signal can be kept stationary while memory data is scrolling.

In an interesting embodiment of the invention, the replicate sequences and parallel output data are 1.0 ms in length and span one C / A code uonic cycle. The data sequence is generated from the RF / IF output signal by sampling at the rate of approximately two samples per C / A code fragment and digitizing at three levels with an A / D converter using a magnitude format and two-bit sign. This sampling rate and the number of levels avoid overlap, avoid substantial degradation of the SNR if the threshold levels A / D are chosen appropriately, and achieve sequence lengths on the order of 2,100 samples. The magnitude and sign format allows a simple multiplier to be used in the multiplier matrix described above. Other interesting data representations, sample rates, and parallel output sequence lengths are possible, as would be obvious to those skilled in the art.

Figure 7 shows a method for generating the parallel output replica sequence. In a code / Doppler generator 1008, a C / A code generator 1001 generates the desired C / A code sequence and a digitized sinusoid generator 1002 generates the digitized sinusoid sequence with the desired phase and Doppler frequency. A multiplier 1003 sequentially multiplies the code and sine sequences provided by the code / Doppler generator 1008 to generate the replica sequence, and this sequence is shifted in a parallel output code / Doppler (replica) recorder 1004.

The replicate sequence was preferably represented in a three-level sign-and-magnitude (two bits) format, or in a two-level sign (one bit) format, since these formats reduce the complexity and power consumption of the parallel correlator with relative to a format that uses more bits. With only three or fewer levels, the Doppler component of the replicate sequence will have a high content of harmonics, and these harmonics can be falsely correlated with an input signal. The problem can be avoided by choosing the frequency of the RF / IF local oscillator so that the RF / IF output signal is substantially offset from zero frequency. By choosing the shift large enough, the resulting harmonics of all necessary Doppler replicate frequencies will be well above the highest Doppler replicate frequency. The harmonics problem is known to those who are experts in the design of superheterodyne receivers. If desired, Doppler replicate harmonic levels can be reduced by using more bits in the replication and Doppler sequence representation and more bits per sample in the replica register. However, this increased the power consumption and complexity (size) of the signal acquisition implementation.

Figure 8 shows a short segment of one embodiment of data memory 33, mirror shift register 1004, and parallel correlator 1000 using the mirror generation method of Figure 7. Both the data and replica sequences use a two-bit sign and magnitude representation, and since the row of elements in each memory 33, shift register 1004, and correlator 1000 are aligned with each other in the form of columns, the Sign (S) and magnitude (M) bits of the corresponding samples of the two sequences can be conveniently applied in each column to a corresponding multiplier 1200. With the sign and magnitude input values ​​of, for example, either -1, 0, or 1 of the two input sequences, each 1200 multiplier generates either -1, 0, or 1 as an output signal. A separate 1300 digital-to-analog converter converts each digital multiplier output signal to analog format. All the output signals of the D / A converter are added by applying them to a common output that represents

ES 2 168 656 T3 the analog result of the correlation. Analog summation is conveniently implemented using load summation, but alternative analog summation formats are also possible. This summation method is spatially efficient, requires very low power, does not need any analog memory, and is very fast. Another advantage of this parallel correlator architecture is that the code and Doppler sequences are programmable, allowing a single correlator to quickly search over various code indices, offsets, and Doppler frequencies in the acquisition process.

Figure 9 shows a one-stage embodiment of the two-sequence parallel correlator of Figure 8. The multiplier 1200 generates the output sign and magnitude bits that control the microswitches 1400 and 1500 of a D / A converter 1300. The switches connect. one end of a charge sum capacitor 1100 either to a positive reference voltage span or to a negative reference span, or to an output reference voltage span (eg, ground). The sum is generated using a two-step procedure. First, the load reset line is brought low, closing a load reset switch 1600 and forcing the switch 1400 of each stage of the parallel correlator to connect to the capacitor associated with the output reference span (ground in figure 9 ). This discharges all the capacitors. The load reset line is then set high, opening the load reset switch 1600 and allowing the data and replica values ​​of each parallel correlator stage to control the associated sign and magnitude switches, 1500 and 1400. respectively. This two-stage process ensures that excess charge does not accumulate on the charge sum capacitors over time. It is advantageous that this parallel correlator can be implemented in low cost digital processes by using, for example, metal-to-metal "crossover" capacitors and binary electronics switches. Finally, it is advantageous that the charge sum can be extended over several integrated circuits simply by spreading the sum lines.

Figure 10 shows another method for generating the replica signal. With this method, the cocode and Doppler sequences are stored in separate parallel output registers. The C / A code generator 1001 of the code / Doppler generator generates the desired C / A code sequence 1010 and this sequence is shifted within a code replica record 1005. Similarly, a digitized sinusoid generator 1002 of the code / Doppler generator generates the digitized sinusoidal sequence with the desired phase and Doppler frequency, and this sequence is shifted within the Doppler replica record 1006.

Figure 11 shows an embodiment of data memory 33, replica code register 1005, replica Doppler register 1006 and parallel correlator 1000 using the replica generation method of figure 10. A separate code register 1005 and a register are used. Doppler 1006, getting separate memory, cocode and Doppler sequences data. The sign (S) and magnitude (M) bits of the corresponding samples of these three sequences are applied to the corresponding multipliers 1201. With sign and magnitude input values ​​of, for example, -1, 0, or 1 of the Doppler and data sequences, and -1 or 1 of the code sequence, each multiplier 1201 generates either -1, 0 or 1 as the output signal. The different multiplier output signals are all summed simultaneously using analog summation as described above for the two-sequence parallel correlator.

Figure 12 shows an embodiment of the three-sequence parallel correlator stage of Figure 11. The correlator stage shown is similar to that of the two-sequence parallel correlator of Figure 9 except that the multiplier has an extra or-exclusive gate 1205 to allow the separate code register bit to affect the sign of the multiplication result.

The two and three sequence parallel correlators of Figures 8 and 11 can be generalized to plural sequence parallel correlators. With respect to the two-sequence correlator, the three-sequence correlator has had one of the crossover correlation sequences (the replica) decomposed into two separate sequences. This decomposition can be applied to both data streams and replica stream in general to provide a plural sequence parallel correlator or inner product machine.

The "differential" analog sum of the parallel correlator may have a lower susceptibility to noise and other advantages. Figure 13 shows a convenient differential sum configuration. At each stage of the parallel correlator, two D / A converters are driven in parallel by the same sign and magnitude output signals of the associated multiplier. One converter is labeled positive and its capacitor connects to a positive-sum line, and the other converter is labeled negative, and its capacitor connects to a negative-sum line. The switches shown in each converter are implemented as electronic switches, as is already known in this art. The two converters work identically except that the sign switch 1500 of the negative converter was connected in reverse of the sign switch of the positive converter. With the differential method, the difference between the positive and negative sum results must be taken to determine the final coherent correlation result. This can be done, for example, using a switched capacitor difference or high-speed linear amplifier, as is known to those skilled in the art. Alternatively, the positive and negative sum results can be converted separately A / D and then their difference calculated digitally before squaring and non-coherent accumulation.

The three-sequence parallel correlation method in Figure 11 uses less power than the

ES 2 168 656 T3 two-sequence method of Figure 8, since only the 1 bit deep code register needs to be shifted when developing the correlation results for subsequent code shifts; the sequence of the separate Doppler recording can be kept fixed. Shifting a register that is two bits deep consumes approximately twice the power of a shift in a register that is one bit deep. Because register shift is a dominant power consumer, with the parallel correlation approach, the three-sequence method is advantageous. On the other hand, the two-stream method uses fewer shift register elements (bits) and fewer exclusive-or gates in multipliers and therefore has a smaller implementation. The size difference of the implementation decreases as the number of bits of the Doppler replica is increased.

The D / A 1300 converters, shown in Figures 9 and 12, use series switches to control the charging of the charge sum capacitors. Figure 18 shows an alternative embodiment for the multiplier and the analog converter (D / A) for the case of three sequences. An advantage of this embodiment is that the digital logic functions directly control the charge sum capacitors and a series connection of switches is not required. This D / A multiplier combination is quickly implemented in a standard digital CMOS process. Capacitors 1101 and 1102 are of substantially the same value and together provide a three-level D / A conversion, eg, -1, 0, and +1. Level -1 is called by putting both capacitors low (digital ground), level +1 is called by putting both capacitors high (Vdd digital), and level 0 is called by putting one capacitor high while the other is set low. In a multiplier 2001, the exclusive NOR gate 1210 and the AND gate 1211 multiply the two-bit data and the Doppler values ​​to form the sign and magnitude product. The exclusive NOR gate 1212 then converts the two-bit product to signals A and B that drive the two capacitors in the same or different directions. Finally, the exclusive NOR gates 1213 multiply the A and B signals by the binary code value, while the NOR gates 1214 are provided to ground the capacitors so that they discharge during the reset phase. For a given length of the stored GPS signal, there is trade-off between the length of the coherent and non-coherent processing. As the length of the coherent correlation has increased, the SNR of each coherent processing result is increased, but the number of coherent processing results available for squaring and non-coherent accumulation (integration) decreases. Those skilled in the art know the SNR improves by 10 dB per decade of coherent processing length increase, but increases only by 5 dB per decade of non-coherent processing length. Thus, for a given memory data length, the predetection SNR is maximized by performing a coherent long correlation. However, unanticipated receiver movement or local oscillator fluctuation will limit the feasible length of coherent processing. Also, as the coherent correlation length increases, the bandwidth of the Doppler containers decreases and this produces more Doppler containers that must be searched. The architectures of Figures 4 and 5 quickly allow the dynamic recording of the coherent and non-coherent processing length through the control of the replica generator, reinitializing the coherent and non-coherent accumulators, and avoiding the squared functions.

It is generally true that the prediction SNR necessary for adequate detection is lower than the SNR necessary for precise localization of the correlation peak (ie, interpolation). In this way, acquisition time and energy can be minimized by using shorter coherent correlations (and thus searching on fewer Doppler containers that are as wide as the detection reliability constraints allow) until a correlation detection is observed and then reprocessing. the data with the longest consistent correlation using code shifts and Doppler shifts close to the values ​​that produced the detection event, to increase the SNR and perform a higher code shift interpolation. The architectures of Figures 4 and 5 allow these two passing processes in a rapid manner.

Figure 14 shows a section of the noiseless autocorrelation waveform for a 1.0 ms (unsampled) C / A code P / N waveform. The autocorrelation value is very close to zero for all displacements of magnitude greater than the width of a fragment and is a triangular function (of the displacement) for displacements between -1 and +1 of fragment width. In another aspect of the invention, accurate sub-fragment correlation peak time estimation is achieved without using sample rates that are substantially higher than twice the C / A fragment rate using a non-multiple sample rate. integer of the fragment rate C / A. With an integer N of samples per C / A code fragment, the autocorrelation sample value in discrete time remains substantially constant over a 1 / N time shift variation of the input signal of the C code fragment period. / A when the receiver bandwidth is substantially larger than the GPS signal bandwidth. This is a form of quantization and produces a significant quantization error if N is not large. For example, a displacement measurement precision of one tenth of a C / A code fragment requires a sampling rate of N = 10 times the C / A code fragment rate. With a more limited receiver bandwidth, the autocorrelation sample value varies with the offset of

ES 2 168 656 T3 time of the input signal, but not necessarily linearly with the offset of the input. If a non-integer multiple sampling rate is used, then the sample precession times or the relative fragment position in the stream are sampled as a sequence of the C / A code fragments of the signal. This precession allows the calculated autocorrelation value to change substantially linearly with time shift of the input signal, and with much smaller time shifts. Although the previous discussion has focused on the autocorrelation of the binary C / A code, the sample precession method is applicable to multilevel signals in general.

With a replica code index and Doppler frequency that matches this with a noisy input signal, the serial or parallel correlator will calculate the noisy samples from the displayed autocorrelation function. By choosing the sample rate of the signal so that there are an integer number of samples (for example, 2183) per 1.0 ms period of C / A code, the result of the correlation of, for example, twenty consecutive sequences of 1.0 ms data memory (using the same replica code offset) will produce twenty noisy samples from the same point on the C / A code autocorrelation waveform. During signal acquisition, the replica Doppler frequency and phase rarely match those of the signal exactly so that it is necessary to square the coherent correlation result to ensure a positive correlation result. Figure 14 also shows the coherent correlation sample points (x) of 1.0 ms squared calculated for various code shifts close to that of the received signal, and with code index and Doppler frequency and phase that are adjusted with those of the input signal. By averaging squared samples of the same code shift, a lower noise estimate of the corresponding autocorrelation value is generated. Averaged typical autocorrelation samples are also shown in the figure. This average is the so-called non-coherent accumulation. The phase of the sample grid, relative to the triangular function, depends on the phase of the received waveform relative to the input A / D sampling clock.

In the waveform of Figure 14, the autocorrelation peak time is a parameter of interest, and this peak time is generally not on the sampling grid. However, using the averaged autocorrelation values ​​surrounding the peak time, the peak time can be estimated by interpolation. Several interpolation methods are known to those skilled in the art, but one method involves ordering the averaged autocorrelation samples according to increasing the code shift and then searching for the two largest adjacent entries. The left input (the first) and its left neighbor (points B and A respectively in the figure) together define a line, while the right input and its right neighbor (points C and D respectively in the figure) together define another line . These two lines intersect somewhere between the two original endpoints (A and D in the figure) when the SNR is high enough, and the time associated with this intersection is the estimated peak correlation time. This method requires the solution of two simultaneous equations, can be used with any of the serial or parallel correlator methods, and will be calculated using the control 35 shown in figure 4 or in figure 5.

Figure 15 shows an acquisition system based on a low-power parallel correlator with full I / Q processing in which the RF / IF section (not shown) generates two quadrature output signals that are passed to A / D converters of input 22 and 56. Control 35 applies power to the RF / IF section and to the input of the A / D converters 700 and 701. The A / D converter 56 generates sampled I data that is stored in the I data memory, while the A / D converter 22 generates sampled Q data that is stored in the Q data memory.

In one embodiment of the system, the input A / D converters sample the I and Q input signals periodically at approximately 2,183 million samples per second, producing 2,183 samples per cycle of C / A code and approximately 2.1 samples per chunk of C / A code. Samples are quantized at 3 levels and a two-bit sign-and-magnitude representation is used, as described above. The I and Q data storage memories are each large enough to store the entire data segment required for signal acquisition. For non-military use, this is generally 20 ms. After 20 ms (2183 x 20 samples) the I and Q data have been stored, power is removed from the RF / IF section and the input A / D converters, and acquisition processing is started. The I and Q data memories are each organized into twenty rows of 2183 two-bit samples, with 2183 simultaneous outputs (one complete row). Four separate three-sequence parallel correlators are used, labeled II, IQ, QI, and QQ. Together these four form a complex parallel correlator 70. Each of the parallel correlators uses sequence lengths of 2183 samples. Data memory directs correlators II and IQ, while data memory Q directs correlators QI and QQ. Also, the Doppler I record directs the II and QI correlators, while the Q Doppler record directs the IQ and QQ correlators. The data processing order is set so that all desired replica code shifts are examined for a given replica code index and Doppler frequency before the code index or Doppler frequency is changed. Also, all desired code offsets are processed for a given row of stored I and Q data before the row is changed. This for the most part will also minimize the combined power usage of memory reading and code register shifting. Other possible

It is 2 memory row processing orders, code index and Doppler frequency, and the order can be chosen to minimize power consumption. The coherent processing results II and QQ are added to form II + QQ by connecting the associated sum lines, and the coherent processing results QI and IQ are summed by connecting their associated sum lines. For proper IQ processing, either the QI result or the IQ result must be inverted, and this can be done, for example, by reversing the direction of all sign switches in all analog converters of the chosen parallel correlator. In this realization, IQ-QI has been formed.

With GPS signals, the SNR of each II + QQ and IQ-QI signal is typically 0 to 4 dB. These signals are adequately represented with only a few levels (for example, -1, 0, 1) and are converted to digital format by the A / D converters 700 and 701, and then separately squared by the quadratic exponents. 702 and 703. The squared signals are summed by means of a digital adder 46 and stored in accumulator 44. Accumulator 44 has a separate storage location associated with each candidate code shift, and the correlation results for each code shift with different received data segments are accumulated at the associated storage location.

Figure 16 shows an embodiment of a fast quadratic exponentiation A / D converter that combines the A / D and quadratic exponentiation functions. Here, two comparators 61 and 62 determine whether the analog value is above, below, or between the two threshold values ​​associated with the levels of the analog representation -1, 0, +1. A log unit 63 then assigns the state of the comparator junction output to the appropriate squared digital value. If desired, the fast quadratic exponentiation converter is quickly generalized to more than three representation levels by adding more comparators and threshold voltages.

Sample rates, stored sequence lengths and simultaneous memory output lengths can be chosen for a better fit of the GPS application. For example, by storing the entire data segment necessary for signal acquisition, the RF / FI section can be turned off after as short a time as possible (in proportion to the reception of the necessary data segment). The stored data set can then be used for the processing of all SCD containers in the acquisition search. Alternatively, a shorter memory can be used at the expense of having to keep the RF / IF section on for a long period of time. For example, another interesting embodiment uses a “Ping-Pong” memory organization and is illustrated in Figure 19. Here, I and Q data storage memories 192 and 194, respectively, are each 2.0 ms long and are located

656 T3 28 are organized as two rows of 1.0 ms parallel output (eg, 2183 samples in each row, as before). In both data channels, I and Q, one row of data is accessed in parallel, for parallel correlation, while the other row of data is written with the digitized data coming from the RF / FI section. The full lengths of the I and Q data sequences are each processed in 1.0 ms segments. The full 20 ms data set is then processed for a single SCD container in approximately 20 ms. Because the entire sequence of data was not stored, the RF / FI section must be powered up and produce another entire sequence if another SCD container is to be checked. On average, this increases the time the RF / IF section must be kept powered during signal acquisition. However, the reduction in memory size can be significant. In some applications (for example, military receivers that are under severe interference conditions), the GPS SNR is very low and the length of the data stream required for acquisition may be so long that data storage is impractical. the entire sequence. Under these circumstances, the Ping-Pong acquisition architecture is advantageous.

In some applications it will be advantageous to further reduce the size of the data storage memories. With the two-segment memory organization (Ping Pong), a long continuous stream of data output from the receiver can be processed. At the expense of longer acquisition time, the two-segment I and Q data memories 192 and 194 (Figure 19) can be reduced to single segment memories by removing one of the 1.0 ms sections from each memory. . With this reduction, adjacent 1.0 ms receiver output segments in time are not processed. Instead, each of the other 1.0 ms segments is captured in memory and processed, and this lengthens the elapsed time to process a given number of received signal segments.

To further reduce the memory size and complexity of the parallel correlator, the length of the parallel correlator and associated memory registers and segments can be made smaller than the desired coherent processing length. The desired coherent processing length can be achieved by processing several short pieces of my data and coherently combining their results. For example, a coherent processing length of 1.0 ms can be achieved by using a single parallel correlator of length 0.5 ms on two adjacent 0.5 ms data segments and adding their results digitally, after A / D conversion. . Various combinations of correlator length, coherent processing length, memory segment numbers, and code offset search width are possible.

When the cost, size, and power dissipation of a standard serial input / serial output (SISO) memory are low enough, it may be advantageous to store the data.

ES 2 168 656 T3 complete quantities of I and Q data needed in said memory, turning off the RF / IF receiver section, and using this memory in combination with Ping-Pong or single element memory architectures to examine all containers Desired SCD. The complete I and Q data sequences are read from SISO memory once for each SCD container tested, and this reading process will consume power. However, because the RF / IF section has been turned off, the power usage of the system would be reduced if the power dissipation of a SISO memory is low enough relative to that of the RF / IF section of the receiver. Other stored sequence lengths, simultaneous memory output lengths, and sample rates are also interesting.

In the two-sequence or three-sequence parallel correlator embodiments of Figures 8 and 11, the product of the associated data and the replica samples is run in parallel within the correlator. This allows different Doppler containers to be tested for acquisition without having to collect the new data received. Figure 20 shows an alternative one-stage embodiment of a parallel correlator and associated parallel memory where the multiplier 2001 multiplies the data and the Doppler samples together prior to storage in the parallel memory 2002. This is advantageous as they are simplified in a way. this way the multipliers of the parallel correlator. Each correlator multiplier now multiplies its associated stored sample by a single associated code bit. The combined multiplier and the D / A converter for this embodiment of the correlator is similar to that shown in Figure 18, except that the Doppler data multiplier and the AB signal converter, formed by the exclusive NOR gates 1210 and 1212 and the AND gate 1211, is taken out of the correlator and ahead of data memory. The disconnected inputs to the exclusive NOR gates 1213 are coupled to the data memory outputs. With this realization, new data must be stored in case a different Doppler container is to be tested for acquisition, but this is not a disadvantage in some applications.

The combined parallel correlator and parallel memory shown in Figure 20 can be advantageously used to form a complete IQ processing GPS acquisition engine. In the IQ full acquisition engine shown in Figure 19, there are four separate parallel correlators coupled to the I and Q data registers and the I and Q Doppler (parallel memory) register, as well as the parallel code register. A complete alternative IQ embodiment is shown in Figure 21 using the simplest memory and correlator organization of Figure 20. In this embodiment, the four parallel Doppler data memories retain the product sequences of Doppler II, QQ, IQ and data. QI, respectively. Each parallel memory can be organized as a Ping-Pong memory or as a uenic segment memory, as described above. There is no separate data or Doppler storage. Each parallel memory connects to an associated parallel correlator, and each parallel correlator also connects to the single parallel code register. The reduced interconnection between the memory sections and the correlator sections enables this complete IQ processor embodiment to have a simpler (ie, smaller and lower cost) integrated circuit implementation.

The complexity of the embodiment of FIG. 21 can be further reduced by performing the addition II + QQ and the subtraction QI-IQ before storing the data. Before storage, the addition and subtraction output signals can often be rounded or truncated to two bits with a small SNR degradation. then, as shown in Figure 22, only two Doppler data memories are needed (one for the II + QQ data, and the other for the QI-IQ data), two parallel correlators, and a code register. Each Doppler data memory can be organized as a Ping-Pong memory or as a single segment memory, as described above. Other arrangements of parallel correlator, parallel memory and sequence multiplications are also possible and advantageous.

Figure 17 shows a combined data store, replica generation, parallel correlator organization (for correlation process II) that reduces the number of code register shifts to 2183 shifts per Doppler code combination and eliminates the need for any Inconsistent stacking RAM. The trade-off is that input memory must now be segmented to allow all stored data to be accessed simultaneously. These data are applied, in 1.0 ms blocks, to separate parallel correlators. These parallel correlators are all controlled by the same code replicas and Doppler replicas, and generate simultaneously (in a complete code cycle) the twenty correlation sequences separated by 1.0 ms that were previously accumulated sequentially in time. Separate quadratic exponentiation A / D converters convert analog correlation sequences to digital format where an adder tree 80 forms the cumulative correlation sequence. Accumulation RAM can be avoided by performing the peak search and interpolation process on the accumulated correlation while it is being generated. In this arrangement, the code and Doppler logs now direct twenty charges where they previously directed one, which may negate some of the energy reduction.

When the parallel correlator is used with data or replica records for the case of two sequences, or with data records, Doppler and code for the case of three sequences, it is advantageous to minimize the energy used in loading (writing) the data. the various registers. In another aspect of the present invention, the loading of the various registers is done by a low energy operation using a scan shift register to determine over which stages of operation.

ES 2 data log, Doppler and code will be written at every moment. FIG. 23 shows a scan shift register 304 in combination with data register 300, Doppler register 301 and code register 302 for the three sequence case. In one operating procedure, the samples arrive sequentially for each of the data, Doppler, and code sequences and the sample rates are the same. As samples arrive for each respective sequence, they are written to corresponding sequential positions in their respective registers. In sync with the arrival samples, a logical uonic 1 is moved along the binary scan register, enabling the writing of the arrival samples at the corresponding sequential positions of the respective registers. The ope

656 The write ration is very low energy, as only two adjacent scan register positions change their stored value at each shift, and neither of the respective registers is shifted during the write operation.

While the invention described is applicable to acquiring a C / A GPS signal, it can also be used to significantly reduce both the time and energy required to directly acquire the military P (Y) GPS signals without first acquiring the P (Y) signals. AC. By altering the satellite code generator component of the code / Doppler generator of Figures 4 or 5 to generate the P (Y) code instead of the C / A code, the procedures and architectures described herein are applicable for the case P (Y).