Power semiconductor
5 claims: 2 independent, 3 dependent
- 1Anordnung umfassend einen Leistungshalbleiter und einen Kühlkörper, auf dem der Leistungshalbleiter montiert ist, wobei der Leistungshalbleiter eine Trägerplatte (2) aufweist, auf der zwei Leistungshalbleiterbauteile angeordnet sind, und ein Gehäuse (1) aufweist, das die Trägerplatte mit den Leistungshalbleiterbauteilen zumindest teilweise umschließt, die Trägerplatte (2) aus einem den Boden des Gehäuses (1) bildenden isolierenden Keramiksubstrat besteht, das sowohl auf der dem Gehäuse (1) zugewandten Seite als auch der dem Gehäuse (1) abgewandten Seite mit einer Metallschicht versehen ist, und die dem Gehäuse (1) zugewandte Metallschicht zu Leiterbahnen strukturiert ist und die dem Kühlkörper zugewandte Seite der Trägerplatte (2) bündig mit dem Gehäuse (1) abschließt und der Gehäuseboden (3) auf dem Kühlkörper aufliegt, die beiden Leistungshalbleiterbauteile mit aus dem Gehäuse (1) herausgeführten Leistungsanschlüssen (4, 5, 6) und Steueranschlüssen (7, 8, 9, 10, 11, 12) elektrisch verbunden sind, die laschenförmig ausgebildete Anschlüsse sind und einen ersten Abschnitt (A) aufweisen, der sich seitlich aus dem Gehäuse (1) erstreckt, einen zweiten Abschnitt (B) aufweisen, der sich von dem ersten Abschnitt zu der Leiterplatte erstreckt, und einen dritten Abschnitt (C) aufweisen, der sich von dem zweiten Abschnitt seitlich nach außen erstreckt, wobei die einzelnen Abschnitte (A, B, C) einen Winkel von 90° einschließen, sämtliche Leistungsanschlüsse (4, 5, 6) der beiden auf der Trägerplatte angeordneten Leistungshalbleiterbauteile auf der einen Seite des Gehäuses (1) aus dem Gehäuse herausgeführt und in einer Reihe angeordnet sind und sämtliche Steueranschlüsse (7, 8, 9, 10, 11, 12) der beiden Leistungshalbleiterbauteile auf der gegenüberliegenden Seite des Gehäuses (1) aus dem Gehäuse herausgeführt und in einer Reihe angeordnet sind, wobei der Abstand (a) zwischen nebeneinander liegenden Leistungsanschlüssen (4, 5, 6) größer als der Abstand (b) zwischen nebeneinander liegenden Steueranschlüssen (7, 8, 9 bzw. 10, 11, 12) ist, und die Leistungshalbleiterbauteile gemeinsame Leistungsanschlüsse (4, 5, 6) aufweisen, die auf der einen Seite des Gehäuses (1) angeordnet sind und getrennte Steueranschlüsse (7, 8, 9, 10, 11, 12) aufweisen, von denen die dem ersten Leistungshalbleiterbauteil zugeordneten Steueranschlüsse (7, 8, 9) in einer ersten Reihe auf der anderen Seite des Gehäuses nebeneinander angeordnet sind und die dem zweiten Leistungshalbleiterbauteil zugeordneten Steueranschlüsse (10, 11, 12) in einer zweiten Reihe auf der anderen Seite des Gehäuses nebeneinander angeordnet sind.
- 2Leistungshalbleiter nach Anspruch 1, dadurch gekennzeichnet, dass die Leistungsanschlüsse (4, 5, 6) einen größeren Querschnitt als die Steueranschlüsse (7, 8, 9, 10, 11, 12) des Leistungshalbleiterbauteils aufweisen.
- 3Leistungshalbleiter nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass der Abstand (c) zwischen der ersten Reihe und der zweiten Reihe von Steueranschlüssen (7, 8, 9, 10, 11, 12) größer als der Abstand (b) zwischen den Steueranschlüssen 7, 8, 9 bzw. 10, 11, 12) in der ersten und zweiten Reihe ist.
- 4Leistungshalbleiter nach Anspruch 3, dadurch gekennzeichnet, dass der Abstand (c) zwischen der ersten Reihe und der zweiten Reihe von Steueranschlüssen (7, 8, 9, 10, 11, 12) dem Abstand (a) zwischen den Leistungsanschlüssen entspricht.
- 5Leistungshalbleiter nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass das mindestens eine Leistungshalbleiterbauteil ein IGBT ist.
Independent claims5
25 paragraphs, as filed
0001The invention relates to an arrangement comprising a power semiconductor with a housing and power and control terminals and a heat sink on which the power semiconductor is mounted.
0002The above-mentioned power semiconductors, for example, the known IGBT's. count, find, for example, in various fields of electrical engineering, for example in drive control devices for electric motors use.
0003From the <patcit id="pcit0001" dnum="EP0513410B1"><text>EP 0 513 410 B1</text></patcit> and <patcit id="pcit0002" dnum="DE19646396C2"><text>DE 196 46 396 C2</text></patcit> are known power semiconductor modules, each having an electrically insulating substrate on which a circuit arrangement is arranged with power semiconductor devices. The substrate forms the bottom of a plastic housing enclosing the circuitry. The contacted with the circuit arrangement electrical power terminals of the semiconductor devices extend through the housing to the outside. The housing is filled to protect the circuit with potting compound. Attachment points on the housing are used to screw the module to a heat sink.
0004The <patcit id="pcit0003" dnum="EP1976358B1"><text>EP 1 976 358 B1</text></patcit> describes a power semiconductor having a support plate of an insulating ceramic substrate forming the bottom of the housing. The carrier plate is provided on the top and bottom with a metal layer, wherein the upper metal layer is structured to form interconnects. A power semiconductor component and the power and control terminals of the semiconductor component are electrically connected to the conductor tracks. The power and control connections are led out of the housing laterally. The power and control terminals of the power semiconductor are formed as terminals of a surface mounted device, which is also referred to as SMD (Surface Mounted Device). The SMD component is mounted on a printed circuit board.
0005To comply with the required for electrical operation isolation distances for creepage distances between the inside of the housing lying portions of the power and control terminals and the support plate and between the lying outside of the housing sections of the power and control terminals and the circuit board are the performance and Control terminals designed such that the connections within the housing initially perpendicular to the support plate away, then extend laterally through the housing to the outside and finally perpendicular to the circuit board. All power and control connections are at the same distance.
0006The <patcit id="pcit0004" dnum="DE19625240A1"><text>DE 196 25 240 A1</text></patcit> describes a semiconductor device having a lead frame to which groups of power and control terminals are connected.
0007From the <patcit id="pcit0005" dnum="WO2004090977A1"><text>WO 2004/090977 A1</text></patcit> For example, a semiconductor device is known in which connection elements of different width are led out of the housing on opposite sides. To reduce the inductance, it is proposed to arrange the power connections directly next to each other, wherein the current-carrying conductor tracks should not form conductor loops.
0008The <patcit id="pcit0006" dnum="US20100140786A1"><text>US 2010/0140786 A1</text></patcit> describes a semiconductor module with power and control terminals on opposite sides of the housing, wherein the control terminals of several components but not each group are combined, which form on a side of the housing in spaced-apart rows of terminals.
0009The <patcit id="pcit0007" dnum="WO03071601A2"><text>WO 03/071601 A2</text></patcit> describes a power semiconductor with a carrier plate, which is divided into three sections. On each carrier section is a power diode and a power transistor. The power supply of the diodes and the transistors and the transmission of control signals to the circuit module is done with flat conductors, which are led out to the side of the housing of the module. The narrower flat conductors for the transmission of the signals are located on one longitudinal side of the housing. The narrow flat conductors are each divided into groups of five conductors, each associated with one of the carrier sections.
0010The invention has for its object to provide a power semiconductor with improved technical properties.
0011This object is achieved with the features specified in claim 1. The subclaims relate to preferred embodiments of the invention.
0012The power semiconductor according to the invention has a carrier plate on which two power semiconductor components are arranged. The carrier plate with the two power semiconductor components is at least partially enclosed by a housing. With the at least one power semiconductor device power and control terminals are electrically connected, which are led out of the housing.
0013The power semiconductor according to the invention is characterized in that the power terminals are arranged on one side of the housing in a row and the control terminals are arranged on the other side of the housing in a row, wherein the distance between adjacent power terminals greater than the distance between side by side lying control terminals. The special arrangement of the power and control connections on the two sides of the housing results in improved electrical properties, especially when used with high voltages and currents, since the isolation distances for clearance and creepage distances are greater than in the known power semiconductors.
0014In a preferred embodiment, the power terminals have a larger cross-section than the control terminals, so that the power semiconductor is suitable for switching high currents.
0015In addition to the above arrangement of the power and control connections critical air or creepage distances are avoided by the special design of the terminals themselves. The power and control terminals have a first portion extending laterally from the housing, a second portion extending from the first portion to the circuit board, and a third portion extending laterally outwardly from the second portion extends. The individual sections include an angle which is 90 °.
0016The invention provides for an arrangement of two power semiconductor components on the carrier plate. In this case, the power semiconductor components on common power terminals, which are arranged on one side of the housing and separate control terminals, which are arranged on the other side of the housing. The control terminals assigned to the first power semiconductor component are arranged side by side in a first row of the housing, and the control terminals assigned to the second power semiconductor component are arranged next to one another in a second row. Preferably, the distance between the first row and the second row of control terminals is greater than the distance between adjacent control terminals in the first and second rows. With this particularly preferred arrangement, the control terminals are subdivided into individual groups, each group of terminals being assigned to only one power semiconductor. This ensures that the control terminals of different groups, which can differ more strongly in terms of electrical potential, are arranged at a sufficient isolation distance, while the control terminals of a group, which can differ less from each other in terms of potential, closer together are arranged. The distance between the first row and the second row of control terminals may be equal to or smaller than the spacing between adjacent power terminals. wherein each group of terminals is associated with only one power semiconductor. This ensures that the control terminals of different groups, which can differ more strongly in terms of electrical potential, are arranged at a sufficient isolation distance, while the control terminals of a group, which can differ less from each other in terms of potential, closer together are arranged. The distance between the first row and the second row of control terminals may be equal to or smaller than the spacing between adjacent power terminals. wherein each group of terminals is associated with only one power semiconductor. This ensures that the control terminals of different groups, which can differ more strongly in terms of electrical potential, are arranged at a sufficient isolation distance, while the control terminals of a group, which can differ less from each other in terms of potential, closer together are arranged. The distance between the first row and the second row of control terminals may be equal to or smaller than the spacing between adjacent power terminals. are arranged at a sufficient isolation distance, while the control terminals of a group, which can differ less in terms of potential from each other, are arranged closer together. The distance between the first row and the second row of control terminals may be equal to or smaller than the spacing between adjacent power terminals. are arranged at a sufficient isolation distance, while the control terminals of a group, which can differ less in terms of potential from each other, are arranged closer together. The distance between the first row and the second row of control terminals may be equal to or smaller than the spacing between adjacent power terminals.
0017For the invention, it is basically irrelevant to which components it is in the power semiconductor modules. The power waveguide modules may be, for example, IGBTs , but also MOSFETs or other known power semiconductor components.
0018For mounting on a heat sink, the side of the carrier facing the heat sink is flush with the housing.
0019In the following an embodiment of the invention will be explained in more detail with reference to the figures.
0020Show it:<dl id="dl0001"><dt>Fig. 1</dt><dd>An embodiment of the power semiconductor according to the invention in a perspective view in the rear view and</dd><dt>Fig. 2</dt><dd>the power semiconductor of <figref idref="f0001">Fig. 1</figref> in the plan view.</dd></dl>
0021The power semiconductor component according to the invention has a housing 1, which preferably consists of an insulating material, for example of an epoxy material. The housing 1 may also be made at least partially of metal. The<figref idref="f0001">FIGS. 1 and 2</figref> show the housing of the power semiconductor from different views. Since power semiconductors are known as such, is dispensed with the representation of the Leistungshalbeiterbauteile and their contact inside the housing. In the present embodiment, the rectangular flat case has the dimensions of 25 mm × 23 mm × 5.5 mm.
0022The housing 1 partially encloses a support plate 2 made of an insulating ceramic substrate, wherein the support plate 2 forms the bottom 3 of the housing 1. The support plate 2 is provided both on its side facing the housing and on its side facing away from the housing with a metal layer, wherein the housing facing the metal layer is structured according to the conductor tracks of a circuit arrangement. In this exemplary embodiment, two power semiconductor components, for example IGBTs, not shown in the figures are arranged on this structured metal layer. The power semiconductor devices may be soldered to the underside with the patterned metal layer. At the top, the power semiconductor components are electrically connected to the conductor tracks of the structured metal layer by means of bonding wires, not shown, wherein the ends of the bonding wires are soldered to the power semiconductor components and the conductor tracks. The power semiconductor is mounted on a heat sink, not shown, wherein the housing bottom 3 rests on the heat sink.
0023Both power semiconductor modules have power terminals 4, 5, 6 and control terminals 7, 8, 9, 10, 11, 12. The power terminals 4, 5, 6 of both power semiconductor components are combined in the present embodiment to three common power terminals, the side of the housing 1 led out. However, the two power semiconductor components each have three separate control terminals 7, 8, 9 and 10, 11, 12, which are also led out of the housing 1.
0024The power and control terminals 4 to 12 are tab-shaped terminals which are used as terminals of a surface-mounted component, ie an SMD component (<b>S</b>urface-<b>M</b>ounted <b>D</b>evice) are formed. All terminals have a first portion A, which extends laterally outwardly from the housing 1 out. The first section A is adjoined by a second section B facing the printed circuit board (not shown), which encloses an angle of approximately 90 ° with the first section. The second section B merges into an outwardly facing third section C, which again encloses an angle of about 90 ° with the second section B. The third portion of each terminal is electrically connected to the printed circuit board, not shown. The power and control terminals 4 to 12 differ in their cross section, wherein the power terminals 4, 5, 6 have a larger cross section than the control terminals 7, 8, 9, 10, 11, 12.
0025The power terminals 4, 5, 6 are arranged in a row at constant intervals a on the one longitudinal side of the housing, while the adjacent control terminals 7, 8, 9, 10, 11, 12 in a row on the other longitudinal side of the housing at a distance b are arranged. The distance a between the adjacent power terminals 4, 5, 6 is greater than the distance of the outer power terminals and the edges of the housing. The adjacent control terminals 7, 8, 9, 10, 11, 12 of both power semiconductor components form a first group 7, 8, 9 and a second group 10, 11, 12, which are arranged on the other longitudinal side of the housing 1 at a distance c next to each other which is larger than the distance b between the adjacent control terminals 4, 5, 6 of a group. The distance c corresponds to the distance a or is smaller than the distance a. Both with the special arrangement and the special design of the power and control connections sufficient air and creepage distances are created for the electrical operation at high voltages and currents, so that the electrical properties of the semiconductor device are improved.
1 sheet
Sheet 1
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| DE102005061772A1 | Cites | Germany | Opposition |
| US6960825B2 | Cites | United States of America | Opposition |
| US7148562B2 | Cites | United States of America | Opposition |
| US7456492B2 | Cites | United States of America | Opposition |
| US7508668B2 | Cites | United States of America | Opposition |
| US7633758B2 | Cites | United States of America | Opposition |
| US7835151B2 | Cites | United States of America | Opposition |
| US7957135B2 | Cites | United States of America | Opposition |
| WO2004090977A1 | Cites | World Intellectual Property Organization (WIPO) | – |
| WO03071601A2 | Cites | World Intellectual Property Organization (WIPO) | – |
| DE19625240A1 | Cites | Germany | – |
| DE102005061772A1 | Cites | Germany | – |
| US2010140786A1 | Cites | United States of America | – |
| US6960825B2 | Cites | United States of America | – |
| US7148562B2 | Cites | United States of America | – |
| US7456492B2 | Cites | United States of America | – |
| US7508668B2 | Cites | United States of America | – |
| US7633758B2 | Cites | United States of America | – |
| US7835151B2 | Cites | United States of America | – |
| US7957135B2 | Cites | United States of America | – |
| Presentation: Case study:"Substrate Free Moulded Power Moduld" held by Frank Osterwald at the ECPE workshop "Power Electronics Substrates _Materials, Performance, Processing and Reliability", on June 17 and 18 2010 in Munich, Germany | Non-patent | – | – |
| Publication "Substrate Free Molded Power Module" published in the Proceedings PCIM Europe 2009 Conference | Non-patent | – | – |
| Presentation: Case study:"Substrate Free Moulded Power Moduld" held by Frank Osterwald at the ECPE workshop "Power Electronics Substrates _Materials, Performance, Processing and Reliability", on June 17 and 18 2010 in Munich, Germany | Non-patent | – | Opposition |
| Publication "Substrate Free Molded Power Module" published in the Proceedings PCIM Europe 2009 Conference | Non-patent | – | Opposition |
17 members in 6 offices
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 202011100820U | Germany | – | |
| 202011100820 | Germany | U |
Members17
| Document | Office | Kind | |
|---|---|---|---|
| DE202011100820U1 | Germany | U1 | |
| CN102790043A | China | A | |
| EP2525397A1 | European Patent Office (EPO) | A1 | |
| KR20120128568A | Republic of Korea | A | |
| KR20120128568A | Republic of Korea | A | |
| JP2012244176A | Japan | A | |
| US2013021759A1 | United States of America | A1 | |
| US9042103B2 | United States of America | B2 | |
| US2015195928A1 | United States of America | A1 | |
| EP2525397B1 | European Patent Office (EPO) | B1 | |
| EP2525397B8 | European Patent Office (EPO) | B8 | |
| US9210818B2 | United States of America | B2 | |
| CN102790043B | China | B | |
| EP2525397B2This record | European Patent Office (EPO) | B2 | |
| KR101941711B1 | Republic of Korea | B1 | |
| KR101941711B1 | Republic of Korea | B1 | |
| JP6513326B2 | Japan | B2 |
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Numbers
- Publication
- 2525397
- Application
- 120038542
Titles3
- German
- Leistungshalbleiter
- English
- Power semiconductor
- French
- Semi-conducteur de puissance
Classification
- CPC, 10
- H05K5/0069
- H10W40/255
- H10W90/00
- H05K1/11
- H05K1/181
- H05K7/1427
- H05K2201/10166
- H10P95/00
- H10W76/157
- H10W74/114
- IPC, 5
- H01L23 057
- H01L23 373
- H01L23 31
- H10W76 157
- H10W40 25
Designated states1
- Contracting states, 1
- Türkiye
