Device having plurality of integrated circuits in a matrix

TECHNICAL FIELD AND PRIOR ART

0001The invention relates to the field of the assembly of microsystems or nanosystems at the scale of a wafer, for example of semiconductor material, such as silicon.

0002It relates in particular to applications for which high density integration technologies for passive components, sensors or optoelectronic components or MEMS or NEMS directly on the circuits, commonly known as "Above IC" are sought.

0003Currently, heterogeneous integration processes can only be performed on whole silicon wafers. "Above IC" processes are therefore limited to areas where the integrator of the microsystem can have platelets, which involves significant costs in terms of mask set and manufacture of platelets in a foundry.

0004In addition, for applications such as telephony, the active surface of the integrated circuits is not sufficient to accommodate all the elements necessary for the system (passive components, amplifiers, switches, SAW components or BAW), which is particularly due the fact that the yield decreases as the complexity of the chips increases. It is therefore necessary to assemble post manufacturing the various elements on substrates of PCB type (printed circuit) or ceramic. Architectures are often complex and assembly and interconnection require a lot of individual operations (component placement and wired cabling).

0005There is another technique that allows the integration of many features on the same chip, while having good returns. In this technique, a wafer is reconstituted from discrete chips arranged on a support wafer and then sealed with a coating material and eliminating the support wafer. This reconstituted wafer makes it possible to carry out integrations of the "above IC" type, mixing components coming from several sources and assembled in a format adapted to the depositing tools available for the industrialist. Moreover, this technique makes it possible to produce complex devices, containing components manufactured on different substrates, by choosing only functional components.

0006This technique, in which the active faces of the components are temporarily glued to an adhesive, then they are coated and rerouted over, was published in <nplcit id="ncit0001" npl-type="s"><text>1992 by Chang-Lee Chen et al. In an article entitled "Bond Wireless Multipocket Packaging Technology for High Speed ​​Circuits", published in "IEEE Transactions On Component Hybrids and Manufacturing Technology, Vol 15 No. 4, pages 451-456</text></nplcit>. "

0007In this type of technique, the processes described in the documents are also known. <patcit id="pcit0001" dnum="US5353498A"><text>US 5,353,498</text></patcit> and <patcit id="pcit0002" dnum="US5497033A"><text>US 5,497,033</text></patcit>, as well as the technique described in the document <patcit id="pcit0003" dnum="FR2857157"><text>FR 2,857,157</text></patcit>. The technique described in the document<patcit id="pcit0004" dnum="FR2864342"><text>FR 2 864 342</text></patcit> Applies to components already in a housing it is very complex because it is then necessary to grind part of the housing to resume the contacts of the components.

0008Finally, according to another method, described in the document <patcit id="pcit0005" dnum="GB2202673A"><text>GB 2,202,673</text></patcit> and schematically represented in the <figref idref="f0006">Figures 8A-8C</figref>, the discrete chips are arranged in cavities <b>107</b> present in a welcome wafer and then sealed with a coating material so as to form a reconstituted wafer containing the components. The technique thus presented uses, in a manner necessary for its unwinding, a support substrate 121 on which an adhesive film 122 is present. The adhesive layer makes it possible to hold the carrier wafer and then the active chips on the support substrate during the process steps during which the filler material is not yet deposited and can therefore ensure the mechanical strength of the components of the reconstituted wafer.

0009This coating layer may have three types of defects illustrated in the <figref idref="f0006">Figures 8A-8C</figref>.

0010Firstly, during the deposition of the coating material, the material may not adhere to the adhesion layer (<figref idref="f0006">figure 8A</figref>); on the contrary, it can interact too strongly with the adhesion layer and so there may be miscibility (<figref idref="f0006">Figure 8B</figref>). As a result, one or more zones of narrowing 113 (<figref idref="f0006">figure 8A</figref>) or zones 123 for mixing the material 103 and adhesive 122 (<figref idref="f0006">Figure 8B</figref>). During the removal of the adherent layer, these cases of miscibility or dewetting can lead to tearing of the coating material, or components, the appearance of significant stresses on the wafer or the poor strength of the components.

0011Different coefficients of thermal expansion (CTE) between, on the one hand, the coating layer 103 (CTE close to 10 ppm / ° C or above this value) and, on the other hand, the substrates of the wafer 102 and / or components 104 (CTE close to 2.3 ppm / ° C for silicon) induce the appearance of strong stresses in the coating layer (<figref idref="f0006">Figure 8C</figref>) during temperature variations, for example during hardening of the coating layer. These constraints induce deformation of the wafer and even breaks. They are identified on the<figref idref="f0006">Figure 8C</figref> by the zones 110, 110 'and are located either on the periphery of the components 104, or on their rear face.

0012The invention aims to solve these problems. It aims in particular to reduce the impact of the CTE difference on the constraints in the wafer.

0013Another object of the invention is to improve the interface between the device being manufactured and the adhesion layer.

0014The document <patcit id="pcit0006" dnum="US2007080458A"><text>US 2007/080458</text></patcit> describes a hybrid module and a method for producing it.

0015The docuent <patcit id="pcit0007" dnum="US20060220222A"><text>US 2006/0220222</text></patcit> discloses an integrated chip structure and method of making same.

0016The document <patcit id="pcit0008" dnum="US6998533B"><text>US 6,998,533</text></patcit> discloses an electronic device having a semiconductor element in a cavity with a thermally insulating layer.

STATEMENT OF THE INVENTION

0017The invention relates firstly to an electronic board, as described in claim 1, having a front face and a rear face, provided with at least one integrated discrete component, the active face of the component appearing on the side of the face. before and including:<ul><li>a coating material, present at least laterally with respect to the component, ensuring the maintenance of said component in the device,</li><li>a buffer layer, absent from the active face of the component, separating the coating material from the component (s).</li></ul>

0018In the case of two neighboring components, the buffer layer does not completely fill the space between the components, the remaining space between the components or between buffer layer portions present on the sidewalls of the components being occupied by the material. 'coating.

0019In one embodiment, the component (s) is (are) placed in at least one cavity present in a host matrix, the cavity or cavities passing through the host matrix, the buffer layer being at least less present on the flanks of the cavity or cavities. The buffer layer thus separates the coating material from the component (s) and the host matrix, and is absent from the front face of the host matrix. It does not completely fill the space between the flanks of the cavity or cavities and the flanks of the components.

0020Whatever the embodiment, the buffer layer has properties enabling it to limit or absorb the stresses that may appear between, on the one hand, the coating material and, on the other hand, the component or components. and the possible plate, during climbs and / or descents at temperatures.

0021According to two variants of each of the preceding devices:<ul><li>the buffer layer can mask the coating material on the front face of the device;</li><li>the coating material may be visible on the front face of the device, the buffer layer being present only on the sidewalls of the component, the coating material and the buffer layer having a shrinkage relative to the active surface of the components.</li></ul>

0022The invention also relates to a method of integrating at least one integrated discrete component into a wafer, as described in claim 9, said reconstituted wafer, in which process:<ol id="ol0001" compact="compact"><li>a) positioning at least one discrete component on a substrate, said support substrate,</li><li>b) then depositing a buffer layer at least on the back side and the sides of the component, said buffer layer not being deposited on the surfaces in contact with the substrate.</li><li>c) subsequently depositing a coating material at least laterally with respect to the component, this material being deposited only on surfaces covered by the buffer layer.</li></ol>

0023Step a) may include the positioning of one or more components in one or more cavities passing through a host matrix.

0024The formation of the buffer layer during step b) is carried out at least on the rear face of the matrix and the flanks of the cavity or cavities, said buffer layer not completely filling the space between the sidewall of the cavities and the cavity. component flank, and separating, at the end of step c), the coating material of the material of the host matrix.

0025The matrix may be positioned first on the support substrate, and then the components are positioned in the cavity (s) of the host matrix. Conversely, the matrix can be placed only once the discrete components are positioned, the cavity or cavities surrounding the components.

0026The support substrate may be silicon, or glass, or alumina, or quartz or polymer.

0027A method according to the invention may further comprise a thinning step of the rear face of the wafer.

0028A method according to the invention may further comprise a bonding step in the rear face of a reinforcing substrate for ensuring the mechanical strength.

0029In a method according to the invention, an adherent layer may be deposited on the support substrate prior to step a), the buffer layer deposited in b) being deposited on at least a portion of the adherent material not occupied by a component, the rear face and the flanks of the component (s) and possibly on the back of the host matrix and the flanks of the cavities.

0030In a process according to the invention, the buffer layer advantageously adheres to the adhesion layer and to the rear face and to the flanks of the component (s) and is preferably immiscible with the adherent layer. Thus, the buffer layer avoids the formation of reaction material on the surface of the adherent layer while maintaining the various elements on the support substrate.

0031In addition, in order to reduce the effects of stresses, the buffer layer, for example appearing in the wafer reconstituted during integration processes above IC or during hardening of the coating material, has a glass transition temperature which is lower than that of the coating material. 'coating. It is then deformed under the influence of compressive stresses. To ensure its deformation during negative temperature variations, the buffer layer preferably also has a low Young's modulus.

0032In a process according to the invention, the buffer layer can be deposited in the gas phase, or by ALD, or by CVD, or by sol-gel process.

0033In a method or a device according to the invention, the component (s) has / have a substrate, for example mainly made of silicon, or AsGa, or InP or glass. In addition, each component may be of different size and type of dimensions or type of other components integrated in the same wafer.

0034Each component is for example of the electronic component type, or MEMS or NEMS, or MOEMS or NOEMS, or bio-component, or passive component or component serving for the conductive passage between the front and rear faces of the device or serving only for the conductive passage between the front and back of the device.

0035The buffer layer advantageously has a thickness of between 10 nm and 10 μm.

0036The buffer layer may be PMDA-DAH or PMDA EAD or PMDA ODA or PMDA DNB, or poly-V3D3, or an organic mineral resin or parylene C or parylene N or parylene D.

0037In a method or a device according to the invention, the coating material may be epoxy or polyurethane or elastomeric or silicone or acrylic or methacrylate or polypropylene or fusible glass or fuse glass mixed with silica particles.

0038In a method or a device according to the invention, in the case where there is a host matrix with cavities, the host matrix may be silicon or AsGA or InP or glass. In addition, the surface of this wafer or host matrix may comprise one or more semiconductor components among electronic components, MEMS or NEMS, MOEMS or NOEMS, or bio-components, or passive components.

BRIEF DESCRIPTION OF THE DRAWINGS

0039<ul><li>The <figref idref="f0001">Figures 1, 2 and 3</figref> represent examples of devices according to the invention,</li><li>the <figref idref="f0002">figure 4</figref> represents one of the devices according to the invention in the form of a reconstituted wafer,</li><li>the <figref idref="f0002 f0003 f0004">Figures 5A - 5F</figref> are steps of an exemplary implementation of a method according to the invention,</li><li>the <figref idref="f0004">figure 6</figref> is a table showing the properties of materials proposed as buffer layer in the context of the invention,</li><li>the <figref idref="f0004 f0005 f0006">Figures 7A-7F</figref> are steps of an exemplary implementation of a second method according to the invention,</li><li>the <figref idref="f0006">Figures 8A-8C</figref> illustrate the problems identified by the inventors,</li><li>the <figref idref="f0007">figure 9</figref> illustrates an example of application of a device made according to the invention after passing through an above-IC processing line.</li></ul>

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

0040Embodiments of the invention are detailed below, illustrated by the <figref idref="f0001 f0002 f0003 f0004 f0005 f0006">Figures 1 to 7</figref> in which the references of the different elements are common to the different figures.

0041A first device according to the invention is shown in section on the <figref idref="f0001">figure 1</figref>.

0042This device comprises one or more electronic components 4 and 4 'of maximum thickness h and width L1. The active faces of the components are designated by the references 10 and 10 ': these are the faces on which are made the elementary components defining the functionalities of the components. The faces 10 and 10 'are flush with the face 8, said front face of the device. The device according to this mode, but also according to the other embodiments, extends substantially in a plane xy, its thickness h in the direction z, perpendicular to the plane xOy being small relative to its directions of extension in this same plane xOy, the thickness h ranging from 10 μm or from 300 μm to a few millimeters, for example 1 mm or 5 mm,

0043The device further comprises a buffer layer <b>6</b> present at least on the sides 5 and 5 'of the components and on the face 8 of the device. In this example but also in the examples which follow, parts of these components which are substantially perpendicular to the xOy plane of the device are referred to as component flanks. This buffer layer is of thickness e. In the case where there is more than one component, the thickness e is chosen so that it does not completely fill the space between two components. Advantageously, e is smaller than 0.1 times w, width of this space.

0044Finally, a coating material 3, different from the material of the buffer layer, is present, separated from the components 4 and 4 'and the face 8 of the device by the buffer layer 6. Thus, between two components, along a parallel axis in the plane of the surface 8 or the xOy plane, except perhaps for a thickness e close to the surface 8, two components are separated by at least a first buffer layer portion, a coating material layer and a second portion of buffer layer.

0045One or more of the components 4 may be chosen from various types of microelectronic components, for example each may be an integrated circuit, and / or a MEMS or NEMS sensor, and / or an optical component (MOEMS or NOEMS) and / or a biocomponent and / or a switch, and / or a component serving solely as conductive passage between the two faces of the device. These components may all be identical or different from each other (they may in particular have different thicknesses from each other).

0046The face 8 can then be treated by microelectronic or "above-IC" methods, as explained below.

0047The buffer layer 6 has properties enabling it to limit or absorb the stresses that may appear between, on the one hand, coating material and, on the other hand, the component or components and the possible plate, when climbs and / or descents at temperatures.

0048Thus, this buffer layer preferably has a low Young's modulus, lower than that of the coating resin. This Young's modulus of the buffer layer is advantageously between 1.5 GPa and 10 GPa.

0049The buffer layer has a glass transition temperature Tg (6) lower than that of the coating material 3 Tg (3), for example between 80 ° C and 150 ° C (this is the case of parylene), the materials coating 3 - and especially those given here as an example - generally having a glass transition temperature between 120 ° C and 220 ° C.

0050For example, the buffer layer may be PMDA-DAH or PMDA EDA or PMDA ODA or PMDA-DNB or PMDA-PDA, or poly-V3D3 (it is poly (1,3 , 5-trivinyltrimethylcyclotrisiloxane)) or an organic mineral resin or parylene C or parylene N or parylene D. Advantageously, the buffer layer 6 is parylene C or parylene N or parylene D whose properties are given in FIG. picture of the <figref idref="f0004">figure 6</figref>. It is recalled that PMDA is 1,2,3,5-benzenetetracarboxylic anhydride, DNB is 2,4-diaminonitrobenzene, ODA is 4,4-oxydianiline and EDA is ethylenediamine, DAH is 1 6-diaminohexane, the PDA is 1,4-phenylenediamine.

0051The coating material 3 advantageously has a low coefficient of thermal expansion (CTE), that is to say for example between 5 ppm / ° C and 50 ppm / ° C, more particularly less than 20 ppm / ° C.

0052As an example of coating material 3, mention may be made of epoxy resin, polyurethane, elastomer, silicone materials, acrylic, methacrylates, polypropylene, or fusible glass. To reduce the CTE of each of these materials, it may be chosen to mix them with particles, for example silica, or another type of material in order to give the coating material thus formed electrical properties and / or thermal and / or mechanical.

0053The <figref idref="f0001">figure 2</figref> represents a particular case of the first embodiment of the invention where the device comprises only one component 4, which has no neighboring components. In this particular case, the buffer layer flush with the surface 8 has, in addition, been removed, updating the surface 9 of the material 3, a step of thickness e then being present between the surface 10 and the surface 9. This device further comprises a reinforcing substrate 80 bonded to the rear face of the device.

0054The <figref idref="f0001">figure 3</figref> illustrates a third embodiment of the invention wherein the various discrete components 4, 4 'and 4 "are arranged in one or more cavities 7 and 7' made inside a matrix 2, of thickness h. note that it is possible to have several components in the same cavity (this is the case of the two components 4, 4 'of the <figref idref="f0001">figure 3</figref>). The front face 11 of the die 2 is flush with the face 8 of the device, and is therefore approximately the same level as the faces 10, 10 'and 10 "of the components 4. Preferably, the host matrix is ​​made of a material whose CTE is identical or similar to that of the discrete components, for example it is a semiconductor material, such as silicon.

0055In the matrix 2, two neighboring cavities 7, 7 'can be separated by a distance designated by L₂, L₁ designating the width of a component. Orders of magnitude for the dimensions of h, L₁ and L₂ are given later.

0056In the embodiment of the <figref idref="f0001">figure 3</figref>the flanks of the cavities 7 are covered by the buffer layer 6 whose thickness e is chosen so that it does not completely fill the spaces between two components and the gaps between the edges of the cavities 7 and the edges 5, 5 or 5 "of the components Advantageously, e is smaller than 0.1 times w and w ', respective widths of these intervals.

0057The <figref idref="f0002">figure 4</figref> represents an integrated device according to the invention, of the type of the <figref idref="f0001">figure 3</figref>. This device therefore comprises a substrate consisting of the home matrix<b>2.</b> In this matrix are inserted a plurality of components 4, 4 ', 4 "whose active surfaces 10, 10', 10" are visible in the plane of a face 8 of the device. The different components may have different thicknesses, and in particular different from that of the matrix 2. The face 11 of the matrix 2 may have been treated (processed), before formation of the cavities<b>7.</b> The reconstituted wafer of the <figref idref="f0002">figure 4</figref> may then, after application of the method of the invention, be treated by methods of type "above IC", as explained below.

0058Examples of materials for the buffer layer and the coating layer of the embodiment of the <figref idref="f0001">figures 3</figref> and <figref idref="f0002">4</figref> are those already given above in connection with the <figref idref="f0001">Figures 1 and 2</figref>.

0059For all the examples described above, orders of magnitude for the dimensions h, w, e, L₁ and L₂ may be:<ul><li>h may be between 10 μm and a few mm, it is for example of the order of 5 mm,</li><li>w and w 'may be between 100 μm and a few mm, these values ​​are for example of the order of 1 mm,</li><li>e may be between 10 nm and some μm, it is for example of the order of 10 μm,</li><li>The₁ may be between 100 μm and a few mm, for example of the order of 2 cm,</li><li>The₂ may be between 100 μm and a few mm, for example of the order of 2 cm,</li></ul>

0060These values ​​are examples, and other values ​​are possible outside the specified ranges.

0061The devices described in connection with the <figref idref="f0001">Figures 1, 2 and 3</figref>with the components 4, the coating material 3, and the buffer layer 6 may, after being made, be the subject of various treatments or processes. Examples of such processes include "Above IC". These "Above-IC" type processes that can be performed on the face<b>8</b> of the device and on the active faces 10 of the components, and possibly on the face 11 of the matrix 2, may be of the type:<ul><li>integration of thin film passive components (resistors and / or capacitors and / or inductors),</li><li>and / or rerouting electrical contacts and / or forming a complex set of tracks and contacts between the components 4, 4 'and 4 ". This assembly can be composed of stacks of metallic and insulating materials, so as to form for example, interconnections (layer 30 of the <figref idref="f0001">figure 3</figref>)</li><li>and / or integrating, on the surface 10 of the components 4, optical components (for example micro-lenses) or interconnect pads, for example by growing fusible beads, or transfer of balls, or manufacturing of "Stud Bump ", or growth of micro-inserts, or hybridization of components on the wafer (Chip on Wafer).</li></ul>

0062These same treatments can be performed on any device, comprising at least one component 4, a buffer layer 6 and a coating material 3, obtained by combining all or part of the 3 embodiments described above.

0063An example of a method according to the invention will be given, in connection with the <figref idref="f0002 f0003 f0004">Figures 5A-5F</figref>. This example of a method makes it possible in particular to obtain the devices of the<figref idref="f0001">Figures 1 and 2</figref>.

0064The component (s) 4 and 4 'are placed on a rigid and plane support 21, which is, for example, a support substrate made of silicon, or glass, or a quartz mask or a plate of alumina or polymer (<figref idref="f0002">Figure 5A</figref>). Advantageously, this substrate has a CTE close to or even identical to that of the components 4 in order to ensure good positioning of the components (thus limiting the displacements and / or stresses at the time of hardening of the coating material 3 (made for example by heating around 200 ° C)).

0065The placement equipment of the component (s) 4 makes it possible to reach a micron lateral precision, with parallelism better than 5.10^-4 rad. These values ​​are sufficient to resume, during the subsequent integration on the face 8, contacts on the connection pads of the components located on the active face and which generally have a width of the order of a few tens of microns.

0066The temporary holding of the component (s) on the support 21 will preferably be done thanks to an adherent layer 22 deposited on the support (<figref idref="f0002">Figure 5A</figref>). This layer 22 is preferably able to withstand the subsequent heat treatment of curing the resin 3. It can be removed later. This may be for example a resin deposited by spinning, or a laminated adhesive film, or a photosensitive polymer, or a spray ...

0067The components are then positioned with their active face turned towards the support 21 or to the possible adhesion layer 22 formed on the support 21. The alignment can be achieved by means of patterns that have been made beforehand on the substrate support 21 or on the adherent layer 22. There will thus be a space X between two components.

0068A thickness e of buffer layer 6 is then deposited with a high degree of conformity (<figref idref="f0003">Figure 5B</figref>). This buffer layer 6 covers the rear face and the sides 5 of the component (s) 4, 4 ', as well as the substrate 21 (or any adhesive layer 22).

0069This layer 6 is preferably chosen for its qualities of wettability and chemical inertness with the material of the substrate 21 (and / or the optional adherent layer 22).

0070Advantageously, to absorb the stress in tension and easily deform when the temperature decreases, the buffer layer has a low Young's modulus advantageously between 1.5 GPa and 10 GPa. Conversely, to absorb compression stresses during annealing, this buffer layer preferably has a glass transition temperature Tg (6) less than the glass transition temperature Tg (3) of the coating material 3. Tg (6) is for example between 80 ° C and 150 ° C, the coating materials 3 generally having a glass transition temperature of between 120 ° C and 220 ° C.

0071The thickness e of this buffer layer 6 is chosen so that it does not completely fill the spaces X between two components. For example, it is chosen less than 0.1 times w, w denoting the width of the space X.

0072This buffer layer 6 can be deposited by ALD, by CVD, by sol-gel process or in the gas phase, which processes are adapted to the desired thicknesses. Advantageously, the buffer layer 6 is in parylene C or in parylene N or in parylene D, the properties of which are given in the table of FIG.<figref idref="f0004">figure 6</figref>.

0073The encasing material 3 is then filled with the free space present between the components 4, covered with the buffer layer 6 (<figref idref="f0003">Figure 5C</figref>). The material 3 is separated from the component or components, the support substrate and the optional adhesive layer by at least the buffer layer 6. This material 3 is for example dispensed locally by syringe or, more coarsely, by depositing a or big drops in a mold or thanks to a spinning deposit. The penetration of coating material between two components can then be facilitated by a vacuum. This coating material 3 is then cured (for example by heating).

0074Thinning and polishing of the rear face 8 'can then be performed (<figref idref="f0003">figure 5D</figref>). For some components 4, or for all components 4, this thinning can remove the buffer layer present on the back of the components 4. In addition, this thinning of the device can lead to the reduction of the thickness of a part or all components.

0075The device can then be detached from the support 21 and the possible adhesion layer 22 (<figref idref="f0003">figure 5E</figref>). These are removed, depending on their nature, by peeling, by chemical etching or by insolation of the adhesion layer 22 through the support 21 if the latter is transparent. In some cases, the support will be maintained, especially if the substrate 21 (and any adhesive layer 22) is transparent at certain wavelengths and if one or more of the components 4 is an optical component.

0076It may be envisaged, before or after the step of removing the support 21, to glue the rear face of the device onto a reinforcing support 80 in order to stiffen the assembly (<figref idref="f0003">figure 5E</figref>).

0077It is then possible to proceed on the front face 8 to a withdrawal of a thickness e of the buffer layer 6, (<figref idref="f0004">figure 5F</figref>), thus updating the coating material 3, in particular in the areas separating the components 4. But the material of the buffer layer is always present so as to allow separation between the coating material 3 and the flanks components 4; the material 3 and the buffer layer 6 then have a step of thickness e with respect to the faces 10 of the component (s) 4.

0078Then the device can be introduced into a microelectronic type line for "Above IC" steps, for example of the type already described above.

0079A method according to a second embodiment of the invention is presented in connection with the <figref idref="f0004 f0005 f0006">Figures 7A-7F</figref>. This process makes it possible, among other things, to implement the device of the<figref idref="f0001">figure 3</figref>.

0080We select (<figref idref="f0004">Figure 7A</figref>) a wafer 1, made of a material having a CTE close to the CTE of the component or components. For example it is in AsGa or virgin silicon or it is already treated. This wafer may comprise, inter alia, positioning patterns and / or components (for example in a thin layer) and / or conducting vias which pass through the wafer.

0081We realize in this plate (<figref idref="f0004">Figure 7B</figref>) cavities <b>7</b> by a technique such as laser engraving, chemical etching or ultrasonic machining. The host matrix was thus formed<b>2.</b>

0082The components 4 are then placed in cavities 7 (<figref idref="f0005">Figure 7C</figref>), the components 4 may be of the same type as those presented in the method described above. The host matrix<b>2</b> may, for this purpose, be positioned on a rigid support substrate 21 and plane, which is for example another wafer, silicon or glass or a quartz mask or an alumina plate. Advantageously, the support substrate also has a CTE close to or even identical to that of the host matrix 2 and components 4 to ensure proper positioning of the components by limiting displacements and / or stresses at the time of hardening of the material coating 3 (made for example by heating around 200 ° C).

0083The temporary holding of the components and the host matrix on the support 21 can be done thanks to an adherent layer 22 deposited on the support (<figref idref="f0005">Figure 7C</figref>). This layer 22 is chosen in the same way as in the first method described above.

0084The components are then positioned with their active face turned towards the support 21 or towards the possible adhesion layer 22 formed on the support 21. The alignment in the cavities can be achieved by means of patterns that have been previously produced. , either on the home matrix <b>2</b> either on the support substrate 21 or on the adherent layer 22. In a variant, it is possible to first have the components on the support 21 (or on the adherent layer 22) and then to bring the host matrix 2 around positioned components.

0085There remain spaces X and X 'between two components or between a component and the flanks of the surrounding cavity.

0086A buffer layer 6 is then deposited with a high degree of conformity (<figref idref="f0005">Figure 7D</figref>). This buffer layer 6 covers the rear face and the sides of the components 5, the rear face 11 'of the wafer, the flanks of the cavities 7 and the substrate 21 (or the optional adherent layer 22). This buffer layer 6 is chosen so as to meet the same criteria as those mentioned above and is deposited by the same means.

0087The thickness e of this buffer layer is chosen so that it does not completely fill the cavities X and X '. This thickness is advantageously less than 0.1 times (at least 10 times smaller than) w ', w' denoting the width of the space X ', w' is of the same order of magnitude as w, width of the space X.

0088Then, in each cavity 7, the free space is filled by the coating material 3 (<figref idref="f0005">figure 7E</figref>), the material 3 being in direct contact only with the buffer layer 6. This material is for example dispensed locally to the syringe or, more coarsely, by depositing one or large drops on the wafer. The penetration of the coating resin in between two components and in the cavities 7 can be facilitated by a vacuum. This filling material 3 is then hardened (for example by heating).

0089It is then possible to carry out polishing steps on the back and / or to remove the support substrate and / or to add a reinforcing substrate (<figref idref="f0006">figure 7F</figref>) as in the previous embodiment.

0090The <figref idref="f0006">figure 7F</figref> illustrates the possibility of removing the buffer layer present on the front face of the device during or after the step of removing the support substrate. In this way, the coating material 3 is updated, the material of the buffer layer is always present so as to allow separation between the coating material 3 and the flanks of the cavities 7 and components 4. Finally, the material 3 and the buffer layer 6 then have a step of thickness e with respect to the face 11 of the host matrix and to the faces 10 of the component or components 4.

0091Then the wafer can be reintroduced into a microelectronic type line for "Above IC" steps, for example of the type already described above.

0092Compared to the previous method, the addition of a host matrix has the advantage of having around the components 4 a surface on which integration of microelectronic components and / or MEMS / NEMS may already have been performed. Thus, this method embodying the invention makes it possible not only to create a multi-component device but to create "system in chip" type devices in which the component (s) can undergo a "above-IC" type integration simultaneously with the device. integration of the components present initially on the host matrix, thus avoiding a thickening of connections.

0093As presented <figref idref="f0005 f0006">Figures 7C to 7F</figref>it is possible to have several components integrated in the same cavity of the host matrix 2.

0094The process illustrated by the <figref idref="f0002 f0003 f0004">Figures 5A to 5F</figref> can be used to integrate more than two components and this method does not use a host matrix around the components, the reconstituted wafer being composed of the integrated discrete component or components, the buffer layer has at least laterally with respect to these components and of a matrix composed at least by the coating material 3.

0095Compared to conventional assembly technologies of components in a wafer ("Chip In Wafer" technique), the methods according to the invention, thanks to the physical properties of the buffer layer, make it possible to minimize the stresses in the filling material which can bend platelets. In addition, these processes facilitate the industrialization of the process by eliminating the risks of miscibility or poor wettability between the coating material 3 and the adhesion layer.

0096Finally, a method according to the invention makes it possible to mix components 4 already tested ("Known Good Die"), sources and different thicknesses in the same matrix 2. It is for example possible to integrate components used only to conductive passage between the two faces of the matrix.

0097The <figref idref="f0007">figure 9</figref> illustrates a case of use of a device 100 according to the invention. According to this device, there was added a layer 30 deposited by "above IC" type process, this thin layer may be composed of redistribution lines of electrical contacts, passive components of the type Resistance, Inductance, Capacity, filters, optical waveguides ... etc.

0098On top of this layer 30 has been deposited at least one electronic component 40 may be of the same type as the components inserted in the reconstituted wafer. This or these upper components 40 are fixed by means of connection elements of the fuse-ball type 45, micro inserts, stud-bump, conductive polymer etc ....