Device having plurality of integrated circuits in a matrix

p0001The invention relates to the field of assembling microsystems or nanosystems across a wafer, eg, semiconductor material such as silicon.

p0002It relates in particular to the applications which call for integration technologies for high density passive components, detectors or optoelectronic components or MEMS or NEMS directly on the circuits, commonly called "Above IC".

p0003Currently, the processes of heterogeneous integration can not be done on entire silicon wafer. The processes "Above IC" are therefore limited to areas where the microsystem integrator may have platelets, which implies significant costs in terms of game masks and wafer fabrication in a foundry.

p0004In addition, for applications such as telephony, the active surface of the integrated circuits is not sufficient to accommodate all the necessary elements to the system y (passive components, amplifiers, switch, SAW or BAW components), which is particularly due the fact that the yield decreases when the complexity of the chip increases. It is therefore necessary to assemble post manufacturing the various elements on PCB type substrates (printed circuit board) or ceramic. The architectures are often complex and assembly and interconnection require many individual operations (component placement and wire bonding).

p0005There is another technique for integrating many features on a single chip, while having good returns. In this technique, a wafer is reconstituted from discrete chips arranged on a carrier wafer and then sealing them with a coating material and removing the supporting wafer. This reconstituted wafer allows for the type of integrations "above IC" mixing components from multiple sources and assembled in a format suitable for submission tools available to the industry. Furthermore, this technique allows for complex devices containing components manufactured on different substrates, choosing only the functional components.

p0006This technique, in which temporarily bonds the active faces of the components of an adhesive and then are coated and sends a rerouting above was published in <nplcit id="ncit0001" npl-type="s"><text>1992 Chang-Lee Chen et al. In an article titled "Bond Wireless Multipchip Packaging Technology for High Speed ​​Circuits," in "IEEE Transactions On component Hybrids and Manufacturing Technology, Vol. 15, No. 4, pages 451-456</text></nplcit>. "

p0007Also known in this type of technique, the methods disclosed in <patcit id="pcit0001" dnum="US5353498A"><text>US 5353498</text></patcit> and <patcit id="pcit0002" dnum="US5497033A"><text>US 5497033</text></patcit>And the technique described in document <patcit id="pcit0003" dnum="FR2857157"><text>FR 2857157</text></patcit>. The technique described in document<patcit id="pcit0004" dnum="FR2864342"><text>FR 2864342</text></patcit> applies to components already in a housing; it is very complex because it must then grinding a portion of the housing to return the component contacts.

p0008Finally, according to another method, described in the document <patcit id="pcit0005" dnum="GB2202673A"><text>GB 2202673</text></patcit> and shown schematically in the <figref idrefs="f0006">Figures 8A-8C</figref>, Discrete chips are arranged in cavities <b>107</b> present in a host plate and sealed with a potting material to form a reconstituted platelet containing components. The thus presented technique uses so required for its unfolding a support substrate 121 on which there is present an adhesive film 122. The adhesive layer enables to maintain the bearing plate and the active chips on the supporting substrate during the method steps during which filling material is not yet filed and therefore can not ensure the mechanical elements of the reconstituted wafer.

p0009This coating layer may have three types of defects illustrated in <figref idrefs="f0006">Figures 8A-8C</figref>.

p0010First, during the deposition of the coating material, the material can not adhere to the adhesive layer (<figref idrefs="f0006">8A</figref>); on the contrary, it can interact so excessive with the adhesive layer and can therefore be miscible (<figref idrefs="f0006">8B</figref>). So we, as appropriate, or an area (s) of constriction 113 (<figref idrefs="f0006">8A</figref>) Or areas 123 of mixing of the material 103 and adhesive 122 (<figref idrefs="f0006">8B</figref>). Upon removal of the adherent layer, these case miscibility or de-wetting can lead to broken away of the coating material, or components, to the appearance of significant constraints on the wafer or the poor performance of the components.

p0011Thermal expansion coefficients (CTE) different from the one hand, the coating layer 103 (CTE close to 10ppm / ° C or greater than this value) and, on the other hand, the substrates of the wafer of host 102 and / or components 104 (near CTE of 2.3 ppm / ° C for silicon) induce the appearance of high stresses in the coating layer (<figref idrefs="f0006">8C</figref>) During temperature changes, for example during curing of the coating layer. These stresses induce a deformation of the wafer and even ruptures. They are identified on the<figref idrefs="f0006">8C</figref> by zones 110, 110 'and are located either on the periphery of the components 104, either on their rear face.

p0012The invention aims to solve these problems.

p0013It aims to reduce the impact of the difference in CTE on the stresses in the plate.

p0014Another object of the invention is to improve the interface between the device during manufacture and the adhesion layer.

PRESENTATION OF THE INVENTION

p0015The invention firstly relates to an electronic device, having a front face and a rear face provided with at least one integrated discrete component, the active face of the component appearing on the side of the front face and comprising:<ul><li>a coating material, present at least laterally with respect to the component, ensuring the maintenance of the said component in the device,</li><li>a buffer layer absent of the active face of the component, separating the coating material or component (s).</li></ul>

p0016In the case of two adjacent components, the buffer layer does not completely fills the space between the components, the remaining space between the components or between the buffer layer portions present on the flanks of the components, being occupied by the material 'coating.

p0017In one embodiment, the or component (s) is (are) provided (s) in at least one cavity present in a host matrix, the cavity or cavities through the host matrix, the buffer layer being at less present on the flanks of the cavity or cavities. The buffer layer thus separates the coating material or component (s) and the receiving matrix, and is absent from the front of the host matrix. It does not entirely fill the space between the flanks of the cavity or cavities and component sides.

p0018Whatever the embodiment, the buffer layer has properties allowing it to restrict or absorb the stresses which may occur between, on the one hand, the coating material and, on the other hand, the component and possible wafer, when driving uphill and / or downhill in temperatures.

p0019According to two variants of each of the previous devices:<ul><li>the buffer layer can mask the coating material on the front face of the device;</li><li>the coating material may be visible on the front of the device, the buffer layer is only present on the flanks of the component, the coating material and the buffer layer having a back with respect to the active surface of the components.</li></ul>

p0020The invention also relates to a method of integrating at least one discrete component integrated in a wafer, said reconstituted wafer, in which method:<ol><li>a) positioning at least one discrete component on a substrate, said support substrate,</li><li>b) subsequently depositing a buffer layer at least on the rear face and the sides of the component, said buffer layer is not deposited on the surfaces in contact with the substrate.</li><li>c) subsequently depositing a coating material at least laterally relative to the component, the material being deposited only on surfaces covered by the buffer layer.</li></ol>

p0021Step a) may include positioning one or more components in one or more cavities extending through a receiving matrix.

p0022The formation of the buffer layer in step b) is performed at least on the rear face of the matrix and the sidewalls of the cavity or cavities, said buffer layer does not completely filling the space between the flanks of the cavities and side components, and separating, after step c), the coating material of the host matrix material.

p0023The matrix may be positioned first on the support substrate, then the components are positioned in the cavity or cavities of the host matrix. Conversely, the matrix may only be placed once the discrete components positioned, the one or more cavities surrounding the components.

p0024The support substrate may be of silicon, or glass, or alumina, or quartz or polymer.

p0025A method according to the invention may further comprise a step of thinning the backside of the wafer.

p0026A method according to the invention may further comprise a step of bonding the rear face of a backing substrate used to provide mechanical strength.

p0027In a method according to the invention, an adherent layer may be deposited on the support substrate prior to step a), the buffer layer deposited in b) being deposited on at least a portion of the material member not occupied by a component, the rear and sides of the or component (s) and optionally on the back of the host matrix and the sidewalls of the cavities.

p0028In a method according to the invention the buffer layer preferably adheres to the adhesion layer and the rear face and the sides of or component (s) and is preferably immiscible with the adherent layer. Thus, the buffer layer prevents the reaction material formed on the surface of the adherent layer while maintaining the various elements on the support substrate.

p0029In addition, to reduce the effects of stress buffer layer, for example occurring in the reconstituted wafer during integration processes above IC or during curing of the coating material, preferably has a glass transition temperature below that of the material coating. It is then deformed under the influence of compressive stresses. To ensure its deformation during negative variations in temperature, the buffer layer also preferably has a low Young's modulus.

p0030In a method according to the invention, the buffer layer may be deposited in the gas phase, or by ALD or CVD, or sol-gel process.

p0031In a method or a device according to the invention, the component (s) has / have a substrate, for example mainly made of silicon, or GaAs, or InP or glass. In addition, each component can be of different sizes and types of the scale or type of other components integrated in the same wafer.

p0032Each component is for example the electronic component type or MEMS or NEMS or MOEMS or NOEMS, or bio-component or passive component or component for the conductive path between the front and back of the device or only used for conductive path between front and rear faces of the device.

p0033The buffer layer preferably has a thickness between 10 nm and 10 microns.

p0034The buffer layer may be PMDA-DAH or PMDA EAD or PMDA ODA or PMDA DNB, or poly-V3D3, or in a mineral organic resin or parylene C or parylene N or parylene D.

p0035In a method or a device according to the invention, the coating material may be epoxy or polyurethane or elastomer or silicone or acrylic or methacrylate or polypropylene or glass or glass fuse type fuse mixed with silica particles.

p0036In a method or a device according to the invention, in the case where there is a host matrix having cavities, the host matrix can be made of silicon or GaAs or InP or glass. In addition, the surface of the wafer or host matrix can include one or more semiconductor components including electronic components, MEMS or NEMS, the MOEMS or NOEMS, or bio-components, and passive components.

BRIEF DESCRIPTION OF DRAWINGS

p0037<ul><li>The <figref idrefs="f0001">Figures 1, 2 and 3</figref> illustrate examples of devices according to the invention,</li><li>the <figref idrefs="f0002">4</figref> represents one of the devices according to the invention in the form of a reconstituted wafer, </li><li>the <figref idrefs="f0002 f0003 f0004">5A - 5F</figref> are steps of an exemplary implementation of a method according to the invention,</li><li>the <figref idrefs="f0004">6</figref> is a table showing the available material properties as a buffer layer in the framework of the invention,</li><li>the <figref idrefs="f0004 f0005 f0006">7A-7E</figref> are steps of an exemplary implementation of a second method according to the invention,</li><li>the <figref idrefs="f0006">Figures 8A-8C</figref> illustrate the problems identified by the inventors,</li><li>the <figref idrefs="f0007">9</figref> illustrates an example of application of a device made according to the invention after passing through a processing line above-IC.</li></ul>

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

p0038Embodiments of the invention are detailed below, illustrated by the <figref idrefs="f0001 f0002 f0003 f0004 f0005 f0006">Figures 1 to 7</figref> in which the references of the various elements are common to various figures.

p0039A first device according to the invention is shown in cross section in <figref idrefs="f0001">figure 1</figref>.

p0040This device includes one or more electronic components 4 and 4 'of h and maximum width L1 thickness. The active component faces are designated by the references 10 and 10 ': these are the faces on which the basic components are made defining the features of the components. The faces 10 and 10 'are flush with the face 8, said front face of the device. The device according to this mode, but also according to other embodiments, extends substantially in the xy-plane, its thickness h in the z direction, perpendicular to the plane xOy is small relative to its directions of extension in the same plane xOy, the thickness h may range from 10 microns or 300 microns to a few millimeters, for example 1 mm or 5 mm, the dimensions of the device in the xOy plane ranging from 150 mm to 400 mm or even more, in particular for glass slab.

p0041The device further comprises a buffer layer <b>6</b> present at least on the sides 5 and 5 'of the components as well as the face 8 of the device. In this example but also in the following examples, called flanks of the part components of these components which are substantially perpendicular to the plane xOy of the device. This buffer layer is of thickness e. In the case where there is more than one component, the thickness e is selected such that it does not completely fill the space between two components. Advantageously, e is smaller than 0.1 times w, width of this space.

p0042Finally, a 3 different coating material of the buffer layer material is present, separated from the components 4 and 4 'and the face 8 of the device by the buffer layer 6. Thus, between the two components, along an axis parallel the surface plane 8 or the plane xOy, except perhaps for a thickness e close to the surface 8, two components are separated by at least a first portion of buffer layer, a layer of coating material and a second portion buffer layer.

p0043One or more of the components 4 can / may be selected from various types of microelectronic components, for example each may be an integrated circuit, and / or a MEMS or NEMS sensor, and / or an optical component (MOEMS or NOEMS) and / or a biocomponent and / or a switch and / or a component serving only conductive pathway between the two faces of the device. These components may all be identical or different between them (in particular they may have different thicknesses from each other).

p0044The face 8 may then be treated by microelectronic type of process or "above-IC", as explained below.

p0045The buffer layer 6 has properties allowing it to restrict or absorb the stresses which may occur between, on the one hand, the coating material and, on the other hand, the component or components and the possible wafer at mounted and / or raids in temperatures.

p0046Thus, the buffer layer preferably has a low Young's modulus lower than that of the sealing resin. The Young's modulus of the buffer layer is advantageously between 1.5 GPa and 10 GPa.

p0047The buffer layer preferably has a glass transition temperature Tg (6) lower than that of the coating material 3 Tg (3), for example between 80 ° C and 150 ° C (this is the case of parylene ), the coating materials 3 - and in particular those given here as an example - generally having a glass transition temperature between 120 ° C and 220 ° C.

p0048For example, the buffer layer may be PMDA-DAH or PMDA EDA or PMDA ODA or PMDA-DNB or PMDA-PDA, or poly-V3D3 (this is poly (1,3 , 5-trivinyltrimethylcyclotrisiloxane)) or an organic mineral resin or parylene C or parylene N or parylene D. Advantageously, the buffer layer 6 is parylene C or parylene N or parylene D whose properties are given in table of <figref idrefs="f0004">6</figref>. Remember that the PMDA is 1,2,3,5-benzenetétracarboxylic dioxide, DNB is 2,4-diaminonitrobenzène, the ODA is 4,4 - oxydianiline and the EDA is ethylenediamine, DHA is 1 , 6-diaminohexane, the PDA is 1,4-phenylenediamine.

p0049The coating material 3 preferably has a coefficient of thermal expansion (CTE) low is - to - say for example between 5 ppm / ° C and 50ppm / ° C, especially less than 20 ppm / ° C.

p0050Examples of coating material 3, there may be mentioned epoxy resin, polyurethane, elastomer, silicone materials, acrylic, methacrylates, polypropylene, or a molten glass. To decrease the CTE of each of these materials, it can be chosen to mix them with particles, for example of silica, or another type of material in order to impart to the coating material thus formed electrical properties and / or thermal and / or mechanical.

p0051The <figref idrefs="f0001">2</figref> is a special case of the first embodiment of the invention where the device has only one component 4, which has no neighboring components. In this particular case, the buffer layer being flush with the surface 8 has, moreover, been withdrawn, updating the surface 9 of the material 3, a step thickness e is then present between the surface 10 and the surface 9. This device further comprises a reinforcing substrate 80 bonded to the rear face of the device.

p0052The <figref idrefs="f0001">3</figref> illustrates a third embodiment of the invention wherein the various discrete components 4, 4 'and 4' 'are arranged in one or more cavities 7 and 7' carried out inside a die 2, a thickness h. It is noted that it is possible to have several components in the same cavity (in the case of the two components 4, 4 'of the<figref idrefs="f0001">3</figref>). The front face 11 of the die 2 is flush with the face 8 of the device, and is therefore approximately the same level as the faces 10, 10 'and 10' 'of the component 4. Preferably, the host matrix is ​​a material which CTE is identical or similar to that of discrete components. It is for example a semiconductor material such as silicon.

p0053In the die 2, two cavities 7, 7 'adjacent may be separated by a distance designated by L₂, L₁ designating for its part the width of a component. Orders of magnitude for the dimensions h, L₁ and I₂ are given below.

p0054In the embodiment of the <figref idrefs="f0001">3</figref>The flanks of the cavities 7 are covered by the buffer layer 6 whose thickness e is selected such that it does not completely fill the spaces between the two components and the intervals between the edges 7 of the cavities and the edges 5, 5 'or 5' 'components. Advantageously, e is smaller than 0.1 times w and w ', respective widths of these intervals.

p0055The <figref idrefs="f0002">4</figref> shows an integrated device according to the invention, the type of the <figref idrefs="f0001">3</figref>. This device therefore comprises a substrate made of the host matrix<b>2.</b> In this matrix are inserted a plurality of components 4, 4 ', 4' 'the working surfaces 10, 10', 10 '' are visible in the plane of a surface 8 of the device. The various components may have different thicknesses, and particularly different from that of the matrix 2. The face 11 of the die 2 may have been processed (processée), before formation of the cavities<b>7.</b> The reconstituted wafer of <figref idrefs="f0002">4</figref> can then, after applying the method of the invention, be treated by such processes "above IC", as explained below.

p0056Examples of materials for the buffer layer and the coating layer of the embodiment of <figref idrefs="f0001">figures 3</figref> and <figref idrefs="f0002">4</figref> are those already given above in connection with <figref idrefs="f0001">Figures 1 and 2</figref>.

p0057For all examples described above, an order of magnitude to the dimensions h, w, e, L₁ and I₂ can be the following:<ul><li>h can be between 10 .mu.m and a few millimeters, it is for example of the order of 5 mm, </li><li>w and w 'may be between 100 microns and a few mm, these values ​​are for example of the order of 1 mm,</li><li>e may be between 10 nm and several microns, it is for example of the order of 10 microns,</li><li>L₁ may be between 100 microns and a few mm, for example of the order of 2 cm,</li><li>L₂ may be between 100 microns and a few mm, for example of the order of 2 cm,</li></ul>

p0058These values ​​are examples, and other values ​​are possible outside these ranges.

p0059The devices described in connection with the <figref idrefs="f0001">Figures 1, 2 and 3</figref>With 4 components, the coating material 3, and the buffer layer 6, after they have been made, be subjected to various treatments or processes. We can cite for example the type of process "Above IC". This type of process "above-IC" which may be made on the face<b>8</b> of the device and on the active faces 10 of the components, and optionally on the face 11 of the die 2 may be of the type:<ul><li>integration of passive components in a thin layer (resistances and / or capacities and / or inductors)</li><li>and / or rerouting of electrical contacts and / or formation of a complex set of tracks and contacts between the components 4, 4 'and 4' '. This set can be composed of stacks of metallic and insulating materials so as to form for example of interconnections (layer 30 of the<figref idrefs="f0001">3</figref>) </li><li>and / or integration, on the surface 10 of the components 4, optical components (e.g. of microlenses) or interconnect pads, for example by growth of fusible beads, or bead transfer, or manufacture of "Stud Bump "or growth of micro-inserts, or hybridization of components on the wafer (Chip on wafer).</li></ul>

p0060These treatments may be performed on any device, comprising at least one component 4, a buffer layer 6 and a coating material 3, obtained by combining all or part of the three embodiments described above.

p0061An exemplary method according to the invention will be given in conjunction with the <figref idrefs="f0002 f0003 f0004">5A-5F</figref>. This example method allows in particular to obtain the devices<figref idrefs="f0001">Figures 1 and 2</figref>.

p0062The procedure is the placement of the component 4 and 4 'on 21 a rigid and level surface, which is for example a silicon support substrate, or glass, or a quartz mask or an alumina plate or polymer (<figref idrefs="f0002">5A</figref>). Advantageously, the substrate has a CTE close or even identical to the components 4 to ensure proper positioning of the components (thus limiting the displacement and / or stresses on curing of the coating material 3 (produced for example by heating around 200 ° C)).

p0063The placement of equipment or components achieve a 4 micron lateral precision with better parallelism 5.10^-4 rad. These values ​​are sufficient to resume, when higher integration on the face 8, contacts on the connection pads of the components on the active face and generally have a width of the order of a few tens of microns.

p0064The temporary holding of the component on the support 21 will preferably through an adhesive layer 22 deposited on the support (<figref idrefs="f0002">5A</figref>). This layer 22 is preferably adapted to support the further hardening heat treatment of the resin 3. It may be withdrawn thereafter. This may for example be a resin deposited by spin coating or a laminated adhesive film or a photosensitive polymer, or a spray ...

p0065The components are then positioned with their active face 10 facing towards the support 21 or to the possible adhesion layer 22 formed on the support 21. The alignment can be achieved through the patterns which have been produced beforehand on the substrate support 21 or the adhesive layer 22. There will thus be a space X between the two components.

p0066A thickness e of buffer layer 6 is then deposited with high conformity (<figref idrefs="f0003">5B</figref>). This buffer layer 6 covers the rear face and the sides 5 of the component 4, 4 'and the substrate 21 (or the possible bonding layer 22).

p0067This layer 6 is preferably chosen for its qualities of wettability and chemical inertness with the substrate 21 material (and / or the possible bonding layer 22).

p0068Advantageously, to absorb tensile stresses and easily deform when the temperature decreases, the buffer layer has a Young's modulus low advantageously between 1.5 GPa and 10 GPa. Conversely, to absorb compressive stresses during annealing, the buffer layer preferably has a glass transition temperature Tg (6) lower than the glass transition temperature Tg (3) of the coating material 3. Tg (6) is for example between 80 ° C and 150 ° C, the coating materials 3 generally having a glass transition temperature between 120 ° C and 220 ° C.

p0069The thickness e of this buffer layer 6 is chosen so it does not completely fill the spaces X between two components. It is for example chosen to be less than 0.1 times w, w is the width of the space X.

p0070This buffer layer 6 may be deposited by ALD, CVD, sol-gel method or gas phase processes which are adapted to the desired thicknesses. Advantageously, the buffer layer 6 is parylene C or parylene N or parylene D whose properties are given in the table of the<figref idrefs="f0004">6</figref>.

p0071One then proceeds to filling, the material 3 by coating, the free space between the components 4, covered with the buffer layer 6 (<figref idrefs="f0003">5C</figref>). The material is separated 3 of the component, the support substrate and the possible release layer by at least the buffer layer 6. This material 3 is for example dispensed locally by syringe or, more crudely, by filing a or large drops in a mold or using a spin coating. The penetration of coating material between the two components can then be facilitated by the application of vacuum. The coating material 3 is then cured (e.g., by heating).

p0072Thinning and polishing the rear face 8 'can then be made (<figref idrefs="f0003">5D</figref>). 4 For some components, or for all components 4, this thinning can remove this buffer layer on the rear panel components 4. Moreover, this thinning of the device can lead to the reduction of the thickness of a part or all of the components.

p0073The device can then be lifted off the support 21 and the possible adhesion layer 22 (<figref idrefs="f0003">5E</figref>). These are removed, depending on their nature, by peeling, by chemical etching or by exposure of the adhesive layer 22 through the support 21 if the latter is transparent. In some cases, the carrier will be maintained, particularly if the substrate 21 (and the possible adhesive layer 22) is transparent to certain wavelengths and one or more of the components 4 is an optical component.

p0074It may be envisaged before or after the removing step the support 21, bonding the rear face of the device on a reinforcing support 80 in order to stiffen the assembly (<figref idrefs="f0003">5E</figref>).

p0075It is then possible to proceed on the front face 8 to a withdrawal of a thickness e of the buffer layer 6, (<figref idrefs="f0004">5F</figref>), Thereby updating the coating material 3, in particular in the areas between the components 4. However, the buffer layer material is still present so as to allow a separation between the coating material and the sides 3 the components 4; the material 3 and the buffer layer 6 then have a thickness of step e relative to the faces 10 of the component 4.

p0076Then the device can be introduced into a microelectronics line type for steps "Above IC", for example of the type already described above.

p0077A method according to a second embodiment of the invention is presented in connection with the <figref idrefs="f0004 f0005 f0006">7A-7E</figref>. This method allows among others to produce the device of the<figref idrefs="f0001">3</figref>.

p0078Selecting (<figref idrefs="f0004">7A</figref>) A wafer 1, a material having a similar CTE CTE of the component. For example it is GaAs or virgin silicon or she is already covered. This plate may comprise, inter alia, positioning patterns and / or components (e.g. thin layer) and / or conductive vias which pass through the wafer.

p0079Is produced in the wafer (<figref idrefs="f0004">7B</figref>) Of the cavities <b>7</b> by such as laser engraving technique, the chemical etching or ultrasonic machining. We formed the receiving matrix<b>2.</b>

p0080The next step is the placement of the components in the cavities 4 7 (<figref idrefs="f0005">7C</figref>), The components 4 can be the same type as those shown in the previously described process. The host matrix<b>2</b> may, for this purpose, be positioned on a rigid support substrate 21 and plane, which is for example another wafer of silicon or glass or a quartz mask or an alumina plate. Advantageously, the support substrate also has a CTE close or even identical to that of the host matrix 2 and the components 4 to ensure proper positioning of the components by limiting the mobility and / or the stresses at the time of hardening of the material coating 3 (produced for example by heating around 200 ° C).

p0081The temporary holding of the components and the host matrix on the support 21 can be done through an adhesive layer 22 deposited on the support (<figref idrefs="f0005">7C</figref>). This layer 22 is selected in the same way as in the first method described above.

p0082It then positions the components with their active face 10 facing support 21 or to the possible adhesion layer 22 formed on the support 21. Alignment in the cavities can be achieved through patterns that have been made beforehand or on the receiving matrix <b>2</b>Or on the support substrate 21 or to the adhesive layer 22. Alternatively it is possible to dispose the first components on the support 21 (or the subbing layer 22) and then to report the receiving matrix 2 around the positioned components.

p0083There remain spaces X and X 'between two components or between a component and the sidewalls of the cavity that surrounds it.

p0084A buffer layer 6 is then deposited with high conformity (<figref idrefs="f0005">7D</figref>). This buffer layer 6 covers the rear face and the sides of the components 5, the rear face 11 'of the plate, the sidewalls of the cavities 7 and the substrate 21 (or the possible bonding layer 22). This buffer layer 6 is chosen to meet the same criteria as those mentioned above and is deposited by the same means.

p0085The thickness e of this buffer layer is chosen such that it does not completely fill the cavities X and X '. This thickness is advantageously less than 0.1 times (at least 10 times smaller) than w ', w' is the width of the space X ', w' is the same order of magnitude as w, width of the space X.

p0086This is followed, in each cavity 7, filling of the free space by the coating material 3 (<figref idrefs="f0005">7E</figref>), The material 3 being in direct contact with the buffer layer 6. This material is for example dispensed locally by syringe or, more crudely, by depositing one or more large drops on the plate. The penetration of the coating resin in between two components and into the cavities 7 can be facilitated by application of vacuum. This filling material 3 is then cured (e.g., by heating).

p0087One can then proceed to the rear side polishing steps and / or withdrawal of the support substrate and / or adding a reinforcing substrate (<figref idrefs="f0006">7F</figref>) As in the previous embodiment.

p0088The <figref idrefs="f0006">7F</figref> illustrates the possibility of a withdrawal of this buffer layer on the front of the device during or after the step of removing the support substrate. In this way, the coating material 3 is updated, the buffer material layer is still present so as to allow a separation between the coating material 3 and the flanks of the cavities 7 and components 4. Finally, the material 3 and the buffer layer 6 then exhibit a step thickness e with respect to the face 11 of the host matrix and the faces 10 of the component 4.

p0089Then the wafer can be reintroduced into a microelectronic line type for steps "Above IC", for example of the type already described above.

p0090Compared to the previous method, the addition of a receiving matrix has the advantage of presenting the components 4 around a surface on which an integration of microelectronic components and / or MEMS / NEMS may have already been performed. Thus this method embodying the invention not only to create a multi-component but to create such devices device "system in chip" in which the component can undergo a type of integration "above-IC" Simultaneous with the integration of components originally present on the receiving matrix, thus avoiding connections allowance.

p0091As presented the <figref idrefs="f0005 f0006">7C to 7F</figref>, It is possible to have several components integrated in the same cavity of the host matrix 2.

p0092The process illustrated by the <figref idrefs="f0002 f0003 f0004">5A to 5F</figref> can be used to incorporate more than two components and this method does not use a host matrix around the components, the reconstituted wafer being composed of discrete components or integrated, of this buffer layer at least laterally with respect to these components and of a matrix composed at least by the coating material 3.

p0093Over conventional joining technologies components in a wafer (technique known as "Chip In Wafer"), the methods of the invention, thanks to the physical properties of the buffer layer serve to minimize stresses in the filling material which can bend platelets. In addition, these methods facilitate the industrialization of the process by eliminating the risks of miscibility or poor wettability between the coating material 3 and the adhesion layer.

p0094Finally, a method of the invention allows mixing of the components 4 already tested ( "Known Good Die"), of different sources and thicknesses in a single array 2. It is for example possible to integrate the components used only conducting passage between the two faces of the matrix.

p0095The <figref idrefs="f0007">9</figref> illustrates a case of using a device 100 according to the invention. According to this device, there has been adding a layer 30 deposited by type of process "above IC", this thin layer can be composed of lines of redistribution of the electrical contacts, type of passive components resistance, inductance, capacity, of filters, optical waveguides ... etc.

p0096Above this layer 30 was deposited at least one electronic component 40 can be the same type as the components inserted in the reconstituted wafer. This or these superior components 40 are fixed by means of connection type fuse elements ball 45 Micro inserts, stud-bump, polymer conductors etc ....