Method for voltage limitation for a transponder
Abstract
Die Erfindung betrifft eine Schaltung zur Spannungsbegrenzung bei einem Transponder mit einem Schwingkreis (19), der wenigstens eine Induktivität (12), eine Kapazität (13), ein Sperrschichtbauteil (27, 35) mit einem Eingang, Ausgang und Steuereingang, einen ersten Schwingkreisanschluss (25), der mit dem Eingang des Sperrschichtbauelements (27, 35) und einen zweiten Schwingkreisanschluss (26), der mit dem Ausgang des Sperrschichtbauelements (27, 35) verbunden ist, umfasst, wobei eine Verbindung des Steuereingangs des Sperrschichtbauteils (27, 35) mit dem ersten Schwingkreisanschluss (25) und mit dem zweiten Schwingkreisanschluss (26) besteht. Weiterhin wird ein Verfahren zur Spannungsbegrenzung bei einem Transponder vorgestellt, bei dem zur Spannungsbegrenzung im Sende- und Empfangsschwingkreis (10) der Steueranschluss des Sperrschichtbauelements (27, 35) mittels der Spannung des ersten (25) und zweiten (26) Schwingkreisanschlusses angesteuert wird.

Term
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Projected expiry 9 February 2027, counted from filing; an application has no term until it is granted.
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9 claims: 3 independent, 6 dependent
- 1Verfahren zur Spannungsbegrenzung bei einem Transponder mit einem ersten Sende- und Empfangsschwingkreis (10), der einen ersten Schwingkreisanschluss (25) und einen zweiten Schwingkreisanschluss (26) aufweist, wobei • ein steuerbares Sperrschichtbauelement (P1), mit einem Eingang, einen Ausgang und einem Steuereingang (27) vorgesehen ist, und • der Eingang mit dem ersten Schwingkreisanschluss (25) verschaltet ist, • der Ausgang mit dem zweiten Schwingkreisanschluss (26) verschaltet ist, und wobei von der Basisstation im Sende- und Empfangschwingkreis (10) zwischen dem ersten und zweiten Schwingkreisanschluss (25, 26) eine Wechselspannung induziert wird, dadurch gekennzeichnet, dass die im Sende- und Empfangsschwingkreis (10) induzierte Wechselspannung auf einen ersten Spannungswert (2.1) begrenzt wird, indem der Steuereingang (27) des Sperrschichtbauelementes (P1) mittels eines Schalters (S1) mit einer Spannungsquelle (Uref3) verbunden wird.
- 2Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass durch Öffnen des Schalters (S1) der Steuereingang (27) von der Spannungsquelle (Uref3) getrennt wird sodass die induzierte Wechselspannung auf einen zweiten Spannungswert (2.2), der kleiner als der erste Spannungswert ist, begrenzt wird.
- 3Verfahren nach Anspruch 2, dadurch gekennzeichnet, dass zur Lastmodulation die Spannung abwechselnd zwischen dem zweiten Spannungswert (2.2) und dem ersten Spannungswert (2.1) begrenzt wird.
- 4Verfahren nach Anspruch 2 oder Anspruch 3, dadurch gekennzeichnet, dass die Änderung von dem zweiten Spannungswert (2.2) auf dem ersten Spannungswert (2.1) kontinuierlich erfolgt, indem nach dem Trennen von der Spannungsquelle (Uref3) ein mit dem Steuereingang (27) verbundenes Speicherelement (C2) entladen wird.
- 5Verfahren nach einem der Anspruch 4, dadurch gekennzeichnet, dass eine stufenlose Modulation durchgeführt wird, indem das Speicherelement (C2) von einer Steuerschaltung (34) mittels des Schalters (S1) mit der Spannungsquelle (Uref3) verbunden und getrennt wird.
- 6Schaltung zur Spannungsbegrenzung bei einem Transponder aufweisend, einem ersten Sende- und Empfangsschwingkreis (10), der einen ersten Schwingkreisanschluss (25) und einen zweiten Schwingkreisanschluss (26) aufweist, wobei • ein steuerbares Sperrschichtbauelement (P1), mit einem Eingang, einen Ausgang und einem Steuereingang (27) vorgesehen ist, und • der Eingang mit dem ersten Schwingkreisanschluss (25) verschaltet ist, • der Ausgang mit dem zweiten Schwingkreisanschluss (26) verschaltet ist, • und wobei von der Basisstation im Sende- und Empfangschwingkreis (10) zwischen dem ersten und zweiten Schwingkreisanschluss (25, 26) eine Wechselspannung induziert wird dadurch gekennzeichnet, dass zur Begrenzung der induzierten Wechselspannung auf einen ersten Spannungswert (2.1) der Steuereingang (27 mittels eines Schalters (S1) mit einer Spannungsquelle (Uref3) verschaltet ist.
- 7Schaltung nach einem der Ansprüche 6, dadurch gekennzeichnet, dass der Schalter (S1) mit einem Steuereingang vorgesehen ist und an dem Steuereingang des Schalters (S1) eine Spannung (nMOD) einer Steuerschaltung (34) anliegt, und wobei der Schalter (S1) mittels der Spannung (nMOD) die Spannungsquelle (Uref3) mit dem Steuereingang (27) des Sperrschichtbauelementes (P1) verbindet oder trennt.
- 8Schaltung nach Anspruch 7, dadurch gekennzeichnet, dass zwischen dem Steuereingang (27) und dem Schalter (S1) ein Kondensator (C2) in Parallelschaltung vorgesehen ist.
- 9Schaltung nach Anspruch 8 oder Anspruch 7, dadurch gekennzeichnet, dass zum Entladen des Kondensators (C2) zwischen dem Steuereingang (27) und dem Kondensator (C2) eine Stromquelle (8) vorgesehen ist.
Independent claims9
36 paragraphs in 1 section, as filed
p0001The invention relates to a method for voltage limitation in accordance with the preamble of claim 1. Moreover, the invention relates to a circuit for voltage limitation in a transponder according to the preamble of patent claim 6.
p0002Such a method and such a circuit are known per se, in particular through RFID applications (RFID = Radio Frequency Identification). Under an RFID application is here understood to mean any application in which a transmitting resonant circuit provides an inductively coupled receiving resonant circuit with energy and reads via the receiving resonant circuit data. Such compounds are used for example for object identification, wherein a transmitting resonant circuit of a reader (reader) via a receiving resonant circuit a with a mark (tag) responds to an object marked and retrieves information.
p0003To contact the transmitting resonant circuit of the reader generates a high frequency magnetic field induced in an inductance of a receiving resonant circuit, which is located near the reader, an AC voltage. The voltage induced in the receiving resonant circuit AC voltage is rectified and used for example for supplying energy to a resonant circuit connected to the receiving integrated circuit. In addition, a clock frequency can be derived, which will put the integrated circuit, that is, for example, a microprocessor and / or memory element as the system clock can also available from the induced alternating voltage. With the addition of the inductance of the transmitting resonant circuit and / or receiving resonant circuit with capacities, particularly with parallel capacity to dither circuits resonance effects are achieved, which greatly improve the efficiency of energy transfer.
p0004A transmission of data from the reader to the receiving resonant circuit (downlink) can be effected for example by switching on and off of the magnetic field. For a data transfer in the reverse direction from the receiving resonant circuit to the reader, the so-called load modulation is used, which requires a sufficient proximity (distance less than 0.16 * wavelength) of transmitting and receiving resonant circuit. With sufficient proximity, the transformer coupling, in which the power consumption of the receiving coil depicting by a feedback to the transmitting resonant circuit in voltage changes at the transmitting resonant circuit. Controlled modulation of the load, ie the impedance of the receive oscillating circuit, therefore, elicit changes in voltage in the transmission resonant circuit, which can be evaluated for data transmission.
p0005With increasing quality of the inductors used in the receiving resonant circuit, that is with an increasing ratio of reactance to resistance to reduce the effective damping of the resonant circuit and the width of the resonance curve. The use of coil higher quality thus causes a higher frequency selectivity and, at the same voltage on the reader side, a higher voltage on the day-side, which increases the range of the communication link. At small distances between reader and tag such large voltages can be induced depending on the transmission power in the day that an existing in the tag integrated circuit can be destroyed.
p0006From the <patcit id="pcit0001" dnum="DE102004020816A1"><text>DE 10 2004 020 816 A1</text></patcit> It is known to reduce the voltage at the receiving resonant circuit to certain values or limit, which is hereinafter referred to as a first terminal voltage. Further, the load modulation between a first voltage is switched ie the first terminal voltage and a second lower voltage in the frame. For this depletion layer elements between resonant circuit terminals and a reference or ground potential can be switched. A lower terminal voltage is, for example, realized in that above the barrier layer components drops whose forward voltage, the voltage drop due to the exponential dependence of the current of the voltage is independent of power supplies in a first approximation.
p0007As a result, the depletion layer elements also act at high coil currents as a reliable limitation of the resonance circuit voltage to a corresponding value. This is for systems with high-Q inductors important that otherwise can cause undesirable high voltages in the proximity of transmitting resonant circuit and receiving resonant circuit.
p0008The upper clamp voltage can be realized by a series connected with reverse conducting direction Zener diode, the short-circuit is controlled or switched. In the short-circuited state takes place, the described limitation on the lower clamping voltage, while in the non-short-circuited state, the breakdown voltage of the Zener diode for a voltage offset additive ensures that defines an upper terminal voltage in the sum with said forward voltages. In the state with short-circuited Zener diode, a comparatively large current from the receiving resonant circuit flows out, corresponding to the loaded state of the resonant circuit. Accordingly, the current drain from the resonant circuit and the load on the resonant circuit by opening the short circuit is reduced across the Zener diode.
p0009The load modulation from the <patcit id="pcit0002" dnum="DE102004020816A1"><text>DE 10 2004 020 816 A1</text></patcit> is the following problem has been observed: When the switching of the modulation, so when limiting the resonant circuit voltage on the lower terminal voltage, particularly a high coil current is induced, so these flows may via the bridging of the Zener diode and, connected in the conducting direction other barrier components from, wherein the resonant circuit voltage may fall below the lower terminal voltage and also below a threshold value, which is used for the detection of oscillations (pulses) of the resonant circuit voltage. So it can happen when the load with unfavorable phase conditions, the voltage at the transmitting resonant circuit decreases due to the reaction of one or more periods below a detection threshold, which distorts the transmission of information. This can result in data loss when transmitting information to the reader.
p0010Namely switched modulation at a high induced Spulensrom, the depletion layer elements for a limitation of the resonant circuit voltage care to a predetermined by the depletion layer elements value. The diodes act in this phase as a DC voltage source and thus do not provide sufficient damping to the coil current counter, so that the induced oscillation is changed. The result is a widening of the present input clock phase (pulse broadening), which leads to at least partial cancellation of the sequential oscillation. It occurs thus in appearance, that at least one oscillation in the amplitude is too small for a predetermined detection threshold.
p0011In the conference report "<nplcit id="ncit0001" npl-type="s"><text>Circuitry for a wireless micorsystem for neural recording micro probes "veröffentllicht in Annual International Conference of IEEE Engineering in The M, Vol. Vol. 1 of 4. Conf. 23, October 25, 2001 Pages 761- 764</text></nplcit> XP010593486 is a voltage limiter for an inductively coupled system is disclosed that the attached circuit protection at high voltages induced from destruction. A disadvantage is that the circuit is used only for a rectified signal.
p0012Against this background, the object of the present invention to provide a method and a circuit arrangement for voltage limitation in a transponder, which reduces the disadvantages of the prior art.
p0013This object is achieved in a method of the type mentioned in that for voltage limitation in a transponder with a first transmitting and receiving resonant circuit having a first resonant circuit terminal and a second resonant circuit terminal, a controllable junction device having an input, an output and a control input is provided, and the input is connected with the first oscillator circuit connection, the output connected with the second oscillator circuit connection, and from the base station in the transmitting and receiving oscillator circuit between the first and second oscillator circuit connection, an alternating voltage is induced, so that the induced in the transmitting and receiving oscillator circuit AC voltage is limited to a first voltage value by the control input of the junction component is connected by a switch to a voltage source.
p0014This method offers the advantage that for both voltage half waves a total of only one barrier component must be provided, while in known processes, a symmetrical structure of at least one barrier layer component for a respective half-wave voltage was provided.
p0015Advantageously, in the inventive method is further, that the limitation of the voltage from a first to a second voltage value to the load modulation.
p0016As has proven particularly advantageous that the voltage limit and the load modulation is performed by means of driving the same barrier device. In this way, the process is considerably simplified.
p0017A further refinement of the method provides that the change takes place from the first to a second voltage in at least two stages by at least two barrier devices for reducing the voltage to the second, lower value, thus cascading bridged successively. This causes the coil current which would flowed abruptly when switching on the modulation transistor, spread over several oscillations. Here, the coil voltage is also reduced to the level of the second voltage over several oscillations.
p0018According to an alternative method, the change from the first to a second voltage is linear, by being controlled by an inverse signal.
p0019Furthermore, the object is achieved by a circuit for voltage limitation in a transponder comprising a resonant circuit, at least an inductance, a capacitance, a barrier component with an input, output and a control input, and a first oscillator circuit connection, to the input of the junction device and a second resonant circuit terminal, which is connected to the output of the junction device comprises, in which a compound of the control input of the junction component is connected to the first resonant circuit terminal and the second resonant circuit terminal.
p0020Particularly advantageous in this case a circuit has been found, in which is provided as barrier layer component is a NMOS transistor.
p0021It is preferred also that are provided for driving the barrier component at least two series-connected, bridgeable depletion layer elements.
p0022In one advantageous embodiment of the circuit switches are provided to bridge the series-junction components controlled by means of staggered modulation signals.
p0023According to a development of the circuit, a polarity reversal circuit is provided with two parallel-connected barrier layer components with opposite forward directions before the series-junction components.
p0024In an alternate circuit is provided as a blocking layer component is a PMOS transistor is provided.
p0025It is particularly advantageous if it is provided for controlling the depletion layer component switchable via an inverse modulation signal capacity.
p0026Further advantages result from the description and the accompanying figures. It is understood that the features mentioned above and those yet to be explained not only in the particular combination indicated but also in other combinations or alone without departing from the scope of the present invention.
p0027Embodiments of the invention are illustrated in the drawings and are explained in more detail in the following description. The drawings show in schematic form:<dl id="dl0001"><dt>Fig. 1</dt><dd>a transmitting and receiving resonant circuit with elements for load modulation for a first voltage half-wave</dd><dt>FIG. 2</dt><dd>the transmitting and receiving oscillator circuit of <figref idrefs="f0001">Fig.1</figref> with elements for load modulation for a second voltage half-wave</dd><dt>Fig. 3</dt><dd>another transmitting and receiving resonant circuit with elements for load modulation for a first voltage half-wave</dd><dt>Fig. 4</dt><dd>the transmitting and receiving oscillator circuit of <figref idrefs="f0003">Fig.3</figref> with elements for load modulation for a second voltage half-wave</dd><dt>Fig. 5</dt><dd>the course of the resonant circuit voltages U<sub>L</sub>, U<sub>C1</sub>; U<sub>C2</sub></dd><dt>Fig. 6</dt><dd>a desired modulation behavior</dd></dl>
p0028In the embodiments according to the <figref idrefs="f0001">figure 1</figref> and the <figref idrefs="f0002">figure 2</figref> not it is a part of the invention which is the subject of this claim desire. The<figref idrefs="f0001">Fig. 1</figref> and <figref idrefs="f0002">FIG. 2</figref> show a transmitting and receiving resonant circuit 10 of a receiving part or tag. Parallel to the resonant circuit 10 including an inductor L 12 and a capacitor C 13, is located between a first oscillator circuit connection C<sub>1</sub> 25 and a second resonant circuit terminal C<sub>2</sub> 26, a barrier member 27, preferably an NMOS transistor. At the output of the junction member 27 is a reference potential terminal 28, which is a ground potential for the circuit. Since the barrier member 27 between the source (source) and drain (drain) can switch, the circuit can be used in the present form both for a first and for a second voltage half-wave.
p0029Also in parallel to the resonant circuit 10 and between the first C<sub>1</sub> 25 and the second resonant circuit terminal C<sub>2</sub> 26, is a series circuit of polarity reversal circuit 14 and diodes 19, 20, 21, 22, 23, 24 which are used to control the depletion layer component 27th In this case, the diodes may be implemented as NMOS transistors, which are connected as diode. Parallel to the barrier member 27 is located further comprises a rectifier circuit 29 with a further reference potential terminal 30th The polarity switching circuit 14 consists of two parallel series circuits each of an ohmic resistor R<sub>1</sub> 15 or R<sub>2</sub> 16 and a diode 17 or 18 include, in which the flow direction of the diodes 17, 18 is different. The diodes 19 to 24 can switch S<sub>1</sub> 31, S<sub>2</sub> 32, S<sub>3</sub> 33 are bridged by the control circuit 34 via cascaded MOD signals MOD<sub>0</sub>, MOD<sub>1</sub> and MOD<sub>2</sub> are actuated. The switches 31, 32, 33 are preferably implemented as transistors, in particular as MOS transistors.
p0030The barrier member 27 is used initially to limit the resonant circuit voltage U<sub>L</sub> 1 between the terminals 25 and 26 of the transmitting and receiving oscillator circuit 10 with open switches 31, 32 and 33. In this state the barrier member 27 is limited in each case when the potential difference between the reference potential terminal 28, 30 and one of the terminals 25 or 26, the forward voltage the depletion layer component exceeds 27th This value defines the upper limit voltage or first clamp voltage U<sub>KL</sub> 2.2. When bypassing the diodes 19 to 24 by the switches 31, 32 and 33, which are not closed simultaneously to stepped modulation of the voltage sequentially clamps the depletion layer component 27 the resonant circuit voltage U<sub>L</sub> 1 to a lower value UL<sub>MOD</sub>2.1.
p0031By opening and closing the switch 31, 32, 33 modulates the control circuit 34 the value of the resonant circuit voltage U<sub>L</sub> 1 corresponding to the data to be transmitted sequence. As described, this modulation of transmitting and receiving resonant circuit 10 forms the day. As a modulation of the load of the transmitting and receiving resonant circuit of the reader provided a transformer coupling
p0032<figref idrefs="f0003">FIGS. 3 and Fig. 4</figref> show another transmitting and receiving resonant circuit 10 of a receiving part or tag. This shows<figref idrefs="f0003">Fig. 3</figref> a circuit for a first voltage half-wave and <figref idrefs="f0003">Fig. 4</figref> the circuit of <figref idrefs="f0003">Fig. 3</figref> for a second voltage half-wave. Parallel to the resonant circuit 10 including an inductor L 12 and a capacitor C 13, is located between a first oscillator circuit connection C<sub>1</sub> 25 and a second resonant circuit terminal C<sub>2</sub> 26, a barrier member 35, preferably a PMOS transistor. At the output of the junction member 35 is a reference potential terminal 28, which is a ground potential for the circuit. To control the depletion layer component 35 are a current source I<sub>e</sub>That turn a discharge for discharging a parallel capacitance 7 makes available, as well as a voltage source U<sub>ref</sub> 3. In this case, between the capacitance 7 and the voltage source U<sub>ref</sub> 3, a switch S<sub>1</sub> 9 is arranged, which is actuated by means of an inverse signal NMOD 4th
p0033The barrier member 35 serves to limit the resonant circuit voltage U<sub>L</sub> 1 to the value of the upper clamping voltage U<sub>KL</sub> 2.2 between the terminals 25 and 26 of the transmitting and receiving oscillator circuit 10. When the switch S<sub>1</sub> 9 is closed, is located at the junction member 35, the voltage U<sub>ref</sub> 3, which by the predetermined voltage U<sub>G</sub> 6 is limited at the gate and thus can not go beyond the threshold voltage of the PMOS transistor. When the switch S<sub>1</sub> 9 by means of 4 NMOD signal of the control circuit 34 is opened, the capacitor 7 to the value U<sub>ref</sub> 3aufgeladen and then by means of the discharge current of the current source l<sub>E2</sub> 8 discharged. The consequence of this is that the voltage U<sub>G</sub> 6 at the gate linearly decreases to zero. This is the resonant circuit voltage U<sub>L</sub> 1 to a second, smaller terminal voltage U<sub>LMOD</sub> 2.1 is limited, corresponding to the threshold voltage of the PMOS transistor.
p0034<figref idrefs="f0003">Fig. 5</figref> shows the course of the resonant circuit voltage U<sub>L</sub> 1, the course of the respective half-wave voltage U<sub>C1</sub> and U<sub>C2</sub> at the two resonant circuit terminals C<sub>1</sub> 25 and C<sub>2</sub> 26 The resonant circuit voltage U<sub>L</sub> 1 is the difference from the voltage values at the terminals. U<sub>L</sub> = U<sub>C1</sub>-U<sub>C2</sub>, If UL 1 is positive, according to the circuit <figref idrefs="f0001">Fig.1</figref> and <figref idrefs="f0003">Fig. 3</figref> the resonant circuit terminal C<sub>2</sub> connected via the rectifier 29 with an internal mass 30th In the opposite case, if U<sub>L</sub> 1 is negative, as shown in the <figref idrefs="f0002">FIG. 2</figref> and <figref idrefs="f0003">Fig. 4</figref> the resonant circuit terminal C<sub>1</sub> 26 connected to the internal ground 30th
p0035<figref idrefs="f0004">Fig. 6</figref> showing a desired profile of the resultant resonant circuit voltage UL in the receiving resonant circuit under the influence of a controlled load modulation according to the present invention over time t. The large amplitudes 2.2 arise with open switches 31, 32, 33 according to<figref idrefs="f0001">Fig. 1</figref> and <figref idrefs="f0002">Fig.2</figref> and the small amplitudes 2.1 arise in closed switches 31, 32, 33 a, which are bridged diodes 19, 20, 21, 22 a.
LIST OF REFERENCE NUMBERS
p0036<dl id="dl0002" compact="compact"><dt>1</dt><dd>U<sub>L</sub> Resonant circuit voltage</dd><dt>2.1</dt><dd>UL<sub>MOD</sub> lower clamping voltage (modulated voltage)</dd><dt>2.2</dt><dd>U<sub>KL</sub> upper clamping voltage</dd><dt>3</dt><dd>U<sub>ref</sub> voltage reference</dd><dt>4</dt><dd>n<sub>MOD</sub> inverse signal</dd><dt>5.1</dt><dd>Modulation signal MOD<sub>0</sub></dd><dt>5.2</dt><dd>Modulation signal MOD<sub>1</sub></dd><dt>5.3</dt><dd>Modulation signal MOD<sub>2</sub></dd><dt>6</dt><dd>U<sub>G</sub> gate voltage</dd><dt>7</dt><dd>C<sub>2</sub> capacitor</dd><dt>8th</dt><dd>lE<sub>2</sub> Current source discharge</dd><dt>9</dt><dd>switch S<sub>1</sub></dd><dt>10</dt><dd>Sending - and receiving resonant circuit</dd><dt>11</dt><dd>day</dd><dt>12</dt><dd>inductance L</dd><dt>13</dt><dd>capacitance C</dd><dt>14</dt><dd>Polarity reversal circuit</dd><dt>15</dt><dd>Ohmic resistance R1</dd><dt>16</dt><dd>Ohmic resistance R2</dd><dt>17</dt><dd>Diode at R1</dd><dt>18</dt><dd>Diode at R2</dd><dt>19</dt><dd>diode</dd><dt>20</dt><dd>diode</dd><dt>21</dt><dd>diode</dd><dt>22</dt><dd>diode</dd><dt>23</dt><dd>diode</dd><dt>24</dt><dd>diode</dd><dt>25</dt><dd>First resonant circuit terminal C<sub>1</sub></dd><dt>26</dt><dd>Second resonant circuit terminal C<sub>2</sub></dd><dt>27</dt><dd>Depletion layer component M1</dd><dt>28</dt><dd>Reference potential terminal</dd><dt>29</dt><dd>Rectifier circuit</dd><dt>30</dt><dd>Reference potential terminal</dd><dt>31</dt><dd>switch S<sub>1</sub></dd><dt>32</dt><dd>switch S<sub>2</sub></dd><dt>33</dt><dd>switch S<sub>3</sub></dd><dt>34</dt><dd>Control circuit (digital to analog converter)</dd><dt>35</dt><dd>Depletion layer component P<sub>1</sub></dd></dl>
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Every citation, both ways
| Document | Relation | Office | Category | Cited during | Relevant claims |
|---|---|---|---|---|---|
| US10231299B2 | Cited by | United States of America | – | Applicant | – |
| WO2016058687A1 | Cited by | World Intellectual Property Organization (WIPO) | – | International search | – |
| DE102004020816A1 | Cites | Germany | – | Applicant | – |
| EP1589656A1 | Cites | European Patent Office (EPO) | AD | Search report | 1-9 |
| EP1589656A1 | Cites | European Patent Office (EPO) | AD | Search report | 1-9 |
| US2004099738A1 | Cites | United States of America | A | Search report | 1-9 |
| US2005156710A1 | Cites | United States of America | A | Search report | 1-9 |
| US5815355A | Cites | United States of America | I | Search report | 1-3,6-7 |
| RAO YU ET AL: "Circuitry for a wireless microsystem for neural recording microprobes", PROCEEDINGS OF THE 23RD. ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY. 2001 CONFERENCE PROCEEDINGS. (EMBS). INSTANBUL, TURKEY, OCT. 25 - 28, 2001, ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN M, vol. VOL. 1 OF 4. CONF. 23, 25 October 2001 (2001-10-25), pages 761 - 764, XP010593486 | Non-patent | – | – | Search report | – |
| "Circuitry for a wireless micorsystem for neural recording microprobes", ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING, vol. 1, 23 October 2001 (2001-10-23), pages 761 - 764 | Non-patent | – | – | Applicant | – |
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Priority claims9
| Document | Office | Kind | Date |
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| 102006006912 | Germany | A | |
| 102006006912 | Germany | A | |
| 102006006912 | Germany | – | |
| 07002790 | European Patent Office (EPO) | A | |
| 07002790 | European Patent Office (EPO) | A | |
| 07002790 | – | – | – |
| 102006006912 | – | – | – |
| DE20061006912 | – | – | – |
| EP20070002790 | – | – | – |
Members8
| Document | Office | Kind | |
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| EP1821405A1 | European Patent Office (EPO) | A1 | |
| US2007194928A1 | United States of America | A1 | |
| EP1821405B1 | European Patent Office (EPO) | B1 | |
| EP2139109A1This record | European Patent Office (EPO) | A1 | |
| DE502007002450D1 | Germany | D1 | |
| US7710213B2 | United States of America | B2 | |
| EP2139109B1 | European Patent Office (EPO) | B1 | |
| DE502007006276D1 | Germany | D1 |
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| Information provided on ipc code assigned before grantRIC1 | RIC1 | EP | |
| Information provided on ipc code assigned before grantRIC1 | RIC1 | EP | |
| Request for examination filed17P | 17P | EP | |
| Divisional application: reference to earlier applicationAC | AC | EP | |
| Designated contracting statesAK | AK | EP | |
| Public reference made under article 153(3) epc to a published international application that has entered the european phaseORIGINAL CODE: 0009012PUAI | PUAI | EP |
Numbers
- Publication
- 2139109
- Publication, DOCDB
- 2139109
- Publication, EPODOC
- EP2139109
- Application
- 9009622
- Application, DOCDB
- 09009622
- Application, EPODOC
- EP20090009622
Titles3
- German
- Verfahren zur Spannungsbegrenzung bei einem Transponder
- English
- Method for voltage limitation for a transponder
- French
- Procédé destiné à limiter la tension dans un transpondeur
Classification
- CPC, 4
- H03G11/02
- G06K19/0701
- G06K19/0715
- G06K19/07749
- IPC, 5
- H03G11 02
- H04B5 02
- G06K19 07
- H03G11 00
- H04B5 48
Designated states1
- Contracting states, 1
- France