Light emitting devices having current reducing structures and methods of forming light emitting devices having current reducing structures

FIELD OF THE INVENTION

0001This invention relates to semiconductor light emitting devices and fabricating methods therefor.

BACKGROUND

0002Semiconductor light emitting devices, such as Light Emitting Diodes (LEDs) or laser diodes, are widely used for many applications. As is well known to those having skill in the art, a semiconductor light emitting device includes a semiconductor light emitting element having one or more semiconductor layers that are configured to emit coherent and/or incoherent light upon energization thereof. As is well known to those having skill in the art, a light emitting diode or laser diode, generally includes a diode region on a microelectronic substrate. The microelectronic substrate may be, for example, gallium arsenide, gallium phosphide, alloys thereof, silicon carbide and/or sapphire. Continued developments in LEDs have resulted in highly efficient and mechanically robust light sources that can cover the visible spectrum and beyond. These attributes, coupled with the potentially long service life of solid state devices, may enable a variety of new display applications, and may place LEDs in a position to compete with the well entrenched incandescent and fluorescent lamps.

0003Much development interest and commercial activity recently has focused on LEDs that are fabricated in or on silicon carbide, because these LEDs can emit radiation in the blue/green portions of the visible spectrum. See, for example, <patcit id="pcit0001" dnum="US5416342A"><text>U.S. Patent 5,416,342 to Edmond et al</text></patcit> discloses a blue light-emitting diode. Publication <patcit id="pcit0002" dnum="WO2005117147A1"><text>WO 2005/117147 A1</text></patcit> discloses a light-emitting diode having a reduced conductivity region extending from a surface of a p-type semiconductor layer towards the active region. There also has been much interest in LEDs that include gallium nitride-based diode regions on silicon carbide substrates, because these devices also may emit light with high efficiency.

0004The efficiency of conventional LEDs may be limited by their inability to emit all of the light that is generated by their active region. When an LED is energized, light emitting from its active region (in all directions) may be prevented from exiting the LED by, for example, a non-transparent wire bond pad. Typically, in gallium nitride based LEDs, a current spreading contact layer is provided to improve the uniformity of carrier injection across the cross section of the light emitting device. Current is injected into the p-side of the LED through the bond pad and the p-type contact. Light generated in an active region of the device is proportional to the carrier injection. Thus, a substantially uniform photon emission across the active region may result from the use of a current spreading layer, such as a substantially transparent p-type contact layer. However, a wire bond pad is typically not a transparent structure and, therefore, photons emitted from the active region of the LED that are incident upon the wire bond pad may be absorbed by the wire bond pad. For example, in some instances approximately 70% of the light incident on the wire bond pad may be absorbed. Such photon absorption may reduce the amount of light that escapes from the LED and may decrease the efficiency of the LED.

SUMMARY

0005A light emitting device according the invention includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. A non-transparent feature is on the p-type semiconductor layer and a reduced conductivity region is in the p-type semiconductor layer and is aligned with the non-transparent feature. The reduced conductivity region extends from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region. The non-transparent region includes a wire bond pad, a passivation region, and/or a current spreading finger.

0006The light emitting device may further include a substrate including first and second opposing surfaces, and the n-type semiconductor may be on the first surface of the substrate and the wire bond pad may be on the second surface of the substrate opposite the n-type semiconductor layer.

0007The light emitting device may further include a metal stack on the surface of the p-type semiconductor layer. The metal stack may include an ohmic layer directly on the p-type semiconductor layer, a reflective layer on the ohmic layer, and a bonding layer on the reflective layer. The light emitting device may further include a barrier layer between the reflective layer and the bonding layer.

0008The reduced conductivity region may extend from the surface of the p-type semiconductor layer to/into/through the active region. The reduced conductivity region may extend through the p-type semiconductor layer, the active region and into or through the n-type semiconductor layer.

0009The wire bond pad may be in contact with the reduced conductivity region, and the light emitting device may further include an ohmic contact on the n-type semiconductor layer adjacent and in electrical contact with the wire bond pad.

0010The active region may include a Group III-nitride based active region. The reduced conductivity region may include an insulating region and/or a region that is not non-transparent. In some embodiments, the reduced conductivity region may include an implanted region. The reduced conductivity region may correspond to a region of damage at an interface between the metal stack and the p-type semiconductor layer. The region of damage may include a wet or dry etched region of the p-type semiconductor layer, a region of the p-type semiconductor layer exposed to a high energy plasma, a region of the p-type semiconductor layer exposed to H₂ and/or a region of the p-type semiconductor layer exposed to a high energy laser.

0011A light emitting device according to further embodiments of the invention includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. The device includes a non-transparent feature on the n-type semiconductor layer opposite the p-type semiconductor layer, and a metal contact on a surface of the p-type semiconductor layer opposite the n-type semiconductor layer. The metal contact forms on ohmic contact to the p-type semiconductor layer in a region other than a reduced conductivity area of the surface of the p-type semiconductor layer that is aligned with the non-transparent feature. The non-transparent region may include a wire bond pad, a passivation region, and/or a current spreading finger

0012The light emitting device may further include a reduced conductivity region in the p-type semiconductor layer and aligned with the non-transparent feature and the reduced conductivity area, and the reduced conductivity region may extend from the surface of the p-type semiconductor layer towards the active region.

0013The light emitting device may further include a reduced conductivity region in the n-type semiconductor layer and aligned with the non-transparent feature, the reduced conductivity region extending from a surface of the n-type semiconductor layer opposite the p-type semiconductor layer towards the active region.

0014The light emitting device may further include a non-ohmic contact on the surface of the p-type semiconductor layer. The non-ohmic contact may include a metal that does not form an ohmic contact with the p-type semiconductor layer and/or an insulator on the surface of the p-type semiconductor layer.

0015A light emitting device according to further embodiments of the invention includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. The device further includes a wire bond pad on the n-type semiconductor layer opposite the p-type semiconductor layer, and a reduced conductivity region in the n-type semiconductor layer and aligned with the wire bond pad. The reduced conductivity region extends from a surface of the n-type semiconductor layer opposite the p-type semiconductor layer towards the active region. The device further includes an ohmic contact on the n-type semiconductor layer adjacent and in electrical contact with the wire bond pad.

0016The light emitting device may further include a metal stack on a surface of the p-type semiconductor layer opposite the n-type semiconductor layer. The metal stack may include an ohmic layer directly on the p-type semiconductor layer, a reflective layer on the ohmic layer, and a bonding layer on the reflective layer.

0017The reduced conductivity region may include a first reduced conductivity region, and the light emitting device may further include a second reduced conductivity region in the p-type semiconductor layer and aligned with the wire bond pad. The second reduced conductivity region may extend from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region.

0018The light emitting device may further include a metal contact on a surface of the p-type semiconductor layer opposite the n-type semiconductor layer. The metal contact forms on ohmic contact to the p-type semiconductor layer in a region other than a reduced conductivity area of the surface of the p-type semiconductor layer that is aligned with the wire bond pad.

0019Methods according to some embodiments of the invention include forming a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer, forming a non-transparent feature on the n-type semiconductor layer opposite the p-type semiconductor layer, and forming a reduced conductivity region in the p-type semiconductor layer and aligned with the non-transparent feature. The reduced conductivity region extends from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region.

0020Methods of forming a light emitting device according to further embodiments of the invention include forming a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer, forming a wire bond pad on the n-type semiconductor layer opposite the p-type semiconductor layer, and forming a metal contact on a surface of the p-type semiconductor layer opposite the n-type semiconductor layer. The metal contact forms on ohmic contact to the p-type semiconductor layer in a region other than a reduced conductivity area of the surface of the p-type semiconductor layer that is aligned with the wire bond pad.

0021A light emitting device according to further embodiments of the invention includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. A bond pad is on the p-type semiconductor layer opposite the n-type semiconductor layer, and a reduced conductivity region is in the p-type semiconductor layer and aligned with the bond pad. The reduced conductivity region extends from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region.

0022The light emitting device may further include a reflector between the bondpad and the p-type semiconductor layer, and/or a current spreading finger on the p-type semiconductor layer, and the reduced conductivity region may further be aligned with the current spreading finger.

BRIEF DESCRIPTION OF THE DRAWINGS

0023<ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001"><b>Figure 1</b></figref> is a cross-sectional view illustrating semiconductor light emitting devices having a current blocking structure.</li><li><figref idref="f0001"><b>Figures 2A</b></figref> and <figref idref="f0002"><b>2B</b></figref> are cross-sectional views illustrating fabrication of semiconductor devices.</li><li><figref idref="f0002"><b>Figures</b> 3</figref>, <figref idref="f0003">4</figref>, <figref idref="f0006">7</figref>, <figref idref="f0007">8</figref> and <figref idref="f0009">11</figref> show cross-sectional views of light emitting devices; <figref idref="f0004">figures 5</figref>, <figref idref="f0005">6</figref>, <figref idref="f0007 f0008">9</figref> and <figref idref="f0008">10</figref> are cross-sectional views of light emitting devices according to further embodiments of the present invention.</li><li><figref idref="f0010"><b>Figures 12</b></figref> and <figref idref="f0011"><b>13</b></figref> are perspective views of light emitting devices according to some embodiments of the present invention.</li></ul>

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

0024The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. As used herein the term "and/or" includes any and all combinations of one or more of the associated listed items.

0025The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

0026It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like numbers refer to like elements throughout the specification.

0027It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

0028Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The exemplary term "lower", can therefore, encompasses both an orientation of "lower" and "upper," depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The exemplary terms "below" or "beneath" can, therefore, encompass both an orientation of above and below.

0029Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated or described as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.

0030Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

0031It will also be appreciated by those of skill in the art that references to a structure or feature that is disposed "adjacent" another feature may have portions that overlap or underlie the adjacent feature.

0032Although various embodiments of LEDs disclosed herein include a substrate, it will be understood by those skilled in the art that the crystalline epitaxial growth substrate on which the epitaxial layers comprising an LED are grown may be removed, and the freestanding epitaxial layers may be mounted on a substitute carrier substrate or submount which may have better thermal, electrical, structural and/or optical characteristics than the original substrate. The invention described herein is not limited to structures having crystalline epitaxial growth substrates and may be utilized in connection with structures in which the epitaxial layers have been removed from their original growth substrates and bonded to substitute carrier substrates.

0033Some embodiments of the present invention may provide for improved efficacy of a light emitting device by reducing and/or preventing current flow in an active region of the device in a region beneath a wire bond pad or other non-transparent structure. Thus, some embodiments of the present invention may provide light emitting devices and methods of fabricating light emitting devices having a current blocking mechanism below the wire bond pad. By reducing and/or preventing current from being injected directly beneath the wire bond pad, the current may be more likely to be converted to photon emission in areas of the device not under the wire bond pad. Thus, there may be a reduced probability of light being absorbed by the wire bond pad. In some embodiments of the present invention, an increase in efficiency of a light emitting device according to some embodiments of the present invention may be proportional to the size of the wire bond pad.

0034Embodiments of the present invention may be particularly well suited for use in nitride-based light emitting devices such as Group III-nitride based devices. As used herein, the term "Group III nitride" refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. As is well understood by those in this art, the Group III elements can combine with nitrogen to form binary (<i>e</i>.<i>g</i>., GaN), ternary (<i>e</i>.<i>g</i>., AlGaN, AlInN), and quaternary (<i>e</i>.<i>g</i>., AIInGaN) compounds. These compounds all have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements. Accordingly, formulas such as Al_xGa_1-xN where 0 ≤ x ≤ 1 are often used to describe them. However, while embodiments of the present invention are described herein with reference to Group III-nitride based light emitting devices, such as gallium nitride based light emitting devices, certain embodiments of the present invention may be suitable for use in other semiconductor light emitting devices, such as for example, GaAs and/or GaP based devices.

0035Light emitting devices according to some embodiments of the present invention may include a light emitting diode, laser diode and/or other semiconductor device which includes one or more semiconductor layers, which may include silicon, silicon carbide, gallium nitride and/or other semiconductor materials, a substrate which may include sapphire, silicon, silicon carbide and/or other microelectronic substrates, and one or more contact layers which may include metal and/or other conductive layers. In some embodiments, ultraviolet, blue and/or green LEDs may be provided. The design and fabrication of semiconductor light emitting devices are well known to those having skill in the art and need not be described in detail herein.

0036For example, light emitting devices according to some embodiments of the present invention may include structures such as the gallium nitride-based LED and/or laser structures fabricated on a silicon carbide substrate such as those devices manufactured and sold by Cree, Inc. of Durham, North Carolina. The present invention may be suitable for use with LED and/or laser structures that provide active regions such as described in United States Patent Nos. <patcit id="pcit0003" dnum="US6201262B"><text>6,201,262</text></patcit>; <patcit id="pcit0004" dnum="US6187606B"><text>6,187,606</text></patcit>; <patcit id="pcit0005" dnum="US6120600A"><text>6,120,600</text></patcit>; <patcit id="pcit0006" dnum="US5912477A"><text>5,912,477</text></patcit>; <patcit id="pcit0007" dnum="US5739554A"><text>5,739,554</text></patcit>; <patcit id="pcit0008" dnum="US5631190A"><text>5,631,190</text></patcit>; <patcit id="pcit0009" dnum="US5604135A"><text>5,604,135</text></patcit>; <patcit id="pcit0010" dnum="US5523589A"><text>5,523,589</text></patcit>; <patcit id="pcit0011" dnum="US5416342A"><text>5,416,342</text></patcit>; <patcit id="pcit0012" dnum="US5393993A"><text>5,393,993</text></patcit>; <patcit id="pcit0013" dnum="US5338944A"><text>5,338,944</text></patcit>; <patcit id="pcit0014" dnum="US5210051A"><text>5,210,051</text></patcit>; <patcit id="pcit0015" dnum="US5027168A"><text>5,027,168</text></patcit>; <patcit id="pcit0016" dnum="US5027168A"><text>5,027,168</text></patcit>; <patcit id="pcit0017" dnum="US4966862A"><text>4,966,862</text></patcit> and/or 4,918,497, the disclosures of which are incorporated herein by reference as if set forth fully herein. Other suitable LED and/or laser structures are described in published U.S. Patent Publication No. <patcit id="pcit0018" dnum="US20030006418A1"><text>US 2003/0006418 A1</text></patcit> entitled <i>Group III Nitride Based Light Emitting Diode Structures With a Quantum Well and Superlattice, Group III Nitride Based Quantum Well Structures and Group III Nitride Based Superlattice Structures,</i> published January 9, 2003, as well as published U.S. Patent Publication No. <patcit id="pcit0019" dnum="US20020123164A1"><text>US 2002/0123164 A1</text></patcit> entitled <i>Light Emitting Diodes Including Modifications for Light Extraction and Manufacturing Methods Therefor.</i> Furthermore, phosphor coated LEDs, such as those described in U.S. Application Serial No. <patcit id="pcit0020" dnum="US10659241B"><text>10/659,241</text></patcit>, entitled <i>Phosphor-Coated Light Emitting Diodes Including Tapered Sidewalls and Fabrication Methods Therefor</i>, filed September 9, 2003, the disclosure of which is incorporated by reference herein as if set forth fully, may also be suitable for use in embodiments of the present invention. The LEDs and/or lasers may be configured to operate such that light emission occurs through the substrate. In such embodiments, the substrate may be patterned so as to enhance light output of the devices as is described, for example, in the above-cited U.S. Patent Publication No. <patcit id="pcit0021" dnum="US20020123164A1"><text>US 2002/0123164 A1</text></patcit>. These structures may be modified as described herein to provide blocking structures according to some embodiments of the present invention.

0037Thus, for example, embodiments of the present invention may be utilized with light emitting devices having bond pads of differing shapes or sizes. The light emitting devices may be on differing substrates, such as silicon carbide, sapphire, gallium nitride, silicon or other substrate suitable substrate for providing Group III-nitride devices. The light emitting devices may be suitable for subsequent singulation and mounting on a suitable carrier. The light emitting devices may include, for example, single quantum well, multi-quantum well and/or bulk active region devices. Some embodiments of the present invention may be used with devices utilizing a tunneling contact on the p-side of the device.

0038<figref idref="f0001"><b>Figure 1</b></figref> is a cross-sectional schematic illustration of a light emitting device according to some embodiments of the present invention. As seen in <figref idref="f0001"><b>Figure 1</b></figref>, a substrate <b>10</b>, such as an n-type silicon carbide substrate, has an optional n-type semiconductor layer <b>12</b>, such as a gallium nitride based layer, provided thereon. The n-type semiconductor layer <b>12</b> may include multiple layers, for example, buffer layers or the like. In some embodiments of the present invention, the n-type semiconductor layer <b>12</b> is provided as an AlGaN layer, that may be of uniform or gradient composition, and/or a GaN layer. The n-type semiconductor layer <b>12</b> may be doped, for example, with silicon, germanium and/or tellurium.

0039While described herein with reference to a silicon carbide substrate, in some embodiments of the present invention other substrate materials may be utilized. For example, a sapphire substrate, GaN or other substrate material may be utilized. In such a case, the contact <b>20</b> may be located, for example, in a recess that contacts the n-type semiconductor layer <b>12</b>, so as to provide a second contact for the device. Other configurations may also be utilized.

0040An active region <b>14</b>, such as a single or double heterostructure, quantum well, multi-quantum well or other such active region may be provided on the n-type semiconductor layer. As used herein, the term "active region" refers to a region of semiconductor material of a light emitting device, that may be one or more layers and/or portions thereof, where a substantial portion of the photons emitted by the device when in operation are generated by carrier recombination. In some embodiments of the present invention, the active region refers to a region where substantially all of the photons emitted by the device are generated by carrier recombination.

0041Also illustrated in <figref idref="f0001"><b>Figure 1</b></figref> is an optional p-type semiconductor layer <b>16</b>. The p-type semiconductor material layer <b>16</b> may, for example, be a gallium nitride based layer, such as a GaN layer. In particular embodiments of the present invention, the p-type semiconductor layer <b>16</b> includes magnesium doped GaN. The p-type semiconductor layer <b>16</b> may include one or multiple layers and may be of uniform or gradient composition. In some embodiments of the present invention, the p-type semiconductor layer <b>16</b> is part of the active region <b>14</b>.

0042A first contact metal layer <b>18</b> of contact metal that provides an ohmic contact to the p-type semiconductor material layer <b>16</b> is also provided. In some embodiments, the first contact metal layer <b>18</b> may function as a current spreading layer. In particular embodiments of the present invention where the p-type semiconductor material layer <b>16</b> is GaN, the first contact metal layer <b>18</b> may include Pt, indium-tin-oxide (ITO) or another transparent material that can form an ohmic contact to p-type GaN. In certain embodiments of the present invention, the first contact metal layer <b>18</b> is light permeable and in some embodiments is substantially transparent. In some embodiments, the first contact metal layer <b>18</b> may be a relatively thin layer of Pt. For example, the first contact metal layer <b>18</b> may be a layer of Pt that is about 15 Å thick. An optional reflective layer <b>23</b> may be provided on the first metal contact layer <b>18</b>. A wire bond pad <b>22</b> or other light absorbing (or otherwise non-transparent) feature is provided on the first contact metal layer <b>18</b>. In the embodiments illustrated in <figref idref="f0001"><b>Figure 1</b></figref>, the wire bond pad <b>22</b> is provided on the reflective layer <b>23</b>, so that the reflective layer <b>23</b> is between the wire bond pad <b>22</b> and the p-type semiconductor material layer <b>16</b>. In some embodiments, a current spreading finger <b>154A</b> (<figref idref="f0011"><b>Figure 13</b></figref>) may be on the first contact metal layer <b>18</b>.

0043A second contact metal layer <b>20</b> of contact metal that provides an ohmic contact to the n-type semiconductor material is also provided. The second contact metal layer <b>20</b> may be provided on a side of the substrate <b>10</b> opposite the active region <b>14</b>. As discussed above, in some embodiments of the present invention the second contact metal layer may be provided on a portion of the n-type semiconductor material layer <b>12</b>, for example, in a recess or at a base of a mesa including the active region. Furthermore, in some embodiments of the present invention, an optional back-side implant or additional epitaxial layers may be provided between the substrate <b>10</b> and the second contact metal layer <b>20</b>.

0044As is further illustrated in <figref idref="f0001"><b>Figure 1</b></figref>, a reduced conductivity region <b>30</b> is provided in the active region <b>14.</b> The reduced conductivity region <b>30</b> may be positioned beneath light absorbing and/or non-transparent features and/or regions of the device. For example, as shown in <figref idref="f0001"><b>Figure 1</b></figref>, the reduced conductivity region <b>30</b> may be positioned beneath the wire bond pad <b>22</b>. A reduced conductivity region <b>30</b> may also be positioned beneath other features of the chip, such as passivation regions along an edge of the chip, current spreading fingers on a surface of the chip, or other features or areas of the chip that may tend to absorb light emitted by the chip.

0045In some embodiments of the present invention, the reduced conductivity region <b>30</b> extends through the active region <b>14</b>. As used herein, reduced conductivity refers to a region with reduced current flow over other portions of the active region. In particular embodiments, the reduction is at least an order of magnitude and in some embodiments, substantially all current flow is blocked in the reduced conductivity region.

0046As noted above, in some embodiments of the present invention the reduced conductivity region <b>30</b> extends through the active region <b>14</b>. In further embodiments of the present invention, the reduced conductivity region <b>30</b> extends from the first contact metal layer <b>18</b> to the active region <b>14</b>. In some embodiments, the reduced conductivity region extends from the first contact layer <b>18</b> into the active region <b>14</b>. In some embodiments, the reduced conductivity region extends from the first contact layer <b>18</b> through the active region <b>14</b>. The reduced conductivity region <b>30</b> may have substantially the same shape and/or area as the area of the wire bond pad <b>22</b> on the first contact metal layer <b>18</b>. In some embodiments of the present invention, the reduced conductivity region <b>30</b> has a slightly larger area than the wire bond pad <b>22</b> while in other embodiments of the present invention, the reduced conductivity region <b>30</b> has a slightly smaller area than the wire bond pad <b>22</b>. In certain embodiments of the present invention, the reduced conductivity region <b>30</b> does not absorb light or only absorbs a relatively small amount of light. In some embodiments of the present invention, the reduced conductivity region <b>30</b> is an insulating region.

0047The reduced conductivity region <b>30</b> may reduce and/or prevent current flow through the active region <b>14</b> in the area beneath the wire bond pad <b>22</b>, so that carriers have a tendency to be injected in areas other than the reduced conductivity region <b>30</b>. Thus, the presence of the reduced conductivity region <b>30</b> may reduce and/or prevent light generation through carrier recombination in this region. While not being bound by a particular theory of operation, this may be the case because the likelihood that a photon generated in the portion of the active region beneath the wire bond pad <b>22</b> is absorbed by the wire bond pad <b>22</b> may be higher than if the photon is generated in a portion of the active region that is not beneath the wire bond pad <b>22</b>. By reducing and/or eliminating the light generated in the active region beneath the wire bond pad <b>22</b>, the portion of the light generated by the light emitting device that is absorbed by the wire bond pad <b>22</b> may be reduced. For a given set of operating conditions, this reduction in the amount of light absorbed by the wire bond pad <b>22</b> may result in increased light extraction from the light emitting device as compared to a device operating under the same conditions where light is generated in the region beneath the wire bond pad <b>22</b>. Thus, some embodiments of the present invention provide a reduced conductivity region <b>30</b> that extends into and, in some embodiments, through the active region <b>14</b> in the area beneath the wire bond pad <b>22</b>. This may reduce the likelihood that carriers may spread and be injected into the active region <b>14</b> beneath the wire bond pad <b>22</b> and, thereby, result in photon generation in the area beneath the wire bond pad <b>22.</b>

0048<figref idref="f0001"><b>Figures 2A</b></figref> and <figref idref="f0002"><b>2B</b></figref> illustrate operations according to some embodiments of the present invention for forming light emitting devices having a reduced conductivity region as illustrated in <figref idref="f0001"><b>Figure 1</b></figref>. As seen in <figref idref="f0001"><b>Figure 2A</b></figref>, the various layers/regions of the light emitting device are fabricated. The particular operations in the fabrication of the light emitting device will depend on the structure to be fabricated and are described in the United States Patents and/or Applications incorporated by reference above and/or are well known to those of skill in the art and, therefore, need not be repeated herein. <figref idref="f0001"><b>Figure 2A</b></figref> also illustrates formation of a mask <b>40</b> having a window <b>42</b> corresponding to the region where the wire bond pad <b>22</b> is to be formed.

0049An implant is performed using the mask <b>40</b> so as to implant atoms into the active region <b>14</b> in the region of the wire bond pad <b>22</b> so as to form the reduced conductivity region <b>30</b> as seen in <figref idref="f0002"><b>Figure 2B</b></figref>. Such an implant may, for example, be a nitrogen implant. For example, for a gallium nitride based device, implant conditions of 60keV, 2 x 10¹³ cm^-3 N₂ may produce a non-absorbing and insulating region in Mg doped GaN. The particular implant energy and/or atoms may depend on the structure in which the reduced conductivity region <b>30</b> is formed.

0050As seen in <figref idref="f0002"><b>Figure 2B</b></figref>, after implantation, the wire bond pad <b>22</b> may be formed in the window <b>42</b>. In some embodiments, a reflective layer <b>23</b> may be formed in the window 42 prior to formation of the wire bond pad <b>22</b>. Thus, in some embodiments of the present invention, the wire bond pad <b>22</b> (and possibly the reflective layer <b>23</b>) and the reduced conductivity region <b>30</b> may be self-aligned. The wire bond pad <b>22</b> may be formed, for example, by forming a layer or layers of metal and then planarizing the layers to provide the wire bond pad <b>22</b>. The mask <b>40</b> may subsequently be removed. Optionally, the mask <b>40</b> may be made of an insulating material, such as SiO₂ and/or AlN, and may remain on the device as, for example, a passivation layer, or be removed.

0051<figref idref="f0002"><b>Figure 3</b></figref> illustrates light emitting devices according to further embodiments of the present invention. In <figref idref="f0002"><b>Figure 3</b></figref>, the first contact metal layer <b>18</b> includes a first portion <b>55</b> in contact with the p-type semiconductor material layer <b>16</b> that provides an ohmic contact to the p-type semiconductor material layer <b>16</b> and a second portion <b>57</b> in contact with the p-type semiconductor material layer <b>16</b> that does not form an ohmic contact to the p-type semiconductor material layer <b>16</b>. As used herein the term "ohmic contact" refers to a contact with a specific contact resistivity of less than about 10 e -03 ohm-cm² and, in some embodiments less than about 10 e -04 ohm-cm². Thus, a contact that is rectifying or that has a high specific contact resistivity, for example, a specific contact resistivity of greater than about 10 e -03 ohm-cm², is not an ohmic contact as that term is used herein.

0052The second portion <b>57</b> corresponds to the location of the wire bond pad <b>22</b>. By not forming an ohmic contact, current injection into the p-type semiconductor material layer <b>16</b> in the portion <b>57</b> may be reduced and/or prevented. The portion <b>57</b> that does not form an ohmic contact may be provided by damaging the p-type semiconductor layer <b>16</b> and/or the first contact metal layer <b>18</b> in the region <b>50</b> beneath the wire bond pad <b>22</b>.

0053For example, in gallium nitride based devices, the quality of the interface between the contact metal and the p-type semiconductor material may determine the quality of the resulting ohmic contact. Thus, for example, the p-type semiconductor material layer <b>16</b> in the region <b>50</b> may be exposed to a high energy plasma, such as Ar, to reduce p-type conductivity before formation of the first contact metal layer <b>18</b>. Also, the p-type semiconductor material layer <b>16</b> and the first contact metal layer <b>18</b> in the region <b>50</b> may be exposed to a high energy plasma to damage the metal/GaN interface after formation of the first contact metal layer <b>18</b>. The p-type semiconductor material <b>16</b> in the region <b>50</b> may be exposed to a H₂ while protecting the other regions of the p-type semiconductor material layer <b>16</b> before formation of the first contact metal layer <b>18</b>. The p-type semiconductor material <b>16</b> in the region <b>50</b> may be wet or dry etched while protecting the other regions of the p-type semiconductor material layer <b>16</b> before formation of the first contact metal layer <b>18</b>. Also, the p-type semiconductor material layer <b>16</b> in the region <b>50</b> may be exposed to a high energy laser while protecting the other regions of the p-type semiconductor material <b>16</b> before formation of the first contact metal layer <b>18</b>.

0054Such selective damaging of the p-type semiconductor material layer <b>16</b> and/or metal layer <b>18</b> may be provided, for example, using a mask such as described above with reference to <figref idref="f0001"><b>Figures 2A</b></figref> and <figref idref="f0002"><b>2B</b></figref> and/or by controlling a laser. The particular conditions utilized may vary depending on the procedure utilized and the composition of the p-type semiconductor material layer <b>16</b> and/or the first metal contact layer <b>18</b>.

0055<figref idref="f0003"><b>Figure 4A</b></figref> illustrates light emitting devices according to further embodiments of the present invention. In <figref idref="f0003"><b>Figure 4A</b></figref>, a Schottky contact <b>60</b> is provided on the p-type semiconductor material layer <b>16</b> and the first contact metal layer <b>18'</b> formed on the p-type semiconductor material layer <b>16</b> and the Schottky contact <b>60</b>. The wire bond pad <b>22</b> is provided on the portion of the first contact metal layer <b>18'</b> on the Schottky contact <b>60</b>. By forming a Schottky contact <b>60</b>, current injection into the p-type semiconductor material layer <b>16</b> from the first contact metal layer <b>18'</b> may be reduced and/or prevented in the region of the Schottky contact <b>60</b>.

0056Alternatively, as shown in <figref idref="f0003"><b>Figure 4B</b></figref>, a rectifying junction may be provided in the region below the wire bond pad <b>22</b>. The rectifying junction may be provided, for example, by implanting the p-type semiconductor material layer <b>16</b> with n-type ions so as to convert the region <b>70</b> beneath the wire bond pad <b>22</b> to n-type semiconductor material. Such an implant may, for example, be carried out using a mask such as discussed above with reference to <figref idref="f0001"><b>Figures 2A</b></figref> and <figref idref="f0002"><b>2B</b></figref>. Alternatively, a region of n-type material could be formed where the Schottky contact <b>60</b> is illustrated in <figref idref="f0003"><b>Figure 4A</b></figref> and the first contact metal <b>18'</b> could be formed on the region of n-type semiconductor material and the p-type semiconductor material layer <b>16.</b>

0057Referring to <figref idref="f0004"><b>Figure 5</b></figref>, some embodiments of the invention provide a light emitting device <b>100A</b> including a substrate <b>110</b> on which an n-type semiconductor layer <b>112</b>, an active region <b>114</b> and a p-type semiconductor layer <b>116</b> are formed. The semiconductor substrate <b>110</b> may include a conductive silicon carbide substrate, for example, and the n-type semiconductor layer <b>112</b>, the active region <b>114</b> and the p-type semiconductor layer <b>116</b> may include group III-nitride based semiconductor layers. The light emitting device <b>100A</b> further includes a reduced conductivity region <b>130</b> in the p-type semiconductor layer <b>116</b>. As seen in <figref idref="f0004"><b>Figure 5</b></figref>, the substrate <b>110</b> may include shaped sidewalls <b>111</b> that may increase the efficiency of light extraction from the device <b>100A</b> by changing the angle at which light generated in the active region <b>114</b> strikes the sidewalls of the device <b>100A</b>. In the structure illustrated in <figref idref="f0004"><b>Figure 5</b></figref>, the reduced conductivity region <b>130</b> may be located a distance <b>D1</b> from the bond pad <b>122</b> of about 50 to 400 µm. The reduced conductivity region <b>130</b> may be formed using any of the methods described above, including implantation of ions into the p-type semiconductor layer <b>116</b>.

0058The light emitting device <b>100A</b> may be suitable for so-called "flip chip" mounting on an underlying support. In particular, the semiconductor structure may be mounted on a submount, bond pad or other surface with the p-type semiconductor layer <b>116</b> facing down and the substrate <b>110</b> facing up. In order to facilitate bonding the light emitting device <b>100A</b> to a support, a p-contact metal stack <b>118</b> is formed on exposed surface of the type semiconductor layer <b>116</b>. Appropriate metal stacks for flip chip mounting of optoelectronic devices are disclosed for example in <patcit id="pcit0022" dnum="US20030015721A"><text>U.S. Patent Publication No. 2003/0015721</text></patcit> entitled "Light Emitting Diodes Including Modifications For Submount Bonding And Manufacturing Methods Therefor," the disclosure of which is incorporated herein by reference. In particular, the p-contact metal stack <b>118</b> may include an ohmic layer <b>118A</b> of a metal, such as platinum, that makes an ohmic contact with the p-type semiconductor layer <b>116</b>. The metal stack <b>118</b> may further include a reflective layer <b>118B</b>, a barrier layer <b>118C</b> and/or a bonding layer <b>118D</b>.

0059The bonding layer <b>118D</b> may include gold and/or tin, and may be provided to facilitate thermosonic and/or thermocompression bonding of the device <b>100A</b> to a submount. The reflective layer <b>118B</b> may include a reflective metal, such as silver or aluminum, and may be provided to reflect light away from a submount and back into the device <b>100A</b> so that it may be usefully extracted. The barrier layer <b>118C</b> may include a metal, such as tungsten, titanium, titanium nitride and/or nickel, that may prevent the metal of the bonding layer <b>118D</b> from contaminating the ohmic metal <b>118A</b> and /or the reflector <b>118B</b>. Barrier layers may be formed as described in <patcit id="pcit0023" dnum="US20050194603A"><text>U.S. Patent Publication No. 2005/0194603</text></patcit> entitled "Light Emitting Diodes Including Barrier Layers/Sublayers And Manufacturing Methods Therefor," the disclosure of which is incorporated herein by reference. An optional adhesion layer (not shown) may be provided between the barrier layer <b>118C</b> and the bonding layer <b>118D.</b>

0060When an optoelectronic device, such as the device <b>100A</b> shown in <figref idref="f0004"><b>Figure 5</b></figref>, is mounted on an opaque support member with the p-side of the device <b>100A</b> facing down (i.e towards the support), it may not be necessary to form a transparent electrode or a current spreading layer on the exposed substrate <b>110</b>, since the conductivity of the substrate <b>110</b> may be high enough that current may spread naturally in the device. Accordingly, as shown in <figref idref="f0004"><b>Figure 5</b></figref>, the device may include a wire bond pad <b>122</b> formed on the substrate <b>110</b>. An ohmic contact (not shown) may be formed between the wire bond pad <b>122</b> and the substrate <b>110</b>. In some embodiments, the ohmic contact may be formed in self-alignment with the bond pad 122.

0061The reduced conductivity region <b>130</b> may extend from a surface of the p-type semiconductor layer <b>116</b> opposite the active region <b>114</b> into the p-type semiconductor layer <b>116</b>. The reduced conductivity region <b>130</b> may extend partially and/or completely through the p-type semiconductor layer <b>116</b>. In some embodiments, including embodiments that include a substrate <b>110</b>, the reduced conductivity region <b>130</b> may extend completely through the active region <b>114</b> to/into the n-type semiconductor layer <b>112</b>. The reduced conductivity region <b>130</b> may be formed using techniques such as those described above with respect to <figref idref="f0001 f0002 f0003"><b>Figures 1-4</b></figref>. For example, the reduced conductivity region <b>130</b> may be formed by implanting ions into the p-type semiconductor layer <b>116</b> through a mask, as described above with reference to <figref idref="f0001"><b>Figure 2A</b></figref>.

0062As further shown in <figref idref="f0004"><b>Figure 5</b></figref>, the reduced conductivity region <b>130</b> may be generally aligned with the bond pad <b>122</b>. Since the p-type semiconductor layer <b>116</b> may be relatively thin compared, for example, to the substrate <b>110</b>, and since current may not spread readily in the p-type semiconductor layer <b>116</b>, the presence of the reduced conductivity region <b>130</b> may reduce the number of photons generated in the device <b>100A</b> directly beneath the wire bond pad <b>122</b>. Accordingly, the reduced conductivity region <b>130</b> may have a shape that is about the same shape as the wire bond pad <b>122</b>. Furthermore, the reduced conductivity region <b>130</b> may have an area that is about the same as, slightly less than or slightly greater than, the area of the wire bond pad <b>122</b>. In some embodiments, the reduced conductivity region may have a diameter that is about 6 to about 30 µm larger than the diameter of the bond pad <b>122</b>. In particular, bond pad <b>122</b> may have a diameter of about 100 to 105 µm, and the reduced conductivity region <b>130</b> may have a diameter that is about 14 µm larger than the diameter of the bond pad <b>122</b>. In embodiments including a substrate (i.e. in which the substrate <b>110</b> has not been removed), it may be desirable to provide a reduced conductivity region <b>130</b> that is larger in area than the bond pad <b>122</b>. For example, if the wire bond pad <b>122</b> has a circular shape, the reduced conductivity region <b>130</b> may also have a circular shape with an area that is less than, about equal to, or slightly greater than the diameter of the wire bond pad <b>122</b>.

0063Further embodiments of the invention are shown in <figref idref="f0005"><b>Figures 6A</b> and <b>6B</b></figref> in which a light emitting device <b>100B</b> is shown including a p-type semiconductor layer <b>116</b> an active region <b>114</b> and an n-type semiconductor layer <b>112</b>. A p-contact metal stack <b>118</b> is formed on a surface of the p-type semiconductor layer <b>116</b>, and a wire bond pad <b>122</b> is formed on a surface of the n-type semiconductor layer <b>112</b> opposite the p-type semiconductor layer <b>116</b>. In particular, the light emitting device <b>100B</b> shown in <figref idref="f0005"><b>Figures 6A</b> and <b>6B</b></figref> may not include a substrate.

0064As further shown in <figref idref="f0005"><b>Figure 6A</b></figref>, a reduced conductivity region <b>130</b> is provided in the p-type semiconductor layer <b>116</b> generally aligned with the wire bond pad <b>122</b>. The reduced conductivity region <b>130</b> may extend from a surface of the p-type semiconductor layer <b>116</b> opposite the active region <b>114</b> into the p-type semiconductor layer <b>116</b>. The reduced conductivity region <b>130</b> may extend partially and/or completely through the p-type semiconductor layer <b>116</b>. The reduced conductivity region <b>130</b> may have an area that is equal to, greater than, or less than the area of the wire bond pad <b>122</b>. The reduced conductivity region <b>130</b> may be located within the device <b>100B</b> a distance <b>D2</b> from the wire bond pad <b>122</b>. In some embodiments, the distance <b>D2</b> may be from 0.3 to 10 µm. In particular, the distance <b>D2</b> may be about 2 to 3 µm.

0065<figref idref="f0009"><b>Figures 11A - 11C</b></figref> are plan view illustrations of a light emitting device <b>100B</b> including a wire bond pad <b>122</b> and an aligned reduced conductivity region <b>130</b>. As shown therein, the reduced conductivity region <b>130</b> may have a peripheral shape that is similar to the peripheral shape of the wire bond pad <b>122,</b> which in the embodiments illustrated in <figref idref="f0009"><b>Figures 11A-11C</b></figref> is generally circular. The wire bond pad <b>122</b> and the reduced conductivity region <b>130</b> may have other peripheral shapes, such as rectangular, star, cross or other shape or combination of shapes.

0066As shown in <figref idref="f0009"><b>Figure 11A</b></figref>, the reduced conductivity region <b>130</b> may have an area that is slightly larger than the area of the wire bond pad <b>122</b> in some embodiments, while in other embodiments the reduced conductivity region <b>130</b> may have an area that is slightly less than (<figref idref="f0009"><b>Figure 11B</b></figref>) or about equal to (<figref idref="f0009"><b>Figure 11C</b></figref>) the area of the wire bond pad <b>122</b>.

0067Referring to <figref idref="f0005"><b>Figure 6B</b></figref>, the reduced conductivity region <b>130</b> may extend completely through the p-type semiconductor layer <b>116</b> and into the active region <b>114</b>. In some embodiments, including embodiments that do not include a substrate, the reduced conductivity region <b>130</b> may extend completely through the active region <b>114</b> to/into the n-type semiconductor layer <b>112</b>.

0068Further embodiments of the invention are shown in <figref idref="f0006"><b>Figure 7A</b></figref>, which illustrates a light emitting device <b>100C</b> that includes a p-type semiconductor layer <b>116</b>, an active region <b>114</b> and an n-type semiconductor layer <b>112</b>. A wire bond pad <b>122</b> is formed on a surface of the n-type semiconductor layer <b>112</b>. A patterned ohmic contact <b>118</b> is formed on a surface of the p-type semiconductor layer <b>116</b> opposite the n-type semiconductor layer <b>112</b>. The light emitting device <b>100C</b> also includes a non-ohmic contact <b>140</b> on the p-type semiconductor layer <b>116</b> opposite the wire bond pad <b>122</b>. In some embodiments, the non-ohmic contact <b>140</b> may include, for example, a rectifying Schottky contact. The formation of rectifying Schottky contacts on nitride-based semiconductor materials is well known to those skilled in the art. In other embodiments, the non-ohmic contact <b>140</b> may include a non-conductive material, such as silicon dioxide.

0069The non-ohmic contact <b>140</b> may have a shape that is about the same as the shape of the wire bond pad <b>122</b>. The contact <b>140</b> may have an area that is slightly less than, about equal to, or slightly greater than the area of the wire bond pad <b>122</b>. Accordingly, when a voltage is applied across the terminals of the device <b>100C</b>, current may not flow from the non-ohmic contact <b>140</b> into the p-type semiconductor layer <b>116</b>, which may reduce the number of photons generated in the active layer <b>114</b> beneath the wire bond pad <b>122</b>.

0070Referring to <figref idref="f0006"><b>Figure 7B</b></figref>, in some embodiments, the metal stack <b>118</b> may be formed on the surface of the p-type semiconductor layer <b>116</b> in regions other than an area of reduced conductivity <b>150</b> opposite the wire bond pad <b>122</b>. That is, because the metal stack <b>118</b> is not formed in the area <b>150</b>, a reduced current may flow through the area <b>150</b> when the device is energized, which may reduce the number of photons generated in the active layer <b>114</b> beneath the wire bond pad <b>122</b>.

0071Further embodiments of the invention are illustrated in <figref idref="f0007"><b>Figure 8</b></figref><b>.</b> In the embodiments of <figref idref="f0007"><b>Figure 8</b></figref>, a device <b>100E</b> includes a p-type semiconductor layer <b>116</b>, an active region <b>114</b>, and an n-type semiconductor layer <b>112</b>. A p-type contact <b>118</b> is formed on a surface of the p-type semiconductor layer <b>116</b> opposite the n-type semiconductor layer <b>112</b>. A wire bond pad <b>122</b> is formed on a surface of the n-type semiconductor layer <b>112</b> opposite the p-type semiconductor layer <b>116</b>. An ohmic contact <b>154</b> is formed on the same surface of the n-type semiconductor layer <b>112</b> as the wire bond pad <b>122</b>, and is electrically connected to the wire bond pad <b>122</b>. The ohmic contact <b>154</b> may include a transparent material that forms an ohmic contact to the n-type semiconductor layer <b>112</b>, such as ITO.

0072A reduced conductivity region <b>152</b> is formed in the n-type semiconductor layer <b>112</b> beneath the wire bond pad <b>122</b>. The reduced conductivity region <b>152</b> may extend from the surface of the n-type semiconductor layer <b>112</b> at least partially into the n-type semiconductor layer <b>112</b>. In some embodiments, the reduced conductivity region <b>152</b> may extend completely through the n-type semiconductor layer <b>112</b> and to/into the active region <b>114</b>.

0073<figref idref="f0007"><b>Figure 9A</b></figref> illustrates a device <b>100F</b> according to further embodiments of the invention. The device <b>100F</b> also includes a p-type semiconductor layer <b>116</b>, an active region <b>114</b>, and an n-type semiconductor layer <b>112</b>. A p-type contact <b>118</b> is formed on a surface of the p-type semiconductor layer <b>116</b> opposite the n-type semiconductor layer <b>112</b>. A wire bond pad <b>122</b> is formed on a surface of the n-type semiconductor layer <b>112</b> opposite the p-type semiconductor layer <b>116</b>. An ohmic contact <b>154</b> is formed on the same surface of the n-type semiconductor layer <b>112</b> as the wire bond pad <b>122</b>.

0074A first reduced conductivity region <b>152</b> is formed in the n-type semiconductor layer <b>112</b> beneath the wire bond pad <b>122</b>. The first reduced conductivity region <b>152</b> may be aligned with the wire bond pad <b>122</b> and may extend from the surface of the n-type semiconductor layer <b>112</b> at least partially into the n-type semiconductor layer <b>112</b>. In some embodiments, the first reduced conductivity region <b>152</b> may extend completely through the n-type semiconductor layer <b>112</b> and to/into/through the active region <b>114</b>.

0075A second reduced conductivity region <b>150</b> is formed in the p-type semiconductor layer <b>116</b>. The second reduced conductivity region <b>150</b> may be aligned with the first reduced conductivity region <b>152</b> and/or the wire bond pad <b>122</b>. The second reduced conductivity region <b>150</b> may extend from the surface of the p-type semiconductor layer <b>116</b> at least partially into the p-type semiconductor layer <b>116</b>, and in some cases to/into/through the active region <b>114</b>.

0076In embodiments including a reduced conductivity region <b>150</b>, <b>152</b> on both sides of the device, such as the first reduced conductivity region <b>152</b> and the second reduced conductivity region <b>150</b> of the device <b>100F</b>, the reduced conductivity regions <b>150</b>, <b>152</b> need not be formed using the same techniques, but could, for example, be formed using different techniques. For example, the first reduced conductivity region <b>152</b> could be formed via ion implantation, while the second reduced conductivity region <b>150</b> could be formed using plasma treatment and or exposure to hydrogen gas, or vice-versa. Furthermore, one or both of the reduced conductivity regions <b>150</b>, <b>152</b> could be formed by forming a non-ohmic material on the surface of the respective semiconductor layer <b>116</b>, <b>112</b> prior to forming an electrical contact thereon, or by not forming the ohmic contact on an area of the surface of the semiconductor layer that corresponds to the bond pad <b>122</b>.

0077<figref idref="f0008"><b>Figure 9B</b></figref> illustrates a device <b>100G</b> according to further embodiments of the invention. The device <b>100G</b> also includes a p-type semiconductor layer <b>116</b>, an active region <b>114</b>, and an n-type semiconductor layer <b>112</b>. A p-type contact <b>118</b> is formed on a surface of the p-type semiconductor layer <b>116</b> opposite the n-type semiconductor layer <b>112</b>. A wire bond pad <b>122</b> is formed on a surface of the n-type semiconductor layer <b>112</b> opposite the p-type semiconductor layer <b>116</b>. An ohmic contact <b>154</b> is formed on the same surface of the n-type semiconductor layer <b>112</b> as the wire bond pad <b>122</b>.

0078A reduced conductivity region <b>152</b> is formed in the n-type semiconductor layer <b>112</b> beneath the wire bond pad <b>122</b>. The reduced conductivity region <b>152</b> may be aligned with the wire bond pad <b>122</b> and may extend from the surface of the n-type semiconductor layer <b>112</b> at least partially into the n-type semiconductor layer <b>112</b>. In some embodiments, the reduced conductivity region <b>152</b> may extend completely through the n-type semiconductor layer <b>112</b> and to/into/through the active region <b>114</b>.

0079A metal contact <b>118</b> is formed on a surface of the p-type semiconductor layer <b>116</b> opposite the n-type semiconductor layer <b>112</b>. The metal contact <b>118</b> forms on ohmic contact to the p-type semiconductor layer <b>116</b> in a region other than a reduced conductivity area of the surface of the p-type semiconductor layer <b>116</b> that is aligned with the wire bond pad <b>122</b>.

0080The light emitting device <b>100G</b> also includes a non-ohmic contact <b>140</b> on the p-type semiconductor layer <b>116</b> opposite the wire bond pad <b>122</b>. In some embodiments, the non-ohmic contact <b>140</b> may include, for example, a rectifying Schottky contact. In other embodiments, the non-ohmic contact <b>140</b> may include a non-conductive material, such as silicon dioxide.

0081The non-ohmic contact <b>140</b> may have a shape that is about the same as the shape of the wire bond pad <b>122</b>. The contact <b>140</b> may have an area that is slightly less than, about equal to, or slightly greater than the area of the wire bond pad <b>122</b>. In other embodiments, the non-ohmic contact <b>140</b> may include a gap on which no contact is formed.

0082Still further embodiments of the invention are illustrated in <figref idref="f0008"><b>Figure 10</b></figref>, which illustrates a semiconductor light emitting device <b>100H</b> that includes a reduced conductivity region <b>160</b> that extends beneath the wire bond pad <b>122</b> from a surface of the n-type semiconductor layer <b>112</b> and through the device <b>100G</b> to the opposite surface of the p-type semiconductor layer <b>116</b>.

0083Some chip structures in which embodiments of the invention may be employed are shown in isometric view in <figref idref="f0010"><b>Figures 12</b></figref> and <figref idref="f0011"><b>13</b></figref>. For example, <figref idref="f0010"><b>Figure 12</b></figref> illustrates a chip structure <b>100J</b> including a carrier substrate <b>210</b>, such as a silicon substrate, on which an LED structure has been bonded via a metal bonding layer <b>220</b>. A reflective layer <b>230</b> is between the bonding layer <b>220</b> and the LED structure that includes a p-type semiconductor layer <b>116</b>, an active layer <b>114</b> and an n-type semiconductor layer <b>112</b>.

0084A pair of bond pads <b>122</b> are on the surface of the n-type semiconductor layer <b>112</b> opposite the substrate <b>210</b>. The bond pads <b>122</b> are electrically connected to a current spreading structure that includes a plurality of current spreading fingers <b>154</b> on the n-type semiconductor layer <b>112</b>.

0085The reduced conductivity region <b>30</b> may be formed underneath the bond pads <b>122</b>, underneath the current spreading fingers <b>154</b>, and/or under both the bond pads <b>122</b> and the current spreading fingers <b>154</b>.

0086An exemplary horizontal chip structure <b>100K</b> is illustrated in <figref idref="f0011"><b>Figure 13</b></figref>. The chip structure <b>100K</b> includes a transparent substrate <b>110</b> on which an n-type semiconductor layer <b>112</b> is formed. A mesa structure including an active region <b>114</b> and a p-type semiconductor layer <b>116</b> is on the n-type semiconductor layer. A transparent ohmic contact <b>118</b>, which may include ITO, is on the p-type semiconductor layer <b>116</b>. A bond pad <b>122A</b> is on the transparent ohmic contact layer <b>118</b>, and a current spreading finger <b>154A</b> extends from the bond pad <b>122A</b>. A bond pad <b>122B</b> is on the n-type semiconductor layer <b>112</b>, and a current spreading finger <b>154B</b> extends from the bond pad <b>122B</b>. A reflective layer <b>23</b> (<figref idref="f0001"><b>Figure 1</b></figref>) may be provided beneath the bond pad <b>122A</b> and/or the current spreading finger <b>154A</b>.

0087The reduced conductivity region <b>30</b> may be formed underneath the bond pad <b>122A</b>, underneath the current spreading fingers <b>154A</b>, and/or under both the bond pad <b>122A</b> and the current spreading finger <b>154A</b>.

0088While embodiments of the present invention are illustrated in <figref idref="f0001 f0002 f0003 f0004 f0005 f0006 f0007 f0008 f0009 f0010 f0011"><b>Figures 1-13</b></figref> with reference to particular light emitting device structures, other structures may be provided according to some embodiments of the present invention. Thus, embodiments of the present invention may be provided by any light emitting structure that includes one or more of the various current blocking mechanisms as described above. For example, current blocking mechanisms according to some embodiments of the present invention may be provided in conjunction with the exemplary light emitting device structures discussed in the United States Patents and/or Applications incorporated by reference above.

0089Embodiments of the present invention have been described with reference to a wire bond pad <b>22,122.</b> As used herein, the term bond pad includes a light absorbing contact structure. A bond pad may be a single or multiple layers, may be a metal and/or metal alloy and/or may be of uniform of non-uniform composition.

0090Furthermore, while embodiments of the present invention have been described with reference to a particular sequence of operations, variations from the described sequence may be provided while still benefiting from the teachings of the present invention. Thus, two or more steps may be combined into a single step or steps performed out of the sequence described herein. For example, a reduced conductivity region may be formed in a semiconductor layer before or after forming a metal layer on the semiconductor layer. Thus, embodiments of the present invention should not be construed as limited to the particular sequence of operations described herein unless stated otherwise herein.

0091It will be understood by those having skill in the art that various embodiments of the invention have been described individually in connection with <figref idref="f0001 f0002 f0003 f0004 f0005 f0006 f0007 f0008 f0009 f0010 f0011"><b>Figures 1-13</b></figref><b>.</b> However, combinations and subcombinations of the embodiments of <figref idref="f0001 f0002 f0003 f0004 f0005 f0006 f0007 f0008 f0009 f0010 f0011"><b>Figures 1-13</b></figref> may be provided according to various embodiments of the present invention.As noted above, the reduced conductivity regions <b>30</b> may be used to reduce/prevent carrier recombination in areas of a device where generated light may be likely to be absorbed by some feature of the device, such as a bond pad, a current spreading finger, a passivation region, etc. Thus, in some embodiments, the reduced conductivity regions <b>30</b> may be aligned with light-absorbing features and/or regions of a device. However, in some cases, it may be desirable to form reduced conductivity regions <b>30</b> in other areas that are not aligned with light absorbing regions or features of a device. For example, it may be desirable to provide reduced conductivity regions <b>30</b> in a device that cause the device to generate light having a desired far-field emission pattern. Thus, in some embodiments, reduced conductivity regions <b>30</b> may be used to shape the light emission pattern of a light emitting device.

0092In the drawings and specification, there have been disclosed embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.