Non-volatile SRAM memory cell with mobile-gate transistors and piezoelectric activation

TECHNICAL AREA

0001The invention relates to the field of static random access memory (SRAM) and that of non-volatile memories. It relates in particular to a non-volatile SRAM memory cell structure comprising modulable threshold voltage transistors, in particular equipped with a movable gate and piezoelectric actuation means able to modulate the position of the gate and to maintain a position of the gate after switching off the power of the transistors. Such a memory cell can combine the performance, in terms of consumption and size, of a conventional SRAM cell, as well as the qualities of maintaining the stored information of a non-volatile cell. An advantageous embodiment of the cell makes it possible to obtain improved reading stability and reduced static consumption.

STATE OF THE PRIOR ART

0002A conventional SRAM memory cell (SRAM for "static random access memory" or RAM) generally comprises two inverters 10, 11, connected in a so-called "flip-flop" configuration and two access transistors 12, 13 connected to so-called bit lines 15 and 16, and controlled by a word line 17 (<figref idref="f0001">figure 1</figref>).

0003The characteristics sought for a memory cell are:<ul id="ul0001" list-style="dash" compact="compact"><li>good stability during the various reading, writing and retention operations, respectively evaluated using a reading stability factor (SNM), a write margin factor (WM), a retention stability factor (RNM),</li><li>a conduction current (I_CELL) or the largest possible load to give the cell a high operating speed,</li><li>a smallest possible cell size to make it possible to produce a memory with a high cell integration density,</li><li>a current in retention (I_OFF) as low as possible to minimize static power consumption.</li></ul>

0004These criteria are difficult to reconcile and cause the memory designers to compromise.

0005By seeking to reduce more and more the sizes of the transistors of the memory cells, the parameters of these transistors fluctuate. This entails, as indicated in the documents [TAK01] and [YAM04] (referenced at the end of the present description in the same way as all the other documents cited in the present application), an increase in the sensitivity of the memory cells to different noise sources such as capacitive coupling, inductive coupling, power supply noise. The margins in writing and reading are becoming weaker, which limits the possibility of reducing the area of ​​the memory cells.

0006Furthermore, the increasing development of multimedia applications, leads to the need to implement non-volatile memory circuits with improved performance. Among the non-volatile memories existing there are for example FLASH type memories, PCM type (PCM for "Phase-Change Memory" or phase change memory). The document [NAT'05] presents, for example, different types of existing nonvolatile memory cells.

0007The main disadvantage of current nonvolatile memories lies in their insufficient performance in terms of speed of reading and writing.

0008There is the problem of finding a new memory cell structure, non-volatile, which has stability and electrical performance and equivalent size or improved over a conventional SRAM memory.

STATEMENT OF THE INVENTION

0009The present invention relates to a random access non-volatile random access memory cell, comprising: at least a first plurality of transistors forming a flip-flop, the transistors of the first plurality of transistors comprising respectively: a gate dielectric and a movable gate, suspended above and disjoint from the gate dielectric, the gate being located at an adjustable distance from said gate dielectric area, the transistors being further surmounted by piezoelectric actuating means adapted to moving the grid relative to said channel area.

0010The piezoelectric actuation means may comprise a stack formed of at least one layer of piezoelectric material resting on a first polarization electrode, a second polarization electrode resting on the layer of piezoelectric material.

0011According to one possible implementation, the gate may be attached to said first electrode.

0012According to a possible implementation of the cell, the gate may be in contact with said first electrode.

0013According to one possible implementation, the transistors of the first plurality of transistors may have a source zone connected to the second electrode of their respective piezoelectric actuating means.

0014According to one variant, the transistors of the first plurality of transistors may advantageously have their respective drain zone connected to the second electrode of their respective piezoelectric actuating means.

0015According to one possibility, the transistors of the first plurality of transistors may be respectively able to adopt: at least a first position in which their gate is located at a first distance from the channel, and to adopt at least a second position in which the gate is located at a second distance from the channel, different from the first distance.

0016The random access non-volatile random access memory cell may further comprise supply means capable of supplying the transistors of the first plurality of transistors, and their respective actuating means. The transistors of the first plurality of transistors may be adapted respectively to adopt a given position among said first and second positions, and further able to maintain the gate in said given position after stopping or extinction of said supply means.

0017The transistors of the first plurality of transistors may respectively be adapted to adopt a state in which the piezoelectric actuation means are placed in a given polarization state, and in which the gate is maintained by means of the actuating means. piezoelectric contacts with the gate dielectric, the transistors of the first plurality of transistors being further adapted to adopt another state in which the piezoelectric actuating means are not polarized, and wherein the gate is held by electrostatic bonding, in contact with the gate dielectric.

0018The transistors of the first plurality of transistors may have a variable threshold voltage that may vary by moving the movable gate with the aid of the piezoelectric actuation means.

0019According to one possibility, said first plurality of transistors may comprise:<ul id="ul0002" list-style="dash" compact="compact"><li>a first load transistor and a second load transistor,</li><li>a first conduction transistor and a second conduction transistor.</li></ul>

0020The random access non-volatile random access memory cell according to the invention is capable of adopting several modes of operation including at least one information retention mode contained in the cell, at least one information reading mode contained in FIG. the cell, and at least one information write mode in the cell, the transistors of the first plurality of transistor respectively having a variable threshold voltage.

0021The invention also relates to an SRAM memory, comprising a plurality of cells as defined above.

0022The invention further relates to a microelectronic device having at least one SRAM memory as defined above.

BRIEF DESCRIPTION OF THE DRAWINGS

0023The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which:<ul id="ul0003" list-style="dash" compact="compact"><li>the <figref idref="f0001">figure 1</figref>illustrates an example of a static random access memory cell according to the prior art,</li><li>the <figref idref="f0001">Figures 2A</figref>, <figref idref="f0002">2B</figref>, illustrate a transistor integrated in a memory cell according to the invention and comprising a suspended gate and piezoelectric actuation means, able to move the gate of the transistor relative to the gate dielectric and to the transistor channel,</li><li>the <figref idref="f0003">Figures 3A, 3B</figref> illustrate different positions of a transistor integrated in a memory cell according to the invention, and provided with a suspended mobile grid and piezoelectric actuation means of the gate,</li><li>the <figref idref="f0004">Figures 4A, 4B</figref>, respectively illustrate steps of bonding the gate to the gate dielectric, and detaching from the grid of the gate dielectric, the suspended gate transistor and piezoelectric actuation integrated to a memory cell according to the invention,</li><li>the <figref idref="f0005">Figures 5A, 5B</figref>, illustrate a non-volatile operation of a piezoelectric suspended mobile gate transistor, integrated in a memory cell according to the invention,</li><li>the <figref idref="f0005">Figures 6A, 6B</figref>, illustrate a method of modulating the threshold voltage of a gate transistor with piezoelectric actuation integrated into a memory cell according to the invention, while the <figref idref="f0006">Figure 6C</figref>, illustrates a gate current-drain voltage characteristic of a transistor according to the invention,</li><li>the <figref idref="f0006 f0007 f0008 f0009 f0010">Figures 7A to 7J</figref>, illustrate, in a sectional view, the steps of an exemplary method for producing a microelectronic device according to the invention, while the <figref idref="f0011 f0012">Figures 8A to 8E</figref> illustrate, according to a view from above, steps of this process,</li><li>the <figref idref="f0013 f0014">Figures 9A to 9D</figref>, illustrate, in a sectional view, the steps of an alternative method of producing a microelectronic device according to the invention, while the <figref idref="f0015">Figures 10A to 10C</figref> illustrate, according to a view from above, different stages of this variant of the process,</li><li>the <figref idref="f0016 f0017">Figures 11A to 11C</figref>, illustrate, in a sectional view, the steps of another alternative method of producing a microelectronic device according to the invention, while the <figref idref="f0017">Figures 12A to 12B</figref> illustrate, according to a view from above, steps of this other variant of the process,</li><li>the <figref idref="f0018">figure 13</figref> illustrates an example of a nonvolatile SRAM memory cell according to the invention, provided with gate-suspended transistors and with piezoelectric actuation of the gate,</li><li>the <figref idref="f0018">figure 14A</figref> represents a piezoelectric gate and piezoelectric gate transistor, in which the source area is connected with the upper electrode of the piezoelectric actuator,</li><li>the <figref idref="f0019">Figure 14B</figref> illustrates an example of a memory cell 6T according to the invention provided with transistors such as that illustrated on FIG. <figref idref="f0018">figure 14A</figref>,</li><li>the <figref idref="f0019">figure 15A</figref> represents a piezoelectric gate and piezoelectric gate transistor, in which the drain region is connected with the upper electrode of the piezoelectric actuator,</li><li>the <figref idref="f0020">figure 15B</figref> illustrates an example of a memory cell 6T according to the invention provided with transistors such as that illustrated on FIG. <figref idref="f0018">figure 14A</figref> piezoelectric,</li><li>the <figref idref="f0020">figure 16</figref> illustrates an SRAM memory cell according to the invention in retention mode,</li><li>the <figref idref="f0021">Figure 17A-17B</figref> illustrates a write phase in an SRAM memory cell according to the invention,</li><li>the <figref idref="f0021">figure 18</figref> illustrates a restart of a memory cell according to the invention and its non-volatile operation.</li></ul>

0024Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.

0025The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.

DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

0026An example of a transistor integrated into a memory cell according to the invention will now be given in connection with the <figref idref="f0001">Figures 2A</figref> and <figref idref="f0002">2B</figref>.

0027This transistor rests on a substrate 100, in which a semiconductor zone 102, able to act as an active zone, has been produced. The semiconductor zone 102 comprises a source region 104, a drain region 106, on either side of a channel zone 105 of the transistor. A layer 111 of gate dielectric covers the semiconductor zone 102. The transistor comprises a suspended gate 116. The gate 116 is not integral with, or is not attached to, the gate dielectric layer 111.

0028The device is adapted to adopt at least one position in which the gate 116 is located at a distance from the gate dielectric layer 111, so that a space exists between the gate 116 and the gate dielectric layer 111. The gate 116 and the gate dielectric layer 111, can be separated by a distance Δ (defined on the <figref idref="f0002">Figure 2B</figref> in a direction parallel to the vector <o ostyle="single">j</o> an orthogonal reference [0;<o ostyle="single">i</o>;<o ostyle="single">j</o>;<o ostyle="single">k</o>]) adjustable or adjustable.

0029The gate 116 is suspended or attached by its upper face to piezoelectric actuating means or to a piezoelectric actuator. The distance between the gate 116 and the channel 102 can be modulated using the piezoelectric actuating means. The piezoelectric actuation means are able to move the gate 116 relative to the channel 105 of the transistor. The gate 116 is capable of adopting several positions relative to the channel 105. By piezoelectric actuation is meant a displacement of the gate due to a deformation of the piezoelectric layer 125 and its associated electrodes 122, 128 by an inverse piezoelectric effect.

0030The piezoelectric actuating means 120 may comprise a stack 120 formed of a lower electrode 122 to which the grid 116 may be attached, a layer of piezoelectric material 125 resting on the lower electrode 122, and an upper electrode 128 resting on the layer of piezoelectric material 125.

0031The device may also comprise one or more elements 121b, 121c, supporting the stack 120 of the piezoelectric actuator, located on the periphery of the latter (<figref idref="f0002">Figure 2B</figref>). Plots (not shown on the<figref idref="f0001 f0002">Figures 2A-2B</figref>) are also provided for making the contacts of the transistor. One or more conductive pads may also be provided for making the contacts of the piezoelectric actuator. Conductive pads may be provided for respectively connecting or electrically connecting source area 104 to source biasing means, drain area 106 to drain biasing means 106, gate 116, and lower electrode 122. from the stack 120 to polarization means of the gate and the lower electrode 122, the upper electrode 128 of the actuator to polarization means of the piezoelectric actuator.

0032An example of operation of a microelectronic device according to the invention will be given in connection with the <figref idref="f0001 f0002">Figures 2A-2B</figref>, <figref idref="f0003">3A-3B</figref> and <figref idref="f0004">4A-4B</figref>.

0033The device can adopt a so-called "rest" position in which the stack 120 is suspended above and at a so-called "rest" height h0 of the gate dielectric layer 111. In the rest position, the gate 116 is at a so-called "rest" distance Δ0 from the dielectric 111, so that a gap 170 is located between the gate 116 and the gate dielectric zone 111. The piezoelectric layer 125 may be flat in the rest position. In the rest position, the supply of the actuating means and the transistor is off, so that all the polarizations are at a zero potential (<figref idref="f0003">figure 3A</figref>).

0034When polarized, the piezoelectric actuation means can actuate the gate 116, and allow to move the latter. According to the direction of the external electric field applied to it by means of the electrodes 122, 128, this piezoelectric layer 125 is able to compress or to relax, and to thereby move the gate 116 attached thereto.

0035In addition to the inverse piezoelectric effect, an electrostatic attraction effect resulting from the potential difference between the gate 116 and the transistor channel 105 is capable of being implemented. This effect of electrostatic attraction results in an electrostatic force tending to bring the gate 116 closer to the channel 105 of the transistor, and which can make it possible to put the gate 116 and the gate dielectric 111 into contact.

0036An additional force called adhesion or also called molecular bonding can also be implemented. Molecular bonding, in particular of the Van der Waals type, is likely to occur between the underside of the gate 116 and the gate dielectric surface 111. The implementation of this additional force depends in particular on the flatness of the lower face of the gate 116 and the facing surface of gate dielectric 111, as well as a suitable dimensioning of the elements of the structure. The implementation of the adhesion or molecular bonding force is described for example in the following documents:<nplcit id="ncit0001" npl-type="s"><text>Asghar Ramezani et al. : "Influence of Van Der Waals Force on the Pull-In Parameters of Cantilever Type Nanoscale Electrostatic Actuators", Microsystem Technologies, 2006, vol. 12, pp. 1153-1161</text></nplcit>; the article of<nplcit id="ncit0002" npl-type="b"><text>W. Merlijn van Spengen et al. : "A Physical Model for Predicting in MEMS," Institute of Physics Publishing, Journal of Micromechanics and Microengineering, 12, (2002), pp.702-713.</text></nplcit> ; and the article of<nplcit id="ncit0003" npl-type="s"><text>Y.-P. ZHAO et al. : Mechanics of Adhesion in MEMS-a Review, J. Adhesion Sci. Technol. Flight. 17, No. 4, pp.519-546</text></nplcit>. Compared to the other forces to which the grid is subjected, the adhesion or molecular bonding force becomes all the more important as the grid is close to the gate dielectric.

0037The implementation of the adhesion force or molecular bonding, allows to give the device a non-volatile operation. The latter is likely to remain in a given position during the power off and polarizations of the actuator and the transistor. When the polarizations are off, the gate 116 is likely to be kept in contact with the gate dielectric 111. When the transistor is biased again, it is likely to adopt the same mode of operation as that in which it had been left before stopping polarizations.

0038On the <figref idref="f0003">figure 3B</figref>, the device is placed in a state of polarization different from that of the rest position and for which the device adopts a first position in which the gate 116 is not in contact with the surface of the gate dielectric layer 111, the gate 116 being maintained at a non-zero distance Δ from the gate dielectric layer 111. For the device to adopt the first position, the piezoelectric means are placed in a suitable state of polarization, a non-zero potential being applied to the electrodes. The suspended gate 116 of the transistor can then be subjected to four forces, a first or electrostatic force F_{electrostatic} due to the potential difference present between the gate and the transistor channel surface, a second force or piezoelectric force F_{piezoelectric}, generated by the potential difference applied between the two electrodes 122, 128 of polarization of the piezoelectric layer, a third force or restoring force F_reminder, corresponding to the stiffness of the mechanical support of the gate 116, that is to say the stiffness of the stack formed of the piezoelectric layer 125 and the electrodes 122, 128, and the layer or insulating elements of support for stacking, a fourth force of molecular bonding or adhesion force F_membership, resulting in particular Van Der Waals forces exerted between the lower face of the gate 116 located opposite the gate dielectric layer 111 and the surface of the gate dielectric layer 111. In the first position, the state of polarization of the electrodes of the actuating means is adapted so that:<maths id="math0001"><math display="block"><mrow><mfenced open="|" close="|"><msub><mi>F</mi><mi mathvariant="italic">electrostatic</mi></msub></mfenced><mo>+</mo><mo>|</mo><msub><mi>F</mi><mi mathvariant="italic">membership</mi></msub><mo>|</mo><mo>&lt;</mo><mo>|</mo><msub><mi>F</mi><mi mathvariant="italic">reminder</mi></msub><mo>|</mo><mo>+</mo><mo>|</mo><msub><mi>F</mi><mi mathvariant="italic">piezoelectric</mi></msub><mo>|</mo></mrow></math><img file="EP2015358A2_D0001.tif" /></maths>

0039A different polarization of the piezoelectric actuating means may allow the latter to be displaced. The fourth force can become significant when Δ is made weak, for example less than 1 nm. A collage (<figref idref="f0004">Figure 4A</figref>) of the gate 116 on the dielectric layer 111 can be realized when the following condition is implemented: <maths id="math0002"><math display="block"><mrow><mfenced open="|" close="|"><msub><mi>F</mi><mi mathvariant="italic">electrostatic</mi></msub></mfenced><mo>+</mo><mo>|</mo><msub><mi>F</mi><mi mathvariant="italic">piezoelectric</mi></msub><mo>|</mo><mo>+</mo><mo>|</mo><msub><mi>F</mi><mi mathvariant="italic">membership</mi></msub><mo>|</mo><mo>></mo><mo>|</mo><msub><mi>F</mi><mi mathvariant="italic">reminder</mi></msub><mo>|</mo></mrow></math><img file="EP2015358A2_D0002.tif" /></maths>

0040A predetermined dimensioning of the elements of the device, and a suitable polarization can make it possible to achieve this condition.

0041In the bonding position, the gate 116 is in contact with the surface of the gate dielectric 111. When the device is polarized, the gate 116 of the transistor is subjected, as a first approximation, to the four forces presented above for the gluing mechanism.

0042A detachment (<figref idref="f0004">Figure 4B</figref>) of the gate 116 is implemented when the following condition is satisfied: <maths id="math0003"><math display="block"><mfenced open="|" close="|"><msub><mi>F</mi><mi mathvariant="italic">piezoelectric</mi></msub><mo>|</mo><mo>+</mo><mo>|</mo><msub><mi>F</mi><mi mathvariant="italic">reminder</mi></msub><mo>|</mo><mo>></mo><mo>|</mo><msub><mi>F</mi><mi mathvariant="italic">electrostatic</mi></msub><mo>|</mo><mo>+</mo><mo>|</mo><msub><mi>F</mi><mi mathvariant="italic">membership</mi></msub></mfenced></math><img file="EP2015358A2_D0003.tif" /></maths>

0043A predetermined dimensioning of the elements of the device and a suitable bias can make it possible to achieve this condition.

0044It may be desired to maintain the operating state of the transistor, even after stopping all polarizations or power supplies, to give the device a non-volatile operation.

0045For this, the gate 116 can be maintained, after stopping the polarizations, in a position in which it was before this stop. When the polarizations are turned off, the gate 116 is subjected only to the restoring forces of the structure and adhesion to the surface of the gate dielectric 111. The piezoelectric and electrostatic forces dependent on the applied potential differences become zero.

0046Two cases of maintaining the position of the gate 116 may for example be made.

0047A first case in which the gate is initially, detached or remote from the gate dielectric 111, and is for example in the first position before extinction of the power supply or polarizations. In this case, after extinction, the adhesion forces are low compared to the restoring forces, which keeps the gate 116 in the rest position (<figref idref="f0005">Figure 5A</figref>). There may be a small displacement of the gate between the first position, when the stack is polarized but kept at a distance from the gate dielectric and the "rest" position for which the polarizations are off. By low displacement is meant a small displacement with respect to the distance Δ0 of rest.

0048A second case in which the gate 116 is initially glued against, or in contact with, the gate dielectric 111 116 before extinguishing the power supply or the polarizations. In this case, after extinction, the adhesion forces are not negligible in the case of the restoring forces (<figref idref="f0005">Figure 5B</figref>). To keep the grid glued without polarization, the following condition is implemented:<maths id="math0004"><math display="block"><mfenced open="|" close="|"><msub><mi>F</mi><mi mathvariant="italic">membership</mi></msub><mo>|</mo><mo>></mo><mo>|</mo><msub><mi>F</mi><mi mathvariant="italic">reminder</mi></msub></mfenced></math><img file="EP2015358A2_D0004.tif" /></maths>

0049A predetermined dimensioning of the elements of the device, in particular a stiffness of the stack and of the piezoelectric layer adapted as well as a distance Δ0 of rest chosen can make it possible to realize this condition. The piezoelectric actuation means and the support elements of the stack have dimensions and a composition adapted to achieve a stiffness at the edge of the stack that allows to fulfill the condition of maintaining the grid in said second case which has just been given. Thus, when the piezoelectric actuation means are not polarized or fed, the gate 116 is likely to remain in its position stuck against the dielectric 111, with the aid of adhesion forces that vary greatly with the distance separating the gate 116 of the gate dielectric 111, more than the restoring forces. The restoring forces may be proportional to this distance while the adhesion forces are inversely proportional to a power of this distance, for example inversely proportional to the cube of this distance for Van der Waals forces.

0050An example of electrical operation of the microelectronic device will now be given in connection with the <figref idref="f0005">Figures 6A-6B</figref> and the <figref idref="f0006">Figure 6C</figref>.

0051Threshold voltage V_T of the transistor can be modulated by varying the insulating thickness between the gate 116 and the channel 105 of the transistor.

0052On the <figref idref="f0005">Figure 6A</figref>, the gate 116 of the transistor is glued against or in contact with the gate dielectric 111. The insulating thickness between the gate 116 and the channel 105 thus corresponds to the thickness e₁ of the gate dielectric layer. In this position, the transistor has a first threshold voltage V_T1.

0053On the <figref idref="f0005">Figure 6B</figref>, the gate 116 of the transistor is located at a distance Δ from the gate dielectric 111 116. The insulating thickness between the gate 116 and the channel 105 corresponds to the thickness of the gate dielectric layer added to a thickness Δ d. air between the gate 116 and the gate dielectric 111. In this position, the transistor has a second threshold voltage V_T2.

0054The transistor may have at least two distinct threshold voltage values:<ul id="ul0004" list-style="dash" compact="compact"><li>a threshold voltage V_T1 low when the grid is in contact with the surface of the gate dielectric (glued grid),</li><li>a threshold voltage V_T2 high when the grid is not in contact with the surface of the gate oxide (open grid).</li></ul>

0055The transistor of the device has a threshold voltage that can be dynamically changed, and have for example a first threshold voltage V_T1 which can for example be weak when the transistor is in the on state and a second threshold voltage V_T2 for example such as V_T2 > V_T1 and which can be high when the transistor is in the off state. The electrical performances of the transistor are thus improved with respect to a conventional MOS transistor of the same dimensions, insofar as with respect to such a transistor, the transistor according to the invention has a current I_WE more important flowing in the channel in the on state, and a current I_OFF channel in the off state, reduced.

0056A characteristic curve representative of the drain current as a function of the potential applied to the gate is given on the <figref idref="f0006">Figure 6C</figref>.

0057A first portion of curve C₁₂ corresponds to a position in which the gate is glued against the gate dielectric 111, while another portion of the curve C₁₁ corresponds to a position in which the grid is detached or in the rest position.

0058Such a device is likely to operate at variable threshold voltage and thus to be able to have a slope below a threshold below the limit of 60mV / dec conventional architectures of MOS transistor single or double grids.

0059An exemplary method for producing a microelectronic device as described above, provided with a transistor comprising a suspended gate and surmounted by piezoelectric actuation means, will now be given in connection with the <figref idref="f0006 f0007 f0008 f0009 f0010">Figures 7A-7J</figref> and <figref idref="f0011 f0012">8A-8E</figref> (the device in progress being represented in a cross-sectional view on the <figref idref="f0006 f0007 f0008 f0009 f0010">Figures 7A-7J</figref> and according to a view from above on the <figref idref="f0011 f0012">Figures 8A-8E</figref>).

0060In this example, the starting material is a semiconductor-on-insulator type substrate, such as an SOI (Silicon On Insulator) substrate. The method according to the invention is not limited to such a substrate and can be adapted for example to an embodiment on a solid substrate or on a constrained substrate. The starting substrate may be formed of a layer 200 of semiconductor material, for example monocrystalline silicon, surmounted by a layer 201 of insulating material, for example silicon oxide, on which a thin layer of material rests. semiconductor, for example monocrystalline silicon, and provided to form an active layer.

0061In the thin layer of semiconductor material is defined, for example by etching, at least one semiconductor zone 202.

0062Subsequently, in this semiconductor zone 202, active source zones 204 and drain zones 206, on either side of a channel zone 205, can be produced.

0063Then, the semiconductor zone 202 is covered with a layer intended to form a gate dielectric zone 211 surmounted by a first sacrificial layer 213. The first sacrificial layer 213 is intended to be removed later in order to disconnect the future transistor gate of the gate dielectric layer 211, and make a gap between this future gate and the grid dielectric zone 211.

0064The gate dielectric zone 211 may for example be based on silicon oxide and produced by thermal oxidation of a silicon layer or by deposition of a dielectric material having a high dielectric constant ("high-k"). Anglo-Saxon terminology) such as HfO₂ or Al₂O₃ or HfSiO_x. The dielectric zone 211 may have a thickness of, for example, between 1 nanometer and 10 nanometers, for example of the order of 2 nanometers.

0065The sacrificial layer 213 is based on a material that can be etched selectively relative to the other materials of the structure. The sacrificial layer 213 is based on a material capable of being etched selectively with respect, in particular, to the dielectric 211 and with respect to the future gate. The choice of the material of the sacrificial layer 213 may also be provided as a function of that of the materials of the piezoelectric layer and support elements of this layer intended to be produced later, so that it can be etched selectively with respect to this layer. piezoelectric and these support elements.

0066The first sacrificial layer 213 may for example be Ge-based or SiGe-based. According to another example, the first sacrificial layer 213 may be based on SiO₂ in the case where the gate dielectric is based on a "high-k" material. The sacrificial layer 213 may have a thickness for example between several nanometers and several tens of nanometers, for example of the order of 4 nanometers (<figref idref="f0006">Figure 7A</figref>).

0067Is then carried out, using deposition steps, lithography and etching, a gate 216 based on at least one gate material, for example metal such as TiN, or semiconductor for example such as polycrystalline silicon, or a stack formed of at least one metal layer and at least one semiconductor layer. The gate 216 may have a thickness for example between 10 nanometers and 1 micrometer, for example of the order of 50 nanometers. The gate 216 may have a critical dimension dc for example between several nanometers and several hundred nanometers, for example of the order of 40 nanometers. (defined on the<figref idref="f0006">Figure 7A</figref> in a direction parallel to the plane [0;<o ostyle="single">i</o>;<o ostyle="single">k</o>] an orthogonal reference [0;<o ostyle="single">i</o>;<o ostyle="single">j</o>;<o ostyle="single">k</o>]).

0068Areas of extension can then be made, for example by ion implantation.

0069Then insulating spacers 217a, 217b are formed on either side of the grid 216, based on an insulating material, for example such as SiO 2₂ or Si₃NOT₄ or a stack of these two materials.

0070The semiconductor zone 202 can then be doped, for example by implantation, so as to produce the source 204 and drain 206 zones.

0071Thus, a structure similar to that of a SOI MOS transistor has been formed, but having a sacrificial layer 213 between the gate dielectric zone 211 and the gate 216 (FIG.<figref idref="f0007">Figure 7B</figref>).

0072The structure is then covered with a second sacrificial layer 219. This second sacrificial layer 219 may be made by deposition and then removed in an area situated above the grid 216. The removal of the second sacrificial layer 219 from above the grid can be performed by planarization CMP (CMP for Chemical Mechanical Planarization) until revealing the upper face of the grid 216. The second sacrificial layer 219 may be based on a material that can be etched selectively relative to the other materials of the structure. The second sacrificial layer 219 may be based on a material that can be etched selectively with respect, in particular, to the gate dielectric 211 and with respect to the future gate. The choice of the material of the second sacrificial layer 219 can also be provided as a function of that of the materials of a piezoelectric layer and of the support elements of this piezoelectric layer intended to be produced later, so that it can be etched selectively with respect to to this piezoelectric layer and these support elements. The second sacrificial layer 219 may for example be based on Si. According to one possibility, the sacrificial layer may be based on the same material as the first sacrificial layer, for example based on SiGe or Ge. The second sacrificial layer 219 may optionally be based on SiO₂ especially in the case where the gate dielectric is based on a "high-k" material.

0073The second sacrificial layer 219 may be based on the same material as the first sacrificial layer 213 (<figref idref="f0007">Figure 7C</figref>).

0074A stack of layers is then deposited from which piezoelectric actuation means are intended to be defined.

0075This stack may be formed of a layer 225 based on a piezoelectric material such as for example AlN, PZT, LiNbO₃ or LiTaO₃, PMN-PT, LiNbO₃, from LiTaO₃ interposed between two conductive layers 222, 228 intended to act as polarization electrodes of the piezoelectric layer 225.

0076The conductive layers 222, 228 may be formed of a metallic material, chosen according to the material used for the piezoelectric layer 225, and which may be, for example, Mo, Ti or Pt. The piezoelectric layer 225 may, for its part, it can be achieved by depositing a piezoelectric material or by transfer of this material on the conductive layer 222, using a gluing mechanism. A transfer advantageously makes it possible to form a layer of monocrystalline piezoelectric material.

0077The choice of the material of the conductive layers 222, 228 and the material of the piezoelectric layer 225 is provided so as to optimize the piezoelectric properties, and in particular the ability of the layer 225 to deform under the action of a voltage. electric imposed by the electrodes, preferably low or the lowest possible.

0078In a case for example where the piezoelectric material of the layer 225 is AlN, the conductive layers 222 and 228 may be based on Mo.

0079The layer of piezoelectric material may have a thickness for example between 100 nanometers and 1 micrometer, for example of the order of 150 nanometers. The conductive layers 222, 228 can have a thickness of between 10 nanometers and 100 nanometers, for example of the order of 10 nanometers.

0080At least one pattern is then produced, for example by photolithography and etching of the stack of layers 222, 225, 228, and of the second sacrificial layer 219, so as to define a block in which, a lower electrode 222a, a block of piezoelectric material 225a on the lower electrode, and an upper electrode 228a on the block 225a of piezoelectric material are made. The formed block may have a rectangular pattern of width W and length L (the length L being defined on the <figref idref="f0007">Figure 7D</figref> in a direction parallel to the vector <o ostyle="single">i</o> orthogonal reference [0;<o ostyle="single">i</o>;<o ostyle="single">j</o>;<o ostyle="single">k</o>]).

0081Then, at least one insulating layer 231 is formed on the structure, for example based on SiO₂ or Si₃NOT₄, or a stack of insulating layers, for example formed of a thin layer based on Si₃NOT₄, covered by a layer of SiO₂.

0082A portion of this insulating layer 231 or this stack is then removed, for example by etching, in an area situated above the upper electrode 228a.

0083The remaining portions of the insulating layer 231 surround the transistor as well as the stack comprising the piezoelectric block 225a and the electrodes 222a, 228a. The remaining portions of the insulating layer 231 thus form a support or a reinforcing element, able to support the stack of layers 222a, 225a, 228a of the piezoelectric actuator. The material of the insulating layer 231 may be chosen to have a rigidity greater than that of the piezoelectric material 225, so as to promote the displacement of the gate induced by the deformation of the piezoelectric layer.

0084We then define (<figref idref="f0008">figures 7E</figref> and <figref idref="f0011">8A</figref>), on either side of the gate of the transistor, for example by photolithography and through the stack of layers 228a, 225a, 222a, sacrificial layers 219, 213, and the gate dielectric zone 211, openings 233, 235, respectively revealing the source zone 204 and the drain zone 206 defined in the semiconductor zone 202. At least one opening 237 is also made through the layers 228a, 225a, 222a so as to reveal the grid 216 or the first conductive layer 222.

0085The openings 233, 235, 237 may be provided with a diameter or critical dimension d1 (defined on the <figref idref="f0008">figure 7F</figref> in a direction parallel to the plane [0;<o ostyle="single">i</o>;<o ostyle="single">k</o>]).

0086Then, the openings 233, 235 and 237 are filled with an insulating material 238, for example SiO 2₂ (<figref idref="f0009">figures 7G</figref>). Then, a chemical mechanical polishing (CMP) of the layer of insulating material 238 can be carried out.

0087In apertures 233, 235, and 237 filled with insulating material 238, holes 243, 245 and 247 of diameter or critical dimension d.sub.2 (defined in FIG. <figref idref="f0009">figure 7H</figref> in a direction parallel to the plane [0;<o ostyle="single">i</o>;<o ostyle="single">k</o>]), holes 243, 245 and 247 respectively reveal the source zone 204, the drain zone 206, and the grid 216 or the first conductive layer 222 (FIG.<figref idref="f0009">Figure 7G</figref>).

0088A hole 249, revealing the upper electrode 228a, is also provided.

0089The holes 243, 245 and 247, 249 are then filled with at least one conductive material, for example a metal such as tungsten, so as to form conductive pads 253, 255 and 257, 259 in the holes. 243, 245 and 247, 249. The conductive pads 253, 255, 257, 259 are respectively in contact with the source zone 204, the drain zone 206, with the gate 216 or with the lower electrode 222a, and with the upper electrode 228a (<figref idref="f0010">figures 7I</figref> and <figref idref="f0011">8C</figref>).

0090At least one opening 261 is then made in the block, passing through the stack 220 and the sacrificial layers 213, 219. The opening 261 may be made, for example by means of photolithography and etching steps (<figref idref="f0012">figure 8D</figref>).

0091Then, a partial or total withdrawal (<figref idref="f0010">figure 7J</figref>) sacrificial layers 213, 219, so as to separate the gate 216 from the gate dielectric 211. The removal of the sacrificial layers 213, 219, can be achieved for example by delocalized plasma etching, the plasma being formed in a given room and relocated in another chamber in which is placed the device comprising the sacrificial layers to be removed.

0092The removal of the first sacrificial layer 213 is performed so as to create a space 270 between the gate 216 and the gate dielectric layer 211. The shrinkage can be achieved by selective etching of the first layer vis-a-vis the grid, the gate dielectric. The shrinkage may for example be achieved by selective etching of a first semiconductive sacrificial layer, for example Si, vis-à-vis a Ti grid, of a SiO-based gate dielectric.₂. The etching may also be selective with respect to spacers and / or support elements, for example when they are based on Si₃NOT₄.

0093The second sacrificial layer 219 can also be removed so as to form a space around or around the grid 216. The shrinkage can be achieved by selective etching of the second layer with respect to the gate, the gate dielectric and support elements.

0094The shrinkage may for example be achieved by selective etching of a first SiGe sacrificial layer, vis-à-vis a Ti grid, of an SiO-based gate dielectric.₂ and spacers and / or Si-based support elements₃NOT₄.

0095In the case where the two sacrificial layers 213 and 219 are based on the same material, the removal of the two sacrificial layers 213 and 219 can be performed at the same time. A withdrawal, possibly total, of the second sacrificial layer 219 can in turn be performed so as to make a cavity 280 around the gate 216. After this step of removing the sacrificial layers 213, 219, the gate 216 is held or attached by its upper face to the lower electrode 222a of the actuator (FIG.<figref idref="f0010">figure 7J</figref>).

0096In the embodiment which has just been given, the upper electrode 228a resting on the piezoelectric layer 225 is not connected or electrically connected to any of the contact pads 253, 255, 257, of source contact, of drain contact , and gate contact 257.

0097If necessary, the upper electrode 228a can be connected or subsequently electrically connected to the source pad 253, or the drain pad 255, during subsequent steps of a process part commonly referred to as "back-end steps" during of which, a plurality of interconnection metal levels of the components of the integrated circuit are produced.

0098According to one possibility, the support layer 231 can be etched again so as to release sides of the stack formed of the electrodes 222a, 228a and the piezoelectric block 225a. In the case where a rectangle pattern has been formed in the stack of layers 222a, 225a, 228a, the etching can be performed to release two sides, for example the two longer sides of the rectangle to allow the layer piezoelectric 225a to deform more easily, under the action of a polarization.

0099On the <figref idref="f0012">figure 8E</figref>the stack formed of the electrodes 222a, 228a and the piezoelectric block 225a is held in suspension above the substrate 200 by means of two insulating elements or support blocks 231b, 231c, insulating formed by etching the insulating layer 231 .

0100A variant of the example of the method which has just been described, and in particular the production of the contact pads, will now be given in connection with the <figref idref="f0013 f0014">Figures 9A-9D</figref>, and <figref idref="f0015">10A-10C</figref> (the device in progress being represented in a cross-sectional view on the <figref idref="f0013 f0014">Figures 9A-9D</figref> and according to a view from above on the <figref idref="f0015">Figures 10A-10C</figref>).

0101For this variant, the same steps are carried out as in the previously described method example until the production of the support layer 231 based on insulating material (up to the <figref idref="f0008">figure 7E</figref> included).

0102Then, on either side of the transistor, for example, photolithography and etching steps are performed through the stack of layers 228a, 225a, 222a, sacrificial layers 219, 213, and the dielectric zone 211. gate, apertures 333, 335, respectively revealing the source zone 204, the drain zone 206 defined in the semiconductor zone 202, and the gate 216. At least one opening 337 is also formed, revealing the grid zone 216 or the first conductive layer 222a. The opening 333 revealing the source zone 204 may be provided with a diameter or a critical dimension greater than that of the other openings 335, 337 (<figref idref="f0015">figure 10A</figref>).

0103The openings 333, 335 and 337 are then filled with an insulating material 238, for example SiO 2₂.

0104In apertures 333, 335, and 337 filled with insulating material 238, holes 343, 345 and 347 are each made with a diameter smaller than that, or with a critical dimension d2 smaller than that of apertures 333, 335 and 337 (<figref idref="f0013">Figures 9A</figref> and <figref idref="f0015">10B</figref>).

0105The mouth 344 is then widened by a hole formed opposite an active zone, for example the mouth 344 of the hole 343 revealing the source zone 204. The mouth of the hole 343 is enlarged so as to reveal a part the upper face of the upper electrode 228a of the piezoelectric actuator. This expansion is carried out so as to maintain an insulating zone 351 or an insulating spacer 351 between the hole 343 and the lower electrode 222a of the actuator.

0106The holes 343, 345 and 347 are then filled with at least one conductive material, for example a metal such as tungsten, so as to form metal studs 353, 355 and 357 in the holes 343, 345. and 347. The metal studs 355 and 357 are respectively in contact with the drain zone, and with the gate 216. The stud 353 formed of the hole 343 with enlarged mouth and filled with metal, is in contact with the upper electrode 228a and the source zone 204 (<figref idref="f0014">Figures 9C</figref> and <figref idref="f0015">10C</figref>).

0107At least one opening is then made, revealing the sacrificial layers 213, 219. The opening may be made so as to pass through the sacrificial layers 213, 219, or alternatively, be made on the periphery of the structure, but in such a way as to reveal the sacrificial layers 213, 219.

0108Then, the sacrificial layers 213, 219 are etched through the opening so as to remove these sacrificial layers 213, 219, and in particular to separate the gate 216 from the gate dielectric 211. A space 270 between the gate 216 and the gate dielectric layer 211 is thus formed. A cavity 280 all around the gate 216 may also be formed following the removal of the second sacrificial layer 219, for example by selective isotropic etching (<figref idref="f0014">Figure 9D</figref>).

0109According to the variant which has just been given, a pad in contact with the source zone 204 and the second conductive layer 222 of the upper electrode 222a has been produced. It is possible, by performing a similar process, to form a pad in contact with the drain zone 206 and the second conductive layer 222 of the upper electrode 222a.

0110Another alternative embodiment of the contact pads, will now be given in connection with the <figref idref="f0016 f0017">Figures 11A-11C</figref>, and <figref idref="f0017">12A-12B</figref> (the device in progress being represented in a cross-sectional view on the <figref idref="f0016 f0017">Figures 11A-11C</figref> and according to a view from above on the <figref idref="f0017">Figures 12A-12B</figref>).

0111For this variant, the same steps as in the previously described process example are carried out until the holes 343, 345 and 347 are made, of smaller diameter d2 than those of the openings 333, 335 and 337.

0112The holes 343, 345 and 347 are then filled with a metal, for example tungsten, so as to form conductive pads 453, 455 and 457 in the holes 343, 345 and 347. The conductive pads 453 , 455 and 457, are respectively in contact with the source zone 204, the drain zone 206, and with the gate 216 or the first electrode 222 (FIG.<figref idref="f0016">Figures 11A</figref> and <figref idref="f0017">12A</figref>).

0113Near the stud 453 in contact with the source zone 204, an additional hole 444 is then made in the insulating material 239 so as to reveal a portion of the upper electrode 228a and flanks of the stud 453. The additional hole 444 is made so that an insulating zone 459 is kept between the stud 453 and the lower electrode 222a (<figref idref="f0016">Figure 11B</figref>).

0114Then, the hole 444 is filled with a metal, for example such as tungsten, so as to form a metal zone 454 for extending the stud 453, in contact with the upper electrode 228a of the metal. piezoelectric actuator (<figref idref="f0017">Figures 11C and 12B</figref>).

0115Then, the steps as described above, of making at least one opening in the structure, are performed to access the sacrificial layers 213, 219.

0116Then, through said opening, the sacrificial layers 213, 219 are etched so as to effect removal of these sacrificial layers 213, 219, and to separate the gate 216 from the gate dielectric 211.

0117The second sacrificial layer 219 can also be removed so as to form a space around or around the grid 216. In the case where the two sacrificial layers 213 and 219 are based on the same material, the removal of the two layers sacrificial 213 and 219 can be realized at the same time.

0118After this step of removing the sacrificial layers, the gate 216 is maintained or attached by its upper face to the lower electrode 222a of the actuator.

0119According to the variant which has just been given, a pad in contact with the source zone 204 and the second conductive layer 222 of the upper electrode 222a has been produced. It is possible, by performing a similar process, to form a pad in contact with the drain zone 206 and the second conductive layer 222 of the upper electrode 222a.

0120A first example of a random access memory cell 500 according to the invention is illustrated in FIG. <figref idref="f0018">figure 13</figref>.

0121This memory cell 500 is a SRAM static memory cell type 6T, that is to say provided with 6 transistors. The cell 500 comprises a first plurality of transistors forming a first inverter and a second inverter, connected in a flip-flop configuration or commonly called "flip-flop". The first TL load transistors_T and conduction TD_T form the first inverter of the flip-flop, while the second load transistors TL_F and conduction TD_F form the second inverter of the rocker.

0122The first plurality of transistors may be formed of a first load transistor TL_T, as well as a second TL load transistor_F. TL load transistors_T and TL_F, can be, for example of type P. The cell 500 can also be provided with a first conduction transistor TD_T and a second conduction transistor TD_F, for example of type N.

0123TL transistors_T, TL_F, TD_T, TD_F of the cell forming the flip-flop are similar to that previously described in connection with the <figref idref="f0001 f0002">Figures 2A-2B</figref>, provided with a mobile suspended grid and piezoelectric actuation means for moving the grid.

0124The cell also includes TA access transistors_T and your_F, for example of the NMOS type.

0125The connections in the cell may be similar to those of a conventional 6T memory cell.

0126In this example, the gate of the second load transistor TL_F is connected to that of the second conduction transistor TD_F, and at a first storage node T of the cell 500. The gate of the first load transistor TL_T is connected to that of the first conduction transistor TD_T, and to a second storage node F.

0127The sources of TL load transistors_T, TL_F, they can be connected to each other and to a supply voltage VDD, whereas the drain of the first load transistor TL_T is connected to the first node T, the drain of the second load transistor TL_F being connected to the second node F.

0128TL load transistors_T and TL_F, connected to the supply voltage VDD, have in this example the function of maintaining a logic level '1', for example equal to a voltage VDD, at one or the other of the storage nodes T or F, by example at the first node T, depending on the logic value stored in the cell 500. TD conduction transistors_T and TD_F, connected to the GND cell mass, have the role of maintaining a logic level '0', equal to GND, to one or the other of the storage nodes according to the stored logic value.

0129Both TA access transistors_T and your_F are provided, depending on the manner in which they are biased, to allow access to the storage node potentials during a read or write cycle, and to block access to the cell 300, when the cell 300 is in an information retention mode.

0130The first TA access transistor_T and the second TA access transistor_F each comprise a grid connected to a word line WL. The source of the first access transistor TA_T is connected to a first bit line BL_T, while the source of the second TA access transistor_F is connected to a second bit line BL_F. The drain of the first access transistor TA_T is in turn connected to the first storage node T, while the drain of the second access transistor TA_F is connected to the second storage node F.

0131Actuation of the suspended grid of TD transistors_T, TD_F, TL_T and TL_F by means of piezoelectric means, it is possible to modulate their threshold voltage V_T. As has been described previously, the piezoelectric actuation means make it possible to give the cell 500 a non-volatile operation, insofar as the movable gate actuated by such means is able to remain in position, even after extinction of the supply voltage VDD. Thus, after switching off the power supply of the cell 500, the latter can be reset or reset when it is restarted in the state in which it was before extinguishing.

0132With regard to the connections between the respective piezoelectric actuator and the respective electrodes, TD transistors_T, TD_F, TL_T and TL_Ftwo configurations can be implemented.

0133According to a first configuration (<figref idref="f0018">figure 14A</figref>), the upper electrode 128 of the piezoelectric actuating means and the source 104 of the transistor are connected together.

0134On the <figref idref="f0019">Figure 14B</figref>, TD transistors_T, TD_F, TL_T and TL_F, a cell 600 similar to cell 500 have this first configuration.

0135According to a second configuration (<figref idref="f0019">figure 15A</figref>), the upper electrode 128 of the piezoelectric actuating means and the drain 106 of the transistor are connected together.

0136On the <figref idref="f0020">figure 15B</figref>, a cell 700 similar to cell 500, comprises TD transistors_T, TD_F, TL_T and TL_F, adopting the second configuration.

0137In the second configuration, it is advantageous to obtain a modulation or a variation of the threshold voltage of the larger transistors.

0138For cell 600 with TD transistors_T, TD_F, TL_T and TL_F, being in the first configuration, the potential difference between gate and source for the first TD conduction transistor_T can be 0V while the potential difference between gate and the source of the second conduction transistor TD_F is + VDD, which gives a total potential difference of 1xVDD.

0139As shown on the <figref idref="f0020">figure 15B</figref>in the cell 700 having transistors adopting the second configuration, the potential difference between gate and drain for the first conduction transistor TD_T may be de -VDD while the potential difference between gate and the drain of the second conduction transistor TD_F is + VDD, which makes it possible to obtain a total potential difference between the two 2xVDD conduction transistors, which is greater than in the first configuration. It is the same for the TL load transistors_T and TL_F.

0140An example of operation of the cell 700 will be given in connection with the <figref idref="f0020">figures 16</figref> and <figref idref="f0021">17</figref>.

0141TD transistors_T, TD_F, TL_T, TL_F, are connected in the second configuration with their respective piezoelectric actuators. The respective threshold voltage of the transistors is capable of being modulated according to the mode, retention or reading or writing, in which the cell 700 is located.

0142In retention mode, the word line WL can be maintained at ground potential GND. TA access transistors_T and your_F are in a locked state and the information stored in the cell 700 is isolated from the bit lines BL_T and BL_F.

0143The cell 700 is configured so that in the retention mode, the threshold voltage of the first conduction transistor TD_T is increased by + ΔVT_NOT with respect to a threshold voltage value VT_NOT, while the threshold voltage of the second load transistor TL_F is increased by + Δ | VT_P| with respect to a threshold voltage value | VT_P|, VT_NOT and VT_P corresponding to the threshold voltage of the PMOS and NMOS transistors when the gate is bonded to the gate dielectric layer, the threshold voltages then being minimal. The cell 700 is also configured so that in the retention mode, the threshold voltage of the second conduction transistor TO_F is equal to a threshold voltage value VT_NOT, while the threshold voltage of the first load transistor TL_T is equal to a threshold voltage value | VT_P|.

0144This configuration of the threshold voltages of the transistors TD_T, TD_F, TL_T, TL_F when cell 700 is in retention mode, is shown on the <figref idref="f0020">figure 16</figref>. Such a configuration makes it possible to obtain an increased retention stability RNM of the cell 700 and, on the other hand, reduced leakage currents. Increasing the threshold voltage of the first TD conduction transistor_T and the second load transistor TL_F allows respectively to reduce their current below the threshold and to limit the discharge of the storage node T and the load of the storage node F, in a case for example where it is desired to maintain a logic level '1' in the first node T and a logic level '0' in the second node.

0145The low threshold voltage of the first load transistor TL_T and the second conduction transistor TD_F allow to increase their conduction current, which reinforces the charge of the node T and the discharge of the node F.

0146Prior to a read access of the cell 700, the bit lines BL_T and BL_F can be charged to an equal potential VDD. Then in read mode, the word line WL is biased to the potential VDD, to allow access to the storage nodes T and F of the cell 700. The stability of the cell 700 in read mode depends in particular on the value of the potential the storage node F which is at logic level '0', for example the second node F. This voltage should preferably remain lower than the switching voltage of the inverter connected to the logic level storage node '1', for example the first node T. This condition is related to the voltage divider between the second bit line BL_F and the GND mass of the cell 700, formed by the second access transistor TA_F and the second conduction transistor TD_F connected to the logical level node '0'.

0147To improve the reading noise margin of the cell 700, this cell is implemented so that the linear current flowing through the second conduction transistor TD_F is greater than the saturation current of the second access transistor TA_F.

0148The current gain ratio, between the conduction and access transistors, is typically of the order of 2. For transistors provided with a grid having a critical dimension of less than 65 nm, this ratio tends to 3. The transistors of FIG. TD conduction_T and TD_F, and TL charge_T and TL_F, with a movable gate and piezoelectric actuation of the gate allow to give the memory cell 700 a current gain ratio greater than that of a SRAM 6T cell according to the prior art and of the same size. The mechanical deformation of the piezoelectric material of TD conduction transistors_T and TD_F and TL charge_T and TL_F, makes it possible to modulate their threshold voltage favorably, so as to reinforce the stability of the cell in reading (SNM).

0149As for the previously described retention mode, in reading mode, the threshold voltage of the first conduction transistor TD_T and the second load transistor TL_F is increased, which allows, respectively, to limit the discharge of the node T and to reduce the load of the node F. The threshold voltage of the first load transistor TL_T and that of the second conduction transistor TD_F are also weak, which increases their conduction current and enhance the load of the first storage node T and the discharge of the second storage node F, in a case for example where the first node T is intended to be at a logic level '1' while the node F is at a logical level '0'. With regard to the current gain ratio, between the conduction and access transistors, the latter increases with respect to the conventional case, where the stored information does not affect the threshold voltage of the transistors by increasing the conduction current of the second conduction transistor of the transistor TD_F related to the decrease of its tension.

0150Prior to writing, one of the two bit lines, for example the second bit line BL_F can be at a potential VDD, while the complementary bit line BL_F can be biased to GND ground potential. Next, the word line WL is biased to a VDD potential in order to write to the cell 700.

0151The switching of the logic information contained in the memory cell 700 is accompanied by a variation of the threshold voltages of the TD conduction transistors._T and TD_F and TL charge_T and TL_F, as illustrated on <figref idref="f0021">Figures 17A-17B</figref>.

0152The cell 700 is configured so that when it goes into a write mode, the threshold voltage of the second conduction transistor TD_F is likely to rise, and go from VT_NOT at (VT_NOT + ΔVT_NOT), while the threshold voltage of the first load transistor TL_T is likely to increase by + Δ | VT_P| with respect to a threshold voltage value | VT_P|. In this case the TD transistors_F and TL_T change from a glued grid state to a peeled grid state

0153The cell 700 is also configured so that in the retention mode, the threshold voltage of the first conduction transistor TD_T is likely to decrease, and go from (VT_NOT + ΔVT_NOT) to (VT_NOT), while the threshold voltage of the second load transistor TL_F is decreased by + Δ | VT_P| with respect to a threshold voltage value (| VT_P| + Δ | VT_P|) In this case, TD transistors_T and TL_F move from a peeled grid state to a glued grid state.

0154This modulation of the threshold voltage is relative to the polarization change of the piezoelectric actuators associated with each of the transistors TL_T, TL_F, TD_T, TD_F. These polarization changes will result in a complementary deformation of the piezoelectric materials, modulating the potential difference between the gate and the channel surface of the transistors.

0155A mode of "off", that is to say when the supply voltage of the cell 700 is cut, does not prevent to keep the information stored in the nodes T and F. Even if these nodes lose their potential after stopping power supplies, the information will be preserved thanks to the non-volatile operation of TL transistors_T, TL_F, TD_T and TD_F as described above in connection with the <figref idref="f0003">figures 3</figref>, <figref idref="f0004">4</figref>, <figref idref="f0005">5</figref>, <figref idref="f0005 f0006">6</figref>.

0156In "start" mode, the memory cell 700 is powered up. The storage nodes of the cell T and F switch voltage according to the last stored state, which is maintained by a suitable difference between the restoring forces on the layers of piezoelectric materials and the bonding forces at the interface grid / gate dielectric TL transistors_T, TL_F, TD_T and TD_F.

0157The <figref idref="f0021">figure 18</figref> illustrates a start-up phase of the memory cell 700. In this figure the curve C0 represents the evolution of the supply potential, while the curves C1 and C2 respectively represent the evolution of the potential at the first node T and the evolution the potential at the second node F. Before a time t0, the cell 700 is not powered. Then at time t0, the cell 700 is fed again (curve C0 arriving gradually at the value VDD).

0158The potential of the first node T finds a value for example equal to VDD corresponding to a logic state "1" (increasing curve C1 reaching the value VDD) while the potential of the second node F finds a value for example equal to GND or 0 volts corresponding to a logic state '0' (curve C2).

0159The information which was present in the nodes T and F before stopping the power supply of the cell 700, is preserved insofar as the nodes T and F find, without a write operation, being necessary. potential they had prior to extinction.

0160A table below gives an example of comparison of the electrical characteristics of the cell 700 described above and a standard 6T SRAM cell.<tables id="tabl0001" num="0001"><table frame="all"><tgroup cols="3"><colspec colnum="1" colname="col1" colwidth="20mm" /><colspec colnum="2" colname="col2" colwidth="32mm" /><colspec colnum="3" colname="col3" colwidth="20mm" /><thead><row><entry align="center" valign="top">cells</entry><entry align="center" valign="top">6T standard cell</entry><entry align="center" valign="top">Cell 700</entry></row></thead><tbody><row><entry align="center">I_OFF (PA)</entry><entry align="center">44</entry><entry align="center">19.4</entry></row><row><entry align="center">I_PG (PA)</entry><entry align="center">7.6</entry><entry align="center">7.6 6</entry></row><row><entry align="center">I_CELL (UA)</entry><entry align="center">42</entry><entry align="center">43</entry></row><row><entry align="center">SNM (mV)</entry><entry align="center">187</entry><entry align="center"><b>237</b></entry></row></tbody></tgroup></table></tables>

0161The results were obtained with grids of critical dimension of the order of 65 nm, cells 700 and 6T standard having the same dimensioning.

0162A modulation of the threshold voltage of TD conduction transistors_T, TD_F, and TL charge_T and TL_F as implemented in the cell 700, makes it possible to improve the SNM static noise margin of the order of 50mV, ie by more than 25%, and to reduce the leakage currents by a factor greater than 2.2 , compared to the standard 6T cell. The current I_CELL of cell 700 is also improved over the cell of the prior art.

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