Enhancement of electron and hole mobilities in 110 under biaxial compressive strain

The present invention relates to semiconductor materials having enhanced electron and hole mobilities, and more particularly, to semiconductor materials that include a silicon (Si)-containing layer having enhanced electron and hole mobilities. The present invention also provides a method of forming such semiconductor materials.

For more than three decades, the continued miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicted for three decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor (MOS) transistors are beginning to reach their traditional scaling limits [A concise summary of near-term and long-term challenges to continued CMOS scaling can be found in the "Grand Challenges" section of the 2002 Update of the International Technology Roadmap for Semiconductors (ITRS). A very thorough review of the device, material, circuit, and systems limits can be found in <nplcit id="ncit0001" npl-type="s"><text>Proc. IEEE, Vol. 89, No. 3, March 2001</text></nplcit>, a special issue dedicated to the limits of semiconductor technology].

Since it has become increasingly difficult to improve MOSFET and therefore complementary metal oxide semiconductor (CMOS) circuit performance through continued miniaturization, methods for improving performance without scaling have become critical. One general approach for doing this is to increase carrier (electron and/or hole) mobilities. This can by done by either: (1) introducing an appropriate strain into the Si lattice; (2) by building MOSFETs on Si surfaces that are oriented in directions different than the conventional &lt;100&gt; Si; or (3) a combination of (1) and (2).

As far as approach (1) is concerned, several methods such as, for example, strained Si on a relaxed SiGe buffer layer and strained Si on relaxed SiGe on insulator have been described for producing Si under biaxial tensile strain. This has been shown to significantly enhance electron mobilities, but requires high Ge fractions to only mildly enhance hole mobilities in &lt;100&gt; Si.

In terms of approach (2), it is well known that hole mobilities in &lt;110&gt; Si are more than twice that of conventional &lt;100&gt; Si. However, electron mobilities in relaxed (unstrained) &lt;110&gt; Si are degraded by about a factor of two compared to the &lt;100&gt; case. This has led to the invention of a somewhat complex "hybrid" scheme for integrating pFETs built in &lt;110&gt; Si and nFETs built in &lt;100&gt; Si [<nplcit id="ncit0002" npl-type="s"><text>M. Yang et al., IEDM Technical Digest, pg. 453, 2003</text></nplcit>]. Although this hybrid approach benefits pFETs significantly, it typically has no benefit for nFETs. Examples of conventional semiconductor structures are described in <patcit id="pcit0001" dnum="US2003227036A1"><text>US 2003/227036A1</text></patcit> and <patcit id="pcit0002" dnum="WO03105189A"><text>WO 03/105189A</text></patcit>.

There is a significant advantage to an approach that can significantly enhance both electron and hole mobilities, while at the same time avoiding the complexities of hybrid crystalline orientation schemes.

A preferred embodiment of the present invention provides a semiconductor material that has enhanced carrier mobilities that comprises a Si-containing layer having a &lt;110&gt; crystal orientation that is under a biaxial compressive strain. The term "biaxial compressive strain" is used herein to describe the net stress caused by longitudinal compressive stress and lateral (or transverse) compressive stress that is induced in the plane of the Si-containing layer during the manufacturing of the semiconductor material.

In accordance with the present invention, there is now provided a semiconductor material comprising a silicon-containing layer having a &lt;110&gt; crystal orientation, said silicon-containing layer is under a biaxial compressive strain characterised by the silicon-containing layer overlying a substrate having a coefficient of thermal expansion that is greater than the coefficient of thermal expansion of silicon.

Viewing the present invention from another aspect, there is now provided a method for forming a silicon-containing semiconductor material comprising the steps of: providing a silicon-containing layer; bonding the silicon-containing layer to a substrate having a coefficient of thermal expansion that is greater than the coefficient of thermal expansion of silicon; during the bonding, heating the silicon-containing layer and the substrate to an elevated temperature; and thereafter, cooling the bonded silicon-containing layer and substrate to create a biaxial compressive strain in said silicon-containing layer.

The Si-containing layer is preferably a crystalline Si-containing layer comprising Si or SiGe.

The creating a biaxial compressive strain preferably comprises forming at least one porous Si layer having an uppermost surface in said &lt;110&gt; Si-containing layer; annealing the uppermost surface to create a non-porous surface layer; forming a crystalline epitaxial Si-containing layer having a &lt;110&gt; orientation on the non-porous surface layer thereby forming a transfer structure; bonding the transfer structure to a material that has a higher coefficient of thermal expansion than Si at a temperature that is elevated above the ultimate device operating temperature to provide a bonded structure; cooling the bonded structure so that a mechanically weak interface forms at said at least one porous Si layer thereby cleaving said bonded structure at said interface; and removing remaining portions of the least one porous Si layer from the cleaved structure. The at least one porous Si layer preferably comprises an electrolytic anodization process. The anodization process preferably includes utilizing an HF-containing solution. The annealing is preferably performed at a temperature from about 900° to about 1150°C. The forming said crystalline epitaxial Si-containing layer may comprise an epitaxial growth process. The epitaxial growth process preferably comprises an UHVCVD process. The method may further comprise forming an oxide layer on said crystalline Si-containing layer prior to bonding.

The bonding preferably comprises bringing that transfer structure and said material together, optionally applying an external force, and heating. The heating is preferably performed at a temperature from about 400° to about 1000°C. The cooling is preferably performed at a rate of about 50°C/min or less. The removing preferably comprises a wet etching process. The method may further comprise smoothing said crystalline epitaxial Si-containing that is under biaxial compressive strain by annealing in a H₂-containing ambient at a temperature of from about 850° to about 1100°C.

Viewing the present invention from yet another aspect, there is now provided a method for forming a silicon-containing semiconductor material comprising the steps of: forming at least one porous Si layer having an uppermost surface in a &lt;110&gt; Si-containing substrate; annealing the uppermost surface to create a non-porous surface layer; forming a crystalline epitaxial Si-containing layer having a &lt;110&gt; orientation on the non-porous surface layer thereby forming a transfer structure; bonding the transfer structure to a material that has a higher coefficient of thermal expansion than Si at a temperature that is elevated above the ultimate device operating temperature to provide a bonded structure; cooling the bonded structure so that a mechanically weak interface forms at said at least one porous Si layer thereby cleaving said bonded structure at said interface; and removing remaining portions of the least one porous Si layer from the cleaved structure so as to provide a semiconductor material that includes at least the crystalline epitaxial Si-containing layer having a &lt;110&gt; orientation atop said material, said crystalline epitaxial Si-containing layer is under biaxial compressive strain.

An example of a semiconductor material embodying the present invention that includes a &lt;110&gt; Si-containing layer with biaxial compressive strain provides enhanced mobilities for both nMOS and pMOS. Another example of the present invention relates to a method of forming such a semiconductor material. Specifically and in broad terms, a method embodying the present invention includes the steps of providing a silicon-containing &lt;110&gt; layer; and creating a biaxial compressive strain in the silicon-containing &lt;110&gt; layer. In one embodiment, the Si-containing layer having the &lt;110&gt; orientation and biaxial compressive strain is created by a method that includes the steps of: forming at least one porous Si layer having an uppermost surface in a &lt;110&gt; Si-containing substrate; annealing the uppermost surface so as to create a non-porous surface layer; forming a crystalline epitaxial Si-containing layer having a &lt;110&gt; orientation on the non-porous surface layer thereby forming a transfer structure; bonding the transfer structure to a material that has a higher coefficient of thermal expansion than Si at a temperature that is elevated above the ultimate device operating temperature to provide a bonded structure; cooling the bonded structure so that a mechanically weak interface forms at said at least one porous Si layer thereby cleaving said bonded structure at said interface; and removing remaining portions of the least one porous Si layer from the cleaved structure to provide a semiconductor material that includes at least the crystalline epitaxial Si-containing layer having a &lt;110&gt; orientation atop said material, said crystalline epitaxial Si-containing layer is under biaxial compressive strain.

Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: <ul id="ul0001" list-style="none"><li><figref idref="f0001">FIGS. 1A-1B</figref> are graphs of the electron mobility (cm²/Vs) vs. electron concentration (cm^-2) for a &lt;100&gt; Si substrate having a conventional orientation and current flow direction (<figref idref="f0001">FIG. 1A</figref>), and for a Si substrate material having a &lt;110&gt; orientation with a 1% biaxial compressive strain (<figref idref="f0001">FIG. 1B</figref>); other strains are also shown.</li><li><figref idref="f0002">FIGS. 2A-2B</figref> are graphs of the hole mobility (cm²/Vs) vs. hole concentration (cm^-2) for a &lt;100&gt; Si substrate having a conventional orientation and current flow direction (<figref idref="f0002">FIG. 2A</figref>), and for a Si substrate material having a &lt;110&gt; orientation with a 1 % biaxial compressive strain (<figref idref="f0002">FIG. 2B</figref>); other strains are also shown.</li><li><figref idref="f0003 f0004">FIGS. 3A-3E</figref> are pictorial representations (through cross sectional views) illustrating the basic processing steps employed in a first embodiment of the present invention.</li><li><figref idref="f0005">FIGS. 4A-4C</figref> are pictorial representations (through cross sectional views) illustrating the basic processing steps employed in a process in which both an at least one multiply connected trench isolation region and a compressive liner are employed to create strain in a Si-containing layer, note that the &lt;110&gt; direction is perpendicular to the Si-containing substrate shown. (This process is given for illustrative purposes only and does not form part of the invention.)</li><li><figref idref="f0006">FIG. 5</figref> shows the strain effect on CMOS performance.</li><li><figref idref="f0006">FIGS. 6A-6B</figref> are graphs illustrating the STI mechanical stress effect on drive current with different crystal orientation and different nitride liner stress. All the devices have narrow widths (120 nm) and nominal (45 nm) length; <figref idref="f0006">FIG. 6A</figref> is for nMOS devices, and <figref idref="f0006">FIG. 6B</figref> is for pMOS devices.</li><li><figref idref="f0006">FIGS. 7A-7B</figref> are graphs illustrating the STI mechanical stress effect of devices with different widths, different crystal orientation and different nitride liner stress; <figref idref="f0006">FIG. 7A</figref> is for nMOS devices, and <figref idref="f0006">FIG. 7B</figref> is for pMOS devices.</li></ul>

A preferred embodiment of the present invention, provides a semiconductor material comprising a Si-containing layer having a &lt;110&gt; crystal orientation and biaxial compressive strain and a method of forming the same, will now be described in greater detail by referring to the accompanying drawings.

The applicants have determined through numerical calculations that when a significant (greater than about 0.2%, preferably greater than about 0.5%) biaxial compressive strain is introduced in a &lt;110&gt; Si-containing layer, both the electron and hole mobilities exceed those in the conventional unstrained &lt;100&gt; Si case. The % strain is defined herein as the percentage change in the crystalline lattice constant of a material in a given direction. The significant advantages of combining both biaxial compressive strain with a &lt;110&gt; Si-containing layer has not previously been recognized in the art.

The results of the above calculations, which have been determined by computing the carrier mobilities using the Kubo-Greenwood formula (which results from a solution of the linearized Boltzmann transport equation) for carriers in inversion layers is shown in <figref idref="f0001">FIGS. 1A-1B</figref> and <figref idref="f0002">FIGS. 2A-2B</figref>. The sub-band structure has been calculated using a model band structure consisting of six ellipsoidal conduction-band valleys (with first-order nonparabolic corrections following Kane) for nFETs, or by solving the six-band k*p Hamiltonian (3 bands times 2 spin states) with spin-orbit interaction for the pFETs. In the case of nFETs, the effect of strain has been accounted for by allowing for the known degeneracy-breaking and energetic shifts of the conduction ellipsoids and the (linear) changes of the effective masses. A full strain Hamiltonian has been added to the total (k*p + spin-orbit) Hamiltonian in the case of nFETs. The carrier momentum relaxation rates due to (intraband, intra- and inter-subband) scattering with acoustic phonons (in the elastic, equipartition approximation, valid for temperatures larger than about 150K) and to inelastic, anisotropic scattering with optical phonons (intervalley for nFETs, intra- and interband for pFETS) have been evaluated numerically using Fermi Golden Rule and deformation potentials obtained from previous bulk calculations (<nplcit id="ncit0003" npl-type="s"><text>MV Fischetti and SE Laux, J. Appl. Phys. 80, 2234 (1996</text></nplcit>)). Scattering with roughness at the Si-SiO₂ interface has been treated according to the full Ando's model and using a rigorous multi-subband model for dielectric screening.

<figref idref="f0001">FIG. 1A</figref> shows the calculated electron mobility in the inversion layer of nFETs (as a function of carrier sheet density) for a more common Si &lt;100&gt; wafer surface along the [110] crystallographic direction, usually employed in present VLSI technology. The application of 1% biaxial tensile strain shows the well-known enhancement of the electron mobility at low electron densities. By contrast, <figref idref="f0001">FIG. 1B</figref> shows that even moderate amounts of compressive strain (0.5% or larger) for &lt;110&gt; surfaces boosts the electron mobility (along the [110] direction) above and beyond the values attained at all densities for the relaxed or strained &lt;100&gt; surface.

As shown by comparing <figref idref="f0001">FIG. 1A and FIG. 1B</figref>, the application of 1% compressive strain on &lt;110&gt; Si surfaces enhances the electron mobility by a factor of approximately 2 above the mobility obtained for &lt;100&gt; relaxed (or with 1% compressive or tensile strain) Si.

<figref idref="f0002">FIGS. 2A-2B</figref> present analogous information regarding the calculated hole mobility for &lt;100&gt; (<figref idref="f0002">FIG. 2A</figref>) and &lt;110&gt; (<figref idref="f0002">FIG. 2B</figref>) Si surfaces. As can be seen in these drawings, the application of 1% compressive strain on &lt;110&gt; surfaces boosts the hole mobility along the [110] direction by a factor of approximately 3 over the hole mobility for the relaxed &lt;100&gt; Si surface.

These enhanced mobilities obtained using the inventive Si substrate simultaneously enable higher performance nFETs and pFETs, and avoid the complexities of a hybrid crystalline orientation approach. The following description, with reference to <figref idref="f0003 f0004">FIGS. 3A-3E</figref> illustrate one method that can be employed in the present invention through which a biaxial compressive strain (greater than about 0.2%, preferably greater than about 0.5%) can be introduced into a &lt;110&gt; Si-containing layer in order to achieve these significantly higher carrier mobilities.

<figref idref="f0003">FIG. 3A</figref> illustrates an initial structure that can be used in forming the inventive substrate material of the present invention. Specifically, the initial structure shown in <figref idref="f0003">FIG. 3A</figref> includes a &lt;110&gt; Si-containing substrate 10 having at least one porous Si layer 12 formed on the surface of Si-containing substrate 10. The at least one porous Si layer 12 has an uppermost surface layer 13. In the drawings, two porous Si layers 12A and 12B are formed. Despite showing the presence of two porous Si layers 12A and 12B, the present invention works equally well when only one porous Si layer or more than two porous Si layers are formed.

The term "Si-containing substrate" is used in the present invention to denote a semiconductor material that includes Si. Illustrative examples of such Si-containing materials that can be employed as substrate 10 include bulk Si, SiGe having a Ge content of about 25% or less, silicon-on-insulators (SOIs) and SiGe-on-insulators. The substrates can be doped or undoped.

The at least one porous Si layer is formed in the present invention by utilizing an electrolytic anodization process that is capable of converting a surface portion of the &lt;110&gt; Si-containing substrate 10 into a porous Si layer. The anodization process is performed by immersing the &lt;110&gt; Si-containing substrate 10 into an HF-containing solution while an electrical bias is applied to the &lt;110&gt; Si-containing substrate 10 with respect to an electrode also placed in the HF-containing solution. In such a process, the &lt;110&gt; Si-containing substrate 10 itself typically serves as the positive electrode of the electrochemical cell, while another semiconducting material such as Si, or a metal is employed as the negative electrode.

The anodization process used in forming the porous Si layers can also be referred to as an anodic etching process. The porous Si layers created using the anodization process are mechanically weak as compared to the remainder of the Si-containing substrate 10, yet the porous Si layers preserve the crystalline quality and orientation of the Si-containing substrate 10.

It should be noted that when more than one porous Si layer 12 is formed, the other porous layers can have the same or different pore morphology. Porous Si layers containing different pore morphologies can be formed in the present invention by changing the current flow conditions during the anodization process.

In general, the HF anodization converts a surface region of the Si-containing substrate 10 into porous Si. The rate of formation and the nature of the porous Si so-formed (porosity and microstructure) are determined by both the material properties as well as the reaction conditions of the anodization process itself (current density, bias, illumination and additives in the HF-containing solution). Generally, the porous Si layers 12A and 12B formed in the present invention have a porosity of about 0.1% or higher.

The thickness of each porous Si layer 12 may vary depending on the anodization conditions employed. Typically, the thickness of each porous Si layer 12 formed in the present invention is from about 100 nm to about several microns, with a thickness from about 300 to about 500 nm being more typical. Each porous Si layer 12 may have the same or different thickness that is within the ranges mentioned above.

The term "HF-containing solution" includes concentrated HF (49%), a mixture of HF and water, a mixture of HF and a monohydric alcohol such as methanol, ethanol, propanol, etc, or HF mixed with at least one conventional surfactant. The amount of surfactant that is present in the HF solution is typically from about 1 to about 50%, based on 49% HF.

The anodization process is performed using a constant current source that operates at a current density from about 0.05 to about 50 milliAmps/cm². A light source may be optionally used to illuminate the sample. More preferably, the anodization process of the present invention is employed using a constant current source operating at a current density from about 0.1 to about 5 milliAmps/cm².

The anodization process is typically performed at room temperature or at a temperature that is slightly elevated from room temperature may be used. Following the anodization process, the structure is typically rinsed with deionized water and dried.

Following the anodization process in which at least one porous Si layer 12 is formed in the &lt;110&gt; Si-containing substrate 10, the structure shown in <figref idref="f0003">FIG. 3A</figref> is subjected to an annealing process that is performed under conditions (temperature and ambient) that are effective in sealing the pores at the uppermost porous Si layer. In the present case shown, the annealing step would seal the pores at the surface of porous Si layer 12B. The annealing step performed at this point of the present invention causes surface diffusion of silicon atoms thereby creating a thin skin of non-porous Si. The thin skin of non-porous Si is designated by reference numeral 14 in <figref idref="f0003">FIG. 3B</figref>. The skin layer of non-porous Si formed at this point of the present invention generally has a thickness from about 5 to about 80 nm, with a thickness from about 10 to about 30 nm being more typical.

The annealing step that is used to seal the pores of the uppermost porous Si layer 13 is performed at high annealing temperatures. By "high annealing temperatures" it is meant annealing temperatures from about 900° to about 1150°C. More preferably, the annealing step is performed at a temperature from about 1000° to about 1100°C. The annealing may be performed using a single ramp up rate. Alternatively, the annealing may be performed using varies ramp-up rates in which optional soak cycles can be employed.

In addition to being performed at high temperatures, the annealing step of the present invention, which is used to seal the pores of the uppermost porous Si layer 13, is also performed in the presence of a hydrogen-containing ambient. Suitable hydrogen-containing ambient that can be employed includes molecular or atomic hydrogen. In some embodiments, the hydrogen-containing ambient may be admixed with an inert gas such as He, Ar, N₂ or Xe. In some preferred embodiments of the present invention, the annealing ambient is H₂.

After sealing the pores at the top of the porous Si layer using the aforementioned high temperature annealing step, an epitaxial layer of a Si-containing material, i.e., Si or SiGe, is formed on the thin skinned Si layer 14. The epitaxial Si-containing layer is a crystalline material that has the same crystal orientation as that of the substrate 10. The epitaxial Si-containing layer is formed by employing an epitaxial growth process that is well known to those skilled in the art. For example, the epitaxial Si-containing layer can be formed by an ultra-high vacuum chemical vapor deposition (UHVCVD) process or any other like technique.

The epitaxial Si-containing layer formed atop the thin skinned non-porous Si surface 14 is designed in <figref idref="f0003">FIG. 3B</figref> by reference numeral 16. The thickness of the epitaxial Si-containing layer 16 formed at this point of the present invention may vary depending on the process used in forming the same. Typically, the epitaxial Si-containing layer 16 has a thickness from about 10 to about 100 nm, with a thickness from about 10 to about 30 nm being more typical.

It is noted that the above discussion regarding Si formation, pore sealing and epi growth is well known to one skilled in the art. The above processing steps are based on the well-known ELTRAN process for SOI wafer manufacture (see <nplcit id="ncit0004" npl-type="b"><text>T. Yonehara and K. Sakaguchi, "ELTRAN (SOI Epi Water) Technology," in The Science of SOI, Chapter 2, Section 2, (4/19/2000</text></nplcit>).

In some embodiments of the present invention, an optional oxide layer 18 (see <figref idref="f0003">FIG. 3B</figref>) can be formed on the epitaxial Si-containing layer 16. The optional oxide layer 18 can be formed by a conventional oxidation process. Alternatively, the optional oxide layer 18 can be formed by a conventional deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), chemical solution deposition, and the like. The thickness of the optional oxide layer 18 formed at this point of the present invention may vary depending on the process used in forming the same. Typically, the optional oxide layer 18 has a thickness from about 10 to about 200 nm, with a thickness from about 20 to about 100 nm being more typical.

The structure shown in <figref idref="f0003">FIG. 3B</figref>, with or without the optional oxide layer 18, is employed in the present invention as a transfer structure that will be bonded to a substrate 20 at elevated temperature. <figref idref="f0004">FIG. 3C</figref> shows substrate 20 which can be bonded to the optional oxide layer 18 or the epitaxial Si-containing layer 16 of the transfer structure. This bonding is achieved by first positioning the two structures as shown in <figref idref="f0004">FIG. 3C</figref>, bringing them in contact with each other, optionally applying an external force to the contacted structures, and heating the two structures.

The substrate 20 includes any material that has a coefficient of thermal expansion that is significantly greater than the Si-containing substrate 10. That is, substrate 20 includes any material having a coefficient of thermal expansion á that is significantly greater than about 2.8 ppm/°C. Illustrative examples of suitable materials for substrate 20 include sapphire (á=8.8 ppm/°C), germanium (á=5.8 ppm/°C at room temperature, which increased significantly with temperature) and calcium fluoride (á=19 ppm/°C).

In some embodiments not shown, an optional oxide layer can be formed on the surface of the substrate 20 prior to bonding. This optional oxide layer can be formed as described above and it alone or together with the optional oxide layer 18 of the transfer structure can be used to facilitate wafer bonding.

The heating step used to bond the two structures together is performed at an elevated temperature that ranges from about 400° to about 1000°C. More preferably, the bonding is performed at a temperature from about 750° to about 925°C. The heating step can be performed using a single ramp-up rate or various ramp-up rates with optional soaking cycles can be employed. In some embodiments, the heating step used to bond the two structures together can be performed in an inert ambient including, for example, He, Ar, N₂, Xe and mixtures therefore. Other ambients can be also be used in bonding the two structures together.

Upon cooling down from the high wafer bonding temperature, substrate 20 will contract more than Si-containing substrate 10 due to its higher coefficient of thermal expansion. This will create significant compressive stress in the Si-containing layer 16 above the optional oxide layer 18 (which will remain rigid at these temperatures) and in the porous Si layers. The cooling down is typically performed using a cool down rate of about 50°C/min or less.

Due to the considerable interfacial stress at the boundary between the porous layers, the bonded wafer will preferentially cleave along the interface of the two porous layers. In <figref idref="f0004">FIG. 3D</figref>, reference numeral 22 denotes the interface in which cleavage occurs. With one porous layer, the cleavage will occur within the porous layer or at the edge or the porous layer. Without the porous Si layer, either substrate 20 or the Si-containing substrate 10 will fracture due to the strong bonding and the mismatch in coefficients of thermal expansion. This cleavage is well-known to one skilled in the art of ELTRAN wafer fabrication.

Due to its extremely high surface-to-volume ratio, the remaining porous Si layer(s) can be removed with high selectivity (greater than 1000:1) to the epitaxial Si-containing layer 16 utilizing a wet etching process. In particular, the remaining porous Si layer not cleaved during the cool down process can be removed using a wet etch process in which the chemical etchant is a solution of hydrofluoric acid, nitric acid and acetic acid. Other chemical etchants that can be employed in selectively removing the remaining porous layers include a mixture of HF, H₂O₂, and H₂O. The selective removing of the remaining porous Si layers exposes a surface of epitaxial Si-containing layer 16.

<figref idref="f0004">FIG. 3E</figref> shows the structure that is formed after cleaving and removing of the remaining porous Si layers. The structure shown in <figref idref="f0004">FIG. 3E</figref> includes substrate 20, optional oxide layer 18 and epitaxial Si-containing layer 16 having a &lt;110&gt; orientation that is under biaxial compressive strain. It is noted that the structure shown in <figref idref="f0004">FIG. 3E</figref> is an SOI like structure since the epitaxial Si-containing &lt;110&gt; layer 16 is located directly upon an insulator, e.g., oxide layer 18.

The newly exposed Si-containing surface of layer 16 can be smoothed at this point of the present invention utilizing an annealing process that is carried out in an H₂-containing ambient. This annealing step is performed at a temperature from about 850° to about 1100°C, with a temperature from about 900° to about 950° being more preferred. Care should be taken during this annealing step so as not to relax the compressively strained Si-containing layer 16 by flowing the oxide 18 with an excessive (&gt;1100°C) thermal treatment. Chemical mechanical polishing (CMP) can also be used.

The thin Si-containing layer 16 is analogous to that formed in strained Si directly on insulator (SSDOI) but with a strain of the opposite sign. The device scaling advantages that can be derived from the thin nature of Si-containing layer 16 would be similar to that of SSDOI, but with the potential for even higher carrier mobility enhancements due to the sign of the strained and the orientation of the wafer.

In embodiments in which the optional oxide layer 18 is not present, the thin Si-containing layer 16 would be formed directly upon substrate 20. Note that since layer 16 is epitaxially grown it has the same crystallographic orientation as substrate 10 which is &lt;110&gt;. In the embodiment in which substrate 20 is sapphire, the method of the present invention can lead to a biaxial compressive strain up to 0.6%. In embodiments in which substrate 20 is calcium fluoride, the method of the present invention can lead to a biaxial compressive strain up to 1.0%. When calcium fluoride is employed as substrate 20, care must be taken to minimize exposure to water vapor at elevated temperatures of greater than about 600°C.

After forming the structure shown in <figref idref="f0004">FIG. 3E</figref>, various CMOS devices, including nFETS, pFETs and a combination thereof, can be formed directly on the Si-containing layer 16. The CMOS devices are formed utilizing conventional processes that are well known to those skilled in the art.

<figref idref="f0006">FIGS. 6A-6B</figref> show the change of saturation current of narrow width devices. For devices on (100) surface, the nMOS current will be degraded by a large S/D overhang region and improved by a smaller S/D overhang region. This threshold region from mobility degradation to improvement indicates the effect from uni-axial to biaxial stress effect. Devices on (110) wafers have higher sensitivity than those on (110) wafers, and the improvement can be as high as 155%. This suggests that the longitudinal compressive stress plus the lateral stress, or simply biaxial compressive stress, can enhance the nMOS current. The nitride liner can also modulate the biaxial stress effect and is more effective on the devices built on the (110) wafer and narrow width devices (<figref idref="f0006">FIGS. 7A-7B). FIGS. 7A-7B</figref> show that nMOS has current improvement instead of degradation with small S/D overhang region when the width is narrower than 0.2 mm. Similarly, pMOS will have higher mobility change for narrower width devices compared to long width devices. Both uni-axial longitudinal and biaxial stress can improve pMOS performance.