Nova Patents
EP1586991A2

Processor with plurality of register banks

Abstract

The present invention provides a processor including: a plurality of memory banks (310-313); a read-address generation circuit (330) for supplying a read address to each of the memory banks (310-313) on the basis of a read-register specification (1231) and a read-register scan direction (1232); a read control circuit (360) for executing control to rearrange a plurality of pieces of read data, which is read out from the memory banks (310-313) in accordance with the read addresses, on the basis of the read-register specification (1231) and a read-register displacement (1233); and a processing unit for carrying out a plurality of operations on the rearranged pieces of read data output by the read control circuit.

EP1586991A2, drawing sheet 1
Sheet 1 of 49

Term

Term ended

Projected expiry passed 15 April 2025, 1.4 years ago.

  1. Priority
  2. Filed
  3. Published
  4. Projected expiry
  5. Today

10 claims: 4 independent, 6 dependent

  1. 1
    A processor comprising:a plurality of memory banks;(310-313) a read-address generation circuit (330) for supplying a read address to each of said memory banks on the basis of a read-register specification (1231) and a read-register scan direction (1232);a read control circuit (360) for executing control to rearrange a plurality of pieces of read data, which is read out from said memory banks (310-313) in accordance with said read addresses, on the basis of said read-register specification (1231) and a read-register displacement (1233);and a processing unit (140) for carrying out a plurality of operations on said rearranged pieces of read data output by said read control circuit (360).
  2. 4
    A processor comprising:a plurality of memory banks (310-313);a write-address generation circuit (320) for supplying a write address to each of said memory banks on the basis of a write-register specification (1221) and a write-register scan direction (1222);a processing unit (140) for carrying out a plurality of operations on a plurality of pieces of data and outputting a plurality of pieces of write data as a result of said operations;and a write control circuit (350) for executing control to rearrange said pieces of write data output by said processing unit (140) on the basis of said write-register specification (1221), a write-register displacement (1223) and the number of write-register elements and supplying said rearranged pieces of write data to said memory banks.
  3. 7
    A processor comprising:a plurality of memory banks (310-313);a read-address generation circuit (330) for supplying a read address to each of said memory banks on the basis of a read-register specification (1231) and a read-register scan direction (1232);a read control circuit (360) for executing control to rearrange a plurality of pieces of read data, which is read out from said memory banks (310-313) in accordance with said read addresses, on the basis of said read-register specification (1231) and a read-register displacement (1233);a processing unit (140) for carrying out a plurality of operations on said rearranged pieces of read data output by said read control circuit (360) and outputting a plurality of pieces of write data as a result of said operations;a write-address generation circuit (320) for supplying a write address to each of said memory banks on the basis of a write-register specification (1221) and a write-register scan direction (1222);and a write control circuit (350) for executing control to rearrange said pieces of write data output by said processing unit (140) on the basis of said write-register specification (1221), a write-register displacement and the number of write-register elements and supplying said rearranged pieces of write data to said memory banks.
  4. 10
    A processor comprising:an instruction decoder (120) for decoding an instruction included in a program;a plurality of memory banks (310-313);a read-address generation circuit (330) for supplying a read address to each of said memory banks on the basis of instruction-decoding results generated by said instruction decoder (120) as results including a read-register specification (1231) and a read-register scan direction (1232);a read control circuit (360) for executing control to rearrange a plurality of pieces of read data, which is read out from said memory banks (310-313) in accordance with said read addresses, on the basis of instruction-decoding results generated by said instruction decoder (120) as results including said read-register specification (1231) and a read-register displacement (1233);a processing unit (140) for carrying out a plurality of operations on said rearranged pieces of read data output by said read control circuit (360) and outputting a plurality of pieces of write data as a result of said operations;a write-address generation circuit (320) for supplying a write address to each of said memory banks on the basis of instruction-decoding results generated by said instruction decoder (120) as results including a write-register specification (1221) and a write-register scan direction (1222);and a write control circuit (350) for executing control to rearrange said pieces of write data output by said processing unit (140) on the basis of instruction-decoding results generated by said instruction decoder (120) as results including said write-register specification (1221), a write-register displacement (1223) and the number of write-register elements and supplying said rearranged pieces of write data to said memory banks.
Independent claims4