Ceramic substrate incorporating an ESD protection for a light emitting diode
12 claims: 2 independent, 10 dependent
- 1A device comprising:a ceramic substrate having a top surface and a bottom surface, the top surface having at least one metal electrode for electrical connection to an electrode of an overlying semiconductor device, the ceramic substrate comprises a first area comprising a first metal oxide, the first metal oxide forming a metal oxide varistor that provides electrostatic discharge or ESD protection of a semiconductor device mounted over a top surface of the ceramic substrate;CHARACTERIZED IN THAT the ceramic substrate further comprising a second area comprising a ceramic second material that does not contain any first metal oxide, the second area not forming a varistor;wherein the first metal oxide comprises zinc oxide, and wherein the zinc oxide is located only around at least a portion of a periphery of the ceramic substrate and the second area is located at the central portion of the ceramic substrate;metal pads on a top surface of the ceramic substrate for connection to the semiconductor device;metal electrodes on a bottom surface for electrical connection to a printed circuit board;and metal vias through the ceramic substrate for electrically connecting the metal pads to the metal electrodes on a bottom surface.
- 2The device of Claim 1, wherein the zinc oxide is located on at least a portion of a top or bottom surface of the ceramic second material around at least a portion of a periphery of the ceramic substrate.
- 3The device of Claim 1, wherein the zinc oxide comprises a majority of the material in the ceramic substrate.
- 4The device of Claim 1, wherein the varistor comprises ceramic grains, the varistor further comprises a plurality of metal layers sandwiching the ceramic grains, the metal layers being electrically connected to exposed substrate electrodes, the ceramic grains providing a low resistance path between the metal layers when an ESD voltage is applied across the metal layers.
- 5The device of Claim 1, wherein the varistor comprises ceramic grains, the varistor further comprising multiple overlying metal layers with the ceramic grains between the metal layers, the metal layers being electrically connected to metal electrodes on the substrate.
- 6The device of Claim 1 further comprising a light emitting diode (LED) chip mounted on the top surface of the substrate and being protected from ESD by the varistor.
- 7The device of Claim 1 wherein the varistor forms part of a heat conduction path between the semiconductor device and a printed circuit board over which the substrate is mounted.
- 8The device of Claim 1 wherein the semiconductor device comprises a semiconductor chip directly affixed to the top surface of the ceramic substrate.
- 9A device comprising a ceramic substrate having a top surface and a bottom surface, the top surface having at least one metal electrode for electrical connection to an electrode of an overlying semiconductor device, the ceramic substrate comprises a first area comprising a first metal oxide, the first metal oxide forming a metal oxide varistor that provides electrostatic discharge or ESD protection of a semiconductor device mounted over a top surface of the ceramic substrate;CHARACTERIZED IN THAT the ceramic substrate further comprising a second area comprising a ceramic second material that does not contain any first metal oxide, the second area not forming a varistor;wherein the first metal oxide comprises zinc oxide, and wherein the zinc oxide forms only a central portion of the ceramic substrate, and a second area surrounds the zinc oxide around a periphery of the ceramic substrate, wherein the second material comprises one of aluminum oxide, aluminum nitride, silicon carbide, and boron nitride.
- 10The device of Claim 9 comprising metal pads on a top surface of the ceramic substrate, as metal electrodes for connection to the semiconductor device, and further metal electrodes on a bottom surface of the ceramic substrate for electrical connection to a printed circuit board.
- 11The device of Claim 10 further comprising metal vias through the ceramic substrate for electrically connecting the metal pads to the metal electrodes.
- 12The device of Claim 10 wherein the metal pads are electrically connected to the metal electrodes by metal portions over a periphery of the ceramic substrate.
Independent claims12
40 paragraphs in 5 sections, as filed
FIELD OF INVENTION
0001This invention relates to electrostatic discharge (ESD) protection of electronic devices and, more particularly, to ESD protection for a semiconductor chip (e.g., a light emitting diode) mounted on a ceramic substrate.
BACKGROUND
0002<figref idref="f0001">Fig. 1</figref> is a cross-sectional view of a prior art light emitting diode (LED) package 10. Package 10 contains an LED chip 12 having cathode and anode contacts coupled, via metal interconnects 18, to metal pads 14 on a ceramic substrate 16. Metal vias 20 extend through substrate 16 and contact backside metal pads 22. The LED chip is encapsulated by epoxy 23. Package 10 is typically solder-mounted onto a printed circuit board or incorporated into another package. Such other package typically includes a lens, reflective walls, a base, and leads. The various metal interconnects in combination with the ceramic substrate 16 conduct heat from the LED chip 12 to the printed circuit board, which may include an additional heat sink.
0003LEDs are well known and are formed from semiconductor materials on a substrate. The LED chip 12 substrate material may be a semiconductor, a conductor, or an insulator.
0004LEDs can be damaged by high voltages from ESD. It is common to provide ESD protection for an LED, such as providing a separate ESD protection circuit in the LED package or on the printed circuit board. Providing a separate ESD protection circuit in the LED package may increase the size of the package and/or reduce the light-emitting area of the chip 12. Forming the ESD protection circuitry on the PC board or in the package also adds complexity in the manufacture of the PC board or package and thus adds cost to the circuit.
0005What is desirable is a technique for providing ESD protection without the need for forming ESD protection circuitry on the LED chip or as a separate element on the PC board or in the package.
SUMMARY
0006The invention relates to a device as defined in claims 1 and 9.
0007A metal oxide varistor comprising one or more zinc oxide layers is formed integral to a ceramic substrate. The portion of the ceramic substrate that is not the varistor may be typically formed of aluminum oxide, aluminum nitride, silicon carbide, or boron nitride. Metal oxide varistors are commonly used for transient voltage suppression. The fabrication techniques for metal oxide varistors are compatible with those used to form ceramic substrates.
0008Accordingly, an ESD protection circuit is provided for an LED chip, or any other type of semiconductor chip, without the need for forming the ESD protection circuitry on the chip or providing a separate ESD protection circuit in the package or external to the package.
0009As further prior art, <patcit id="pcit0001" dnum="US4506285A"><text>US4506285</text></patcit> discloses a homogeneous substrate body consisting of a high-resistivity zinc oxide mixture. The substrate body is subjected to selective doping to form varistor areas. The non-doped portions remain highly resistive. Moreover, <patcit id="pcit0002" dnum="US3743897A"><text>US3743897</text></patcit> discloses a discrete electronic circuit module comprising laterally spaced electrodes shunted by a metal oxide varistor. Finally, <patcit id="pcit0003" dnum="US5889308A"><text>US5889308</text></patcit> discloses a semiconductor device comprising a chip electrically connected to I/O pins and a varistor functioning as a substrate for mounting the chip and shunting the chip between the pins.
BRIEF DESCRIPTION OF THE DRAWINGS
0010<ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001">Fig. 1</figref> is a cross-sectional view of a prior art surface-mounted LED package.</li><li><figref idref="f0001">Fig. 2</figref> is a cross-sectional view of a typical metal oxide varistor comprising zinc oxide grains.</li><li><figref idref="f0002">Fig. 3</figref> is a cross-sectional view of an LED package incorporating a metal oxide varistor as an ESD protection circuit in the central portion of the ceramic substrate.</li><li><figref idref="f0002">Fig. 4</figref> is a cross-sectional view of another embodiment of an LED package where the varistor forms almost the entire ceramic substrate.</li><li><figref idref="f0003">Fig. 5</figref> is a cross-sectional view of an LED package where the LED chip electrodes are connected with wires to a ceramic substrate incorporating a metal oxide varistor.</li><li><figref idref="f0003">Fig. 6</figref> is a cross-sectional view of another embodiment of an LED package where the ceramic substrate incorporates a metal oxide varistor around a periphery of the substrate.</li><li><figref idref="f0004">Fig. 7</figref> is a top-down view of the structure of <figref idref="f0003">Fig. 6</figref>.</li><li><figref idref="f0004">Fig. 8</figref> is a cross-sectional view of another embodiment of an LED package where the substrate incorporates a zinc oxide varistor as a top layer of the substrate and where the zinc oxide is sandwiched between two varistor electrodes.</li><li><figref idref="f0005">Fig. 9</figref> is a cross-sectional view of another embodiment of an LED package where the substrate incorporates a zinc oxide varistor as a top layer of the substrate and where the varistor electrodes are formed on a top surface of the zinc oxide layer.</li><li><figref idref="f0005">Fig. 10</figref> is a cross-sectional view of another embodiment of an LED package where the substrate incorporates a zinc oxide varistor as a top layer of the substrate along the outer portions of the substrate.</li></ul>
DETAILED DESCRIPTION
0011Ceramic substrates are commonly used to provide a hermetic seal, electrical insulation, mechanical stability, and a conductive heat path for integrated circuits. Ceramic substrates are easy to form by mixing ceramic powder in a binder and casting it into the desired form. The ceramic grains may also be sintered under pressure to bind the grains together. Suitable metal patterns are then deposited on the formed ceramic substrate. Ceramic substrates typically comprise aluminum oxide, aluminum nitride, silicon carbide, or boron nitride particles.
0012ESD protection circuitry generally operates to create a low resistance path between its terminals when a high voltage is applied across its terminals. There are many types of ESD protection circuits. One such ESD protection circuit is a metal oxide varistor. When a power surge or voltage spike is sensed, the varistor's resistance rapidly decreases, creating an instant shunt path, thereby preventing the current spike from being discharged through the protected components. A varistor acts similarly to back-to-back zener diodes.
0013<figref idref="f0001">Fig. 2</figref> is a cross-section of a simple metal oxide varistor comprising zinc oxide grains 24 in a binder 26 sandwiched between two electrodes 28. The varistor is typically formed by mixing the zinc oxide grains with a binder and heating the grains under pressure to form a structure of conductive zinc oxide grains surrounded by electrically insulating barriers, creating varistor-like behavior. The number of grain-boundary interfaces between conducting electrodes determines the breakdown voltage of the device. High voltage applications require many grains between electrodes, while low voltage applications require few grains between the electrodes to establish the appropriate breakdown voltage. Varistors may be a single layer between electrodes or may be multiple layers, where each layer is sandwiched between opposing electrodes. The formation of zinc oxide varistors is well known.
0014The processing of these metal oxide varistors is compatible with the processing of standard ceramic substrates used for semiconductor chip packaging since the metal oxide is a ceramic. We use this compatibility to integrate the metal oxide varistor for ESD protection into the standard ceramic packaging. The range of integration ranges from the ceramic substrate having only a small portion forming the zinc oxide varistor to the substrate being completely formed by the zinc oxide varistor.
0015The same or similar elements in the various figures are assigned the same numeral.
0016<figref idref="f0002">Fig. 3</figref> is a cross-sectional view of an LED package 30 where a central portion of the substrate 32 is formed of doped zinc oxide 34 having metal layers 36 forming partially overlapping electrodes. The doping may be cobalt. The varistor structure may be formed by depositing (e.g., evaporating or sputtering) or laminating thin metal films upon layers of the zinc oxide grains in a binder and then using heat and pressure to form a stacked laminated structure. The varistor becomes a monolithic block during the heating cycle, providing uniform energy dissipation in a small volume.
0017The varistor portion of the substrate is surrounded by a conventional aluminum oxide, aluminum nitride, silicon carbide, or boron nitride ceramic substrate portion 40 for mechanical stability, hermetic sealing, and other properties. The ceramic substrate portion 40 may be formed by placing the varistor portion in a mold with aluminum oxide, aluminum nitride, silicon carbide, or boron nitride grains, then sintering the structure. Other techniques may be used.
0018The varistor portion can be made any size and thickness and may be completely surrounded (including the top and bottom surfaces) by the aluminum oxide, aluminum nitride, silicon carbide, or boron nitride ceramic substrate portion or have any or all of its sides exposed if the varistor provides the desired properties for the substrate.
0019A metallization step forms a metal via 42 extending from a top metal pad 14 to a bottom metal pad 22. The via 42 contacts the various varistor metal layers 36. The openings for the metal via may be formed during the molding process or may be drilled or etched.
0020The various heating, pressure, metal deposition, and other processes for forming the varistor and the aluminum oxide, aluminum nitride, silicon carbide, or boron nitride ceramic substrate are compatible. The zinc oxide varistor may be first formed, followed by forming the ceramic substrate around the varistor, followed by a metallization step. Or, the ceramic substrate may be first formed followed by forming the varistor. Or, the varistor and ceramic substrate can be formed at the same time. The same heating steps can be performed on both structures.
0021Solder or gold interconnects 18 are then provided over the metal pads 14. These interconnects may be solder balls, solder paste, stud-bumps, or a plated or otherwise deposited layer. In one embodiment, the surface mounted LED chip 12 is then mounted so that its bottom electrodes align with the solder interconnects, and the structure is heated to melt the interconnects and form an electrical and structural bond between the LED chip 12, the varistor/substrate, and the backside metal pads 22. In another embodiment, for bonding the LED chip 12 to the pads 14 through the use of gold interconnects, thermocompression bonding or thermosonic bonding would typically be used. An LED chip having both contacts on the bottom side is sometimes referred to as a flip chip.
0022The LED chip 12 is encapsulated using silicon or epoxy 23 with an optional phosphor powder incorporated into the encapsulation material if desirable for a particular light output.
0023The heat-sinking of the LED chip 12 occurs through the combination of the metal, the varistor/substrate, and the PC board.
0024Any voltage surge applied to a backside pad 22 will be shorted across pads 22 by the reduced resistance of the varistor so as to shunt the current away from the LED chip 12.
0025<figref idref="f0002">Fig. 4</figref> is cross-sectional view of an illustrative example where the entire ceramic substrate is a varistor 50 formed of doped zinc oxide 52 and metal layers 54. The varistor 50 is at least partially surrounded by wrap-around metallization 56, which provides mechanical stability, heat conductivity, and enhanced electrical properties. In the embodiment of <figref idref="f0002">Fig. 4</figref>, no through-metallization is required since the varistor metal layers 54 extend to the edge of the ceramic substrate.
0026<figref idref="f0003">Fig. 5</figref> is a cross-section of another embodiment of an LED package similar to that of <figref idref="f0002">Fig. 3</figref> except that the LED chip 60 is not a flip chip but has its contacts on a top surface, which are connected via wires 62 to the pads 14 of the ceramic substrate. The LED chip 60 is attached to a metal pad of the ceramic substrate by solder or die attaches epoxy 63.
0027In the embodiment of <figref idref="f0003">Fig. 5</figref>, a reflector 64 surrounds the LED chip 60 to reflect light through the top surface of the package. The reflective walls may be a refractive interface between two materials, a refractive index step from one encapsulant to another or to air, or a reflective metal slope. The reflective walls may also be formed by the ceramic material. For example, aluminum oxide is white and can thus act as a reflector and a diffuser. A molded lens 66 is formed over the LED chip 60.
0028<figref idref="f0003">Fig. 6</figref> is a cross-sectional view of another embodiment of the invention where the varistor 70 is formed along at least a portion of the outer surface of the aluminum oxide, aluminum nitride, silicon carbide, or boron nitride ceramic substrate 72. The varistor portion of the substrate may be formed along any portion of the aluminum oxide, aluminum nitride, silicon carbide, or boron nitride substrate. The metal layers 54 in the varistor alternately contact the two metal vias 42. Additional vias may be provided as desired.
0029<figref idref="f0004">Fig. 7</figref> is a top-down view of the structure of <figref idref="f0003">Fig. 6</figref> showing that the varistor 70 portion completely surrounds the outer perimeter of the aluminum oxide, aluminum nitride, silicon carbide, or boron nitride substrate 72. Also shown are metal interconnects 18 for the anode and cathode terminals of the LED chip 12 coupled to metal pads 14. Four contacts are used for reproducible orientation of the chip 12 on the substrate.
0030<figref idref="f0004">Fig. 8</figref> is a cross-section of an illustrative example where an aluminum nitride, aluminum oxide, silicon carbide, or boron nitride ceramic substrate 74 portion has formed on top of it a zinc oxide varistor 76 having a bottom metal layer 78 and an upper metal layer 80. Metal layers 78 and 80 are electrically coupled to contacts on the LED chip 12 and to the bottom metal pads 22. The varistor presents a low resistance path between metal layers 78 and 80 when a voltage surge is applied across metal pads 22. The varistor could also be formed on the bottom of the substrate.
0031The embodiment of <figref idref="f0004">Fig. 8</figref> is simple to form because the zinc oxide material is a single layer formed on top of the aluminum oxide, aluminum nitride, silicon carbide, or boron nitride substrate 74. The zinc oxide varistor may form any portion of the top or bottom surface of the ceramic substrate. The ceramic substrate 74 portion may be a conventional rectangular substrate. If desirable, additional metal layers may be interdigitated within the zinc oxide layer.
0032<figref idref="f0005">Fig. 9</figref> illustrates an illustrative example, similar to <figref idref="f0004">Fig. 8</figref>, except that the metal layers 84 and 86 for the varistor 76 are formed on an upper surface of the zinc oxide layer so the varistor breaks down across the top surface between the ends of the two metal layers. A large breakdown voltage may be achieved with a thin zinc oxide layer. Another advantage of the structure of <figref idref="f0005">Fig. 9</figref> is that the metal can be applied after the substrate has been completely manufactured such as by screen printing and firing. The varistor may also be formed on the bottom surface of the substrate.
0033<figref idref="f0005">Fig. 10</figref> illustrates another embodiment of the invention where the varistor 90 is formed on a top surface of the aluminum oxide, aluminum nitride, silicon carbide, or boron nitride ceramic substrate portion only near the edge of the substrate. The varistor may be formed along any number of sides of the substrate. The metal layer portions 92 are deposited on top of the ceramic substrate 74, and the varistor material is then formed over the metal layer portions 92. In one embodiment, the varistor material on the left side of <figref idref="f0005">Fig. 10</figref> is continuous with the varistor material on the right side of <figref idref="f0005">Fig. 10</figref>, and the varistor breaks down between the two metal layer portions 92. In another embodiment, other electrode metal layer(s) for the varistor may be formed over the varistor material or may be formed as interdigitated metal layers in the varistor material so the varistor breaks down vertically instead of horizontally.
0034The varistor portion of <figref idref="f0005">Fig. 10</figref> may also be formed on a bottom surface of the substrate.
0035The various packages described herein may be incorporated into another package. Such other package will typically include a lens, reflective walls, a base, and leads for connection to a PC board. Alternatively, the ceramic substrate incorporating the varistor may be directly attached to the PC board. Additionally, the LED chip may be directly mounted on a submount, such as a semiconductor chip with conductive traces and active components, and the submount is then mounted to the ceramic substrate incorporating the varistor.
0036The patterning of the metal layers contacting the zinc oxide may be used to select the desired breakdown voltage of the varistor for any of the embodiments described herein. The zinc oxide grains and other properties of the zinc oxide layer may also be adjusted to achieve a desired breakdown voltage.
0037Although the ceramic substrate incorporating a metal oxide varistor has been shown for supporting and protecting an LED chip, the ceramic substrate may be used to protect any type of chip, such as a conventional integrated circuit chip. Various forms of the varistor may be incorporated using any pattern of electrodes and any shape of the varistor, using up any substrate volume. Multiple varistors can be connected in series and/or parallel.
0038Although a varistor comprising zinc oxide has been described, varistors may be formed of other metal oxides or a combination of such oxides with zinc oxide. Examples of other oxides include Sb<sub>2</sub>O<sub>3</sub>, Bi<sub>2</sub>O<sub>3</sub>, CoO, MnO, and Cr<sub>2</sub>O<sub>3</sub>. Metal oxide varistors are described in more detail in the publication, "<nplcit id="ncit0001" npl-type="s"><text>The Physics of Metal Oxide Varistors," by Levinson and Philipp, Journal of Applied Physics, Volume 46, No. 3, March 1975</text></nplcit>. Those skilled in the art of manufacturing ceramic substrates will be able to form any of the embodiments described herein without undue experimentation since the methods of forming aluminum oxide, aluminum nitride, silicon carbide, and boron nitride substrates and metal oxide varistors are well known.
0039Further information regarding metal oxide varistors is described in the article entitled "<nplcit id="ncit0002" npl-type="s"><text>Improved Metal Oxide Varistor Packaging Technology for Transient Voltage Surge Suppressers (TVSS)," by Drabkin</text></nplcit> et al.
0040Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the scope of the inventive concepts described herein. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.
Contents5
5 sheets
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Every citation, both ways
| Document | Relation | Office |
|---|---|---|
| US3725836A | Cites | United States of America |
| US3743897A | Cites | United States of America |
| US4506285A | Cites | United States of America |
| US5235310A | Cites | United States of America |
| US5889308A | Cites | United States of America |
| US2002179914A1 | Cites | United States of America |
11 members in 4 offices
Priority claims2
| Document | Office | Kind | Date |
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| 787657 | United States of America | – | |
| 78765704 | United States of America | A |
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| Document | Office | Kind | |
|---|---|---|---|
| US2005184387A1 | United States of America | A1 | |
| JP2005244220A | Japan | A | |
| EP1580809A2 | European Patent Office (EPO) | A2 | |
| TW200541108A | Taiwan Province of China | A | |
| US7279724B2 | United States of America | B2 | |
| US2007297108A1 | United States of America | A1 | |
| EP1580809A3 | European Patent Office (EPO) | A3 | |
| US7768754B2 | United States of America | B2 | |
| TWI377692B | Taiwan Province of China | B | |
| EP1580809B1This record | European Patent Office (EPO) | B1 | |
| JP5698424B2 | Japan | B2 |
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Numbers
- Publication
- 1580809
- Application
- 51008993
Titles3
- German
- Keramisches Substrat beinhaltend einen ESD-Schutz für eine Leuchtdiode
- English
- Ceramic substrate incorporating an ESD protection for a light emitting diode
- French
- Substrate en céramique incorporant une protection ESD pour une diode émettrice de lumière
Classification
- CPC, 16
- H10W90/00
- H01C7/112
- H05K1/0259
- Y10T29/49147
- Y10T29/4913
- Y10T29/49171
- Y10T29/49144
- H10H20/8506
- H10W42/60
- H10W90/734
- H10W72/07251
- H10W72/20
- H10W90/726
- H10W90/754
- H10W72/884
- H10W74/00
- IPC, 6
- H01L25 07
- H01L25 16
- H01C7 112
- H10D62 86
- H01L23 60
- H01L33 48
Designated states1
- Contracting states, 1
- Türkiye
