EP1580809A2

Ceramic substrate incorporating an ESD protection for a light emitting diode

Abstract

A device comprising: A ceramic substrate (48) having a top surface and a bottom surface, the top surface having at least one metal electrode (14) for electrical connection to an electrode of an overlying semiconductor device (60), the ceramic substrate (40) comprising a metal oxide varistor that provides electrostatic discharge (ESD) protection of a semiconductor device mounted over a top surface of the ceramic substrate.

EP1580809A2, drawing sheet 1
Sheet 1 of 6

Term

Term ended

Projected expiry passed 9 February 2025, 1.6 years ago.

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  2. Filed
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21 claims: 2 independent, 19 dependent

  1. 1
    A device comprising:a ceramic substrate having a top surface and a bottom surface, the top surface having at least one metal electrode for electrical connection to an electrode of an overlying semiconductor device, the ceramic substrate comprising a metal oxide varistor that provides electrostatic discharge (ESD) protection of a semiconductor device mounted over a top surface of the ceramic substrate.
  2. 2
    The device of Claim 1 wherein the varistor comprises zinc oxide, and wherein the zinc oxide forms only a central portion of the ceramic substrate.
  3. 3
    The device of Claim 1 wherein the varistor comprises zinc oxide, and wherein the zinc oxide is located only around at least a portion of a periphery of the ceramic substrate.
  4. 4
    The device of Claim 1 wherein the varistor comprises zinc oxide, and wherein the zinc oxide is located on at least a portion of a top or bottom surface of the ceramic substrate that does not form the varistor.
  5. 5
    The device of Claim 1 wherein the varistor comprises zinc oxide, and wherein the zinc oxide comprises a majority of the material in the ceramic substrate.
  6. 6
    The device of Claim 1 wherein a portion of the ceramic substrate that is not a varistor comprises one of aluminum oxide, aluminum nitride, silicon carbide, or boron nitride, and the varistor comprises zinc oxide.
  7. 7
    The device of Claim 1 wherein the varistor comprises ceramic grains, and wherein the varistor comprises a plurality of metal layers sandwiching the ceramic grains, the metal layers being electrically connected to exposed substrate electrodes, the ceramic grains providing a low resistance path between the metal layers when an ESD voltage is applied across the metal layers.
  8. 8
    The device of Claim 1 wherein the varistor comprises ceramic grains, the varistor further comprising multiple overlying metal layers with the ceramic grains between the metal layers, the metal layers being electrically connected to metal electrodes on the substrate.
  9. 9
    The device of Claim 1 wherein the varistor comprises ceramic grains forming a surface, and wherein the varistor comprises a plurality of metal layers electrically connected to exposed substrate electrodes, the plurality of metal layers being in physical contact with only a single surface of the ceramic grains, the ceramic grains providing a low resistance path between the metal layers when an ESD voltage is applied across the metal layers.
  10. 10
    The device of Claim 1 further comprising a light emitting diode (LED) chip mounted on the top surface of the substrate and being protected from ESD by the varistor.
  11. 11
    The device of Claim 1 wherein the varistor forms part of a heat conduction path between the semiconductor device and a printed circuit board over which the substrate is mounted.
  12. 12
    The device of Claim 1 wherein the ceramic substrate has a top and bottom surface comprising one of aluminum oxide, aluminum nitride, silicon carbide, or boron nitride, and wherein the varistor comprises zinc oxide formed as one or more layers fixed to the top or bottom surface of the ceramic substrate, a first metal layer being formed to physically contact a top surface of the one or more layers, and a second metal layer being formed to physically contact a bottom surface of the one or more layers, the one or more layers providing a low resistance path between the first metal layer and the second metal layer when an ESD voltage is applied across the first metal layer and the second metal layer.
  13. 13
    The device of Claim 1 wherein the ceramic substrate has a top and bottom surface comprising one of aluminum oxide, aluminum nitride, silicon carbide, or boron nitride, and wherein the varistor comprises zinc oxide formed as a single layer fixed to the top or bottom surface of the ceramic substrate, a first metal layer being formed to physically contact a first surface of the single layer, and a second metal layer being formed to also physically contact the first surface of the single layer, the single layer providing a low resistance path between the first metal layer and the second metal layer when an ESD voltage is applied across the first metal layer and the second metal layer.
  14. 14
    The device of Claim 1 further comprising metal pads on a top surface of the ceramic substrate, for connection to the semiconductor device, and metal electrodes for electrical connection to a printed circuit board.
  15. 15
    The device of Claim 14 further comprising metal vias through the ceramic substrate for electrically connecting the metal pads to the metal electrodes.
  16. 16
    The device of Claim 14 wherein the metal pads are electrically connected to the metal electrodes by metal portions over a periphery of the ceramic substrate.
  17. 17
    The device of Claim 1 wherein the semiconductor device comprises a semiconductor chip directly affixed to the top surface of the ceramic substrate.
  18. 18
    A method for forming a ceramic substrate for providing electrostatic discharge (ESD) protection of a semiconductor device comprising:forming a ceramic substrate having a top surface and a bottom surface;and forming at least one metal electrode on the top surface of the ceramic substrate for electrical connection to an electrode of an overlying semiconductor device, the ceramic substrate comprising a metal oxide varistor that provides electrostatic discharge (ESD) protection to a semiconductor device mounted on the top surface of the ceramic substrate.
  19. 19
    The method of Claim 18 wherein the varistor comprises zinc oxide.
  20. 20
    The method of Claim 19 wherein a portion of the ceramic substrate does not form part of the varistor, the portion of the ceramic substrate that does not form part of the varistor comprising one of aluminum oxide, aluminum nitride, silicon carbide, or boron nitride.
  21. 21
    The method of Claim 18 wherein a portion of the ceramic substrate does not form part of the varistor, the portion of the ceramic substrate that does not form part of the varistor comprising one of aluminum oxide, aluminum nitride, silicon carbide, or boron nitride.