Semiconductor component and production method

0001The invention relates to a semiconductor component and a method for producing a semiconductor component with a light-emitting semiconductor layer or a light-emitting semiconductor element and two contact points which are designed as a contact layer and a contact.

0002Such a component is, for example, from <nplcit id="ncit0001" npl-type="s"><text>Wada et. al., Jpn. Appl. Phys. Vol. 31 (1992) pp. L78-L81</text></nplcit> known. Another is from the<patcit id="pcit0001" dnum="DE10040448A1"><text>DE 100 40 448 A1</text></patcit> known. There, a semiconductor chip with contact points on both sides and a reinforcing layer is described, which is sufficiently reinforced by a thick contact layer and the reinforcing layer that no carrier body is necessary for mechanical stabilization of the chip. A surface-covering auxiliary carrier layer, which can be removed selectively with respect to the reinforcement layer, is additionally applied to the reinforcement layer. The selective removal of the auxiliary carrier layer enables the chips to be separated without a sawing process.

0003A disadvantage of such components is the sensitivity of the component to changing temperatures during the manufacturing process and during operation. These lead to thermal stresses between the relatively sensitive semiconductor layer and the carrier body, which usually has a higher coefficient of expansion than the semiconductor layer. When heated, the carrier substrate expands more than the semiconductor and, as a result, the component bends. Such thermal stresses can cause cracks in the semiconductor, which leads to the failure of the component.

0004The object of the present invention is therefore to develop a semiconductor component of the type mentioned at the outset which at least reduces the thermal stresses between the semiconductor layer and the carrier body or substrate and a method for producing semiconductor components (including but not limited to the type mentioned above) specify in which a faster production of the component and a more reliable end product is achieved.

0005This object is achieved by a semiconductor component with the features of claim 1 and a method with the features of claims 14 and 15. Advantageous embodiments of the invention emerge from further claims.

0006According to the invention, a semiconductor component with a light-emitting semiconductor layer and two electrical contact points has a vertically structured carrier substrate. The structured carrier substrate is designed in such a way that, in particular, stresses in the component caused by temperature differences are at least partially compensated for.

0007In a preferred embodiment, the carrier substrate has vertical structural elements and a carrier base. The vertical structural elements stand on the support floor and are separated from one another by spaces. The vertical structural elements connect the carrier base to the semiconductor layer or the contact layer or a wetting layer. If the carrier substrate expands more than the semiconductor, the difference in elongation can be compensated for by bending the structural elements. Although the semiconductor layer will also bend, it is no longer subjected to tensile stress as would be the case with a homogeneous, unstructured carrier substrate.

0008The carrier substrate is preferably formed in one piece. With regard to the carrier substrate, one-piece means in particular that the carrier substrate is not formed from different layers or that the carrier substrate has a composition that is as homogeneous as possible.

0009The intermediate spaces can advantageously be filled with a filler material which is more elastic than the carrier substrate material. This improves the stability of the component without impairing the ability of the structured carrier substrate to absorb thermal stresses.

0010Another preferred embodiment has a single vertical structural element which is arranged under the center of the semiconductor layer or element. This structural element serves as a stable core of the component and is limited in cross-section parallel to the support base in size so that thermal tension does not yet lead to failures. The outer space around the individual structural element is covered with a softer or filled more elastic material that can absorb the thermal stresses and can also dissipate the heat from the semiconductor element.

0011In the above embodiments, the thermal stresses can additionally be reduced by selecting a carrier substrate material whose coefficient of expansion is as close as possible to that of the semiconductor layer.

0012In a further embodiment, the carrier substrate has a multilayer structure. This layer sequence consists of materials that have different coefficients of expansion and modulus of elasticity. At least one additional carrier substrate layer is applied or laminated to the underside of the first carrier substrate in order to compensate for the tension on the top of the first carrier substrate. The top of the first carrier substrate is closer to the semiconductor layer than the bottom. Since the layers are firmly connected, they must expand to the same length. Due to the different expansion coefficients of the semiconductor and the carrier substrate and therefore the different linear expansion, bending moments arise about a neutral axis of the layer package when heated. In order to reduce deflection, the layers must be matched to one another in such a way that the bending moments of each layer, including the semiconductor layer, add up to almost zero, ie the bending moments must cancel each other out. The following rule applies as a condition for planarity:<maths id="math0001"><math display="block"><mn mathvariant="normal">0</mn><mo>=</mo><mo>∑</mo><msub><mrow><mspace width="1em" /><mi mathvariant="normal">e.g.</mi></mrow><mi mathvariant="normal">i</mi></msub><mo>⁢</mo><msub><mrow><mspace width="1em" /><mi mathvariant="normal">E</mi></mrow><mi mathvariant="normal">i</mi></msub><mo>⁢</mo><msub><mrow><mspace width="1em" /><mi mathvariant="normal">d</mi></mrow><mi mathvariant="normal">i</mi></msub><mo>⁢</mo><msub><mrow><mspace width="1em" /><mi mathvariant="normal">α</mi></mrow><mi mathvariant="normal">i</mi></msub><mspace width="1em" /><mi mathvariant="normal">T</mi></math><img file="EP1547162B1_D0001.tif" /></maths> in which<ul id="ul0001" list-style="none" compact="compact"><li>e.g._i the distance between the neutral axis and element i,</li><li>E_i the Hooke's modulus of elasticity of element i,</li><li>d_i the thickness of the element i,</li><li>α_i the thermal expansion coefficient of element i and</li><li>T is the temperature of the component.</li></ul>

0013In practice, it is also sufficient if the equation sums up to almost zero, namely: <maths id="math0002"><math display="block"><mn mathvariant="normal">0</mn><mo>≅</mo><mo>∑</mo><msub><mrow><mspace width="1em" /><mi mathvariant="normal">e.g.</mi></mrow><mi mathvariant="normal">i</mi></msub><mo>⁢</mo><msub><mrow><mspace width="1em" /><mi mathvariant="normal">E</mi></mrow><mi mathvariant="normal">i</mi></msub><mo>⁢</mo><msub><mrow><mspace width="1em" /><mi mathvariant="normal">d</mi></mrow><mi mathvariant="normal">i</mi></msub><mo>⁢</mo><msub><mrow><mspace width="1em" /><mi mathvariant="normal">α</mi></mrow><mi mathvariant="normal">i</mi></msub><mspace width="1em" /><mi mathvariant="normal">T</mi></math><img file="EP1547162B1_D0002.tif" /></maths>

0014The method according to the invention for producing a semiconductor component essentially has the following method steps:<ol id="ol0001"><li>(a) epitaxially depositing a light-emitting semiconductor layer on a growth substrate,</li><li>(b) providing the semiconductor layer with a metallic contact layer,</li><li>(c) producing an adhesive and wetting layer at least over the metallic contact layer,</li><li>(d) applying, producing or depositing a mechanically stable carrier substrate on the adhesive and wetting layer,</li><li>(e) separating the semiconductor layer from the growth substrate,</li><li>(f) etching mesa trenches to define individual chips between the mesa trenches, the mesa trenches extending at least through the entire semiconductor layer and the entire contact layer,</li><li>(g) applying an electrical contact to the semiconductor layer and</li><li>(h) Separating the chips by separating them along the mesa trenches.</li></ol>

0015In a further embodiment, process step (f) is carried out before process step (c).

0016The generation or the deposition of a mechanically stable carrier substrate on the adhesive and wetting layer according to process step (d) is preferably carried out by means of a galvanic process. This has the advantage that small unevenness in the surface of the wetting layer can be compensated for without presenting problems with the adhesion.

0017Such bumps can cause problems with conventional connection techniques. For example, a pplying the carrier substrate using Van der Waals bonding requires extremely smooth surfaces so that the atomic forces can act. On the other hand, gluing can compensate for larger differences in height, but it usually requires organic materials that are not temperature or solvent resistant. Such materials also have low conductivity for heat and electrical current.

0018Soldering methods for applying the carrier substrate have none of the problems mentioned above, but are sensitive to contaminants. A fault in the wetting layer can, for example, result in the solder not adhering to this point and withdrawing. Larger foreign particles also mean that the solder cannot completely fill the gap. The area affected can be much larger than the particle. Faults in the structure of the solder are another possible source of errors. These are due to the metallurgy of the solder and are in principle not harmful if the structure is not subjected to strong and uneven mechanical or thermal stress, particularly when the growth substrate is separated. Such loads do not occur with the conventional III / V material systems because the growth substrate can be removed by chemical etching.

0019In contrast, in the case of semiconductors made from nitrides, only separation processes with high thermal (e.g. laser liftoff) and mechanical (e.g. crack separation) loads have been used so far. In such cases, the solder connection between the semiconductor layer and the carrier substrate is subjected to greater stress and is therefore susceptible to the problems mentioned above. With mechanical separation, it can occur that a weakening of the solder connection can induce a parasitic crack course in the solder layer and thus can impair the adhesion of the semiconductor to the carrier substrate. In the laser liftoff, the semiconductor (the nitride) is thermally decomposed locally by the laser bombardment at the interface between the growth substrate and the nitride. Excess heat generated must be dissipated through the semiconductor and the bond layer. Interruptions in the solder lead to increased heat resistance and thus to local overheating. Possible consequences range from thermal damage to the semiconductor or the contact to cracking or delamination due to the different coefficients of thermal expansion or local melting of the solder. For these reasons, the galvanic application of the carrier substrate without the need for a solder layer is particularly advantageous for nitride-based semiconductor components.

0020Features of advantageous further developments result from the subclaims.

0021In the following, the invention is illustrated by means of embodiments in connection with the <figref idref="f0001 f0002 f0003 f0004 f0005 f0006 f0007 f0008 f0009 f0010 f0011 f0012 f0013 f0014 f0015 f0016 f0017">Figures 1 to 13</figref> explained in more detail.

0022Show it<ul id="ul0002" list-style="none"><li><figref idref="f0001">Figure 1</figref> 2 shows a schematic sectional illustration of a first exemplary embodiment of a component according to the invention,</li><li><figref idref="f0001">Figures 2a and b</figref> in each case a schematic sectional illustration of a component under thermal stresses and a schematic sectional illustration of a bent wafer,</li><li><figref idref="f0002">Figures 3a, b and c</figref> in each case a schematic sectional illustration of a second exemplary embodiment of a component according to the invention under different operating conditions,</li><li><figref idref="f0003">Figure 4</figref> 2 shows a schematic sectional illustration of a third exemplary embodiment of a component according to the invention,</li><li><figref idref="f0003">Figure 5</figref> 2 shows a schematic sectional illustration of a fourth exemplary embodiment of a component according to the invention,</li><li><figref idref="f0004">Figures 6a and b</figref> each a schematic sectional illustration of a fifth exemplary embodiment of a component according to the invention under different operating conditions,</li><li><figref idref="f0005 f0006 f0007">Figures 7a to 7g</figref> schematic sectional views of some method steps of a first embodiment of a method according to the invention,</li><li><figref idref="f0008">Figure 8</figref> 2 shows a schematic sectional illustration of a sixth exemplary embodiment of a component according to the invention,</li><li><figref idref="f0009 f0010">Figures 9a to 9f</figref> schematic sectional views of some method steps of a second embodiment of a method according to the invention,</li><li><figref idref="f0011 f0012 f0013">Figures 10a to 10g</figref> schematic sectional representations of some method steps of a third embodiment of a method according to the invention,</li><li><figref idref="f0014 f0015">Figures 11a to 11d</figref> schematic sectional representations of some method steps of a fourth embodiment of a method according to the invention,</li><li><figref idref="f0016">Figures 12a and 12b</figref> each in a schematic sectional view of an assembly method of the fourth exemplary embodiment and</li><li><figref idref="f0017">Figures 13a and 13b</figref> schematic sectional views of some process steps of a fifth embodiment of a method according to the invention.</li></ul>

0023The same or equivalent elements are provided with the same reference numerals in the figures. In particular, the thickness of the layers is not shown to scale in the figures in order to facilitate understanding.

0024This in <figref idref="f0001">Figure 1</figref> The semiconductor component shown has a semiconductor layer 2, which is arranged between a contact point 8 and a contact layer 3. The contact layer 3 can also be designed as an interrupted and / or structured layer, which has, for example, a plurality of circular surfaces. For example, the semiconductor layer 2 contains GaN and the contacts 3, 8 platinum, palladium or aluminum. The contact layer 3 (less than approx. 5 nm thick) lies on a reflection layer 4 (approx. 100 nm thick), which is very important for the light efficiency, particularly in optoelectronic applications. Depending on the wavelength of the light, the reflection layer 4 can have gold for the red spectral range or silver and aluminum for the blue, for example. If the reflection layer can be impaired by alloying with other metals, then a diffusion barrier 5 (for example made of TiW (N) and approximately 0.5 μm thick) is then preferably applied to the reflection layer 4. In order to achieve better adhesion, the diffusion barrier 5 is coated with an adhesive and wetting layer 6 (for example having chrome and approximately 1 μm thick). A carrier substrate 7 adjoins the wetting layer 6 and approx. 50 µm is thick and for example made of metal such as nickel, chromium, copper, tungsten. The thickness of the carrier substrate is determined by the desired mechanical stability of the component and the measures that may be used to compensate for the thermal expansions. A passivation layer 9 covers at least the semiconductor layer 2 in order to protect it from impurities.

0025Unless otherwise stated, the above materials and dimensions also apply to the other exemplary embodiments of the device and the method.

0026In <figref idref="f0001">Figure 2a</figref> is illustrated with the aid of arrows, as when the heating of a known component causes the different expansion coefficients of the semiconductor 2 and the carrier substrate 7 to cause stresses in the component. Since the coefficient of expansion of the semiconductor 2 is generally lower than that of the carrier substrate 7 (usually a metal), the carrier substrate 7 expands more than the semiconductor when heated. This can lead to deflections during processing and in operation. Under certain circumstances, these deflections caused by thermal stresses as in the<figref idref="f0001">Figure 2a</figref> shown lead to the appearance of cracks in the semiconductor layer 2, which means the failure of the component. In<figref idref="f0001">Figure 2b</figref> the deflection 22 of the wafer 23, namely the maximum deviation of the wafer from the plane, is shown. In order to protect the semiconductor layer and to ensure processability, the deflection 22 should be limited to less than 100 μm. In the case of GaN epitaxial layers on an SiC substrate, massive cracks can already occur if the deflection 22 in a wafer (diameter 5 cm) exceeds 100 μm. Without special measures to reduce the thermal stresses, temperature-related damage to the semiconductor 2 can already occur if the carrier substrate 7 is thicker than approximately 5 μm. Such problems certainly arise when the carrier substrate 7 is thicker than 15 μm. Therefore, a carrier substrate 7 should not exceed 15 μm without any compensation measures. Since this thickness is still too thin for the mechanical stability required during processing, one or more of the following measures according to the invention must be taken.

0027This in <figref idref="f0002">Figure 3a</figref> executed example has a vertically structured carrier substrate 7, which consists of a carrier base 24, a plurality of vertical structural elements 25 and a plurality of interstices 26. A wetting layer 6, a diffusion barrier 5, a reflection layer 4, a contact layer 3 and a semiconductor layer 2 are arranged thereon in this order. A second contact point is not shown here. In this example, the structural elements 25 have a circular cross section, but can also take other forms. The height of the structural elements is preferably scaled with the lateral dimension of the semiconductor 2, so that the ratio of the semiconductor width to the structural element height does not exceed a factor of 15. The structural elements preferably have a high aspect ratio (ie Height / width) of at least two, so that they can bend better and balance thermal stresses. For example, the structural elements are 5-20 µm high and have a diameter of 5-10 µm. The thickness of the support base is preferably chosen to be at least as thick as the structural elements are high and is generally between 20 μm and 100 μm. The thickness must give the component sufficient mechanical stability during processing and in operation. In addition, the thickness is a matter of time, material and ultimately a question of cost. The intermediate spaces 26 can remain filled with a photoresist used during the structuring, remain unfilled (ie empty) or be filled up with another material as in the following exemplary embodiment.

0028In <figref idref="f0002">Figure 3b</figref> will that in <figref idref="f0002">Figure 3a</figref> executed component shown when heated. The component is attached to a connecting conductor track 19 with a very small part of the carrier substrate surface. When heated, the carrier substrate 7 expands more than the semiconductor layer 2, the lower part of the structural elements 25 adapting to the expansion of the carrier base 24 and the upper part adapting to the expansion of the semiconductor layer 2. The structural elements compensate for this difference in expansion by bending, so that in this example the structural elements bend inwards. This has the consequence that the edges of the carrier base 24 and the edges of the semiconductor layer 2 bend slightly upwards. This would also be the case if the component or the carrier substrate 7 were not fastened.

0029In contrast, as in <figref idref="f0002">Figure 3c</figref> shown, the edges of the semiconductor layer 2 bend downward when the component is fastened flat on a circuit board or connecting conductor track 19. Here the upper part of the structural elements 25 also bends, as in FIG<figref idref="f0002">Figure 3b</figref> shown, inwards, but due to the rigid, surface-mounted carrier base 24, a small bulge of the surface of the semiconductor layer 2 is formed.

0030In a further embodiment, the spaces 26 of the in <figref idref="f0002">Figure 3a</figref> Component shown with a filler 27, which is more elastic than the material of the carrier substrate 7, to improve the stability of the component. This is in<figref idref="f0003">Figure 4</figref> shown. Here, the structural elements 25 and the carrier base 24 consist, for example, of nickel and the filler 27 of gold.

0031Other materials such as polymers are also conceivable as filler 27.

0032In <figref idref="f0003">Figure 5</figref> An exemplary embodiment is shown which still offers a possibility for reducing the thermal bending stresses in such a component. The carrier substrate 7 of the in<figref idref="f0003">Figure 5</figref> The example shown consists of two different materials with different coefficients of expansion and moduli of elasticity. The thinner carrier substrate layer 20 has, for example, a higher modulus of elasticity and smaller expansion coefficients than the thicker carrier substrate layer 21. The pull of the carrier substrate 7 on the semiconductor layer 2 is partially compensated for by the carrier substrate layer with a smaller coefficient of expansion 20 and the thickness of the layers. For example, the upper carrier substrate layer 21 consists of copper with a thickness of 50 μm and the lower 20 of tungsten with a thickness of 1.3 μm or chromium with a thickness of 2.7 μm. More than two different materials can also be provided. The second contact point 8 and a possible passivation layer 9 are not shown here.

0033In <figref idref="f0004">Figure 6a</figref> will be a modification of the <figref idref="f0003">Figure 4</figref> shown component shown. The carrier substrate 7 here has a single vertical structure element 25, which is arranged centrally or centrally below the semiconductor layer 2, ie centered on the semiconductor layer 2. This structure element 25 thereby forms a stable core for the component and is limited in size such that thermal tension does not yet lead to failures. For example, this structural element 25 is circular in cross section and has a diameter of approximately 100 μm if the component has a diameter of approximately 300 μm. Other shapes and sizes of the structural element 25 are also conceivable. The remaining outside space is filled with a softer material that can absorb the thermal tension. As above<figref idref="f0003">Figure 4</figref> described, nickel, for example, is suitable for the structural element 25 and carrier base 24 and gold for the filler material 27. However, the filler material 27 should still be able to remove the heat from the component.

0034<figref idref="f0004">Figure 6b</figref> shows that in <figref idref="f0004">Figure 6a</figref> Component shown under thermal stress. Here the semiconductor layer is stressed much less than that in<figref idref="f0001">Figure 1</figref> Component shown, because a smaller interface between the more extensive carrier substrate and the semiconductor layer is claimed and therefore only a fraction of the stresses that the <figref idref="f0001">Figure 1</figref> Component shown senses, can have a harmful effect on the semiconductor layer 2. The filling material 27 adapts both to the extent of the carrier substrate 7 and to the extent of the semiconductor layer 2.

0035In the <figref idref="f0005 f0007">Figures 7a to g</figref> the schematic sequence of the method for producing the in <figref idref="f0001">Figure 1</figref> shown component shown according to the invention. The desired semiconductor layer 2 is deposited epitaxially on a growth substrate 1 (see<figref idref="f0005">Figure 7a</figref>). In this example, GaN is epitaxially deposited on sapphire.

0036As in <figref idref="f0005">Figure 7b</figref> is shown, the semiconductor layer 2 is then provided with a contact layer 3, preferably by means of vapor deposition or sputtering. Since the layers applied later are not translucent, this layer should be highly reflective in optoelectronic components. However, the contact of the mirror metallization to the semiconductor layer 3 is often poor. Therefore, an additional reflection layer 4 can be applied to the contact layer 3, the contact layer 3 being formed by very thin semitransparent or perforated layers of better electrically conductive contact metals, so that it absorbs little light. If the mirror can be destroyed by alloying with other metals, a diffusion barrier 5 should then be applied to the reflection layer 4. The reflection layer 4 and / or diffusion barrier 5 can be applied by means of vapor deposition or sputtering.

0037An adhesive and wetting layer 6 is applied to the diffusion barrier 5 as the top layer. This is preferably applied by means of vapor deposition or sputtering and can consist of chromium, nickel or conductive TiO. (Please refer<figref idref="f0005">Figure 7c</figref>.)

0038A carrier substrate 7 is deposited on the adhesive and wetting layer 6 to the desired thickness, for example by means of sputtering, a CVD process (namely a chemical vapor deposition process), a galvanic process, electroless plating or another known process. Please refer<figref idref="f0006">Figure 7d</figref>. The thickness of the carrier substrate depends essentially on the mechanical stability required during processing and operation, the maximum permitted thermal stresses before cracks occur in the semiconductor, and on whether measures such as the installation of an auxiliary substrate (as explained below) have been taken are. Without measures to compensate for thermal stresses, the carrier substrate should not exceed 15 µm in thickness. Since this thickness is too thin for processing, an auxiliary substrate 12 can be used. (Please refer<figref idref="f0008">Figure 8</figref> and the description below.)

0039The carrier substrate 7 should consist of a material that is thermally and electrically highly conductive and mechanically stable. Bumps and foreign particles should also be compensated for by the carrier substrate 7. Since the deposition can take place at room temperature, there is no fear of interdiffusion during the process. A galvanic method is preferably used. Evaporation has the disadvantages that the deposition rates are relatively low and the applied layer has low strength. In contrast, sputtering processes, deposition from the gas phase (CVD process) and deposition from a liquid phase are more suitable.

0040As in <figref idref="f0008">Figure 8</figref> shown, a solder layer 11 can optionally be additionally applied to the carrier substrate 7 in order to bond another auxiliary substrate 12 thereon. For example, a mechanically stable semiconductor such as silicon, germanium, silicon carbide or a metal substrate made of molybdenum or tungsten can be used. The solder layer 11 has, for example, a gold / tin mixture. An auxiliary substrate 12 may be required if the metal layer itself is not to be too thick, or if it is very expensive to deposit it. Since the solder layer 11 is now at a greater distance from the semiconductor layer 2, its poor mechanical properties, as already explained above, do not influence the separation process. The solder layer 11 and / or the auxiliary substrate 12 can be applied by means of sputtering, vapor deposition or galvanically. After the growth substrate 1 has been removed, there is the possibility, when a low-melting solder is selected, of removing the auxiliary substrate 12 again and returning it to the process or exchanging it for another (for example cheaper aluminum or copper). In addition, the auxiliary substrate 12 can also be used by means of an adhesive process (for example NanoPierce^®, see http://www.nanopierce.com).

0041After the application of the carrier substrate and possibly the auxiliary substrate, the growth substrate 1 is separated from the semiconductor layer 2. Depending on the selected growth substrate 1 and semiconductor 2, this process step can be carried out by chemical dissolution of the growth substrate 1, a sacrificial layer, a laser lift-off method, a laminated growth substrate equipped with predetermined breaking points or another known method.

0042Substrate materials such as GaAs or silicon can easily be chemically dissolved. The growth substrate is lost. In addition, the semiconductor must either be inert to the etching solution itself or be equipped with special etching stop layers. Another possibility is to incorporate a sacrificial layer in the semiconductor layer 2, which can be selectively etched. In this way, the growth substrate 1 is not lost and can also be reintroduced into the process.

0043In the material system of the nitrides, which are used for light generation in the short-wave spectral range, no suitable chemical etching methods for common substrates such as sapphire or silicon carbide as well as semiconductors (such as AlN, GaN, InN) are known. The laser liftoff method is therefore used here, for example, to separate the semiconductor layer 2. This takes advantage of the fact that GaN can decompose into gallium and gaseous nitrogen when bombarded with a laser. A laser with photon energy is used sufficiently to decompose the GaN but not sufficiently to decompose the growth substrate. The laser is emitted through the sapphire, which is still transparent at the required wavelengths. The GaN is thus decomposed at the boundary layer with the sapphire, and the semiconductor layer 2 is separated from the sapphire growth substrate 1 on account of the formation of the gases and the pressure. The component after the growth substrate 1 has been separated is shown in FIG <figref idref="f0006">Figure 7e</figref> pictured. However, this method is not possible with GaN deposited on SiC, since SiC has a smaller band gap than GaN and is therefore decomposed before GaN.

0044Furthermore, there is also the possibility of depositing the semiconductor layer 2 on an already laminated growth substrate 1. Such a laminated growth substrate 1 (for example SMARTCUT^® or UNIBOND^®) has an adhesive layer as the top layer, which is equipped with suitable predetermined breaking points. At these points, the thin semiconductor layer 2 is separated from the growth substrate 1 after the application of the carrier substrate 7.

0045Now, mesa trenches 10 are etched at least into the semiconductor layer 2 and the contact layer 3 such that individual chips are defined between the mesa trenches 10. The mesa trenches 10 extend at least through the entire semiconductor layer 2 and the contact layer 3. The shape of the mesa trenches 10 in cross section is, for example, in FIG<figref idref="f0007">Figure 7f</figref> pictured. Other shapes are also possible. The etching of mesa trenches 10 can be carried out by means of photolithography or other known methods in combination with dry etching, for example the RIE method (ie reactive ion etching).

0046In a further process step, according to <figref idref="f0007">Figure 7f</figref> the contact 8 is applied to the semiconductor layer 2 by means of sputtering or vapor deposition. The contact 8 contains aluminum, for example. A passivation layer 9 (eg made of silicon nitride or silicon oxide) can possibly be applied by means of sputtering or a CVD method over the part of the semiconductor layer 2 that is not covered by the contact 8 and at least over the side surfaces of the contact layer 3.

0047Optionally, three-dimensional structures can be produced in the semiconductor or in the passivation layer 9 in order to optimize the coupling out of light. Since the light is first coupled out of the semiconductor, such structures have a better effect when they are produced in the semiconductor layer 2 than in the passivation layer 9. Structures for improving the light coupling can of course be produced in both layers.

0048For example, pyramid structures which have at least three visible surfaces per pyramid are etched into the semiconductor layer 2 before the contacts 8 or the possible passivation layer 9 are applied. After the semiconductor layer 2 has been separated from the growth substrate 1, the surface of the semiconductor layer 2 is somewhat rough.

0049The pyramid structures are created in particular by an anisotropic etching process such as an RIE process. Depending on the semiconductor selected, the structures can also be produced by means of wet chemical etching or dry etching processes. For example, an RIE or ICP (ie inductively coupled plasma) method is more suitable for structuring the GaN, and wet-chemical etching can also be used for a GaAs semiconductor. After such structuring, the contact 8 and preferably also a passivation layer 9 is applied in order to protect the surface from contamination.

0050Finally, the chips are separated along the mesa trenches 10, for example by sawing or laser cutting. In the<figref idref="f0007">Figure 7g</figref> the separation is shown with a saw blade.

0051In the <figref idref="f0009 f0010">Figures 9a to 9f</figref> the process steps of a modification of the in the <figref idref="f0005 f0006 f0007">Figures 7a to 7g</figref> method outlined in part. The information on materials and processes from the above exemplary embodiment also apply to the following exemplary embodiments, unless stated otherwise. The application of the semiconductor 2, contact 3 and reflection layer 4 on the growth substrate 1 becomes the according to the description above<figref idref="f0005">Figures 7a and 7b</figref> carried out. In this case, the reflection layer 4 is integrated in the contact layer 3. This combined layer is identified by the designation 3 + 4 in the figures.

0052As in <figref idref="f0009">Figure 9a</figref> shown here, the mesa trenches 10 are etched before the semiconductor layer 2 is separated from the growth substrate 1 into the contact / reflection 3 + 4 and semiconductor layer 2. This can be advantageous if the mesa etch process causes problems with an underlying layer. For example, the diffusion barrier 5, the wetting layer or the carrier substrate 7 are applied before the mesa etching process in the above method, but only after the mesa etching process in this method and are therefore not exposed to the etching. After the etching, the layer stack (namely the contact / reflection 3 + 4 and semiconductor layer 2) is in the form of individual islands on the growth substrate 1. A diffusion barrier 5 is applied to these islands, ie on the contact / reflection layer 3 + 4. Subsequently, a passivation layer 9 is applied areally over the contact / reflection 3 + 4 and semiconductor layer 2 not covered by the diffusion barrier and over the part of the growth substrate 1 located in mesa trench 10.

0053An adhesive and wetting layer 6 is applied to the entire surface, including the surface of the mesa trenches 10. Please refer<figref idref="f0009">Figure 9b</figref>.

0054According to <figref idref="f0009">Figure 9c</figref> For example, the carrier substrate 7 is applied galvanically to the wetting layer 6 to the desired thickness, so that the mesa trenches 10 are also filled.

0055The growth substrate 1 is separated from the semiconductor layer 2 by one of the separation methods mentioned above. The parts of the passivation layer 9 which lie in the mesa trenches are also removed. Please refer<figref idref="f0010">Figure 9d</figref>.

0056According to <figref idref="f0010">Figure 9e</figref> the contacts 8 are applied to the semiconductor layer 2. In order to better protect the semiconductor layer 2 from impurities, the passivation layer 9 is expanded to the semiconductor layer 2.

0057Finally, the chips are separated along the mesa trenches by means of sawing or laser cutting. Please refer<figref idref="f0010">Figure 9f</figref>.

0058Another procedural embodiment is in the <figref idref="f0011 f0012 f0013">Figures 10a to 10g</figref> shown. This method immediately follows the previous method after the application of the wetting layer 6 (cf.<figref idref="f0009">Figures 9b</figref> and <figref idref="f0011">10a</figref>). Instead of the substrate 7 flat as in<figref idref="f0009">Figure 9c</figref> shown, separating webs 13 are applied, for example, from a photoresist by means of photolithography, the LIGA process or a similar process with galvanic molding. This is achieved by applying the photoresist to the wetting layer 6 over a surface area of ​​up to at least 10 μm thick, so that all the mesa trenches are completely filled over their entire length. After suitable exposure, the photoresist that lies between the mesa trenches and above the semiconductor layer 2 can be selectively removed (see <figref idref="f0011">Figure 10b</figref>). It is important that this material can be removed selectively. The separating webs 13 can achieve very high aspect ratios with modern resist systems (for example a LIGA process or a suitable photoresist such as the ma-P 100 or the SU-8 from MicroChem Corp.). Separators that are as narrow as possible are advantageous. The narrower the dividers 13, the less usable wafer area is wasted by the dividers. This in turn means that the number of chips per wafer is increased and the costs are reduced.

0059The spaces between the separating webs 13 above the semiconductor layer 2 become <figref idref="f0011">Figure 10c</figref> for example, galvanically filled with a material suitable as a carrier substrate 7 up to the height of the separating webs. Then the separators are selectively removed using a solvent or by etching. The carrier substrate islands 71 ​​thus created are shown in<figref idref="f0012">Figure 10d</figref> pictured. To simplify handling for further processing, the carrier substrate islands 71, including the mesa trenches, are completely overmolded with an auxiliary material 14 of stable thickness. The components after this overmolding are in<figref idref="f0012">Figure 10e</figref> pictured. The auxiliary material 14 can be applied by a sputtering process, a CVD process, a galvanic process, electroless plating or another known process. The use of metals, suitable polymers (eg polyimide) or SpinOn glasses is conceivable. Mechanical strength can also be imparted by gluing or soldering onto a second substrate. However, it is important that the auxiliary material 14 can be selectively removed again.

0060After overmolding with auxiliary material 14, the growth substrate 1 is separated from the semiconductor layer 2 by one of the methods already mentioned. As in<figref idref="f0013">Figure 10f</figref> shown, the contacts 8 are then applied to the semiconductor layer 2.

0061The components can now be separated without mechanical force. A carrier film 15 is applied over the contacts 8 on the semiconductor layer and the auxiliary material 14 is selectively removed, for example by etching. Then the components are automatically separated and, as in<figref idref="f0013">Figure 10g</figref> mapped are available on a carrier film 15. This separation process can be very fast, provided that sufficient etching rates are used. Unlike saws, for which the time consumption is simply proportional to the number of components, the time consumption here is independent of the number of components and the wafer size. This has an additional advantage over the sawing process that any geometry restrictions on the component are eliminated. Round or square components can also be produced. The narrow separating webs 13 also reduce the waste of the wafer surface, which is not used as a sawing track.

0062In the <figref idref="f0014 f0015">Figures 11a to 11d</figref> a further exemplary embodiment is outlined, which represents a variation of the last method. In this embodiment, the method essentially runs according to the in<figref idref="f0011">Figures 10a to 10c</figref> summarized scheme with the exception that the top of the dividers 13 is formed in cross section as a tip. Instead of applying the carrier substrate 7 only up to the height of the separating webs 13, this process is continued, so that the entire structure including the dividing webs 13 is overmolded. This is in<figref idref="f0014">Figure 11a</figref> shown and can be done with the same material as that used for the carrier substrate 7, or with another.

0063The overmolded structure should now be sufficiently load-bearing that the growth substrate 1 can be removed easily. The contacts 8 are applied to the semiconductor layer 2. Please refer<figref idref="f0014">Figure 11b</figref>.

0064<figref idref="f0015">Figure 11c</figref> shows the components after the separating webs 13 have been dissolved from the side of the semiconductor layer 2, for example by means of organic solvent. This means that each chip is virtually free on carrier substrate islands that are connected by a carrier substrate layer. Since the connecting carrier substrate layer is now comparatively thin, the components, as in<figref idref="f0015">Figure 11d</figref> shown to be sheared off with little force. The pointed shape of the separators supports the shearing process and can also have an advantageous effect on a carrier substrate material that has low shear strength.

0065The <figref idref="f0016">Figures 12a and 12b</figref> show the subdivision of an entire wafer with components in lines and how the lines can be attached to connecting tracks 19, for example by means of thermocompression. At the same time, an assembly machine 18 breaks or breaks the connection and moves to the next field. Since only short distances are covered, the process is also suitable for equipping areas with larger quantities (e.g. self-illuminating RGB displays).

0066In the <figref idref="f0017">Figures 13a and 13b</figref> Another embodiment is outlined, which is an alternative to that in the <figref idref="f0011 f0012 f0013">Figures 10a to 10g</figref> method shown. Here the component is manufactured without photoresist and without structuring. Instead of the wetting layer 6 as in<figref idref="f0011">Figure 10a</figref> is applied to the entire surface, in this exemplary embodiment the wetting layer 6 is only applied to the outermost layer above the semiconductor layer 2, ie there is no wetting material on the side or surface of the mesa trenches. As in<figref idref="f0017">Figure 13a</figref> an anti-wetting layer 16 is applied to the sides and surfaces of the mesa trenches. This anti-wetting layer 16 can be a dielectric such as silicon nitride or silicon oxide. The wetting layer 6 consists, for example, of gold or titanium.

0067For example, the carrier substrate material (for example Nikkel) only grows on the wetting layer 6 during electroless deposition. If the process is stopped before the mesa trenches grow, separate carrier substrate islands 71 ​​as in FIG<figref idref="f0017">Figure 13b</figref> pictured, achieved. These components can now be like those in<figref idref="f0012">Figure 10d</figref> pictured components are processed further. The structural fidelity of the carrier substrate islands 71 ​​is not as good as with the photoresist method (namely that in the FIGS<figref idref="f0011 f0012 f0013">Figures 10a to 10g</figref> described methods), but this saves the costs for a coating processing and exposure.

0068The in the <figref idref="f0002">Figures 3a</figref>, <figref idref="f0003">4</figref> and <figref idref="f0004">6a</figref> The components according to the invention shown can also be produced with suitable modifications using the methods according to the invention, namely after modifications of the components shown in FIGS <figref idref="f0005 f0006 f0007">Figures 7</figref>, <figref idref="f0009 f0010">9</figref>, <figref idref="f0011 f0012 f0013">10</figref>, <figref idref="f0014 f0015">11</figref> and <figref idref="f0017">13</figref> procedures shown.

0069For the production of in the <figref idref="f0002">Figures 3a</figref>, <figref idref="f0003">4</figref> and <figref idref="f0004">6a</figref> illustrated components, the carrier substrate 7 or the carrier substrate island 71 must be structured. This structuring can be achieved for example by means of photolithography, a LIGA process or another known process. Using photolithography as an example, a suitable photoresist should be applied to the wetting layer 6 before the carrier substrate 7 is applied, appropriately exposed and etched, so that the negative shape of the vertical structural elements or the structural element 25 of the desired component is achieved. To achieve structural elements 25 with high aspect ratios, a LIGA process or a suitable photoresist (for example the ma-P 100 or the SU-8 from Nano ™).

0070To do that in <figref idref="f0003">Figure 4</figref> or <figref idref="f0004">6a</figref> To produce the illustrated component, the photoresist can be left in the component if it is sufficiently elastic, for example using the LIGA method, or the intermediate spaces 26 can be filled with an additional filler 27. The last alternative should be done after the photoresist has dissolved. This can be done by a spraying process in which, for example, a thermoplastic is injected into the interspaces, by flowing a filler 27 in the liquid phase, for example at high temperatures, by flowing in an adhesive in the liquid phase that dries or hardens later (such as epoxy resin) or by another known method.

0071As part of the in the <figref idref="f0005 f0006 f0007">Figures 7a to 7g</figref> The method shown comes the branch for the production of a <figref idref="f0002">Figure 3a</figref>, <figref idref="f0003">4</figref> or <figref idref="f0004">6a</figref> component shown after that in <figref idref="f0005">Figure 7c</figref> pictured stage of manufacture is reached. As already described above, the photoresist is applied here to the wetting layer 6 and structured with a plurality of negative forms of structural elements 25, if that in FIG<figref idref="f0002">Figure 3a</figref> or <figref idref="f0003">4</figref> pictured component is aimed. In the alternative, the photoresist is patterned with a negative form of the structural element 25 if that in<figref idref="f0004">Figure 6a</figref> shown component can be reached. The carrier substrate 7 is then deposited using one of the methods mentioned above, but beyond the photoresist to the desired thickness of the carrier base 24 (for example 50 μm). The carrier substrate is thus formed, for example, in one piece. The photoresist may or may not be dissolved at any time before the components are separated. If the photoresist is more elastic or softer than the material of the carrier substrate 7, then the photoresist can also be used as filler 27 for the in the <figref idref="f0003">Figures 4</figref> or <figref idref="f0004">6a</figref> pictured component serve. Otherwise, the component can be like the<figref idref="f0006 f0007">Figures 7e to 7g</figref> already described, can be further processed.

0072The carrier substrate 7 can also be structured after the in <figref idref="f0009">Figure 9b</figref> shown process stage is reached. As already described above, the photoresist is applied to the wetting layer 6 and structured and the carrier substrate 7 is applied in such a way that at least one structural element and an intermediate space are formed and a carrier base 24 is formed. After the optional resolution of the photoresist and the optional use of a filling material 27, the further processing according to the<figref idref="f0010">Figures 9d to 9f</figref> respectively.

0073Similarly, the structuring according to the in <figref idref="f0011">Figure 10b</figref> reached manufacturing stage. Here, the photoresist is applied to the wetting layer 6 between the separating webs 13 and structured. As already described above, the carrier substrate 7 is applied to the wetting layer 6 lying between the separating webs or to the photoresist, so that a carrier base 24 is also formed. Further processing in accordance with<figref idref="f0012 f0013">Figures 10d to 10g</figref> can be done with or without dissolving the photoresist or using a filler 27.

0074After that in the <figref idref="f0014 f0015">Figures 11a to 11d</figref> illustrated method, the carrier substrate can be structured as already described above. The structural elements 25 are lower than the separating webs 13, so that the component can be given sufficient mechanical stability during a possible shearing process. For example, the structural elements 25 are approximately 15 µm high and the separating webs 13 approximately 50 µm high. The dividers 13 can usually be between 50 μm and 200 μm high, but the higher the separating webs 13, the thicker the carrier substrate 7 and the more material is required, which in turn is a question of cost.

0075According to the in <figref idref="f0017">Figures 13a and 13b</figref> The method illustrated can be the production of a structured carrier substrate 7 for the production of a in the <figref idref="f0002">Figures 3a</figref>, <figref idref="f0003">4</figref> or <figref idref="f0004">6a</figref> component shown above in <figref idref="f0017">Figure 13a</figref> shown wetting layer 6 take place.

0076This patent application claims the priority of the German patent application <patcit id="pcit0002" dnum="DE10245631333"><text>102 45 631.3-33</text></patcit>, the disclosure of which is hereby incorporated by reference.

0077The scope of the invention is not limited by the description of the invention based on the exemplary embodiments. Rather, the invention encompasses every new feature and every combination of features, which includes in particular every combination of features in the patent claims, even if this combination is not explicitly specified in the patent claims.