Semiconductor component and production method

Translation of description of equivalent WO 2004032247 A2

p0001description

p0002Semiconductor device and process for producing

p0003The invention relates to a semiconductor device and a method of manufacturing a semiconductor device with a semiconductor light-emitting layer or a light-emitting semiconductor element and two contact points, which are formed as a contact layer and a contact.

p0004Such a device is known for example from DE 100 40 448 AI. There, a semiconductor chip will be described with two-sided contact points and a reinforcing layer, which is sufficiently reinforced by a thick contact layer and the reinforcing layer, that for the mechanical stabilization of the chip carrier body is not necessary. A comprehensive auxiliary carrier layer, which can be selectively removed relative to the reinforcing layer is additionally applied to the reinforcing layer. The selective removal of the auxiliary carrier layer enables the separation of the chips without sawing process.

p0005A disadvantage of such devices is the sensitivity of the device to changing temperatures during the manufacturing process and in use. These lead to thermal stress between the relatively delicate semiconductor layer and the carrier body, which typically has a higher coefficient of expansion than the semiconductor layer. When heated, the carrier substrate expands more than the semiconductor and as a result, the device turns on. Such thermal stresses can cause cracks in the semiconductor, leading to failure of the component.

p0006Object of the present invention is therefore to provide a semiconductor component of the type mentioned to develop, which at least reduces the thermal stresses between the semiconductor layer and the support body or substrate and a method for the production of semiconductor devices (including the above-mentioned type but not limited to) indicate where a faster production of the component and a reliable end product is achieved.

p0007This object is achieved by a semiconductor device having the features of claim 1 and a method having the features of claims 14 and 15. FIG. Advantageous embodiments of the invention will become apparent from the other claims.

p0008According to the invention, a semiconductor device with a semiconductor light-emitting layer and two electrical contact points to a vertically structured carrier substrate. The structured carrier substrate is designed so that resulting in particular by temperature differences in the component voltages are at least partially compensated.

p0009In a preferred embodiment, the carrier substrate has vertical structural elements and a support floor. The vertical structural elements are on the support floor and are separated by gaps. The vertical structural elements connecting the support base with the semiconductor layer and the contact layer or a wetting layer. Stretches the carrier substrate is now stronger than the semiconductor, the difference in expansion can be accommodated by bending of the structural elements. Although the semiconductor layer will bend, but it is not as heavily used to train as would be the case with a homogeneous, unstructured carrier substrate.

p0010The carrier substrate is preferably formed integrally. Under integral means in particular that the carrier substrate not from different layers is formed or that the carrier substrate having a very homogeneous composition with respect to the carrier substrate. Advantageously, the gaps may be filled with a filling material that is more elastic than the carrier substrate material. This improves the stability of the device, without compromising the ability of the structured carrier substrate to absorb thermal stresses, will be affected.

p0011A further preferred embodiment includes a single vertical structural element that is disposed under the center of the semiconductor layer or element. This structural element is used as the stable core of the device and is parallel to the support floor so restricted in cross-section in the size that do not lead to thermal strains failures. The outside space to the individual structural element is filled with a softer or more elastic material, which can absorb the thermal stresses and also dissipate heat from the semiconductor element.

p0012In the above embodiments, the thermal volt- age levels additionally by selecting a carrier substrate material whose coefficient of expansion as close to the semiconductor layer is located can be reduced.

p0013In a further embodiment, the carrier substrate has a multi-layer structure. This sequence of layers consisting of materials having different coefficients of expansion and modulus of elasticity. At least one additional carrier substrate layer is applied to the underside of the first carrier substrate and laminated to compensate for the train to the top of the first support substrate. The top of the first carrier substrate is closer to the semiconductor layer as the bottom. Since the layers are fixed to each other, they must be extended to the same length. Due to the different expansion coefficients of the semiconductor and the supporting substrate, and therefore the difference in length expansion produced during heating, bending moments about a neutral axis of the layer packet. Around to reduce sagging, the layers in the thickness must be adjusted so that the bending moments of each layer including the semiconductor layer add up to almost zero, ie the bending moments must cancel. As a condition of planarity apply the following rule:

p00140 = Σ Z_j_ e_L d_i a T where z_i the distance between the neutral axis and the element i, E of the Hooke's modulus of elasticity of the element i, di the thickness of the element i, α. * _ the thermal expansion coefficient of the element i and T is the temperature of the device.

p0015In practice, it is also sufficient if the equation adds up to almost zero, namely:

p00160 s Σ z_i E d T cti

p0017The inventive method for producing a semiconductor component essentially comprises the steps of:

p0018(A) epitaxially depositing a light emitting semiconductor layer on a growth substrate,

p0019(B) providing the semiconductor layer with a metallic contact layer,

p0020(C) generating a tackifier and wetting layer, at least over the metal contact layer,

p0021(D) applying, generating or depositing a mechanically stable carrier substrate on the adhesive and wetting layer,

p0022(E) separating the semiconductor layer from the growth substrate, (F) etching of mesa trenches for defining individual chips between the mesa trenches, wherein the mesa trenches through rich at least through the entire semiconductor layer and the entire contact layer,

p0023(G) depositing an electrical contact on the semiconductor layer, and

p0024(H) dig the chips by separation along the mesa.

p0025In a further embodiment of the process, step (f) prior to step (c) is carried out.

p0026The production or deposition of a mechanically stable supporting substrate on the adhesive and wetting layer according to method step (d) is preferably carried out by means of a galvanic process. This has the advantage that small irregularities in the surface of the wetting layer can be compensated, without presenting problems of adhesion.

p0027In conventional joining techniques such irregularities can cause problems. Applying the carrier substrate by means of Van der Waals bonding, for example, requires extremely smooth surfaces, so that the atomic forces can act. By contrast, bonding can indeed chen greater height differences compensate, but requires but mostly organic materials that are not temperature or solvent resistance. In addition, such materials have a low thermal conductivity and electricity.

p0028Soldering for applying the carrier substrate have any of the above problems, but are sensitive to contaminants. A disturbance in the wetting layer can, for example, cause the solder at this point is not liable and retreats. Also bring greater foreign particles that the solder gap can not fully populate. The affected area may be much larger than the particle. Disturbances in the structure of the solder are another possible source of error. These are energy by the metallurgy of the solder due and in principle not harmful when the structure particularly when separating the growth substrate is not strong and uneven mechanical or thermi is charged sch. Such loads do not occur in the conventional III / V material systems because the growth substrate can be wet-chemically removed by etching.

p0029By contrast, in semiconductors of nitrides come so far only Abtrennenverfahren high thermal (z. B. Laserliftoff) and mechanical (eg. B. Tear Disconnect) fertil burden to application. In such cases, the solder joint between the semiconductor layer and the carrier substrate is more highly stressed and is therefore susceptible to the problems mentioned above. it can occur when mechanical separation that a weakening of the solder induce a parasitic crack path in the solder layer which may interfere with the adhesion of the semiconductor on the carrier substrate. When Laserliftoff is decomposed (the nitride) through the laser-markable shot thermally locally at the interface between the growth substrate and the nitride semiconductor. Resulting Excess warmth must be dissipated by the semiconductor and the bonding layer. Interruptions in the Lot, however, lead to an increased heat resistance and therefore to local overheating. Possible consequences range from thermal damage to the semiconductor or contact cracking or delamination due to the different thermal expansion coefficients or local melting of the solder. For these reasons, the galvanic depositing of the carrier substrate without the need for a solder layer is particularly advantageous for nitride-based semiconductor devices.

p0030Features of advantageous developments result from the dependent claims. The invention using preferred embodiments will play in conjunction with Figures 1 to 13 described in more detail.

p0031Show it

p0032Figure 1 is a schematic sectional view of a first embodiment of a device according to the invention,

p0033Figures 2a and b are each a schematic sectional view of a component under thermal strains and a schematic sectional view of a wafer by curved,

p0034Figures 3a, b and c are each a schematic sectional view of a second embodiment of a device according to the invention under different operating conditions,

p0035Figure 4 is a schematic sectional view of a third embodiment of a device according to the invention,

p0036Figure 5 is a schematic sectional view of a fourth embodiment of a device according to the invention,

p0037Figures βa and b are each a schematic sectional view of a fifth embodiment of a device according to the invention under different operating conditions,

p0038Figures 7a to 7g are schematic sectional views of some process steps of a first embodiment of a method according to the invention,

p0039Figure 8 is a schematic sectional view of a sixth embodiment of a device according to the invention, Figures 9a to 9d are schematic sectional views of some process steps of a second embodiment of a method according to the invention

p0040Figures 10a to 10g are schematic sectional views of some process steps of a third embodiment of a method according to the invention

p0041Figures 11a-lld show schematic sectional views of some process steps of a fourth embodiment of a method according to the invention,

p0042Figures 12a and 12b respectively in a schematic sectional representation of an assembly method of the fourth exemplary embodiment and procedural

p0043Figures 13a and 13b show schematic sectional views of some process steps of a fifth embodiment of a method according to the invention.

p0044Identical or functionally identical elements are provided in the figures with the same reference numerals. In particular, the thickness of the layers is not shown to scale in the figures, to serve for better understanding.

p0045The semiconductor device shown in Figure 1, a semiconductor layer 2 which is disposed between a contact point 8 and a contact layer 3rd The contact layer 3 may be formed as a broken and / or patterned layer, for example, has a plurality of circular areas. For example, the semiconductor layer includes GaN 2 and the contacts 3, 8 platinum, palladium or aluminum. The contact layer 3 (less than about 5 nm thick) is on a reflective layer 4 (about lOOnm thick) in optoelectronic applications is particularly important for the light efficiency. Depending on the wavelength of light, the reflection layer 4, for example, for the gold have red spectral or silver and aluminum for the blue. Can the reflection layer be adversely affected by alloying with other metals, so then a diffusion barrier is preferably 5 (thick example TiW (N) and about 0, 5 microns) is applied to the reflective layer. 4 In order to achieve better adhesion, the diffusion barrier 5 with an adhesion and wetting layer 6 (for example, chromium and comprising about 1 micron thick). a carrier substrate 7 adjoins the wetting layer 6, which is approximately 50 microns thick and for example of metal, such as, inter alia, nickel, chromium, copper, tungsten. The thickness of the carrier substrate is determined by the desired mechanical stability of the component and the measures used if necessary, to compensate for thermal expansions. A passivation layer 9 covers at least the semiconductor layer 2 to protect this from impurities.

p0046Unless otherwise specified, the above materials- and dimensions also apply to the other fixture moderate and procedural embodiments.

p0047In Figure 2a is shown by means of arrows, causing as warming a known device the different expansion coefficients of the semiconductor 2 and the carrier substrate 7 stresses in the component. Since the expansion coefficient of the semiconductor 2 is generally lower than that of the support substrate 7 (usually a metal) is, the support substrate 7 expands when heated more strongly than the semiconductors. This can lead to deflections during production zessierung and in operation. Under certain circumstances, these deflections caused by thermal stresses can as shown in the figure 2a for appearance of cracks in the semiconductor layer 2 lead, which means a failure of the device. In Figure 2b, the deflection 22 of the wafer 23, namely, the maximum deviation of the wafer from the level shown. To protect the semiconductor layer and to ensure the workability, the deflection should 22 be limited to less than 100 microns. When GaN epitaxial layers on SiC substrate massive cracks may already occur if the deflection 22 in a wafer (diameter 5 cm) exceeds 100 microns. Without special measures to reduce the thermal stresses, a temperature-related damage to the semiconductor 2 already occur if the carrier substrate 7 is thicker than about 5 microns. Such problems arise certainly, if the carrier substrate 7 is thicker than 15 microns. Therefore, a carrier substrate 7 should not exceed 15 microns without any compensatory measures. Since this thickness for required during the processing is still too thin mechanical stability, one or more of the following measures according to the invention must be taken.

p0048The executed in Example 3a has a vertically structured support substrate 7 consists of a support base 24, a plurality of vertical structural elements 25 and a plurality of interstices 26th Then, a diffusion barrier 5, a reflection layer 4, a contact layer 3 and a semiconductor layer 2 in this order, a wetting layer β arranged. A second contact point is not shown here. In this example, the structural elements 25 has a circular cross-section, but may take other forms. The height of the structure elements is preferably scaled by the lateral dimension of the semiconductor 2, so that the ratio of width to the semiconductor structure element height does not exceed the factor 15th The structural elements preferably have a high aspect ratio (ie height / width) of at least two on, so that they can bend better and compensate thermal stresses. For example, the structural elements are 5-20 microns high and have a diameter of 5-10 microns. The thickness of the tray is preferably at least as thick chosen as the structural elements are high and is usually between 20 .mu.m and 100 .mu.m. The thickness of the component has sufficient mechanical stability during processing and impart during operation. Moreover, the thickness is a waste of time, material and ultimately a question of cost. The gaps 26 can remain filled with a photoresist used during patterning, remain unfilled (ie empty) or as filled in the following embodiment with another material.

p00493b shows that exported to figure 3a component is shown at warming. The device is attached to a very small part of the carrier substrate surface on a ground Anschlußleiter- 19th On heating, the carrier substrate 7 expands more than the semiconductor layer 2, the lower part of the structural elements 25, adapts to the expansion of the carrier bottom 24 and the upper part of the extension of the semiconductor layer 2. FIG. The structural elements of this same difference in expansion by bending, so that the structural elements in this example, turn inwardly. This has the consequence that easily bend the edges of the tray 24 and the edges of the semiconductor layer 2 upward. This would also be the case if the component or the carrier substrate 7 would not fixed.

p0050By contrast, as shown in Figure 3c, the edges of the semiconductor layer 2 to bend down when the component is surface mounted on a circuit board or connection interconnect 19th Here, the upper part of the structural elements 25 also bends, as shown in Figure 3b, to the inside, but forms a small Auswδlbung the surface of the semiconductor layer 2 due to the rigid, flat fixed support base 24th

p0051In another embodiment, the interstices 26 of the device shown in Figure 3a with a filler material 27 that is more elastic than the material of the support substrate 7, filled up to improve the stability of the component. This is illustrated in FIG. 4 Here there are the structural elements 25 and carrier base 24, for example, of nickel and the filler material 27 made of gold. Other materials such as polymers are conceivable as filler 27th

p0052In figure 5 an embodiment is represented, which still provides a possibility to reduce the thermal bending stresses in such a device. The support substrate 7 of the embodiment shown in Figure 5 consists of two different materials having different expansion coefficients and elastic moduli. The thinner carrier substrate layer 20 has, for example, a higher elastic modulus and smaller coefficient of expansion than the thicker carrier substrate layer 21. The carrier substrate layer with a smaller expansion coefficient 20 and the thickness of the layers of the train of the carrier substrate 7 on the semiconductor layer 2 is partially compensated. For example, the upper substrate support layer 21 made of copper with a thickness of 50 microns and the bottom 20 of tungsten having a thickness of 1.3 microns or chromium having a thickness of 2.7 microns. More than two different materials may also be provided. The second contact point 8 and a possible passivation layer 9 are not shown here.

p0053In Figure 6a a modification of the device shown in Figure 4 is shown. The carrier substrate 7 has here a single vertical structural element 25 of which is arranged centrally or centrally under the semiconductor layer 2, that is centered on the semiconductor layer 2. This structure element 25, thereby forming a stable core for the device and is limited in size so that not cause thermal stresses to failures. For example, this

p0054Structural element 25 circular in cross section and has a diameter of about 100 microns, when the device has a diameter of about 300 microns. Other shapes and sizes of the structure element 25 are also conceivable. The remaining outer ßenraum is padded with a softer material, which can absorb the thermal strains. As described above for Figure 4, for example, nickel is suitable for the structural turelement 25 and support base 24 and gold for the filler 27. The filler 27 but should still be able to dissipate the heat from the component.

p00556b shows the device shown in Figure 6a under thermal stresses. Here, the semiconductor layer is much less stressed than the device illustrated in Figure 1, because a smaller interface between the more extensive support substrate and the semiconductor layer is claimed and therefore only a fraction of the tensions that can feel the device shown in Figure 1, an adverse effect on the semiconductor layer can act. 2 The filler material 27 adapts to both the expansion of the carrier substrate 7 and the expansion of the semiconductor layer 2. FIG.

p0056In the Figures 7a to g of the schematic procedure of the method for forming the device shown in Figure 1, according to the invention is shown. The desired semiconductor layer 2 is epitaxially grown on a growth substrate 1 is deposited (see FIG. 7a). In this example, GaN is epitaxially deposited on sapphire.

p0057As shown in Figure 7b, the semiconductor layer 2 is then preferably provided by vapor deposition or sputtering with a contact layer. 3 Since the later-applied layers are not transparent, this layer should be good at reflecting optoelectronic components. Often, however, the contact of the mirror metallization for semiconductor layer 3 bad. Therefore, an additional reflective layer 4 is applied to the contact layer 3, wherein the contact layer 3 is formed by very thin semi-transparent or apertured layers of better electrically conductive contact metals so that it absorbs little light. Can the mirror be destroyed by alloying with other metals, then a diffusion barrier should be 5 applied to the reflective layer 4 the. The application of the reflection layer 4 and / or diffusion barrier 5 can be effected by means of vapor deposition or sputtering.

p0058an adhesion and wetting layer 6 is applied to the diffusion barrier 5 as the uppermost layer. This is preferably applied by means of vapor deposition or sputtering, and may consist of chromium, nickel or conductive TiO exist. (See Figure 7c.)

p0059On the adhesion and wetting layer 6, a carrier substrate 7 to the desired thickness, for example, by sputtering, a CVD method (namely, a chemical vapor deposition) method, an electroplating method, electroless plating, or other known method deposited. See Figure 7d. been The thickness of the support substrate depends essentially on the stage during the processing and necessary during operation, mechanical stability, the maximum permissible thermal stresses before cracks in the semiconductor occur and whether measures such as incorporating an auxiliary substrate (as explained below) taken are. Without measures to compensate thermal stresses, the carrier substrate should not exceed 15 microns in thickness. Since this thickness is too thin for the processing, an auxiliary substrate 12 may be used. (See Figure 8 and the description on this below.)

p0060The carrier substrate 7 should be made of a material that is thermally and electrically highly conductive and mechanically stable. Bumps and foreign particles should be compensated by the carrier substrate. 7 Since the deposition can be carried out at room temperature, inter-diffusion is not to be feared during the process. Preferably, a galvanic process is used. Vapor deposition has the disadvantages that the deposition rates are relatively small and the coated layer having low strength. In contrast, sputtering, deposition from the gas phase (CVD Method), and deposition from a liquid phase more suitable.

p0061As shown in Figure 8, may optionally be applied in addition a solder layer 11 to the support substrate 7 to it, a further auxiliary substrate to bond 12th For example, a mechanically stable semiconductor such as silicon, germanium, silicon carbide, or a metal substrate made of molybdenum or tungsten may be used. The solder layer 11 has for example a gold / tin mixture. An auxiliary substrate 12 may be required, if the metal layer itself should not be too thick, or their deposition is very expensive. Since the solder layer 11 is now located at a greater distance from the semiconductor layer 2, not influence their poor th mechanical properties, as already explained above, the separation process. The solder layer 11 and / or the auxiliary substrate 12 can by means of sputtering, vapor deposition or be electroplated. After removal of the growth substrate 1 is possible, the auxiliary substrate 12 to remove at choice of a low-melting solder and again due to the process or exchanged for another (such as cheaper aluminum or copper). In addition, the auxiliary substrate 12 may also by means of a bonding process (eg NanoPierce^®See http://www.nanopierce.com) are attached.

p0062After the application of the carrier substrate and possibly the auxiliary substrate, the growth substrate 1 is separated from the semiconductor layer 2. FIG. Depending on the selected growth substrate 1 and semiconductor 2, this process step by chemical

p0063Resolution of the growth substrate 1, a sacrificial layer, a laser lift-off method, equipped with predetermined breaking points, laminated growth substrate or any other known method can be performed.

p0064Substrate materials such as GaAs or silicon can easily be chemically dissolved. The growth substrate is here lost. In addition, the semiconductor must either itself be inert against the etchant or be equipped with special etch stop layers. Another possibility is to incorporate a sacrificial layer in the semiconductor layer 2, which can be selectively etched. In this way, the growth substrate is 1 not lost and can be reintroduced in the process.

p0065In the material system of the nitrides which are used for generating light in the short wavelength spectral range, no suitable chemical etching techniques both for common substrates such as sapphire or silicon carbide and semiconductor (such as AlN, GaN, InN) have so far been known. For separating the semiconductor layer 2, therefore the method of laser lift-offs is used here for example. This exploits that GaN in bombardment with a laser can decompose in gallium and gaseous nitrogen. It is a laser with a photon energy sufficient for the decomposition of the GaN, but not sufficient for the decomposition of the growth substrate used. The laser is irradiated through the sapphire, which is transparent still at the required wavelengths. At the boundary layer on sapphire as the GaN is decomposed and, due to the formation of the gases and the pressure, the semiconductor layer 2 is separated from the sapphire growth substrate. 1 The component after separating the growth substrate 1 is shown in Figure 7e. However, this method is not possible with SiC deposited on GaN, since SiC has a smaller band gap than GaN and is therefore decomposed before GaN.

p0066Further, it is also possible to deposit the semiconductor layer 2 on an already laminated growth substrate first Such laminated growth substrate 1 (eg SMARTCUT^® or UNIBOND^®) Has as a top layer on an adhesive layer, which is equipped with suitable predetermined breaking points. At these points, the semiconductor thin film 2 is separated after the application of the support substrate 7 from the growth substrate first Now mesa trenches 10 are etched at least in the semiconductor layer 2 and the contact layer 3 so that individual chips are defined between the mesa trenches 10th The mesa trenches 10 extend at least through the entire semiconductor layer 2 and the contact layer 3. The form of the mesa trenches 10 in cross section is shown for example in Figure 7f. Other forms are also possible. The etching of mesa trenches 10 can by photolithography or other known methods in combination with dry etching, for example, the RIE

p0067Process (ie reactive ion etching) to be performed.

p0068In a further step, the contact 8 by sputtering or vapor deposition is shown in FIG 7f on the semiconductor layer 2 applied. The contact 8, for example, contains aluminum. Possibly, a passivation layer 9 (for example of silicon nitride or silicon oxide) may be applied by sputtering or a CVD method over the part of the semiconductor layer 2 which is not covered by the contact 8 and at least over the side surfaces of the contact layer 3rd

p0069Optional three-dimensional structures in the semiconductor or in the passivation layer 9 can be made to optimize the light output. Since the light is first extracted from the semiconductor, such structures have better effect if they are produced in the semiconductor layer 2, as in the passivation layer 9. structures to improve the light coupling can of course be in two produces the layers.

p0070For example, pyramid structures having at least three visible faces each pyramid, etched into the semiconductor layer 2 before the contacts 8 or the possible passivation layer 9 are applied. After the semiconductor layer 2 is separated from the growth substrate 1, the surface of the semiconductor layer 2 is fairly rough. arise the pyramid structures particular by an anisotropic etching method such as RIE. Depending on the selected semiconductor, the structures may also be produced by means of wet chemical etching or dry-etching process. For example, a RIE or ICP method (ie, inductively coupled plasma) is more suitable for the structuring of the GaN, which also wet chemical etching can be used for a GaAs semiconductor. After a patterning of such a contact 8 and preferably also a passivation layer 9 is applied to protect the surface from contamination.

p0071Finally, the chips are separated along the mesa trenches 10, for example by sawing or laser cutting. In the figure 7g singling is shown with a saw blade.

p0072In Figures 9a to 9f, the process steps of a modification of the 7a to 7g approaches presented are procedure outlined in part. The information on materials and processes from the above embodiment also apply to the following examples, unless otherwise indicated. The application of the semiconductor 2, contacts 3 and reflective layer 4 on the growth substrate 1 is carried out according to the above description of FIGS 7a and 7b. In this case, the reflection layer 4 is integrated in the contact layer 3rd This combined layer is labeled as 3 + 4 in the figures.

p0073As shown in Figure 9a, the mesa trenches are here etched 10 before separating the semiconductor layer 2 of the growth substrate 1 in the contact / reflection 3 + 4 and semiconductor layer 2. FIG. This may be advantageous when the Mesaätzprozeß causes problems with an underlying layer. For example, the diffusion barrier 5, the wetting layer or the supporting substrate 7 may be applied in the above procedure before the Mesaätzprozeß, in this method, but only after Mesaätzprozeß and are therefore not exposed to the etching. After etching the layer stack (the contact / reflection 3 + 4 and semiconductor layer 2 that is) is in the form of individual islands on the growth substrate 1. A diffusion barrier 5 is applied on the islands, that is on the contact / reflection layer 3+ . 4 Subsequently, a passivation layer 9 is applied evenly over the non-covered by the diffusion barrier contact / reflection 3 + 4 and the semiconductor layer 2 and over the mesa trenches 10 located in part of the growth substrate. 1

p0074A tackifier and wetting layer 6 is deposited on the entire surface including the surface of the mesa trenches 10th See Figure 9b.

p0075According to Figure 9c, the carrier substrate 7 is for example galvanically applied to the wetting layer 6 to the desired thickness, so that the mesa trenches are 10 well filled.

p0076The growth substrate 1 according to any of the above

p0077Separation methods separately from the semiconductor layer 2. FIG. In this case, the portions of the passivation layer 9 which are located in the mesa trenches, also be removed. See figure 9d.

p0078According to Figure 9e, the contacts 8 is applied to the semiconductor layer. 2 To better protect the semiconductor layer 2 from contamination, the passivation layer 9 extends to the semiconductor layer. 2

p0079Finally, the chips are along the mesa trenches means

p0080Sawing or laser cutting sporadically. See Figure 9f.

p0081Another method excessive embodiment is illustrated in Figures 10a to 10g. This method involves directly to the previous method, after the application of the wetting layer 6 on (see FIGS. 9b and 10a). Instead, the carrier substrate 7 surface as shown in Figure 9c shown provides deposit, separators 13 are applied, for example, of a photoresist by photolithography, the LIGA process, or similar arrangements with galvanic impression. This is achieved by the photoresist is flat up to at least 10 microns thick applied to the wetting layer 6, so that all the mesa trenches are completely filled over their entire length. After suitable exposure, the photoresist that lies between the mesa trenches and above the semiconductor layer 2 are selectively removed (see FIG 10b). It is important that this material can be selectively removed. The dividers 13 can (as the ma-P 100 or the SU-8, a LIGA process, or for suitable photoresist from MicroChem Corp. for example) reach very high aspect ratios with modern resist systems. Advantageously, the narrowest possible dividers. The narrower the separating webs 13 are, the less usable wafer area is wasted by the separating webs. This in turn means that the number of chips per wafer is increased and the cost is lowered.

p0082The spaces between the partitions 13 above the semiconductor layer 2, for example, galvanically maximum replenished as 10c with a suitable as a carrier substrate 7 material to the height of the partitions. Then the separating webs by means of a solvent, or by

p0083Etching selectively removed. In the resulting carrier substrate islands 71 ​​are shown in Figure lOd. For ease of use for further processing, the carrier substrate islands 71 ​​including the mesa trenches are completely overmolded with an auxiliary material 14 of sound thickness. The components for this overmolding are shown in FIG Loe. The auxiliary material 14 may be deposited by a sputtering method, a CVD method, an electroplating method, electroless plating, or another known method the. The use of metals, polymers suitable (eg polyimide) or spinon glasses is conceivable. Mechanical strength can also by gluing or soldering to a second substrate are awarded. But it is important that the auxiliary material 14 may be selectively removed.

p0084After the overmolding with auxiliary material 14, the growth substrate 1 is separated by one of the above-mentioned method of the semiconductor layer 2. FIG. As shown in Figure lOf, the contacts 8 are then applied to the semiconductor layer. 2

p0085The components can then be isolated without mechanical force. A carrier film 15 is applied to the semiconductor layer over the contacts 8 and the auxiliary material 14 is selectively removed, for example by etching. Then the components are automatically separated and, as shown in Figure 10g, are available on a carrier film 15th This separation process can be very fast, provided sufficient etch rates. Unlike sawing, for the time consumption is simply proportional to the number of components, the time consumption is here, regardless of the number of components and the wafer size. This has as an additional

p0086Advantage over the sawing process that any geometry restrictions eliminated to the device. It can be prepared including round or square elements. Through the narrow partitions 13 and the waste of the wafer is surface that will be invisible as unused saw track is reduced.

p0087In the figures 11a-lld a further exemplary embodiment is sketched game that is a variation of the last process. In this embodiment, the process proceeds essentially by the results summarized in Figures 10a to 10c scheme except that the upper side of the separating webs 13 is formed in cross section as a peak. Instead of applying the carrier substrate 7 only to the height of the partitions 13, this process will be continued, so that the whole structure, including separators 13 is overmolded area. This is illustrated in Figure 11a and can with the same material as that of the carrier substrate 7 used, or happen to another.

p0088The overmolded structure should now be sufficiently strong that the growth substrate 1 can be readily removed. The contacts 8 are applied to the semiconductor layer. 2 See Figure 11b.

p0089Figure 11c shows the components after the partitions 13 of the example by means of organic solvent

p0090Side of the semiconductor layer 2 are dissolved ago. Thus, each chip is virtually free on carrier substrate islands, which are connected by a carrier substrate layer. Since the connecting carrier substrate layer is now comparatively thin, can the components as shown in Figure lld, are sheared with little force. The pointed shape of the dividers and supports the shearing process can also advantageously act on a supporting substrate material, which has a low shear strength.

p0091Figures 12A and 12B show the division of a whole wafer with components such as in rows and may be secured by thermocompression on the lines connecting conductors 19, for example. At the same crack or break an assembly machine 18 off the connection and moves to the next field. Since this only short distances to be covered, the method is also suitable for loading areas with larger numbers (eg from self-luminous RGB displays).

p0092In the Figures 13a and 13b, a further embodiment will be outlined, which is an alternative to the method shown in Figures 10a to 10g. Here the component without photoresist and without structuring is produced. Instead of the wetting layer 6 is applied as in Figure 10a on the entire surface, the wetting layer 6 is listed in this embodiment, only the outermost layer above the semiconductor layer 2 introduced, ie, no wetting material is located on the side or surface of the mesa trenches. As shown in Figure 13a, an anti-wetting layer 16 is applied to the side and surfaces of the mesa trenches. These anti-wetting layer 16 may be a dielectric such as silicon nitride or silicon oxide. The wetting layer 6 composed for example of gold or titanium.

p0093For example, the support substrate material (for example, NIK kel) grows in electroless plating only on the wetting layer. 6 If the process is stopped before the mesa trenches grow, separate carrier substrate islands 71 ​​as shown in Figure 13b, achieved. These components can then be further processed as the components shown in Figure lOd. Although the structure of the carrier substrate Loyalty Islands 71 ​​is not as good as the photoresist process (namely, the method illustrated in Figures 10a to 10g), but it saves the cost of a Lackprozessierung and exposure.

p0094The shown in the figures 3a, 4 and 6a, the inventive devices can be fabricated with appropriate modifications even after the process of the invention, namely by modifications of in Figures 7, 9, 10, 11 and 13 illustrated method.

p0095For the fabrication of the devices shown in Figures 3a, 4 and 6a of the carrier substrate 7 and the carrier substrate island 71 must be structured. This structuring can be achieved for example by photolithography, a LIGA process, or other known method. Using the photolithography, as an example, a suitable photo-resist should be applied to the wetting layer 6 may be exposed and etched accordingly, so that the negative shape of the vertical structural elements and the structural element 25 of the desired component is obtained prior to the application of the carrier substrate. 7 To achieve Structural elements 25 with high aspect ratios, a LIGA method or a suitable therefor photoresist is preferably (for example the MA-P 100 or the SU-8 of Nano ™) was used.

p0096In order to produce the component shown in Figure 4, or 6, can resist when it is sufficiently elastic, be left to the LIGA process in the component as, or can the gaps are filled 26 with an additional filler 27th The last alternative should be carried out after the dissolution of the photoresist. This may be by an injection method in which, for example, a thermoplastic is injected into the spaces, by inflow of a filler material 27 in the liquid phase, for example at high temperatures, by inflow of an adhesive bers in the liquid phase, which is dried later or cures (as epoxy resin) or by another known method.

p0097In the context of the in the figures 7a to 7g proceedings represented the diversion comes to producing a in Figure 3a,

p00984 or 6a illustrated device after the depicted in Figure 7c stage of manufacture is achieved. As already described above, the photoresist is applied here to the wetting layer 6 and a plurality of negative forms of structural elements 25 is structured, when the device shown in Figure 3A or 4 is desired. In the alternative, the photoresist is patterned with a negative form of the structural element 25, when the device shown in Figure 6a is reached. Thereafter, the support substrate 7 is deposited according to one of the above methods, however, over the photoresist addition to the desired thickness of the tray 24 (for example, 50 microns). The carrier substrate is thus formed, for example in one piece. The photoresist can be dissolved at any time prior to the dicing of wafers are to, or may not. If the photoresist is more elastic or softer than the material of the support substrate 7, then the photoresist may at the same time as a filling material 27 for the in Figures are 4 or 6 device pictured. Otherwise, the device may as to Figures 7e to 7g already described, be further processed.

p0099The carrier substrate 7 can also be patterned after the process stage shown in Figure 9b is achieved. As already described above, the photoresist is applied on the wetting layer 6 and patterned and the support substrate 7 applied so that at least a struc element and a gap formed, and a support floor 24 is formed. After the optional resolution of the photoresist and the optional use of a filler 27, the further processing may take place after the figures 9d to 9f.

p0100Similarly, the structuring can take place after the manufacturing stage reached in Figure 10b. Here, the photoresist is applied to the lying between the dividers 13 wetting layer 6 and patterned. As already described above, the support substrate 7 is applied to the lying between the dividers wetting layer 6 and on the photoresist, so that even a support base 24 is formed. The further processing of FIGS lOd to ​​10g can be done with or without resolution of the photoresist or the application of a filler 27th

p0101According to the method to lld shown in the figures 11a, the carrier substrate can be as already described above, structured. The structural elements 25 are lower than the partitions 13 so that the component during a contingent rush shearing process sufficient mechanical stability can be imparted. For example, the structural elements 25 are about 15 microns high and the partitions 13 about 50 microns high. The dividers 13 may be high between 50 microns and 200 microns usually, but the higher the separators 13 are, the thicker the carrier substrate 7 and the more material is required, which in turn is a cost issue. According to the method shown in Figures 13a and 13b, producing a structured support substrate 7 for manufacturing a device over the depicted in Figure 13a wetting layer 6 illustrated in Figures 3a, 4 or 6a can take place.

p0102This patent application claims priority from German Patent Application 102 45 631.3-33, the disclosure of which is hereby incorporated by reference.

p0103The scope of the invention is not limited by the description of the invention based on the embodiments. Rather, the invention encompasses any new feature and also any combination of features, including in particular any combination of features in the patent claims, even if this combination is not explicitly specified in the patent claims.