Electronic circuit for decoding of an asynchronous biphase signal, corresponding method and corresponding control device.

1. Field of the invention

0001The field of the invention is that of decoding digital data.

0002More specifically, the invention relates to two-phase asynchronous data decoders, in particular coded according to the Manchester code.

0003More precisely still, the invention relates to the synchronization of two-phase asynchronous signal decoders.

0004The invention can find applications in all fields using Manchester type transmissions, such as that of industrial control or telecommunications, in particular when it is desirable to have simple decoders and at low cost. For example, the invention can be applied to communication in the field of lighting, and in particular to the DALI standard (“Digital Addressable Lighting Interface” or “Digital Addressable Lighting Interface”).

2. Prior art

2.1. Manchester coding

0005Manchester coding is a technique that has been known for a long time and applied in many fields. There are several methods for retrieving the corresponding clock from a receiver, and in particular the use of a phase-locked loop or an accurate clock.

2.2. Using a phase locked loop

0006Frame decoders encoded according to the Manchester principle therefore generally require the use of a phase locked loop, also called PLL (for “Phase-Locked Loop”) for synchronization. According to this principle, the phase of the output signal is locked on that of the input signal, which forces the frequency of the output signal to lock on the frequency of the input signal, allowing a frequency control, therefore a synchronization. .

0007A major drawback of this technique of the prior art is that during the phase locking step which will allow synchronization, the first transmitted data are lost.

0008Another drawback of this technique is that it is expensive and relatively complex to implement, due in particular to the presence of a phase locked loop.

2.3. Using an accurate clock

0009For other remote transmission systems, it is necessary to use an accurate clock in order to reliably decode the data received.

0010A major drawback of this technique is that it requires knowing at the receiver the speed of the transmission (or "baud rate").

0011Furthermore, it requires having a precise local clock, both at the transmitter and at the receiver, which makes this technique more costly and complex to implement.

2.4 other prior art

0012The request of <patcit id="pcit0001" dnum="EP1347609A"><text>EP patent 1,347,609 A</text></patcit> describes a method of clock recovery and decoding of Manchester codes using a counter powered by an internal clock to detect mid-bit transitions and to mask the initial transitions, which eliminates the need to use a very precise clock.

0013The documents <patcit id="pcit0002" dnum="DE10163702A"><text>DE 10 163 702 A</text></patcit>, and <nplcit id="ncit0001" npl-type="b"><text>J. Horstmann, "Biphase / NRZ decoder solves jitter problems", EDN electrical design news, Cahners publishing co., Newton, MA / US, vol 28, no 6, March 17, 1983, pages 222, 224</text></nplcit> also describe methods of clock recovery for two-phase codes using a counter powered by an internal clock.

3. Objectives of the invention

0014The invention particularly aims to overcome these drawbacks of the prior art.

0015More specifically, an objective of the invention is to provide a technique for decoding a two-phase asynchronous data signal making it possible to recover a decoding clock in a simple and efficient manner, without requiring a phase locked loop or precise clock. .

0016Another object of the invention is to provide such a technique which allows a receiver to automatically adapt to the data transmission speed, without prior knowledge of this speed.

0017Yet another objective of the invention is to generate the decoding clock in a simple and inexpensive manner.

0018The invention also aims to implement such a decoding technique which is particularly robust.

4. Essential features of the invention

0019These objectives, as well as others which will appear subsequently, are achieved by means of an electronic circuit for decoding a two-phase asynchronous data signal.

0020According to the invention, such a circuit comprises means for generating a decoding clock implementing a counter powered by an internal clock, and repeating cycles comprising an incrementation of the counter until the detection of a transition in the data signal, then decrement the counter to zero.

0021Thus, the invention relates to an electronic decoding circuit which makes it possible to recover at output the transmitted data and their transmission clock using a simple counter and this without requiring a precise internal clock.

0022Such a circuit will automatically adapt to the speed of data transmission, without requiring precise knowledge of the local clock.

0023We can then assimilate the count value at the output of the counter to a sawtooth signal, the peaks of each of the teeth corresponding to the transitions in the data signal. It is from these transitions that we will recover the decoding clock and the decoded data.

0024Thus, the invention proves to be particularly effective and not very complex and is based on a completely new and inventive approach to the decoding of asynchronous two-phase frame using a simple counter.

0025Preferably, the decoding clock is generated by taking into account each peak of a signal representative of the content of the counter.

0026In particular, each peak is used to locate a transition which carries the value of a bit of the data signal.

0027In this case, we will analyze the direction of each of the transitions to decode the value of a bit.

0028By decoding the direction of the transition, the circuit thus makes it possible both to determine the value of a bit of the data signal and to reconstruct a clock making it possible to parallelize the decoded data.

0029According to an advantageous embodiment, the electronic circuit comprises at least one register for storing the content of the counter when a transition in the data signal is detected.

0030This register will make it possible to improve the robustness of the electronic circuit of the invention by comparing the output of the counter with the value stored in this register.

0031Preferably, the electronic circuit comprises initialization means which, during the first falling edge, activate the incrementation of the counter, the latter being previously forced to zero.

0032Advantageously, the electronic circuit includes windowing means limiting the detection of a transition over predetermined intervals.

0033In this case, each of the predetermined intervals covers approximately 50% of a binary time and is centered on each of the transitions.

0034We consider here that a binary time corresponds to the duration (or width) of a bit.

0035In particular, the predetermined interval is controlled by a first comparator supplied by the output of the storage register divided by two and by the counter.

0036Thus, when the value of the counter is greater than the value of the storage register divided by two, an edge detection authorization window is created, corresponding to this predetermined interval.

0037According to another advantageous aspect of the invention, the electronic circuit comprises means for detecting the interruption of the data signal.

0038In particular, these interruption detection means comprise a second comparator supplied by the output of the storage register multiplied by two and by the counter.

0039Thus, one can determine if the transmission is not interrupted, by checking that one always receives transitions.

0040The robustness of the system is thus improved by reducing the probability of false detection and by prohibiting detection on the inter-bit edges when the consecutive bits are of the same value using the first comparator, and / or by detecting the absence of transmission. using the second comparator.

0041Preferably, the electronic circuit comprises means for rejection of the parasites on the data signal.

0042In particular, these rejection means comprise a digital filter supplied by the data signal and controlled by the internal clock.

0043In particular, these rejection means can take into account at least three successive samples to decide the existence of a transition.

0044These rejection means allow the decoder to avoid confusion between a parasite and a transition.

0045Advantageously, the internal clock is of frequency at least greater than 16 times the bit rate of the data signal, which makes it possible to parallelize the data at the output of the decoder.

0046According to an advantageous embodiment of the invention, the data signal is encoded according to a Manchester encoding.

0047Transition coding is thus used, where the bits are encoded by transitions and not by states.

0048Preferably, the data signal is organized in successive frames each starting with a start bit.

0049According to an advantageous embodiment, the electronic circuit makes it possible to receive and decode a sequence comprising an undefined number of data.

0050Thus, the circuit automatically adapts to each sequence it receives, even if the length of the sequences varies during transmission.

0051The invention also relates to a method for decoding a two-phase asynchronous data frame, comprising steps of generating a decoding clock implementing a counter powered by an internal clock, and repeating cycles comprising an incrementation of the counter up to 'upon detection of a transition in the data signal, then decrementing the counter to zero.

0052The invention also relates to devices for controlling at least one piece of equipment using at least one electronic circuit as described above.

0053In particular, the equipment controlled by these control devices can be lighting.

5. List of Figures

0054Other characteristics and advantages of the invention will appear more clearly on reading the following description of a preferred embodiment, given by way of simple illustrative and nonlimiting example, and of the appended drawings, among which:<ul id="ul0001" list-style="dash" compact="compact"><li>FIG. 1 presents a general diagram of a decoder of a signal encoded according to the Manchester principle;</li><li>FIG. 2 illustrates a two-phase asynchronous data frame (Manchester) received by the decoder of FIG. 1;</li><li>Figure 3 describes the operation of the decoder of Figure 1, according to the invention, in the form of a block diagram;</li><li>FIG. 4 presents a timing diagram of the various input / output signals and of the intermediate signals of the diagram of FIG. 3.</li></ul>

6. Description of an embodiment of the invention

0055The general principle of the invention is based on an electronic asynchronous biphase frame decoding circuit making it possible to recover at output the transmitted data and their transmission clock using a simple counter and this without requiring a precise internal clock or phase locked loop.

0056This electronic circuit can in particular automatically adapt to any variable transmission speed, even if it does not know the internal clock precisely. It suffices for this to implement a counter deep enough to adapt to a relatively low transmission speed, and a local clock fast enough with respect to a higher transmission speed.

0057It is considered according to the invention that the data frame received at the decoder is of the asynchronous type because it consists of a series of asynchronous binary elements of the receiver. It is also of the biphase type because the data bits are not encoded by states but by transition bits. This coding is known as Manchester coding.

0058Referring to FIG. 1, the inputs and outputs of the decoder 14 are presented.

0059This decoder 14 has two inputs, the first 11 on which the two-phase asynchronous frames are sent (denoted RxD in the figure) and the second 12 corresponding to the input of the local clock (L_CLK in the figure), also called the internal clock . In the embodiment described, the local clock can be of imprecise frequency, but greater than 16 times the bit rate of the data to be decoded.

0060This decoder 14 also has an output 13 which makes it possible to find the decoded data DATA, placed in parallel over a width of <i>not</i> bits, the number <i>not</i> varying according to the application.

0061In the embodiment described, the transmitted signal is organized in frames. The two-phase asynchronous frames received on the RxD input 11 of the decoder 14 consist of a start bit (called "start" bit), are followed by data bits and end with one or more stop bits. These different bits are not encoded by states but by transitions, as illustrated in Figure 2.

0062Thus, according to Manchester coding, the bits equal to '1' are coded by rising edges 21 and the bits equal to '0' are coded by falling edges 22. The start bit 23 is also encoded according to the principle of Manchester.

0063It is understood that the invention presented also applies to any other type of coding where the bits are encoded by transitions and not by states. It will thus be possible, in another embodiment, to code the bits equal to '1' by falling edges and the bits equal to '0' by rising edges.

0064In the absence of transmission or between the data, one remains in an inactive state 24, during which there is no transition.

0065More specifically, in relation to FIG. 3, the block diagram of the decoder 14 is presented.

0066In a preferred embodiment, this decoder 14 is composed:<ul id="ul0002" list-style="dash" compact="compact"><li>a counter 31, which can be incremented or decremented;</li><li>a register 32 used to store the value of the counter 31 at a given time;</li><li>a comparator 33 comparing the value of the counter 31 to zero, called comparator to zero;</li><li>two other comparators called first comparator 34 and second comparator 35;</li><li>a “Logic and State Machine” block 36;</li><li>a digital filter 37;</li><li>and a parallelizer 38.</li></ul>

0067In order to improve the decoding, it is desirable to place a digital filter 37 at the input of the assembly. This filter 37 will allow the rejection of the parasites, avoiding the decoder 14 to confuse a parasite with a transition. For this, we can take into account several successive signal samples, for example three: depending on the level of these three successive samples, we can decide whether they correspond to a transition (rising edge or falling edge) or to a parasite.

0068During the inactive state 24, the counter 31 is maintained at the value zero. The zero comparator 33 comparing the output of the counter 31 to the zero value is therefore in the 'true' position, and this information is transmitted to the "Logic and State Machine" block 36. Nothing happens: the transmission line is in an inactive state. In this position, the counter 31 is at zero, under the action of a reset command 313 (called “clear”).

0069During the first falling edge 25, the counter 31 receives a command 311 from the “Logic and State Machine” block 36, launching an incrementation (“up” or rising direction) until a transition in the signal is detected. of data. The value K of the counter 31 is then stored in the register 32 and the counter 31 starts again in the other direction: when the “Logic and State Machine” block 36 detects a transition, it sends a decrementation command 312 (sense “ down ”or descending).

0070When the zero comparator 33 detects that the counter 31 has reached the zero value, the latter starts again in the up direction, under the action for example of the logic defined in the “Logic and State Machine” block 36.

0071At the next transition, the new value of the counter 31 is stored in the register 32 and the counter 31 is again decremented.

0072In this preferred embodiment described, the circuit also includes two other comparators 34 and 35 making it possible to improve the decoding performance.

0073The first comparator 34 makes it possible to compare the value of the counter 31 with the value N of the register 32 divided by two. When the value of the counter 31 is greater than the value N of the register 32 divided by two (N / 2), a window is created, authorizing the transition detection in this window. Such a window covers about 50% of a binary time and is centered on the transition.

0074This first comparator 34 therefore improves the robustness of the system since it reduces the probability of false detection and prohibits detection on the inter-bit edges when the consecutive bits are of the same value.

0075The second comparator 35 makes it possible to compare the value of the counter 31 with the value N of the register 32 multiplied by two. This comparison makes it possible to detect if transitions are still received, and therefore if the transmission is not interrupted. The robustness of the decoder is therefore further improved.

0076Finally, in this described embodiment, the “Logic and State Machine” block 36 will make it possible to recover two signals, a decoding clock signal 361 and an intermediate decoded data signal 362, called S_Clock and S_Data on the block diagram.

0077This “Logic and State Machine” block 36 intervenes at different stages during decoding: its role is to detect changes of edges on the asynchronous biphase data signal to be decoded, to count the number of bits received according to the application and manage the counter 31 and the register 32 taking into account the output of the three comparators 33, 34 and 35.

0078A last paralleling block 38 makes it possible to reconstruct the decoded data signal 13 DATA, consisting of the data decoded in parallel over a width <i>not</i> bits, or the number <i>not</i> depends on the application.

0079FIG. 4 makes it easier to visualize the operation of the decoder 14, and more particularly that of the counter 31. Certain signals of the preferred embodiment described above are represented on this timing diagram, as a function of a two-phase asynchronous data frame 41 received, composed of a start bit and data bits, similar to the signal in Figure 2.

0080The counting value at the output of counter 31 can be compared to a sawtooth signal 421. These sawtooths 421 are not necessarily regular because the duty cycle can be different from 50%.

0081Each peak 422 of the sawtooth signal corresponds (45) to a transition 411 which carries the value of a bit on the data signal. It is by decoding the direction of the transition that the decoder as described will recover the value of the bit and reconstruct a clock 44 to parallelize the data.

0082The third curve 43 represents the windows 431 determined using the first comparator 34. It is these windows 431 which give the authorization to detect an edge in the interval which they define. It is by means of these predetermined intervals and of the sawtooth signal 42 of the counter 31 that the decoding clock 361 (also represented by the fourth curve 44) and the decoded data can be recovered.

0083In a particular embodiment, the electronic circuit of the invention also makes it possible to decode an unfrozen sequence of data. Indeed, as explained above, the analysis of each window 431 indicates to us the presence or not of a transition in this window. In the case where we have just detected a series of M transitions, we will analyze the content of the following window for authorization of detection of an edge: if there is no transition in this window, we can consider that the last bit received (bit M) is a stop bit. Otherwise, we should expect to receive other data.

0084Suppose for example that the decoder can receive several 16 or 17 bit frames, without knowing in advance in what order it will receive them. In this case, the electronic decoding circuit will first decode the first 16 bits received, as described above. Not knowing exactly how many data it should receive, the decoder will continue to study the sequence received, after reception and decoding of the first 16 bits.

0085It will therefore continue to analyze the content of the new transition detection authorization window, created after reception of the first 16 bits. If the new window contains a transition, we consider that this transition corresponds to 17^th bit. We therefore decide that we have received a 17-bit frame. On the other hand, if the content of the new window is empty, it must be considered that the last transition received corresponded to a stop bit and that consequently the frame received was composed of 16 bits.

0086It is understood that this particular embodiment is not restricted to 16 and 17 bit frames, and that those skilled in the art can easily extend it to frames of different lengths.

0087The decoder according to the invention therefore makes it possible to receive and process frames comprising an unfixed number of data.

0088In general, the width of the counter and of the register is given by the ratio between the "baud rate" of the data signal and the value of the local clock.

0089For example, with a data at 1200 baud and a local clock at 1MHz, the counting capacity must be greater than <maths id="math0001" num=""><math display="inline"><mfrac><msup><mn>10</mn><mn>6</mn></msup><mn>2400</mn></mfrac><mo>,</mo></math><img file="EP1536566B1_D0001.tif" /></maths>, or 416, which defines a 9-bit counter. To make it possible to absorb the tolerances on the data and on the local clock (± 10% for example) and to set up the detection of frame errors, the use of a counter of at least 10 bits is recommended .

0090This electronic decoding circuit can in particular be implemented for the decoding of DALI type frames. It can therefore be used, for example, in a lighting control device.